AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_bank_state Member List

This is the complete list of members for mig_7series_v1_9_bank_state, including all inherited members.

rp_timer_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
inhbt_act_rrd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
my_inhbt_act_faw (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_req (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rts_act_denied (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_starve_limit_cntr_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_starve_limit_cntr_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_act_priority_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_act_priority_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_demanded (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
row_demand_ok (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_this_rank_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
req_bank_rdy_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
req_bank_rdy_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rts_col_denied (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
STARVE_LIMIT_CNT (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
STARVE_LIMIT_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
starve_limit_cntr_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
starve_limit_cntr_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
starved (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_priority_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_priority_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rdy_for_priority (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
not_req_or_q_rdy_for_priority (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demanded (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demanded_prior_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demanded_prior_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rnk_config_match (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
my_inhbt_rd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
my_inhbt_wr (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
allow_rw (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
col_rdy (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
col_cmd_rts (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
phy_mc_ctl_full_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
phy_mc_cmd_full_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ofs_rdy_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
override_demand_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
override_demand_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
wr_this_rank_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rd_this_rank_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
TCQ (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
BM_CNT_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
BURST_MODE (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
CWL (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
DATA_BUF_ADDR_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
DRAM_TYPE (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ECC (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ID (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nBANK_MACHS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nCK_PER_CLK (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nOP_WAIT (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRAS_CLKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRP (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRTP (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRCD (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nWTP_CLKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ORDERING (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RANKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RANK_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RAS_TIMER_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
STARVE_LIMIT (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rmw_rd_done (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rd_half_rmw_lcl (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rmw_wait_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
col_wait_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
TWO (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
passed_ras_timer (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
i (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
start_wtp_timer (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_passed_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_zero_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_zero_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRTP_CLKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRTP_CLKS_M1 (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RTP_TIMER_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rtp_timer_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rtp_timer_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
sending_col_not_rmw_rd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
end_rtp_lcl (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
OP_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
allow_auto_pre (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
start_pre (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
pre_wait_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
pre_request (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRP/4)+((nRP%4)?1:0) (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRP_CLKS_M2 (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RP_TIMER_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
clogb2sizeclkrstbm_end (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_438clkpass_open_bank_rsending_rowrcv_open_bankstart_rcd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_439clkact_wait_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_440clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_441ras_timer_ns_in or rb_hit_busies_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_442bm_end_r1 or ras_timer_r or rst or start_rcd_lcl or start_wtp_timer (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_443clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_444clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_445pass_open_bank_r or rst or rtp_timer_r or sending_col_not_rmw_rd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_446clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_447clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_448clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_449clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_450act_wait_r or req_rank_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_451clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_452clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_453col_wait_r or rts_col_denied or starve_limit_cntr_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_454clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_455clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_456clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_457clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_458clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_459clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_460rd_wr_r or req_rank_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_461clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_462clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass