AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_bank_cntrl Member List

This is the complete list of members for mig_7series_v1_9_bank_cntrl, including all inherited members.

rp_timer_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
inhbt_act_rrd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
my_inhbt_act_faw (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_req (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rts_act_denied (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_starve_limit_cntr_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_starve_limit_cntr_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_act_priority_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_act_priority_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_demanded (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
row_demand_ok (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
act_this_rank_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
req_bank_rdy_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
req_bank_rdy_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rts_col_denied (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
STARVE_LIMIT_CNT (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
STARVE_LIMIT_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
starve_limit_cntr_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
starve_limit_cntr_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
starved (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_priority_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demand_priority_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rdy_for_priority (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
not_req_or_q_rdy_for_priority (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demanded (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demanded_prior_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
demanded_prior_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rnk_config_match (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
my_inhbt_rd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
my_inhbt_wr (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
allow_rw (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
col_rdy (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
col_cmd_rts (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
phy_mc_ctl_full_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
phy_mc_cmd_full_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ofs_rdy_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
override_demand_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
override_demand_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
wr_this_rank_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rd_this_rank_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
TCQ (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
BANK_WIDTH (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
BM_CNT_WIDTH (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
BURST_MODE (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
COL_WIDTH (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
CWL (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
DATA_BUF_ADDR_WIDTH (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
DRAM_TYPE (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ECC (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ID (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nBANK_MACHS (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nCK_PER_CLK (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nOP_WAIT (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nRAS_CLKS (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nRCD (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nRTP (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nRP (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
nWTP_CLKS (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ORDERING (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
RANK_WIDTH (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
RANKS (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
RAS_TIMER_WIDTH (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ROW_WIDTH (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
STARVE_LIMIT (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
accept_internal_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
accept_req (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
adv_order_q (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
bank (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
bm_end_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
clk (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
cmd (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
col (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
data_buf_addr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
demand_act_priority_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
demand_priority_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
phy_rddata_valid (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
dq_busy_data (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
hi_priority (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
idle_cnt (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
inhbt_act_faw_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
inhbt_rd (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
inhbt_wr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rnk_config (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rnk_config_strobe (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rnk_config_kill_rts_col (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rnk_config_valid_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
low_idle_cnt_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
maint_idle (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
maint_rank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
maint_req_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
maint_zq_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
maint_sre_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
op_exit_grant (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
order_cnt (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
passing_open_bank_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
periodic_rd_ack_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
periodic_rd_insert (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
periodic_rd_rank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
phy_mc_ctl_full (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
phy_mc_cmd_full (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
phy_mc_data_full (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rank (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ras_timer_ns_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rb_hit_busy_cnt (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rb_hit_busy_ns_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rd_data_addr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rd_rmw (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_rank_r_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
row (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rst (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
sending_col (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
sending_row (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
sending_pre (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
sent_col (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
sent_row (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
size (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
start_rcd_in (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
use_addr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
was_priority (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
was_wr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
act_this_rank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
col_addr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
col_rdy_wr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
demand_act_priority (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
demand_priority (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
end_rtp (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
op_exit_req (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ordered_issued (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ordered_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rank_busy_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
ras_timer_ns (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rb_hit_busy_ns (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rd_this_rank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_bank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_cas (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_periodic_rd_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_ras (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_row_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_size_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
row_addr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
row_cmd_wr (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rtc (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rts_col (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rts_row (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rts_pre (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
start_pre_wait (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
start_rcd (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
wr_this_rank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
act_wait_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
allow_auto_pre (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
auto_pre_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
bank_wait_in_progress (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
order_q_zero (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
pass_open_bank_ns (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
pass_open_bank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
pre_wait_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
precharge_bm_end (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
q_has_priority (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
q_has_rd (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rb_hit_busies_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rcv_open_bank (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rd_half_rmw (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_priority_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
row_hit_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
tail_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
wait_for_maint_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
idle_ns (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_wr_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rd_wr_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
bm_end (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
idle_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
head_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_rank_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
rb_hit_busy_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
passing_open_bank (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
maint_hit (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
req_data_buf_addr_r (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
BANK_WIDTH (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
TCQ (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
BURST_MODE (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
COL_WIDTH (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
DATA_BUF_ADDR_WIDTH (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
ECC (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
RANK_WIDTH (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
RANKS (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
ROW_WIDTH (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
idle_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
idle_r (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
data_buf_addr (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_data_buf_addr_r (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_data_buf_addr_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
periodic_rd_insert (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_periodic_rd_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_periodic_rd_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_periodic_rd_r (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
size (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_size_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_cmd_r (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_cmd_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
rd_wr_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
rd_wr_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_rank_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_rank_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_bank_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_bank_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_row_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_row_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_col_r (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_col_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_wr_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_wr_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
req_priority_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
rank_hit (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
bank_hit (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
rank_bank_hit (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
rb_hit_busy_ns_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
row_hit_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
col_addr_template (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
ONE (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
rank_busy_ns (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
TCQ (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
BM_CNT_WIDTH (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
nBANK_MACHS (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
ORDERING (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
ID (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
ZERO (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
ONE (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
BM_CNT_ZERO (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
BM_CNT_ONE (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
rst (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
idle_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
head_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
accept_internal_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
bm_ready (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
use_addr (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
periodic_rd_ack_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
accept_this_bm (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
bm_end_in (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
idlers_below (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
i (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
idlers_above (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
idle_cnt (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
rb_hit_busy_cnt (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
accept_req (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
bm_end_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
adv_queue (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
q_entry_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
q_entry_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
temp (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
head_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
head_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
rb_hit_busy_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
tail_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
clear_req (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
idle_ns_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
maint_hit_this_bm (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
pass_open_bank_eligible (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
wait_for_maint_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
pass_open_bank_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
pass_open_bank_ns_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
auto_pre_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
sending_col_not_rmw_rd (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
pre_bm_end_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
pre_bm_end_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
pre_passing_open_bank_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
pre_passing_open_bank_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
ordered_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
set_order_q (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
ordered_issued_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
ordered_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
order_q_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
order_q_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
rb_hit_busies_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
q_has_rd_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
q_has_rd_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
q_has_priority_r (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
q_has_priority_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
wait_for_maint_ns (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
TCQ (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
BM_CNT_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
BURST_MODE (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
CWL (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
DATA_BUF_ADDR_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
DRAM_TYPE (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ECC (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ID (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nBANK_MACHS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nCK_PER_CLK (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nOP_WAIT (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRAS_CLKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRP (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRTP (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRCD (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nWTP_CLKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ORDERING (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RANKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RANK_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RAS_TIMER_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
STARVE_LIMIT (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rmw_rd_done (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rd_half_rmw_lcl (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rmw_wait_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
col_wait_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
TWO (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
passed_ras_timer (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
i (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
start_wtp_timer (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_passed_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_zero_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
ras_timer_zero_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRTP_CLKS (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRTP_CLKS_M1 (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RTP_TIMER_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rtp_timer_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
rtp_timer_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
sending_col_not_rmw_rd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
end_rtp_lcl (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
OP_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
allow_auto_pre (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
start_pre (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
pre_wait_ns (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
pre_request (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRP/4)+((nRP%4)?1:0) (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
nRP_CLKS_M2 (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
RP_TIMER_WIDTH (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
clogb2sizeclkrstbm_end (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
mig_7series_v1_9_bank_compare (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
mig_7series_v1_9_bank_queue (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
mig_7series_v1_9_bank_state (defined in mig_7series_v1_9_bank_cntrl)mig_7series_v1_9_bank_cntrlClass
PROCESS_404clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_405clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_406clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_407clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_408clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_409clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_410clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_411clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_412clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_413clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_414clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_415auto_pre_r or rd_half_rmw or req_col_r or req_size_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_416act_wait_r or req_row_r_lcl (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_417clk (defined in mig_7series_v1_9_bank_compare)mig_7series_v1_9_bank_compareClass
PROCESS_418bm_end_in (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_419bm_end_in (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_420 (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_421clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_422accept_req or accept_this_bm or adv_queue or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl or idlers_below or q_entry_r or rb_hit_busy_cnt or rst (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_423clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_424accept_this_bm or clear_req or idle_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_425clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_426clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_427accept_req or allow_auto_pre or auto_pre_r_lcl or clear_req or maint_hit_this_bm or rb_hit_busy_r or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_428clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_429clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_430clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_431ordered_issued_lcl or ordered_r_lcl or rst or set_order_q (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_432clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_433adv_order_q or order_cnt or order_q_r or rst or set_order_q (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_434clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_435clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_436clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_437clk (defined in mig_7series_v1_9_bank_queue)mig_7series_v1_9_bank_queueClass
PROCESS_438clkpass_open_bank_rsending_rowrcv_open_bankstart_rcd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_439clkact_wait_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_440clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_441ras_timer_ns_in or rb_hit_busies_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_442bm_end_r1 or ras_timer_r or rst or start_rcd_lcl or start_wtp_timer (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_443clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_444clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_445pass_open_bank_r or rst or rtp_timer_r or sending_col_not_rmw_rd (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_446clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_447clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_448clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_449clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_450act_wait_r or req_rank_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_451clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_452clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_453col_wait_r or rts_col_denied or starve_limit_cntr_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_454clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_455clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_456clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_457clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_458clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_459clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_460rd_wr_r or req_rank_r (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_461clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
PROCESS_462clk (defined in mig_7series_v1_9_bank_state)mig_7series_v1_9_bank_stateClass
Generated on Wed Apr 18 2018 10:55:30 for AMC13 by   doxygen 1.8.1