AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
daqlink_7s_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : daqlink_7s_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module DAQLINK_7S_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity DAQLINK_7S_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80  STABLE_CLOCK_PERIOD : integer := 16; --Period of the stable clock driving this state-machine, unit is [ns]
81  EXAMPLE_USE_CHIPSCOPE : integer := 0; -- Set to 1 to use Chipscope to drive resets
82  -- REFCLK frequency, select one among 100, 125, 200 and 250 If your REFCLK frequency is not in the list, please contact wusx@bu.edu
83  F_REFCLK : integer := 125
84 
85 );
86 port
87 (
88  SYSCLK_IN : in std_logic;
89  SOFT_RESET_IN : in std_logic;
90  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
91  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
92  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
93  GT0_DATA_VALID_IN : in std_logic;
94 
95  --_________________________________________________________________________
96  --GT0 (X1Y0)
97  --____________________________CHANNEL PORTS________________________________
98  --------------------------------- CPLL Ports -------------------------------
99  GT0_CPLLFBCLKLOST_OUT : out std_logic;
100  GT0_CPLLLOCK_OUT : out std_logic;
101  GT0_CPLLLOCKDETCLK_IN : in std_logic;
102  GT0_CPLLRESET_IN : in std_logic;
103  -------------------------- Channel - Clocking Ports ------------------------
104  GT0_GTREFCLK0_IN : in std_logic;
105  ---------------------------- Channel - DRP Ports --------------------------
106  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
107  GT0_DRPCLK_IN : in std_logic;
108  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
109  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
110  GT0_DRPEN_IN : in std_logic;
111  GT0_DRPRDY_OUT : out std_logic;
112  GT0_DRPWE_IN : in std_logic;
113  ------------------------------- Loopback Ports -----------------------------
114  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
115  --------------------- RX Initialization and Reset Ports --------------------
116  GT0_RXUSERRDY_IN : in std_logic;
117  -------------------------- RX Margin Analysis Ports ------------------------
118  GT0_EYESCANDATAERROR_OUT : out std_logic;
119  ------------------------- Receive Ports - CDR Ports ------------------------
120  GT0_RXCDRLOCK_OUT : out std_logic;
121  ------------------- Receive Ports - Clock Correction Ports -----------------
122  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
123  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
124  GT0_RXUSRCLK_IN : in std_logic;
125  GT0_RXUSRCLK2_IN : in std_logic;
126  ------------------ Receive Ports - FPGA RX interface Ports -----------------
127  GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
128  ------------------- Receive Ports - Pattern Checker Ports ------------------
129  GT0_RXPRBSERR_OUT : out std_logic;
130  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
131  ------------------- Receive Ports - Pattern Checker ports ------------------
132  GT0_RXPRBSCNTRESET_IN : in std_logic;
133  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
134  GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
135  GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
136  --------------------------- Receive Ports - RX AFE -------------------------
137  GT0_GTXRXP_IN : in std_logic;
138  ------------------------ Receive Ports - RX AFE Ports ----------------------
139  GT0_GTXRXN_IN : in std_logic;
140  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
141  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
142  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
143  ------------- Receive Ports - RX Initialization and Reset Ports ------------
144  GT0_GTRXRESET_IN : in std_logic;
145  GT0_RXPMARESET_IN : in std_logic;
146  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
147  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
148  GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
149  -------------- Receive Ports -RX Initialization and Reset Ports ------------
150  GT0_RXRESETDONE_OUT : out std_logic;
151  --------------------- TX Initialization and Reset Ports --------------------
152  GT0_GTTXRESET_IN : in std_logic;
153  GT0_TXUSERRDY_IN : in std_logic;
154  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
155  GT0_TXUSRCLK_IN : in std_logic;
156  GT0_TXUSRCLK2_IN : in std_logic;
157  --------------- Transmit Ports - TX Configurable Driver Ports --------------
158  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
159  ------------------ Transmit Ports - TX Data Path interface -----------------
160  GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
161  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
162  GT0_GTXTXN_OUT : out std_logic;
163  GT0_GTXTXP_OUT : out std_logic;
164  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
165  GT0_TXOUTCLK_OUT : out std_logic;
166  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
167  GT0_TXOUTCLKPCS_OUT : out std_logic;
168  --------------------- Transmit Ports - TX Gearbox Ports --------------------
169  GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
170  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
171  GT0_TXRESETDONE_OUT : out std_logic;
172  ------------------ Transmit Ports - pattern Generator Ports ----------------
173  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
174 
175 
176  --____________________________COMMON PORTS________________________________
177  ---------------------- Common Block - Ref Clock Ports ---------------------
178  GT0_GTREFCLK0_COMMON_IN : in std_logic;
179  ------------------------- Common Block - QPLL Ports ------------------------
180  GT0_QPLLLOCK_OUT : out std_logic;
181  GT0_QPLLLOCKDETCLK_IN : in std_logic;
182  GT0_QPLLRESET_IN : in std_logic
183 
184 
185 );
186 
187 end DAQLINK_7S_init;
188 
189 architecture RTL of DAQLINK_7S_init is
190 
191 --**************************Component Declarations*****************************
192 
193 
194 component DAQLINK_7S
195 generic
196 (
197  -- Simulation attributes
198  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to 1 to speed up sim reset
199  -- REFCLK frequency, select one among 100, 125, 200 and 250 If your REFCLK frequency is not in the list, please contact wusx@bu.edu
200  F_REFCLK : integer := 100
201 
202 );
203 port
204 (
205 
206  --_________________________________________________________________________
207  --_________________________________________________________________________
208  --GT0 (X1Y0)
209  --____________________________CHANNEL PORTS________________________________
210  --------------------------------- CPLL Ports -------------------------------
211  GT0_CPLLFBCLKLOST_OUT : out std_logic;
212  GT0_CPLLLOCK_OUT : out std_logic;
213  GT0_CPLLLOCKDETCLK_IN : in std_logic;
214  GT0_CPLLREFCLKLOST_OUT : out std_logic;
215  GT0_CPLLRESET_IN : in std_logic;
216  -------------------------- Channel - Clocking Ports ------------------------
217  GT0_GTREFCLK0_IN : in std_logic;
218  ---------------------------- Channel - DRP Ports --------------------------
219  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
220  GT0_DRPCLK_IN : in std_logic;
221  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
222  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
223  GT0_DRPEN_IN : in std_logic;
224  GT0_DRPRDY_OUT : out std_logic;
225  GT0_DRPWE_IN : in std_logic;
226  ------------------------------- Loopback Ports -----------------------------
227  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
228  --------------------- RX Initialization and Reset Ports --------------------
229  GT0_RXUSERRDY_IN : in std_logic;
230  -------------------------- RX Margin Analysis Ports ------------------------
231  GT0_EYESCANDATAERROR_OUT : out std_logic;
232  ------------------------- Receive Ports - CDR Ports ------------------------
233  GT0_RXCDRLOCK_OUT : out std_logic;
234  ------------------- Receive Ports - Clock Correction Ports -----------------
235  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
236  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
237  GT0_RXUSRCLK_IN : in std_logic;
238  GT0_RXUSRCLK2_IN : in std_logic;
239  ------------------ Receive Ports - FPGA RX interface Ports -----------------
240  GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
241  ------------------- Receive Ports - Pattern Checker Ports ------------------
242  GT0_RXPRBSERR_OUT : out std_logic;
243  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
244  ------------------- Receive Ports - Pattern Checker ports ------------------
245  GT0_RXPRBSCNTRESET_IN : in std_logic;
246  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
247  GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
248  GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
249  --------------------------- Receive Ports - RX AFE -------------------------
250  GT0_GTXRXP_IN : in std_logic;
251  ------------------------ Receive Ports - RX AFE Ports ----------------------
252  GT0_GTXRXN_IN : in std_logic;
253  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
254  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
255  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
256  -------------------- Receive Ports - RX Equailizer Ports -------------------
257  GT0_RXLPMHFHOLD_IN : in std_logic;
258  GT0_RXLPMLFHOLD_IN : in std_logic;
259  --------------- Receive Ports - RX Fabric Output Control Ports -------------
260  GT0_RXOUTCLK_OUT : out std_logic;
261  ------------- Receive Ports - RX Initialization and Reset Ports ------------
262  GT0_GTRXRESET_IN : in std_logic;
263  GT0_RXPMARESET_IN : in std_logic;
264  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
265  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
266  GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
267  -------------- Receive Ports -RX Initialization and Reset Ports ------------
268  GT0_RXRESETDONE_OUT : out std_logic;
269  --------------------- TX Initialization and Reset Ports --------------------
270  GT0_GTTXRESET_IN : in std_logic;
271  GT0_TXUSERRDY_IN : in std_logic;
272  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
273  GT0_TXUSRCLK_IN : in std_logic;
274  GT0_TXUSRCLK2_IN : in std_logic;
275  --------------- Transmit Ports - TX Configurable Driver Ports --------------
276  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
277  ------------------ Transmit Ports - TX Data Path interface -----------------
278  GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
279  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
280  GT0_GTXTXN_OUT : out std_logic;
281  GT0_GTXTXP_OUT : out std_logic;
282  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
283  GT0_TXOUTCLK_OUT : out std_logic;
284  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
285  GT0_TXOUTCLKPCS_OUT : out std_logic;
286  --------------------- Transmit Ports - TX Gearbox Ports --------------------
287  GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
288  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
289  GT0_TXRESETDONE_OUT : out std_logic;
290  ------------------ Transmit Ports - pattern Generator Ports ----------------
291  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
292 
293 
294  --____________________________COMMON PORTS________________________________
295  ---------------------- Common Block - Ref Clock Ports ---------------------
296  GT0_GTREFCLK0_COMMON_IN : in std_logic;
297  ------------------------- Common Block - QPLL Ports ------------------------
298  GT0_QPLLLOCK_OUT : out std_logic;
299  GT0_QPLLLOCKDETCLK_IN : in std_logic;
300  GT0_QPLLREFCLKLOST_OUT : out std_logic;
301  GT0_QPLLRESET_IN : in std_logic
302 
303 
304 );
305 end component;
306 
307 component DAQLINK_7S_TX_STARTUP_FSM
308  Generic(
309  GT_TYPE : string := "GTX";
310  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
311  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
312  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
313  RX_QPLL_USED : boolean := False; -- share these two generic values
314  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
315  -- is enough. For single-lane applications the automatic alignment is
316  -- sufficient
317  );
318  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
319  --or reference-clock present at startup.
320  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
321  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
322  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
323  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
324  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
325  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
326  TXRESETDONE : in STD_LOGIC;
327  MMCM_LOCK : in STD_LOGIC;
328  GTTXRESET : out STD_LOGIC:='0';
329  MMCM_RESET : out STD_LOGIC:='0';
330  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
331  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
332  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
333  TXUSERRDY : out STD_LOGIC:='0';
334  RUN_PHALIGNMENT : out STD_LOGIC:='0';
335  RESET_PHALIGNMENT : out STD_LOGIC:='0';
336  PHALIGNMENT_DONE : in STD_LOGIC;
337 
338  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
339  -- Retries it took to get the transceiver up and running
340  );
341 end component;
342 
343 component DAQLINK_7S_RX_STARTUP_FSM
344  Generic(
345  EXAMPLE_SIMULATION : integer := 0;
346  EQ_MODE : string := "DFE";
347  GT_TYPE : string := "GTX";
348  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
349  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
350  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
351  RX_QPLL_USED : boolean := False; -- share these two generic values
352  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
353  -- is enough. For single-lane applications the automatic alignment is
354  -- sufficient
355  );
356  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
357  --or reference-clock present at startup.
358  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
359  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
360  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
361  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
362  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
363  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
364  RXRESETDONE : in STD_LOGIC;
365  MMCM_LOCK : in STD_LOGIC;
366  RECCLK_STABLE : in STD_LOGIC;
367  RECCLK_MONITOR_RESTART : in STD_LOGIC;
368  DATA_VALID : in STD_LOGIC;
369  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
370  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
371  GTRXRESET : out STD_LOGIC:='0';
372  MMCM_RESET : out STD_LOGIC:='0';
373  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
374  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
375  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
376  RXUSERRDY : out STD_LOGIC:='0';
377  RUN_PHALIGNMENT : out STD_LOGIC;
378  PHALIGNMENT_DONE : in STD_LOGIC;
379  RESET_PHALIGNMENT : out STD_LOGIC:='0';
380  RXDFEAGCHOLD : out STD_LOGIC;
381  RXDFELFHOLD : out STD_LOGIC;
382  RXLPMLFHOLD : out STD_LOGIC;
383  RXLPMHFHOLD : out STD_LOGIC;
384  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
385  -- Retries it took to get the transceiver up and running
386  );
387 end component;
388 
389 
390 
391 
392 
393 
394  function get_cdrlock_time(is_sim : in integer) return integer is
395  variable lock_time: integer;
396  begin
397  if (is_sim = 1) then
398  lock_time := 1000;
399  else
400  lock_time := 50000 / integer(5); --Typical CDR lock time is 50,000UI as per DS183
401  end if;
402  return lock_time;
403  end function;
404 
405 
406 --***********************************Parameter Declarations********************
407 
408  constant DLY : time := 1 ns;
409  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
410  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
411 
412  -------------------------- GT Wrapper Wires ------------------------------
413  signal gt0_cpllreset_i : std_logic;
414  signal gt0_cpllreset_t : std_logic;
415  signal gt0_cpllrefclklost_i : std_logic;
416  signal gt0_cplllock_i : std_logic;
417  signal gt0_txresetdone_i : std_logic;
418  signal gt0_rxresetdone_i : std_logic;
419  signal gt0_gttxreset_i : std_logic;
420  signal gt0_gttxreset_t : std_logic;
421  signal gt0_gtrxreset_i : std_logic;
422  signal gt0_gtrxreset_t : std_logic;
423  signal gt0_rxdfelpmreset_i : std_logic;
424  signal gt0_txuserrdy_i : std_logic;
425  signal gt0_txuserrdy_t : std_logic;
426  signal gt0_rxuserrdy_i : std_logic;
427  signal gt0_rxuserrdy_t : std_logic;
428 
429  signal gt0_rxdfeagchold_i : std_logic;
430  signal gt0_rxdfelfhold_i : std_logic;
431  signal gt0_rxlpmlfhold_i : std_logic;
432  signal gt0_rxlpmhfhold_i : std_logic;
433 
434 
435 
436  signal gt0_qpllreset_i : std_logic;
437  signal gt0_qpllreset_t : std_logic;
438  signal gt0_qpllrefclklost_i : std_logic;
439  signal gt0_qplllock_i : std_logic;
440 
441 
442  ------------------------------- Global Signals -----------------------------
443  signal tied_to_ground_i : std_logic;
444  signal tied_to_vcc_i : std_logic;
445 
446  signal gt0_rxoutclk_i : std_logic;
447  signal gt0_recclk_stable_i : std_logic;
448 
449 
450 
451 
452 
453 
454  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
455  signal rx_cdrlocked : std_logic;
456 
457 
458 
459 
460 
461 --**************************** Main Body of Code *******************************
462 begin
463  -- Static signal Assigments
464  tied_to_ground_i <= '0';
465  tied_to_vcc_i <= '1';
466 
467  ----------------------------- The GT Wrapper -----------------------------
468 
469  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
470  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
471  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
472  -- enabled, bonding should occur after alignment.
473 
474 
475  DAQLINK_7S_i : DAQLINK_7S
476  generic map
477  (
478  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
479  F_REFCLK => F_REFCLK
480  )
481  port map
482  (
483 
484  --_____________________________________________________________________
485  --_____________________________________________________________________
486  --GT0 (X1Y0)
487 
488  --------------------------------- CPLL Ports -------------------------------
489  GT0_CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT ,
490  GT0_CPLLLOCK_OUT => gt0_cplllock_i,
491  GT0_CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN ,
492  GT0_CPLLREFCLKLOST_OUT => gt0_cpllrefclklost_i ,
493  GT0_CPLLRESET_IN => gt0_cpllreset_i,
494  -------------------------- Channel - Clocking Ports ------------------------
495  GT0_GTREFCLK0_IN => GT0_GTREFCLK0_IN,
496  ---------------------------- Channel - DRP Ports --------------------------
497  GT0_DRPADDR_IN => GT0_DRPADDR_IN,
498  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
499  GT0_DRPDI_IN => GT0_DRPDI_IN,
500  GT0_DRPDO_OUT => GT0_DRPDO_OUT,
501  GT0_DRPEN_IN => GT0_DRPEN_IN,
502  GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
503  GT0_DRPWE_IN => GT0_DRPWE_IN,
504  ------------------------------- Loopback Ports -----------------------------
505  GT0_LOOPBACK_IN => GT0_LOOPBACK_IN,
506  --------------------- RX Initialization and Reset Ports --------------------
507  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
508  -------------------------- RX Margin Analysis Ports ------------------------
509  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
510  ------------------------- Receive Ports - CDR Ports ------------------------
511  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
512  ------------------- Receive Ports - Clock Correction Ports -----------------
513  GT0_RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT ,
514  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
515  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
516  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
517  ------------------ Receive Ports - FPGA RX interface Ports -----------------
518  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
519  ------------------- Receive Ports - Pattern Checker Ports ------------------
520  GT0_RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
521  GT0_RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
522  ------------------- Receive Ports - Pattern Checker ports ------------------
523  GT0_RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
524  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
525  GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT,
526  GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
527  --------------------------- Receive Ports - RX AFE -------------------------
528  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
529  ------------------------ Receive Ports - RX AFE Ports ----------------------
530  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
531  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
532  GT0_RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
533  GT0_RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
534  -------------------- Receive Ports - RX Equailizer Ports -------------------
535  GT0_RXLPMHFHOLD_IN => gt0_rxlpmhfhold_i,
536  GT0_RXLPMLFHOLD_IN => gt0_rxlpmlfhold_i,
537  --------------- Receive Ports - RX Fabric Output Control Ports -------------
538  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
539  ------------- Receive Ports - RX Initialization and Reset Ports ------------
540  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
541  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
542  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
543  GT0_RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT ,
544  GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT,
545  -------------- Receive Ports -RX Initialization and Reset Ports ------------
546  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
547  --------------------- TX Initialization and Reset Ports --------------------
548  GT0_GTTXRESET_IN => gt0_gttxreset_i,
549  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
550  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
551  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
552  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
553  --------------- Transmit Ports - TX Configurable Driver Ports --------------
554  GT0_TXDIFFCTRL_IN => GT0_TXDIFFCTRL_IN,
555  ------------------ Transmit Ports - TX Data Path interface -----------------
556  GT0_TXDATA_IN => GT0_TXDATA_IN,
557  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
558  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
559  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
560  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
561  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
562  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
563  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
564  --------------------- Transmit Ports - TX Gearbox Ports --------------------
565  GT0_TXCHARISK_IN => GT0_TXCHARISK_IN,
566  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
567  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
568  ------------------ Transmit Ports - pattern Generator Ports ----------------
569  GT0_TXPRBSSEL_IN => GT0_TXPRBSSEL_IN,
570 
571 
572 
573 
574  --____________________________COMMON PORTS________________________________
575  ---------------------- Common Block - Ref Clock Ports ---------------------
576  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
577  ------------------------- Common Block - QPLL Ports ------------------------
578  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
579  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
580  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
581  GT0_QPLLRESET_IN => gt0_qpllreset_i
582 
583  );
584 
585 
586  gt0_rxdfelpmreset_i <= tied_to_ground_i;
587 
588 
589 
590 
591  GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
592  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
593  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
594  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
595 
596 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
597  gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
598  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
599  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
600  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
601  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
602  gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
603 end generate chipscope;
604 
605 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
606  gt0_cpllreset_i <= gt0_cpllreset_t;
607  gt0_gttxreset_i <= gt0_gttxreset_t;
608  gt0_gtrxreset_i <= gt0_gtrxreset_t;
609  gt0_txuserrdy_i <= gt0_txuserrdy_t;
610  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
611  gt0_qpllreset_i <= gt0_qpllreset_t;
612 end generate no_chipscope;
613 
614 
615 gt0_txresetfsm_i: DAQLINK_7S_TX_STARTUP_FSM
616 
617  generic map(
618  GT_TYPE => "GTX", --GTX or GTH or GTP
619  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
620  RETRY_COUNTER_BITWIDTH => 8,
621  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
622  RX_QPLL_USED => FALSE, -- share these two generic values
623  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
624  -- is enough. For single-lane applications the automatic alignment is
625  -- sufficient
626  )
627  port map (
628  STABLE_CLOCK => SYSCLK_IN,
629  TXUSERCLK => GT0_TXUSRCLK_IN,
630  SOFT_RESET => SOFT_RESET_IN,
631  QPLLREFCLKLOST => tied_to_ground_i,
632  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
633  QPLLLOCK => tied_to_vcc_i,
634  CPLLLOCK => gt0_cplllock_i,
635  TXRESETDONE => gt0_txresetdone_i,
636  MMCM_LOCK => tied_to_vcc_i,
637  GTTXRESET => gt0_gttxreset_t,
638  MMCM_RESET => open,
639  QPLL_RESET => open,
640  CPLL_RESET => gt0_cpllreset_t,
641  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT ,
642  TXUSERRDY => gt0_txuserrdy_t,
643  RUN_PHALIGNMENT => open,
644  RESET_PHALIGNMENT => open,
645  PHALIGNMENT_DONE => tied_to_vcc_i,
646  RETRY_COUNTER => open
647  );
648 
649 
650 
651 
652 
653 
654 gt0_rxresetfsm_i: DAQLINK_7S_RX_STARTUP_FSM
655 
656  generic map(
657  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
658  GT_TYPE => "GTX", --GTX or GTH or GTP
659  EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM
660  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
661  RETRY_COUNTER_BITWIDTH => 8,
662  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
663  RX_QPLL_USED => FALSE, -- share these two generic values
664  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
665  -- is enough. For single-lane applications the automatic alignment is
666  -- sufficient
667  )
668  port map (
669  STABLE_CLOCK => SYSCLK_IN,
670  RXUSERCLK => GT0_RXUSRCLK_IN,
671  SOFT_RESET => SOFT_RESET_IN,
672  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
673  QPLLREFCLKLOST => tied_to_ground_i,
674  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
675  QPLLLOCK => tied_to_vcc_i,
676  CPLLLOCK => gt0_cplllock_i,
677  RXRESETDONE => gt0_rxresetdone_i,
678  MMCM_LOCK => tied_to_vcc_i,
679  RECCLK_STABLE => gt0_recclk_stable_i ,
680  RECCLK_MONITOR_RESTART => tied_to_ground_i,
681  DATA_VALID => GT0_DATA_VALID_IN,
682  TXUSERRDY => gt0_txuserrdy_i,
683  GTRXRESET => gt0_gtrxreset_t,
684  MMCM_RESET => open,
685  QPLL_RESET => open,
686  CPLL_RESET => open,
687  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT ,
688  RXUSERRDY => gt0_rxuserrdy_t,
689  RUN_PHALIGNMENT => open,
690  RESET_PHALIGNMENT => open,
691  PHALIGNMENT_DONE => tied_to_vcc_i,
692  RXDFEAGCHOLD => gt0_rxdfeagchold_i ,
693  RXDFELFHOLD => gt0_rxdfelfhold_i,
694  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
695  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
696  RETRY_COUNTER => open
697  );
698 
699 
700 
701  cdrlock_timeout:process(SYSCLK_IN)
702  begin
703  if rising_edge(SYSCLK_IN) then
704  if(gt0_gtrxreset_i = '1') then
705  rx_cdrlocked <= '0';
706  rx_cdrlock_counter <= 0 after DLY;
707  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
708  rx_cdrlocked <= '1';
709  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
710  else
711  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
712  end if;
713  end if;
714  end process;
715 
716 gt0_recclk_stable_i <= rx_cdrlocked;
717 
718 
719 
720 
721 
722 
723 
724 end RTL;
725 
726 
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