AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
daqlink_7s.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : daqlink_7s.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module DAQLINK_7S (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity DAQLINK_7S is
74 generic
75 (
76  QPLL_FBDIV_TOP : integer := 16;
77 
78  -- Simulation attributes
79  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
81  PMA_RSV_IN : bit_vector := x"00018480";
82  -- REFCLK frequency, select one among 100, 125, 200 and 250 If your REFCLK frequency is not in the list, please contact wusx@bu.edu
83  F_REFCLK : integer := 100
84 
85 );
86 port
87 (
88  --_________________________________________________________________________
89  --_________________________________________________________________________
90  --GT0 (X0Y0)
91  --____________________________CHANNEL PORTS________________________________
92  --------------------------------- CPLL Ports -------------------------------
93  GT0_CPLLFBCLKLOST_OUT : out std_logic;
94  GT0_CPLLLOCK_OUT : out std_logic;
95  GT0_CPLLLOCKDETCLK_IN : in std_logic;
96  GT0_CPLLREFCLKLOST_OUT : out std_logic;
97  GT0_CPLLRESET_IN : in std_logic;
98  -------------------------- Channel - Clocking Ports ------------------------
99  GT0_GTREFCLK0_IN : in std_logic;
100  ---------------------------- Channel - DRP Ports --------------------------
101  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
102  GT0_DRPCLK_IN : in std_logic;
103  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
104  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
105  GT0_DRPEN_IN : in std_logic;
106  GT0_DRPRDY_OUT : out std_logic;
107  GT0_DRPWE_IN : in std_logic;
108  ------------------------------- Loopback Ports -----------------------------
109  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
110  --------------------- RX Initialization and Reset Ports --------------------
111  GT0_RXUSERRDY_IN : in std_logic;
112  -------------------------- RX Margin Analysis Ports ------------------------
113  GT0_EYESCANDATAERROR_OUT : out std_logic;
114  ------------------------- Receive Ports - CDR Ports ------------------------
115  GT0_RXCDRLOCK_OUT : out std_logic;
116  ------------------- Receive Ports - Clock Correction Ports -----------------
117  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
118  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
119  GT0_RXUSRCLK_IN : in std_logic;
120  GT0_RXUSRCLK2_IN : in std_logic;
121  ------------------ Receive Ports - FPGA RX interface Ports -----------------
122  GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
123  ------------------- Receive Ports - Pattern Checker Ports ------------------
124  GT0_RXPRBSERR_OUT : out std_logic;
125  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
126  ------------------- Receive Ports - Pattern Checker ports ------------------
127  GT0_RXPRBSCNTRESET_IN : in std_logic;
128  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
129  GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
130  GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
131  --------------------------- Receive Ports - RX AFE -------------------------
132  GT0_GTXRXP_IN : in std_logic;
133  ------------------------ Receive Ports - RX AFE Ports ----------------------
134  GT0_GTXRXN_IN : in std_logic;
135  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
136  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
137  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
138  -------------------- Receive Ports - RX Equailizer Ports -------------------
139  GT0_RXLPMHFHOLD_IN : in std_logic;
140  GT0_RXLPMLFHOLD_IN : in std_logic;
141  --------------- Receive Ports - RX Fabric Output Control Ports -------------
142  GT0_RXOUTCLK_OUT : out std_logic;
143  ------------- Receive Ports - RX Initialization and Reset Ports ------------
144  GT0_GTRXRESET_IN : in std_logic;
145  GT0_RXPMARESET_IN : in std_logic;
146  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
147  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
148  GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
149  -------------- Receive Ports -RX Initialization and Reset Ports ------------
150  GT0_RXRESETDONE_OUT : out std_logic;
151  --------------------- TX Initialization and Reset Ports --------------------
152  GT0_GTTXRESET_IN : in std_logic;
153  GT0_TXUSERRDY_IN : in std_logic;
154  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
155  GT0_TXUSRCLK_IN : in std_logic;
156  GT0_TXUSRCLK2_IN : in std_logic;
157  --------------- Transmit Ports - TX Configurable Driver Ports --------------
158  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
159  ------------------ Transmit Ports - TX Data Path interface -----------------
160  GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
161  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
162  GT0_GTXTXN_OUT : out std_logic;
163  GT0_GTXTXP_OUT : out std_logic;
164  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
165  GT0_TXOUTCLK_OUT : out std_logic;
166  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
167  GT0_TXOUTCLKPCS_OUT : out std_logic;
168  --------------------- Transmit Ports - TX Gearbox Ports --------------------
169  GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
170  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
171  GT0_TXRESETDONE_OUT : out std_logic;
172  ------------------ Transmit Ports - pattern Generator Ports ----------------
173  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
174 
175 
176  --____________________________COMMON PORTS________________________________
177  ---------------------- Common Block - Ref Clock Ports ---------------------
178  GT0_GTREFCLK0_COMMON_IN : in std_logic;
179  ------------------------- Common Block - QPLL Ports ------------------------
180  GT0_QPLLLOCK_OUT : out std_logic;
181  GT0_QPLLLOCKDETCLK_IN : in std_logic;
182  GT0_QPLLREFCLKLOST_OUT : out std_logic;
183  GT0_QPLLRESET_IN : in std_logic
184 
185 
186 );
187 
188 
189 end DAQLINK_7S;
190 
191 architecture RTL of DAQLINK_7S is
192 
193  attribute CORE_GENERATION_INFO : string;
194  attribute CORE_GENERATION_INFO of RTL : architecture is "DAQLINK_7S,gtwizard_v2_7,{protocol_file=Start_from_scratch}";
195 
196 
197 --***********************************Parameter Declarations********************
198 
199  constant DLY : time := 1 ns;
200 
201 --***************************** Signal Declarations *****************************
202 
203  -- ground and tied_to_vcc_i signals
204  signal tied_to_ground_i : std_logic;
205  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
206  signal tied_to_vcc_i : std_logic;
207  signal gt0_qplloutclk_i : std_logic;
208  signal gt0_qplloutrefclk_i : std_logic;
209 
210 
211  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
212  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
213 
214 
215  signal gt0_qpllclk_i : std_logic;
216  signal gt0_qpllrefclk_i : std_logic;
217 
218 
219 --*************************** Component Declarations **************************
220 component DAQLINK_7S_GT
221 generic
222 (
223  -- Simulation attributes
224  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
225  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
226  PMA_RSV_IN : bit_vector := X"00000000";
227  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000";
228  -- REFCLK frequency, select one among 100, 125, 200 and 250 If your REFCLK frequency is not in the list, please contact wusx@bu.edu
229  F_REFCLK : integer := 100
230 );
231 port
232 (
233  --------------------------------- CPLL Ports -------------------------------
234  CPLLFBCLKLOST_OUT : out std_logic;
235  CPLLLOCK_OUT : out std_logic;
236  CPLLLOCKDETCLK_IN : in std_logic;
237  CPLLREFCLKLOST_OUT : out std_logic;
238  CPLLRESET_IN : in std_logic;
239  -------------------------- Channel - Clocking Ports ------------------------
240  GTREFCLK0_IN : in std_logic;
241  ---------------------------- Channel - DRP Ports --------------------------
242  DRPADDR_IN : in std_logic_vector(8 downto 0);
243  DRPCLK_IN : in std_logic;
244  DRPDI_IN : in std_logic_vector(15 downto 0);
245  DRPDO_OUT : out std_logic_vector(15 downto 0);
246  DRPEN_IN : in std_logic;
247  DRPRDY_OUT : out std_logic;
248  DRPWE_IN : in std_logic;
249  ------------------------------- Clocking Ports -----------------------------
250  QPLLCLK_IN : in std_logic;
251  QPLLREFCLK_IN : in std_logic;
252  ------------------------------- Loopback Ports -----------------------------
253  LOOPBACK_IN : in std_logic_vector(2 downto 0);
254  --------------------- RX Initialization and Reset Ports --------------------
255  RXUSERRDY_IN : in std_logic;
256  -------------------------- RX Margin Analysis Ports ------------------------
257  EYESCANDATAERROR_OUT : out std_logic;
258  ------------------------- Receive Ports - CDR Ports ------------------------
259  RXCDRLOCK_OUT : out std_logic;
260  ------------------- Receive Ports - Clock Correction Ports -----------------
261  RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
262  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
263  RXUSRCLK_IN : in std_logic;
264  RXUSRCLK2_IN : in std_logic;
265  ------------------ Receive Ports - FPGA RX interface Ports -----------------
266  RXDATA_OUT : out std_logic_vector(15 downto 0);
267  ------------------- Receive Ports - Pattern Checker Ports ------------------
268  RXPRBSERR_OUT : out std_logic;
269  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
270  ------------------- Receive Ports - Pattern Checker ports ------------------
271  RXPRBSCNTRESET_IN : in std_logic;
272  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
273  RXDISPERR_OUT : out std_logic_vector(1 downto 0);
274  RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
275  --------------------------- Receive Ports - RX AFE -------------------------
276  GTXRXP_IN : in std_logic;
277  ------------------------ Receive Ports - RX AFE Ports ----------------------
278  GTXRXN_IN : in std_logic;
279  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
280  RXMCOMMAALIGNEN_IN : in std_logic;
281  RXPCOMMAALIGNEN_IN : in std_logic;
282  -------------------- Receive Ports - RX Equailizer Ports -------------------
283  RXLPMHFHOLD_IN : in std_logic;
284  RXLPMLFHOLD_IN : in std_logic;
285  --------------- Receive Ports - RX Fabric Output Control Ports -------------
286  RXOUTCLK_OUT : out std_logic;
287  ------------- Receive Ports - RX Initialization and Reset Ports ------------
288  GTRXRESET_IN : in std_logic;
289  RXPMARESET_IN : in std_logic;
290  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
291  RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
292  RXCHARISK_OUT : out std_logic_vector(1 downto 0);
293  -------------- Receive Ports -RX Initialization and Reset Ports ------------
294  RXRESETDONE_OUT : out std_logic;
295  --------------------- TX Initialization and Reset Ports --------------------
296  GTTXRESET_IN : in std_logic;
297  TXUSERRDY_IN : in std_logic;
298  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
299  TXUSRCLK_IN : in std_logic;
300  TXUSRCLK2_IN : in std_logic;
301  --------------- Transmit Ports - TX Configurable Driver Ports --------------
302  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
303  ------------------ Transmit Ports - TX Data Path interface -----------------
304  TXDATA_IN : in std_logic_vector(15 downto 0);
305  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
306  GTXTXN_OUT : out std_logic;
307  GTXTXP_OUT : out std_logic;
308  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
309  TXOUTCLK_OUT : out std_logic;
310  TXOUTCLKFABRIC_OUT : out std_logic;
311  TXOUTCLKPCS_OUT : out std_logic;
312  --------------------- Transmit Ports - TX Gearbox Ports --------------------
313  TXCHARISK_IN : in std_logic_vector(1 downto 0);
314  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
315  TXRESETDONE_OUT : out std_logic;
316  ------------------ Transmit Ports - pattern Generator Ports ----------------
317  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
318 
319 
320 );
321 end component;
322 
323 
324 
325 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
326  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
327  begin
328  if (qpllfbdiv_top = 16) then
329  return "0000100000";
330  elsif (qpllfbdiv_top = 20) then
331  return "0000110000" ;
332  elsif (qpllfbdiv_top = 32) then
333  return "0001100000" ;
334  elsif (qpllfbdiv_top = 40) then
335  return "0010000000" ;
336  elsif (qpllfbdiv_top = 64) then
337  return "0011100000" ;
338  elsif (qpllfbdiv_top = 66) then
339  return "0101000000" ;
340  elsif (qpllfbdiv_top = 80) then
341  return "0100100000" ;
342  elsif (qpllfbdiv_top = 100) then
343  return "0101110000" ;
344  else
345  return "0000000000" ;
346  end if;
347  end function;
348 
349  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
350  begin
351  if (qpllfbdiv_top = 16) then
352  return '1';
353  elsif (qpllfbdiv_top = 20) then
354  return '1' ;
355  elsif (qpllfbdiv_top = 32) then
356  return '1' ;
357  elsif (qpllfbdiv_top = 40) then
358  return '1' ;
359  elsif (qpllfbdiv_top = 64) then
360  return '1' ;
361  elsif (qpllfbdiv_top = 66) then
362  return '0' ;
363  elsif (qpllfbdiv_top = 80) then
364  return '1' ;
365  elsif (qpllfbdiv_top = 100) then
366  return '1' ;
367  else
368  return '1' ;
369  end if;
370  end function;
371 
372  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
373  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
374 
375 --********************************* Main Body of Code**************************
376 
377 begin
378 
379  tied_to_ground_i <= '0';
380  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
381  tied_to_vcc_i <= '1';
382 -- gt0_qpllclk_i <= gt0_qplloutclk_i;
383 -- gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
384  gt0_qpllclk_i <= '0';
385  gt0_qpllrefclk_i <= '0';
386 
387 
388 
389  --------------------------- GT Instances -------------------------------
390 
391  --_________________________________________________________________________
392  --_________________________________________________________________________
393  --GT0 (X0Y0)
394 
395  gt0_DAQLINK_7S_i : DAQLINK_7S_GT
396  generic map
397  (
398  -- Simulation attributes
399  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
400  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
401  PMA_RSV_IN => PMA_RSV_IN,
402  PCS_RSVD_ATTR_IN => X"000000000000",
403  -- REFCLK frequency, select one among 100, 125, 200 and 250 If your REFCLK frequency is not in the list, please contact wusx@bu.edu
404  F_REFCLK => F_REFCLK
405  )
406  port map
407  (
408  --------------------------------- CPLL Ports -------------------------------
409  CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT ,
410  CPLLLOCK_OUT => GT0_CPLLLOCK_OUT,
411  CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN ,
412  CPLLREFCLKLOST_OUT => GT0_CPLLREFCLKLOST_OUT ,
413  CPLLRESET_IN => GT0_CPLLRESET_IN,
414  -------------------------- Channel - Clocking Ports ------------------------
415  GTREFCLK0_IN => GT0_GTREFCLK0_IN,
416  ---------------------------- Channel - DRP Ports --------------------------
417  DRPADDR_IN => GT0_DRPADDR_IN,
418  DRPCLK_IN => GT0_DRPCLK_IN,
419  DRPDI_IN => GT0_DRPDI_IN,
420  DRPDO_OUT => GT0_DRPDO_OUT,
421  DRPEN_IN => GT0_DRPEN_IN,
422  DRPRDY_OUT => GT0_DRPRDY_OUT,
423  DRPWE_IN => GT0_DRPWE_IN,
424  ------------------------------- Clocking Ports -----------------------------
425  QPLLCLK_IN => gt0_qpllclk_i,
426  QPLLREFCLK_IN => gt0_qpllrefclk_i,
427  ------------------------------- Loopback Ports -----------------------------
428  LOOPBACK_IN => GT0_LOOPBACK_IN,
429  --------------------- RX Initialization and Reset Ports --------------------
430  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
431  -------------------------- RX Margin Analysis Ports ------------------------
432  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
433  ------------------------- Receive Ports - CDR Ports ------------------------
434  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
435  ------------------- Receive Ports - Clock Correction Ports -----------------
436  RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT ,
437  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
438  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
439  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
440  ------------------ Receive Ports - FPGA RX interface Ports -----------------
441  RXDATA_OUT => GT0_RXDATA_OUT,
442  ------------------- Receive Ports - Pattern Checker Ports ------------------
443  RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
444  RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
445  ------------------- Receive Ports - Pattern Checker ports ------------------
446  RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
447  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
448  RXDISPERR_OUT => GT0_RXDISPERR_OUT,
449  RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
450  --------------------------- Receive Ports - RX AFE -------------------------
451  GTXRXP_IN => GT0_GTXRXP_IN,
452  ------------------------ Receive Ports - RX AFE Ports ----------------------
453  GTXRXN_IN => GT0_GTXRXN_IN,
454  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
455  RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
456  RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
457  -------------------- Receive Ports - RX Equailizer Ports -------------------
458  RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN,
459  RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN,
460  --------------- Receive Ports - RX Fabric Output Control Ports -------------
461  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
462  ------------- Receive Ports - RX Initialization and Reset Ports ------------
463  GTRXRESET_IN => GT0_GTRXRESET_IN,
464  RXPMARESET_IN => GT0_RXPMARESET_IN,
465  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
466  RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT ,
467  RXCHARISK_OUT => GT0_RXCHARISK_OUT,
468  -------------- Receive Ports -RX Initialization and Reset Ports ------------
469  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
470  --------------------- TX Initialization and Reset Ports --------------------
471  GTTXRESET_IN => GT0_GTTXRESET_IN,
472  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
473  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
474  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
475  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
476  --------------- Transmit Ports - TX Configurable Driver Ports --------------
477  TXDIFFCTRL_IN => GT0_TXDIFFCTRL_IN,
478  ------------------ Transmit Ports - TX Data Path interface -----------------
479  TXDATA_IN => GT0_TXDATA_IN,
480  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
481  GTXTXN_OUT => GT0_GTXTXN_OUT,
482  GTXTXP_OUT => GT0_GTXTXP_OUT,
483  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
484  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
485  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
486  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
487  --------------------- Transmit Ports - TX Gearbox Ports --------------------
488  TXCHARISK_IN => GT0_TXCHARISK_IN,
489  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
490  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT ,
491  ------------------ Transmit Ports - pattern Generator Ports ----------------
492  TXPRBSSEL_IN => GT0_TXPRBSSEL_IN
493 
494  );
495 
496  --_________________________________________________________________________
497  --_________________________________________________________________________
498  --_________________________GTXE2_COMMON____________________________________
499 
500 -- gtxe2_common_0_i : GTXE2_COMMON
501 -- generic map
502 -- (
503 -- -- Simulation attributes
504 -- SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
505 -- SIM_QPLLREFCLK_SEL => ("001"),
506 -- SIM_VERSION => "4.0",
507 --
508 --
509 -- ------------------COMMON BLOCK Attributes---------------
510 -- BIAS_CFG => (x"0000040000001000"),
511 -- COMMON_CFG => (x"00000000"),
512 -- QPLL_CFG => (x"06801C1"),
513 -- QPLL_CLKOUT_CFG => ("0000"),
514 -- QPLL_COARSE_FREQ_OVRD => ("010000"),
515 -- QPLL_COARSE_FREQ_OVRD_EN => ('0'),
516 -- QPLL_CP => ("0000011111"),
517 -- QPLL_CP_MONITOR_EN => ('0'),
518 -- QPLL_DMONITOR_SEL => ('0'),
519 -- QPLL_FBDIV => (QPLL_FBDIV_IN),
520 -- QPLL_FBDIV_MONITOR_EN => ('0'),
521 -- QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
522 -- QPLL_INIT_CFG => (x"000006"),
523 -- QPLL_LOCK_CFG => (x"21E8"),
524 -- QPLL_LPF => ("1111"),
525 -- QPLL_REFCLK_DIV => (1)
526 --
527 --
528 -- )
529 -- port map
530 -- (
531 -- ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
532 -- DRPADDR => tied_to_ground_vec_i(7 downto 0),
533 -- DRPCLK => tied_to_ground_i,
534 -- DRPDI => tied_to_ground_vec_i(15 downto 0),
535 -- DRPDO => open,
536 -- DRPEN => tied_to_ground_i,
537 -- DRPRDY => open,
538 -- DRPWE => tied_to_ground_i,
539 -- ---------------------- Common Block - Ref Clock Ports ---------------------
540 -- GTGREFCLK => tied_to_ground_i,
541 -- GTNORTHREFCLK0 => tied_to_ground_i,
542 -- GTNORTHREFCLK1 => tied_to_ground_i,
543 -- GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN,
544 -- GTREFCLK1 => tied_to_ground_i,
545 -- GTSOUTHREFCLK0 => tied_to_ground_i,
546 -- GTSOUTHREFCLK1 => tied_to_ground_i,
547 -- ------------------------- Common Block - QPLL Ports -----------------------
548 -- QPLLDMONITOR => open,
549 -- ----------------------- Common Block - Clocking Ports ----------------------
550 -- QPLLOUTCLK => gt0_qplloutclk_i,
551 -- QPLLOUTREFCLK => gt0_qplloutrefclk_i,
552 -- REFCLKOUTMONITOR => open,
553 -- ------------------------- Common Block - QPLL Ports ------------------------
554 -- QPLLFBCLKLOST => open,
555 -- QPLLLOCK => GT0_QPLLLOCK_OUT,
556 -- QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN,
557 -- QPLLLOCKEN => tied_to_vcc_i,
558 -- QPLLOUTRESET => tied_to_ground_i,
559 -- QPLLPD => tied_to_vcc_i,
560 -- QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT,
561 -- QPLLREFCLKSEL => "001",
562 -- QPLLRESET => GT0_QPLLRESET_IN,
563 -- QPLLRSVD1 => "0000000000000000",
564 -- QPLLRSVD2 => "11111",
565 -- --------------------------------- QPLL Ports -------------------------------
566 -- BGBYPASSB => tied_to_vcc_i,
567 -- BGMONITORENB => tied_to_vcc_i,
568 -- BGPDB => tied_to_vcc_i,
569 -- BGRCALOVRD => "00000",
570 -- PMARSVD => "00000000",
571 -- RCALENB => tied_to_vcc_i
572 --
573 -- );
574 
575 
576 
577 end RTL;
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