AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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amc_gtx5gpd_sync_block.vhd
1 --////////////////////////////////////////////////////////////////////////////////
2 --// ____ ____
3 --// / /\/ /
4 --// /___/ \ / Vendor: Xilinx
5 --// \ \ \/ Version : 3.6
6 --// \ \ Application : 7 Series FPGAs Transceivers Wizard
7 --// / / Filename : amc_gtx5gpd_sync_block.vhd
8 --// /___/ /\
9 --// \ \ / \
10 --// \___\/\___\
11 --//
12 --//
13 --
14 -- Description: Used on signals crossing from one clock domain to
15 -- another, this is a flip-flop pair, with both flops
16 -- placed together with RLOCs into the same slice. Thus
17 -- the routing delay between the two is minimum to safe-
18 -- guard against metastability issues.
19 --
20 --
21 -- Module amc_gtx5Gpd_sync_block
22 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
23 --
24 --
25 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
26 --
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70 
71 
72 
73 
74 
75 library ieee;
76 use ieee.std_logic_1164.all;
77 
78 library unisim;
79 use unisim.vcomponents.all;
80 
82  generic (
83  INITIALISE : bit_vector(5 downto 0) := "000000"
84  );
85  port (
86  clk : in std_logic; -- clock to be sync'ed to
87  data_in : in std_logic; -- Data to be 'synced'
88  data_out : out std_logic -- synced data
89  );
90 
91 -- attribute dont_touch : string;
92 -- attribute dont_touch of amc_gtx5Gpd_sync_block : entity is "yes";
93 
94 end amc_gtx5Gpd_sync_block;
95 
96 
97 architecture structural of amc_gtx5Gpd_sync_block is
98 
99 
100  -- Internal Signals
101  signal data_sync1 : std_logic;
102  signal data_sync2 : std_logic;
103  signal data_sync3 : std_logic;
104  signal data_sync4 : std_logic;
105  signal data_sync5 : std_logic;
106 
107  -- These attributes will stop timing errors being reported in back annotated
108  -- SDF simulation.
109  attribute ASYNC_REG : string;
110  attribute ASYNC_REG of data_sync_reg1 : label is "true";
111  attribute ASYNC_REG of data_sync_reg2 : label is "true";
112  attribute ASYNC_REG of data_sync_reg3 : label is "true";
113  attribute ASYNC_REG of data_sync_reg4 : label is "true";
114  attribute ASYNC_REG of data_sync_reg5 : label is "true";
115  attribute ASYNC_REG of data_sync_reg6 : label is "true";
116 
117  -- These attributes will stop XST translating the desired flip-flops into an
118  -- SRL based shift register.
119  attribute shreg_extract : string;
120  attribute shreg_extract of data_sync_reg1 : label is "no";
121  attribute shreg_extract of data_sync_reg2 : label is "no";
122  attribute shreg_extract of data_sync_reg3 : label is "no";
123  attribute shreg_extract of data_sync_reg4 : label is "no";
124  attribute shreg_extract of data_sync_reg5 : label is "no";
125  attribute shreg_extract of data_sync_reg6 : label is "no";
126 
127 
128 begin
129 
130  data_sync_reg1 : FD
131  generic map (
132  INIT => INITIALISE(0)
133  )
134  port map (
135  C => clk,
136  D => data_in,
137  Q => data_sync1
138  );
139 
140  data_sync_reg2 : FD
141  generic map (
142  INIT => INITIALISE(1)
143  )
144  port map (
145  C => clk,
146  D => data_sync1,
147  Q => data_sync2
148  );
149 
150  data_sync_reg3 : FD
151  generic map (
152  INIT => INITIALISE(2)
153  )
154  port map (
155  C => clk,
156  D => data_sync2,
157  Q => data_sync3
158  );
159 
160  data_sync_reg4 : FD
161  generic map (
162  INIT => INITIALISE(3)
163  )
164  port map (
165  C => clk,
166  D => data_sync3,
167  Q => data_sync4
168  );
169 
170  data_sync_reg5 : FD
171  generic map (
172  INIT => INITIALISE(4)
173  )
174  port map (
175  C => clk,
176  D => data_sync4,
177  Q => data_sync5
178  );
179 
180  data_sync_reg6 : FD
181  generic map (
182  INIT => INITIALISE(5)
183  )
184  port map (
185  C => clk,
186  D => data_sync5,
187  Q => data_out
188  );
189 
190 
191 
192 end structural;
193 
194