1 --////////////////////////////////////////////////////////////////////////////////
4 --// /___/ \ / Vendor: Xilinx
5 --// \ \ \/ Version : 3.
6
6 --// \ \ Application : 7 Series FPGAs Transceivers Wizard
7 --// / / Filename : amc_gtx5gpd_rx_startup_fsm.vhd
13 -- Description : This module performs RX reset and initialization.
17 -- Module amc_gtx5Gpd_rx_startup_fsm
18 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
21 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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68 --*****************************************************************************
71 use IEEE.STD_LOGIC_1164.
ALL;
72 use IEEE.NUMERIC_STD.
ALL;
74 use unisim.vcomponents.
all;
77 Generic( EXAMPLE_SIMULATION : := 0;
78 EQ_MODE : := "DFE";
--RX Equalisation Mode; set to DFE or LPM
79 STABLE_CLOCK_PERIOD : range 4 to 250 := 8;
--Period of the stable clock driving this state-machine, unit is [ns]
80 RETRY_COUNTER_BITWIDTH : range 2 to 8 := 8;
81 TX_QPLL_USED : := False;
-- the TX and RX Reset FSMs must
82 RX_QPLL_USED : := False;
-- share these two generic values
83 PHASE_ALIGNMENT_MANUAL : := True -- Decision if a manual phase-alignment is necessary or the automatic
84 -- is enough. For single-lane applications the automatic alignment is
87 Port ( STABLE_CLOCK : in ;
--Stable Clock, either a stable clock from the PCB
88 --or reference-clock present at startup.
89 RXUSERCLK : in ;
--RXUSERCLK as used in the design
90 SOFT_RESET : in ;
--User Reset, can be pulled any
92 QPLLREFCLKLOST : in ;
--QPLL Reference-clock for the GT is lost
93 CPLLREFCLKLOST : in ;
--CPLL Reference-clock for the GT is lost
94 QPLLLOCK : in ;
--Lock Detect from the QPLL of the GT
95 CPLLLOCK : in ;
--Lock Detect from the CPLL of the GT
99 RECCLK_MONITOR_RESTART : in :='0';
101 TXUSERRDY : in ;
--TXUSERRDY from GT
102 DONT_RESET_ON_DATA_ERROR : in ;
--Used to control the Auto-Reset of FSM when Data Error is detected
105 QPLL_RESET : out :='0';
--Reset QPLL (only if RX uses QPLL)
106 CPLL_RESET : out :='0';
--Reset CPLL (only if RX uses CPLL)
107 RX_FSM_RESET_DONE : out ;
--Reset-sequence has sucessfully been finished.
108 RXUSERRDY : out :='0';
109 RUN_PHALIGNMENT : out ;
110 PHALIGNMENT_DONE : in ;
111 RESET_PHALIGNMENT : out :='0';
116 RETRY_COUNTER : out (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
117 -- Retries it took to get the transceiver up and running
119 end amc_gtx5Gpd_RX_STARTUP_FSM;
122 -- * Timing depends on the frequency of the stable clock. Hence counters-sizes
123 -- are calculated at design-time based on the Generics
125 -- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
126 -- => signal which PLL has been reset
135 INITIALISE : (
5 downto 0) := "
000000"
143 type rx_rst_fsm_type is(
144 INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
145 RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
146 MONITOR_DATA_VALID, FSM_DONE);
148 signal rx_state : rx_rst_fsm_type := INIT;
150 constant MMCM_LOCK_CNT_MAX : := 256;
151 constant STARTUP_DELAY : := 500;
--AR43482: Transceiver needs to wait for 500 ns
after configuration
152 constant WAIT_CYCLES : := STARTUP_DELAY / STABLE_CLOCK_PERIOD;
-- Number of Clock-Cycles to wait after configuration
153 constant WAIT_MAX : := WAIT_CYCLES + 10;
-- 500 ns plus some additional margin
154 constant WAIT_TIMEOUT_2ms : := 2000000 / STABLE_CLOCK_PERIOD;
-- 2 ms time-out
155 constant WAIT_TLOCK_MAX : := 100000 / STABLE_CLOCK_PERIOD;
--100 us time-out
156 constant WAIT_TIMEOUT_500us : := 500000 / STABLE_CLOCK_PERIOD;
--500 us time-out
157 constant WAIT_TIMEOUT_1us : := 1000 / STABLE_CLOCK_PERIOD;
--1 us time-out
158 constant WAIT_TIMEOUT_100us : := 100000 / STABLE_CLOCK_PERIOD;
--100 us time-out
159 constant WAIT_TIME_ADAPT : := (37000000 /(5.
0))/STABLE_CLOCK_PERIOD;
160 constant WAIT_TIME_MAX : := 100 ;
--10 us time-out
162 signal init_wait_count : range 0 to WAIT_MAX:=0;
163 signal init_wait_done : := '0';
164 signal pll_reset_asserted : := '0';
167 signal rx_fsm_reset_done_int : := '0';
168 signal rx_fsm_reset_done_int_s2 : := '0';
169 signal rx_fsm_reset_done_int_s3 : := '0';
171 signal rxresetdone_s2 : := '0';
172 signal rxresetdone_s3 : := '0';
174 constant MAX_RETRIES : := 2**RETRY_COUNTER_BITWIDTH-1;
175 signal retry_counter_int : range 0 to MAX_RETRIES := 0;
176 signal time_out_counter : range 0 to WAIT_TIMEOUT_2ms := 0;
177 signal recclk_mon_restart_count : range 0 to 3:= 0;
178 signal recclk_mon_count_reset : := '0';
180 signal reset_time_out : := '0';
181 signal time_out_2ms : := '0';
--\Flags that the various time-out points
182 signal time_tlock_max : := '0';
--|have been reached.
183 signal time_out_500us : := '0';
--|
184 signal time_out_1us : := '0';
--/
185 signal time_out_100us : := '0';
--/
186 signal check_tlock_max : := '0';
188 signal mmcm_lock_count : range 0 to MMCM_LOCK_CNT_MAX-1:=0;
189 signal mmcm_lock_int : := '0';
190 signal mmcm_lock_i : := '0';
191 signal mmcm_lock_reclocked : := '0';
192 signal gtrxreset_i : := '0';
193 signal gtrxreset_tx_i : := '0';
194 signal gtrxreset_rx_i : := '0';
195 signal mmcm_reset_i : := '1';
196 signal rxpmaresetdone_i : := '0';
197 signal txpmaresetdone_i : := '0';
198 signal rxpmaresetdone_ss : := '0';
199 signal rxpmaresetdone_sync : ;
200 signal txpmaresetdone_sync : ;
201 signal rxpmaresetdone_s : ;
202 signal rxpmaresetdone_rx_s : ;
203 signal pmaresetdone_fallingedge_detect : ;
204 signal pmaresetdone_fallingedge_detect_s : ;
206 signal run_phase_alignment_int: := '0';
207 signal run_phase_alignment_int_s2 : := '0';
208 signal run_phase_alignment_int_s3 : := '0';
210 constant MAX_WAIT_BYPASS : := 5000;
--5000 RXUSRCLK cycles is the max for Multi lanes designs
211 signal wait_bypass_count : range 0 to MAX_WAIT_BYPASS-1;
212 signal time_out_wait_bypass : := '0';
213 signal time_out_wait_bypass_s2 : := '0';
214 signal time_out_wait_bypass_s3 : := '0';
216 signal refclk_lost : ;
218 signal time_out_adapt : := '0';
219 signal adapt_count_reset : := '0';
220 signal adapt_count : range 0 to WAIT_TIME_ADAPT-1;
221 signal data_valid_sync: := '0';
222 signal cplllock_sync: := '0';
223 signal qplllock_sync: := '0';
224 signal cplllock_prev: := '0';
225 signal qplllock_prev: := '0';
226 signal cplllock_ris_edge: := '0';
227 signal qplllock_ris_edge: := '0';
228 signal wait_time_cnt : range 0 to WAIT_TIME_MAX;
229 signal wait_time_done : ;
232 attribute shreg_extract : ;
233 attribute ASYNC_REG : ;
236 signal reset_sync_reg1_tx : ;
237 signal reset_sync_reg1 : ;
238 signal gtrxreset_s : ;
239 signal gtrxreset_tx_s : ;
240 signal txpmaresetdone_s : ;
242 --Alias section, signals used within this module mapped to output ports:
243 RETRY_COUNTER <= (TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
244 RUN_PHALIGNMENT <= run_phase_alignment_int;
245 RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
246 GTRXRESET <= gtrxreset_i;
247 MMCM_RESET <= mmcm_reset_i;
248 process(STABLE_CLOCK,SOFT_RESET)
250 if (SOFT_RESET = '1') then
251 init_wait_done <= '0';
252 init_wait_count <= 0 ;
253 elsif rising_edge(STABLE_CLOCK) then
254 -- The counter starts running when configuration has finished and
255 -- the clock is stable. When its maximum count-value has been reached,
256 -- the 500 ns from Answer
Record 43482 have been passed.
257 if init_wait_count = WAIT_MAX then
258 init_wait_done <= '1';
260 init_wait_count <= init_wait_count + 1;
266 adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
267 time_out_adapt <= '1';
270 adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
271 process(STABLE_CLOCK)
273 if rising_edge(STABLE_CLOCK) then
274 if(adapt_count_reset = '1') then
276 time_out_adapt <= '0';
277 elsif(adapt_count = WAIT_TIME_ADAPT -1) then
278 time_out_adapt <= '1';
280 adapt_count <= adapt_count + 1;
286 retries_recclk_monitor:
process(STABLE_CLOCK)
288 --This counter monitors, how many retries the RECCLK monitor
289 --runs. If during startup too many retries are necessary, the whole
290 --initialisation-process of the transceivers gets restarted.
291 if rising_edge(STABLE_CLOCK) then
292 if recclk_mon_count_reset = '1' then
293 recclk_mon_restart_count <= 0;
294 elsif RECCLK_MONITOR_RESTART = '1' then
295 if recclk_mon_restart_count = 3 then
296 recclk_mon_restart_count <= 0;
298 recclk_mon_restart_count <= recclk_mon_restart_count + 1;
304 timeouts:
process(STABLE_CLOCK)
306 if rising_edge(STABLE_CLOCK) then
307 -- One common large counter for generating three time-out signals.
308 -- Intermediate time-outs are derived from calculated values, based
309 -- on the period of the provided clock.
310 if reset_time_out = '1' then
311 time_out_counter <= 0;
313 time_tlock_max <= '0';
314 time_out_500us <= '0';
316 time_out_100us <= '0';
318 if time_out_counter = WAIT_TIMEOUT_2ms then
321 time_out_counter <= time_out_counter + 1;
324 if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
325 time_tlock_max <= '1';
328 if time_out_counter = WAIT_TIMEOUT_500us then
329 time_out_500us <= '1';
332 if time_out_counter = WAIT_TIMEOUT_1us then
336 if time_out_counter = WAIT_TIMEOUT_100us then
337 time_out_100us <= '1';
346 mmcm_lock_wait:
process(STABLE_CLOCK)
348 --The lock-signal from the MMCM is not immediately used but
349 --enabling a counter. Only when the counter hits its maximum,
350 --the MMCM is considered as "really" locked.
351 --The counter avoids that the FSM already starts on only a
352 --coarse lock of the MMCM (=toggling of the LOCK-signal).
353 if rising_edge(STABLE_CLOCK) then
354 if mmcm_lock_i = '0' then
355 mmcm_lock_count <= 0;
356 mmcm_lock_reclocked <= '0';
358 if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
359 mmcm_lock_count <= mmcm_lock_count + 1;
361 mmcm_lock_reclocked <= '1';
368 -- Clock Domain Crossing
374 data_in => run_phase_alignment_int ,
375 data_out => run_phase_alignment_int_s2
381 data_in => rx_fsm_reset_done_int,
382 data_out => rx_fsm_reset_done_int_s2
387 if rising_edge(RXUSERCLK) then
388 run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
390 rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
398 data_in => RXRESETDONE,
399 data_out => rxresetdone_s2
406 data_in => time_out_wait_bypass,
407 data_out => time_out_wait_bypass_s2
414 data_in => MMCM_LOCK,
415 data_out => mmcm_lock_i
422 data_in => DATA_VALID,
423 data_out => data_valid_sync
426 process(STABLE_CLOCK)
428 if rising_edge(STABLE_CLOCK) then
429 rxresetdone_s3 <= rxresetdone_s2;
431 time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
433 cplllock_prev <= cplllock_sync;
434 qplllock_prev <= qplllock_sync;
443 data_out => cplllock_sync
451 data_out => qplllock_sync
456 process (STABLE_CLOCK)
458 if rising_edge(STABLE_CLOCK) then
459 if(SOFT_RESET = '1' ) then
460 cplllock_ris_edge <= '0';
461 elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
462 cplllock_ris_edge <= '1';
463 elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
464 cplllock_ris_edge <= cplllock_ris_edge;
466 cplllock_ris_edge <= '0';
471 process (STABLE_CLOCK)
473 if rising_edge(STABLE_CLOCK) then
474 if(SOFT_RESET = '1' ) then
475 qplllock_ris_edge <= '0';
476 elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
477 qplllock_ris_edge <= '1';
478 elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
479 qplllock_ris_edge <= qplllock_ris_edge;
481 qplllock_ris_edge <= '0';
487 timeout_buffer_bypass:
process(RXUSERCLK)
489 if rising_edge(RXUSERCLK) then
490 if run_phase_alignment_int_s3 = '0' then
491 wait_bypass_count <= 0;
492 time_out_wait_bypass <= '0';
493 elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
494 if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
495 time_out_wait_bypass <= '1';
497 wait_bypass_count <= wait_bypass_count + 1;
503 refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
506 timeout_max:
process(STABLE_CLOCK)
508 if rising_edge(STABLE_CLOCK) then
509 if((rx_state = ASSERT_ALL_RESETS) or
510 (rx_state = RELEASE_MMCM_RESET)) then
511 wait_time_cnt <= WAIT_TIME_MAX;
512 elsif (wait_time_cnt > 0 ) then
513 wait_time_cnt <= wait_time_cnt - 1;
518 wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
521 --FSM for resetting the GTX/GTH/GTP in the 7-series.
522 --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
524 -- Following steps are performed:
525 -- 1)
After configuration wait for approximately
500 ns as specified
in
526 -- answer-record 43482
527 -- 2)
Assert all resets
on the GT
and on an MMCM potentially connected.
528 -- After that wait until a reference-clock has been detected.
529 -- 3)
Release the reset
to the GT
and wait until the GT-PLL has locked.
530 -- 4)
Release the MMCM-reset
and wait until the MMCM has signalled lock.
531 -- Also get info from the TX-side which PLL has been reset.
532 -- 5)
Wait for the RESET_DONE-signal from the GT.
533 -- 6)
Signal to start the phase-alignment
procedure and wait for it
to
535 -- 7) Reset-sequence has successfully run through.
Signal this
to the
536 -- rest of the design by asserting RX_FSM_RESET_DONE.
538 reset_fsm:
process(STABLE_CLOCK)
540 if rising_edge(STABLE_CLOCK) then
541 if (SOFT_RESET = '1' ) then
542 --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
547 rx_fsm_reset_done_int <= '0';
550 pll_reset_asserted <= '0';
551 reset_time_out <= '1';
552 retry_counter_int <= 0;
553 run_phase_alignment_int <= '0';
554 check_tlock_max <= '0';
555 RESET_PHALIGNMENT <= '1';
556 recclk_mon_count_reset <= '1';
557 adapt_count_reset <= '1';
567 --Initial state after configuration. This state will be left after
568 --approx. 500 ns
and not be re-entered.
569 if init_wait_done = '1' then
570 rx_state <= ASSERT_ALL_RESETS;
573 when ASSERT_ALL_RESETS =>
574 --This is the state into which the FSM will always jump back if any
575 --time-outs will occur.
576 --The number of retries is reported on the output RETRY_COUNTER. In
577 --case the transceiver never comes up for some reason, this machine
578 --will still continue its best and rerun until the FPGA is turned off
579 --or the transceivers come up correctly.
580 if RX_QPLL_USED and not TX_QPLL_USED then
581 if (pll_reset_asserted = '0' and refclk_lost = '0') then
583 pll_reset_asserted <= '1';
587 elsif not RX_QPLL_USED and TX_QPLL_USED then
588 if (pll_reset_asserted = '0' and refclk_lost = '0') then
590 pll_reset_asserted <= '1';
599 run_phase_alignment_int <= '0';
600 RESET_PHALIGNMENT <= '1';
601 check_tlock_max <= '0';
602 recclk_mon_count_reset <= '1';
603 adapt_count_reset <= '1';
605 if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1' ) or
606 (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1' ) or
607 (not RX_QPLL_USED and not TX_QPLL_USED ) or
608 (RX_QPLL_USED and TX_QPLL_USED ) then
609 rx_state <= WAIT_FOR_PLL_LOCK;
610 reset_time_out <= '1';
613 when WAIT_FOR_PLL_LOCK =>
614 if(wait_time_done = '1') then
615 rx_state <= RELEASE_PLL_RESET;
618 when RELEASE_PLL_RESET =>
619 --PLL-Reset of the GTX gets released and the time-out counter
621 pll_reset_asserted <= '0';
622 reset_time_out <= '0';
624 if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '1')) or
625 (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '1')) then
626 rx_state <= VERIFY_RECCLK_STABLE;
627 reset_time_out <= '1';
628 recclk_mon_count_reset <= '0';
629 adapt_count_reset <= '0';
630 elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
631 (not RX_QPLL_USED and (cplllock_sync = '1')) then
632 rx_state <= VERIFY_RECCLK_STABLE;
633 reset_time_out <= '1';
634 recclk_mon_count_reset <= '0';
635 adapt_count_reset <= '0';
638 if time_out_2ms = '1' then
639 if retry_counter_int = MAX_RETRIES then
640 -- If too many retries are performed compared to what is specified in
641 -- the generic, the counter simply wraps around.
642 retry_counter_int <= 0;
644 retry_counter_int <= retry_counter_int + 1;
646 rx_state <= ASSERT_ALL_RESETS;
649 when VERIFY_RECCLK_STABLE =>
650 --reset_time_out <= '0';
651 --Time-out counter is not released in this state as here the FSM
652 --does not wait for a certain period of but checks on the number
653 --of retries in the RECCLK monitor
655 if RECCLK_STABLE = '1' then
656 rx_state <= RELEASE_MMCM_RESET;
657 reset_time_out <= '1';
661 if recclk_mon_restart_count = 2 then
662 --If two retries are performed in the RECCLK monitor
663 --the whole initialisation-sequence gets restarted.
664 if retry_counter_int = MAX_RETRIES then
665 -- If too many retries are performed compared to what is specified in
666 -- the generic, the counter simply wraps around.
667 retry_counter_int <= 0;
669 retry_counter_int <= retry_counter_int + 1;
671 rx_state <= ASSERT_ALL_RESETS;
674 when RELEASE_MMCM_RESET =>
675 --Release of the MMCM-reset. Waiting for the MMCM to lock.
676 check_tlock_max <= '1';
679 reset_time_out <= '0';
681 if mmcm_lock_reclocked = '1' then
682 rx_state <= WAIT_FOR_RXUSRCLK;
683 reset_time_out <= '1';
686 if (time_tlock_max = '1' and reset_time_out = '0' )then
687 if retry_counter_int = MAX_RETRIES then
688 -- If too many retries are performed compared to what is specified in
689 -- the generic, the counter simply wraps around.
690 retry_counter_int <= 0;
692 retry_counter_int <= retry_counter_int + 1;
694 rx_state <= ASSERT_ALL_RESETS;
697 when WAIT_FOR_RXUSRCLK =>
698 if wait_time_done = '1' then
699 rx_state <= WAIT_RESET_DONE;
702 when WAIT_RESET_DONE =>
703 --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
704 --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
705 if TXUSERRDY = '1' then
708 reset_time_out <= '0';
709 if rxresetdone_s3 = '1' then
710 rx_state <= DO_PHASE_ALIGNMENT;
711 reset_time_out <= '1';
714 if time_out_2ms = '1' and reset_time_out = '0' then
715 if retry_counter_int = MAX_RETRIES then
716 -- If too many retries are performed compared to what is specified in
717 -- the generic, the counter simply wraps around.
718 retry_counter_int <= 0;
720 retry_counter_int <= retry_counter_int + 1;
722 rx_state <= ASSERT_ALL_RESETS;
725 when DO_PHASE_ALIGNMENT =>
726 --The direct handling of the signals for the Phase Alignment is done outside
727 --this state-machine.
728 RESET_PHALIGNMENT <= '0';
729 run_phase_alignment_int <= '1';
730 reset_time_out <= '0';
732 if PHALIGNMENT_DONE = '1' then
733 rx_state <= MONITOR_DATA_VALID;
734 reset_time_out <= '1';
737 if time_out_wait_bypass_s3 = '1' then
738 if retry_counter_int = MAX_RETRIES then
739 -- If too many retries are performed compared to what is specified in
740 -- the generic, the counter simply wraps around.
741 retry_counter_int <= 0;
743 retry_counter_int <= retry_counter_int + 1;
745 rx_state <= ASSERT_ALL_RESETS;
748 when MONITOR_DATA_VALID =>
749 reset_time_out <= '0';
751 if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then
752 rx_state <= ASSERT_ALL_RESETS;
753 rx_fsm_reset_done_int <= '0';
754 elsif (data_valid_sync = '1') then
755 rx_state <= FSM_DONE;
756 rx_fsm_reset_done_int <= '0';
757 reset_time_out <= '1';
761 reset_time_out <= '0';
762 if data_valid_sync = '0' then
763 rx_fsm_reset_done_int <= '0';
764 reset_time_out <= '1';
765 rx_state <= MONITOR_DATA_VALID;
767 elsif(time_out_1us = '1' and reset_time_out = '0') then
768 rx_fsm_reset_done_int <= '1';
771 if(time_out_adapt = '1') then
772 if(EQ_MODE = "DFE") then