AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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amc_gtx5gpd_multi_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : amc_gtx5gpd_multi_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module amc_gtx5Gpd_multi_gt (a Multi GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity amc_gtx5Gpd_multi_gt is
74 generic
75 (
76  -- Simulation attributes
77  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
78  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
79 
80  PMA_RSV_IN : bit_vector := x"001E7080"
81 );
82 port
83 (
84  --_________________________________________________________________________
85  --_________________________________________________________________________
86  --GT0 (X0Y0)
87  --____________________________CHANNEL PORTS________________________________
88  ---------------------------- Channel - DRP Ports --------------------------
89  gt0_drpaddr_in : in std_logic_vector(8 downto 0);
90  gt0_drpclk_in : in std_logic;
91  gt0_drpdi_in : in std_logic_vector(15 downto 0);
92  gt0_drpdo_out : out std_logic_vector(15 downto 0);
93  gt0_drpen_in : in std_logic;
94  gt0_drprdy_out : out std_logic;
95  gt0_drpwe_in : in std_logic;
96  --------------------------- Digital Monitor Ports --------------------------
97  gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
98  ------------------------------- Loopback Ports -----------------------------
99  gt0_loopback_in : in std_logic_vector(2 downto 0);
100  ------------------------------ Power-Down Ports ----------------------------
101  gt0_rxpd_in : in std_logic_vector(1 downto 0);
102  gt0_txpd_in : in std_logic_vector(1 downto 0);
103  --------------------- RX Initialization and Reset Ports --------------------
104  gt0_eyescanreset_in : in std_logic;
105  gt0_rxuserrdy_in : in std_logic;
106  -------------------------- RX Margin Analysis Ports ------------------------
107  gt0_eyescandataerror_out : out std_logic;
108  gt0_eyescantrigger_in : in std_logic;
109  ------------------- Receive Ports - Clock Correction Ports -----------------
110  gt0_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
111  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
112  gt0_rxusrclk_in : in std_logic;
113  gt0_rxusrclk2_in : in std_logic;
114  ------------------ Receive Ports - FPGA RX interface Ports -----------------
115  gt0_rxdata_out : out std_logic_vector(15 downto 0);
116  ------------------- Receive Ports - Pattern Checker Ports ------------------
117  gt0_rxprbserr_out : out std_logic;
118  gt0_rxprbssel_in : in std_logic_vector(2 downto 0);
119  ------------------- Receive Ports - Pattern Checker ports ------------------
120  gt0_rxprbscntreset_in : in std_logic;
121  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
122  gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
123  gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
124  --------------------------- Receive Ports - RX AFE -------------------------
125  gt0_gtxrxp_in : in std_logic;
126  ------------------------ Receive Ports - RX AFE Ports ----------------------
127  gt0_gtxrxn_in : in std_logic;
128  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
129  gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
130  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
131  gt0_rxmcommaalignen_in : in std_logic;
132  gt0_rxpcommaalignen_in : in std_logic;
133  --------------------- Receive Ports - RX Equalizer Ports -------------------
134  gt0_rxdfeagchold_in : in std_logic;
135  gt0_rxdfelfhold_in : in std_logic;
136  gt0_rxdfelpmreset_in : in std_logic;
137  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
138  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
139  --------------- Receive Ports - RX Fabric Output Control Ports -------------
140  gt0_rxoutclk_out : out std_logic;
141  gt0_rxoutclkfabric_out : out std_logic;
142  ------------- Receive Ports - RX Initialization and Reset Ports ------------
143  gt0_gtrxreset_in : in std_logic;
144  gt0_rxpmareset_in : in std_logic;
145  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
146  gt0_rxchariscomma_out : out std_logic_vector(1 downto 0);
147  gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
148  -------------- Receive Ports -RX Initialization and Reset Ports ------------
149  gt0_rxresetdone_out : out std_logic;
150  --------------------- TX Initialization and Reset Ports --------------------
151  gt0_gttxreset_in : in std_logic;
152  gt0_txuserrdy_in : in std_logic;
153  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
154  gt0_txusrclk_in : in std_logic;
155  gt0_txusrclk2_in : in std_logic;
156  --------------- Transmit Ports - TX Configurable Driver Ports --------------
157  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
158  ------------------ Transmit Ports - TX Data Path interface -----------------
159  gt0_txdata_in : in std_logic_vector(15 downto 0);
160  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
161  gt0_gtxtxn_out : out std_logic;
162  gt0_gtxtxp_out : out std_logic;
163  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
164  gt0_txoutclk_out : out std_logic;
165  gt0_txoutclkfabric_out : out std_logic;
166  gt0_txoutclkpcs_out : out std_logic;
167  --------------------- Transmit Ports - TX Gearbox Ports --------------------
168  gt0_txcharisk_in : in std_logic_vector(1 downto 0);
169  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
170  gt0_txresetdone_out : out std_logic;
171  ------------------ Transmit Ports - pattern Generator Ports ----------------
172  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
173 
174  --GT1 (X0Y1)
175  --____________________________CHANNEL PORTS________________________________
176  ---------------------------- Channel - DRP Ports --------------------------
177  gt1_drpaddr_in : in std_logic_vector(8 downto 0);
178  gt1_drpclk_in : in std_logic;
179  gt1_drpdi_in : in std_logic_vector(15 downto 0);
180  gt1_drpdo_out : out std_logic_vector(15 downto 0);
181  gt1_drpen_in : in std_logic;
182  gt1_drprdy_out : out std_logic;
183  gt1_drpwe_in : in std_logic;
184  --------------------------- Digital Monitor Ports --------------------------
185  gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
186  ------------------------------- Loopback Ports -----------------------------
187  gt1_loopback_in : in std_logic_vector(2 downto 0);
188  ------------------------------ Power-Down Ports ----------------------------
189  gt1_rxpd_in : in std_logic_vector(1 downto 0);
190  gt1_txpd_in : in std_logic_vector(1 downto 0);
191  --------------------- RX Initialization and Reset Ports --------------------
192  gt1_eyescanreset_in : in std_logic;
193  gt1_rxuserrdy_in : in std_logic;
194  -------------------------- RX Margin Analysis Ports ------------------------
195  gt1_eyescandataerror_out : out std_logic;
196  gt1_eyescantrigger_in : in std_logic;
197  ------------------- Receive Ports - Clock Correction Ports -----------------
198  gt1_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
199  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
200  gt1_rxusrclk_in : in std_logic;
201  gt1_rxusrclk2_in : in std_logic;
202  ------------------ Receive Ports - FPGA RX interface Ports -----------------
203  gt1_rxdata_out : out std_logic_vector(15 downto 0);
204  ------------------- Receive Ports - Pattern Checker Ports ------------------
205  gt1_rxprbserr_out : out std_logic;
206  gt1_rxprbssel_in : in std_logic_vector(2 downto 0);
207  ------------------- Receive Ports - Pattern Checker ports ------------------
208  gt1_rxprbscntreset_in : in std_logic;
209  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
210  gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
211  gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
212  --------------------------- Receive Ports - RX AFE -------------------------
213  gt1_gtxrxp_in : in std_logic;
214  ------------------------ Receive Ports - RX AFE Ports ----------------------
215  gt1_gtxrxn_in : in std_logic;
216  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
217  gt1_rxbufstatus_out : out std_logic_vector(2 downto 0);
218  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
219  gt1_rxmcommaalignen_in : in std_logic;
220  gt1_rxpcommaalignen_in : in std_logic;
221  --------------------- Receive Ports - RX Equalizer Ports -------------------
222  gt1_rxdfeagchold_in : in std_logic;
223  gt1_rxdfelfhold_in : in std_logic;
224  gt1_rxdfelpmreset_in : in std_logic;
225  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
226  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
227  --------------- Receive Ports - RX Fabric Output Control Ports -------------
228  gt1_rxoutclk_out : out std_logic;
229  gt1_rxoutclkfabric_out : out std_logic;
230  ------------- Receive Ports - RX Initialization and Reset Ports ------------
231  gt1_gtrxreset_in : in std_logic;
232  gt1_rxpmareset_in : in std_logic;
233  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
234  gt1_rxchariscomma_out : out std_logic_vector(1 downto 0);
235  gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
236  -------------- Receive Ports -RX Initialization and Reset Ports ------------
237  gt1_rxresetdone_out : out std_logic;
238  --------------------- TX Initialization and Reset Ports --------------------
239  gt1_gttxreset_in : in std_logic;
240  gt1_txuserrdy_in : in std_logic;
241  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
242  gt1_txusrclk_in : in std_logic;
243  gt1_txusrclk2_in : in std_logic;
244  --------------- Transmit Ports - TX Configurable Driver Ports --------------
245  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
246  ------------------ Transmit Ports - TX Data Path interface -----------------
247  gt1_txdata_in : in std_logic_vector(15 downto 0);
248  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
249  gt1_gtxtxn_out : out std_logic;
250  gt1_gtxtxp_out : out std_logic;
251  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
252  gt1_txoutclk_out : out std_logic;
253  gt1_txoutclkfabric_out : out std_logic;
254  gt1_txoutclkpcs_out : out std_logic;
255  --------------------- Transmit Ports - TX Gearbox Ports --------------------
256  gt1_txcharisk_in : in std_logic_vector(1 downto 0);
257  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
258  gt1_txresetdone_out : out std_logic;
259  ------------------ Transmit Ports - pattern Generator Ports ----------------
260  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
261 
262  --GT2 (X0Y2)
263  --____________________________CHANNEL PORTS________________________________
264  ---------------------------- Channel - DRP Ports --------------------------
265  gt2_drpaddr_in : in std_logic_vector(8 downto 0);
266  gt2_drpclk_in : in std_logic;
267  gt2_drpdi_in : in std_logic_vector(15 downto 0);
268  gt2_drpdo_out : out std_logic_vector(15 downto 0);
269  gt2_drpen_in : in std_logic;
270  gt2_drprdy_out : out std_logic;
271  gt2_drpwe_in : in std_logic;
272  --------------------------- Digital Monitor Ports --------------------------
273  gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
274  ------------------------------- Loopback Ports -----------------------------
275  gt2_loopback_in : in std_logic_vector(2 downto 0);
276  ------------------------------ Power-Down Ports ----------------------------
277  gt2_rxpd_in : in std_logic_vector(1 downto 0);
278  gt2_txpd_in : in std_logic_vector(1 downto 0);
279  --------------------- RX Initialization and Reset Ports --------------------
280  gt2_eyescanreset_in : in std_logic;
281  gt2_rxuserrdy_in : in std_logic;
282  -------------------------- RX Margin Analysis Ports ------------------------
283  gt2_eyescandataerror_out : out std_logic;
284  gt2_eyescantrigger_in : in std_logic;
285  ------------------- Receive Ports - Clock Correction Ports -----------------
286  gt2_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
287  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
288  gt2_rxusrclk_in : in std_logic;
289  gt2_rxusrclk2_in : in std_logic;
290  ------------------ Receive Ports - FPGA RX interface Ports -----------------
291  gt2_rxdata_out : out std_logic_vector(15 downto 0);
292  ------------------- Receive Ports - Pattern Checker Ports ------------------
293  gt2_rxprbserr_out : out std_logic;
294  gt2_rxprbssel_in : in std_logic_vector(2 downto 0);
295  ------------------- Receive Ports - Pattern Checker ports ------------------
296  gt2_rxprbscntreset_in : in std_logic;
297  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
298  gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
299  gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
300  --------------------------- Receive Ports - RX AFE -------------------------
301  gt2_gtxrxp_in : in std_logic;
302  ------------------------ Receive Ports - RX AFE Ports ----------------------
303  gt2_gtxrxn_in : in std_logic;
304  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
305  gt2_rxbufstatus_out : out std_logic_vector(2 downto 0);
306  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
307  gt2_rxmcommaalignen_in : in std_logic;
308  gt2_rxpcommaalignen_in : in std_logic;
309  --------------------- Receive Ports - RX Equalizer Ports -------------------
310  gt2_rxdfeagchold_in : in std_logic;
311  gt2_rxdfelfhold_in : in std_logic;
312  gt2_rxdfelpmreset_in : in std_logic;
313  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
314  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
315  --------------- Receive Ports - RX Fabric Output Control Ports -------------
316  gt2_rxoutclk_out : out std_logic;
317  gt2_rxoutclkfabric_out : out std_logic;
318  ------------- Receive Ports - RX Initialization and Reset Ports ------------
319  gt2_gtrxreset_in : in std_logic;
320  gt2_rxpmareset_in : in std_logic;
321  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
322  gt2_rxchariscomma_out : out std_logic_vector(1 downto 0);
323  gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
324  -------------- Receive Ports -RX Initialization and Reset Ports ------------
325  gt2_rxresetdone_out : out std_logic;
326  --------------------- TX Initialization and Reset Ports --------------------
327  gt2_gttxreset_in : in std_logic;
328  gt2_txuserrdy_in : in std_logic;
329  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
330  gt2_txusrclk_in : in std_logic;
331  gt2_txusrclk2_in : in std_logic;
332  --------------- Transmit Ports - TX Configurable Driver Ports --------------
333  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
334  ------------------ Transmit Ports - TX Data Path interface -----------------
335  gt2_txdata_in : in std_logic_vector(15 downto 0);
336  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
337  gt2_gtxtxn_out : out std_logic;
338  gt2_gtxtxp_out : out std_logic;
339  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
340  gt2_txoutclk_out : out std_logic;
341  gt2_txoutclkfabric_out : out std_logic;
342  gt2_txoutclkpcs_out : out std_logic;
343  --------------------- Transmit Ports - TX Gearbox Ports --------------------
344  gt2_txcharisk_in : in std_logic_vector(1 downto 0);
345  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
346  gt2_txresetdone_out : out std_logic;
347  ------------------ Transmit Ports - pattern Generator Ports ----------------
348  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
349 
350  --GT3 (X0Y3)
351  --____________________________CHANNEL PORTS________________________________
352  ---------------------------- Channel - DRP Ports --------------------------
353  gt3_drpaddr_in : in std_logic_vector(8 downto 0);
354  gt3_drpclk_in : in std_logic;
355  gt3_drpdi_in : in std_logic_vector(15 downto 0);
356  gt3_drpdo_out : out std_logic_vector(15 downto 0);
357  gt3_drpen_in : in std_logic;
358  gt3_drprdy_out : out std_logic;
359  gt3_drpwe_in : in std_logic;
360  --------------------------- Digital Monitor Ports --------------------------
361  gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
362  ------------------------------- Loopback Ports -----------------------------
363  gt3_loopback_in : in std_logic_vector(2 downto 0);
364  ------------------------------ Power-Down Ports ----------------------------
365  gt3_rxpd_in : in std_logic_vector(1 downto 0);
366  gt3_txpd_in : in std_logic_vector(1 downto 0);
367  --------------------- RX Initialization and Reset Ports --------------------
368  gt3_eyescanreset_in : in std_logic;
369  gt3_rxuserrdy_in : in std_logic;
370  -------------------------- RX Margin Analysis Ports ------------------------
371  gt3_eyescandataerror_out : out std_logic;
372  gt3_eyescantrigger_in : in std_logic;
373  ------------------- Receive Ports - Clock Correction Ports -----------------
374  gt3_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
375  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
376  gt3_rxusrclk_in : in std_logic;
377  gt3_rxusrclk2_in : in std_logic;
378  ------------------ Receive Ports - FPGA RX interface Ports -----------------
379  gt3_rxdata_out : out std_logic_vector(15 downto 0);
380  ------------------- Receive Ports - Pattern Checker Ports ------------------
381  gt3_rxprbserr_out : out std_logic;
382  gt3_rxprbssel_in : in std_logic_vector(2 downto 0);
383  ------------------- Receive Ports - Pattern Checker ports ------------------
384  gt3_rxprbscntreset_in : in std_logic;
385  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
386  gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
387  gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
388  --------------------------- Receive Ports - RX AFE -------------------------
389  gt3_gtxrxp_in : in std_logic;
390  ------------------------ Receive Ports - RX AFE Ports ----------------------
391  gt3_gtxrxn_in : in std_logic;
392  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
393  gt3_rxbufstatus_out : out std_logic_vector(2 downto 0);
394  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
395  gt3_rxmcommaalignen_in : in std_logic;
396  gt3_rxpcommaalignen_in : in std_logic;
397  --------------------- Receive Ports - RX Equalizer Ports -------------------
398  gt3_rxdfeagchold_in : in std_logic;
399  gt3_rxdfelfhold_in : in std_logic;
400  gt3_rxdfelpmreset_in : in std_logic;
401  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
402  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
403  --------------- Receive Ports - RX Fabric Output Control Ports -------------
404  gt3_rxoutclk_out : out std_logic;
405  gt3_rxoutclkfabric_out : out std_logic;
406  ------------- Receive Ports - RX Initialization and Reset Ports ------------
407  gt3_gtrxreset_in : in std_logic;
408  gt3_rxpmareset_in : in std_logic;
409  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
410  gt3_rxchariscomma_out : out std_logic_vector(1 downto 0);
411  gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
412  -------------- Receive Ports -RX Initialization and Reset Ports ------------
413  gt3_rxresetdone_out : out std_logic;
414  --------------------- TX Initialization and Reset Ports --------------------
415  gt3_gttxreset_in : in std_logic;
416  gt3_txuserrdy_in : in std_logic;
417  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
418  gt3_txusrclk_in : in std_logic;
419  gt3_txusrclk2_in : in std_logic;
420  --------------- Transmit Ports - TX Configurable Driver Ports --------------
421  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
422  ------------------ Transmit Ports - TX Data Path interface -----------------
423  gt3_txdata_in : in std_logic_vector(15 downto 0);
424  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
425  gt3_gtxtxn_out : out std_logic;
426  gt3_gtxtxp_out : out std_logic;
427  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
428  gt3_txoutclk_out : out std_logic;
429  gt3_txoutclkfabric_out : out std_logic;
430  gt3_txoutclkpcs_out : out std_logic;
431  --------------------- Transmit Ports - TX Gearbox Ports --------------------
432  gt3_txcharisk_in : in std_logic_vector(1 downto 0);
433  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
434  gt3_txresetdone_out : out std_logic;
435  ------------------ Transmit Ports - pattern Generator Ports ----------------
436  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
437 
438  --GT4 (X0Y4)
439  --____________________________CHANNEL PORTS________________________________
440  ---------------------------- Channel - DRP Ports --------------------------
441  gt4_drpaddr_in : in std_logic_vector(8 downto 0);
442  gt4_drpclk_in : in std_logic;
443  gt4_drpdi_in : in std_logic_vector(15 downto 0);
444  gt4_drpdo_out : out std_logic_vector(15 downto 0);
445  gt4_drpen_in : in std_logic;
446  gt4_drprdy_out : out std_logic;
447  gt4_drpwe_in : in std_logic;
448  --------------------------- Digital Monitor Ports --------------------------
449  gt4_dmonitorout_out : out std_logic_vector(7 downto 0);
450  ------------------------------- Loopback Ports -----------------------------
451  gt4_loopback_in : in std_logic_vector(2 downto 0);
452  ------------------------------ Power-Down Ports ----------------------------
453  gt4_rxpd_in : in std_logic_vector(1 downto 0);
454  gt4_txpd_in : in std_logic_vector(1 downto 0);
455  --------------------- RX Initialization and Reset Ports --------------------
456  gt4_eyescanreset_in : in std_logic;
457  gt4_rxuserrdy_in : in std_logic;
458  -------------------------- RX Margin Analysis Ports ------------------------
459  gt4_eyescandataerror_out : out std_logic;
460  gt4_eyescantrigger_in : in std_logic;
461  ------------------- Receive Ports - Clock Correction Ports -----------------
462  gt4_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
463  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
464  gt4_rxusrclk_in : in std_logic;
465  gt4_rxusrclk2_in : in std_logic;
466  ------------------ Receive Ports - FPGA RX interface Ports -----------------
467  gt4_rxdata_out : out std_logic_vector(15 downto 0);
468  ------------------- Receive Ports - Pattern Checker Ports ------------------
469  gt4_rxprbserr_out : out std_logic;
470  gt4_rxprbssel_in : in std_logic_vector(2 downto 0);
471  ------------------- Receive Ports - Pattern Checker ports ------------------
472  gt4_rxprbscntreset_in : in std_logic;
473  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
474  gt4_rxdisperr_out : out std_logic_vector(1 downto 0);
475  gt4_rxnotintable_out : out std_logic_vector(1 downto 0);
476  --------------------------- Receive Ports - RX AFE -------------------------
477  gt4_gtxrxp_in : in std_logic;
478  ------------------------ Receive Ports - RX AFE Ports ----------------------
479  gt4_gtxrxn_in : in std_logic;
480  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
481  gt4_rxbufstatus_out : out std_logic_vector(2 downto 0);
482  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
483  gt4_rxmcommaalignen_in : in std_logic;
484  gt4_rxpcommaalignen_in : in std_logic;
485  --------------------- Receive Ports - RX Equalizer Ports -------------------
486  gt4_rxdfeagchold_in : in std_logic;
487  gt4_rxdfelfhold_in : in std_logic;
488  gt4_rxdfelpmreset_in : in std_logic;
489  gt4_rxmonitorout_out : out std_logic_vector(6 downto 0);
490  gt4_rxmonitorsel_in : in std_logic_vector(1 downto 0);
491  --------------- Receive Ports - RX Fabric Output Control Ports -------------
492  gt4_rxoutclk_out : out std_logic;
493  gt4_rxoutclkfabric_out : out std_logic;
494  ------------- Receive Ports - RX Initialization and Reset Ports ------------
495  gt4_gtrxreset_in : in std_logic;
496  gt4_rxpmareset_in : in std_logic;
497  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
498  gt4_rxchariscomma_out : out std_logic_vector(1 downto 0);
499  gt4_rxcharisk_out : out std_logic_vector(1 downto 0);
500  -------------- Receive Ports -RX Initialization and Reset Ports ------------
501  gt4_rxresetdone_out : out std_logic;
502  --------------------- TX Initialization and Reset Ports --------------------
503  gt4_gttxreset_in : in std_logic;
504  gt4_txuserrdy_in : in std_logic;
505  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
506  gt4_txusrclk_in : in std_logic;
507  gt4_txusrclk2_in : in std_logic;
508  --------------- Transmit Ports - TX Configurable Driver Ports --------------
509  gt4_txdiffctrl_in : in std_logic_vector(3 downto 0);
510  ------------------ Transmit Ports - TX Data Path interface -----------------
511  gt4_txdata_in : in std_logic_vector(15 downto 0);
512  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
513  gt4_gtxtxn_out : out std_logic;
514  gt4_gtxtxp_out : out std_logic;
515  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
516  gt4_txoutclk_out : out std_logic;
517  gt4_txoutclkfabric_out : out std_logic;
518  gt4_txoutclkpcs_out : out std_logic;
519  --------------------- Transmit Ports - TX Gearbox Ports --------------------
520  gt4_txcharisk_in : in std_logic_vector(1 downto 0);
521  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
522  gt4_txresetdone_out : out std_logic;
523  ------------------ Transmit Ports - pattern Generator Ports ----------------
524  gt4_txprbssel_in : in std_logic_vector(2 downto 0);
525 
526  --GT5 (X0Y5)
527  --____________________________CHANNEL PORTS________________________________
528  ---------------------------- Channel - DRP Ports --------------------------
529  gt5_drpaddr_in : in std_logic_vector(8 downto 0);
530  gt5_drpclk_in : in std_logic;
531  gt5_drpdi_in : in std_logic_vector(15 downto 0);
532  gt5_drpdo_out : out std_logic_vector(15 downto 0);
533  gt5_drpen_in : in std_logic;
534  gt5_drprdy_out : out std_logic;
535  gt5_drpwe_in : in std_logic;
536  --------------------------- Digital Monitor Ports --------------------------
537  gt5_dmonitorout_out : out std_logic_vector(7 downto 0);
538  ------------------------------- Loopback Ports -----------------------------
539  gt5_loopback_in : in std_logic_vector(2 downto 0);
540  ------------------------------ Power-Down Ports ----------------------------
541  gt5_rxpd_in : in std_logic_vector(1 downto 0);
542  gt5_txpd_in : in std_logic_vector(1 downto 0);
543  --------------------- RX Initialization and Reset Ports --------------------
544  gt5_eyescanreset_in : in std_logic;
545  gt5_rxuserrdy_in : in std_logic;
546  -------------------------- RX Margin Analysis Ports ------------------------
547  gt5_eyescandataerror_out : out std_logic;
548  gt5_eyescantrigger_in : in std_logic;
549  ------------------- Receive Ports - Clock Correction Ports -----------------
550  gt5_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
551  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
552  gt5_rxusrclk_in : in std_logic;
553  gt5_rxusrclk2_in : in std_logic;
554  ------------------ Receive Ports - FPGA RX interface Ports -----------------
555  gt5_rxdata_out : out std_logic_vector(15 downto 0);
556  ------------------- Receive Ports - Pattern Checker Ports ------------------
557  gt5_rxprbserr_out : out std_logic;
558  gt5_rxprbssel_in : in std_logic_vector(2 downto 0);
559  ------------------- Receive Ports - Pattern Checker ports ------------------
560  gt5_rxprbscntreset_in : in std_logic;
561  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
562  gt5_rxdisperr_out : out std_logic_vector(1 downto 0);
563  gt5_rxnotintable_out : out std_logic_vector(1 downto 0);
564  --------------------------- Receive Ports - RX AFE -------------------------
565  gt5_gtxrxp_in : in std_logic;
566  ------------------------ Receive Ports - RX AFE Ports ----------------------
567  gt5_gtxrxn_in : in std_logic;
568  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
569  gt5_rxbufstatus_out : out std_logic_vector(2 downto 0);
570  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
571  gt5_rxmcommaalignen_in : in std_logic;
572  gt5_rxpcommaalignen_in : in std_logic;
573  --------------------- Receive Ports - RX Equalizer Ports -------------------
574  gt5_rxdfeagchold_in : in std_logic;
575  gt5_rxdfelfhold_in : in std_logic;
576  gt5_rxdfelpmreset_in : in std_logic;
577  gt5_rxmonitorout_out : out std_logic_vector(6 downto 0);
578  gt5_rxmonitorsel_in : in std_logic_vector(1 downto 0);
579  --------------- Receive Ports - RX Fabric Output Control Ports -------------
580  gt5_rxoutclk_out : out std_logic;
581  gt5_rxoutclkfabric_out : out std_logic;
582  ------------- Receive Ports - RX Initialization and Reset Ports ------------
583  gt5_gtrxreset_in : in std_logic;
584  gt5_rxpmareset_in : in std_logic;
585  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
586  gt5_rxchariscomma_out : out std_logic_vector(1 downto 0);
587  gt5_rxcharisk_out : out std_logic_vector(1 downto 0);
588  -------------- Receive Ports -RX Initialization and Reset Ports ------------
589  gt5_rxresetdone_out : out std_logic;
590  --------------------- TX Initialization and Reset Ports --------------------
591  gt5_gttxreset_in : in std_logic;
592  gt5_txuserrdy_in : in std_logic;
593  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
594  gt5_txusrclk_in : in std_logic;
595  gt5_txusrclk2_in : in std_logic;
596  --------------- Transmit Ports - TX Configurable Driver Ports --------------
597  gt5_txdiffctrl_in : in std_logic_vector(3 downto 0);
598  ------------------ Transmit Ports - TX Data Path interface -----------------
599  gt5_txdata_in : in std_logic_vector(15 downto 0);
600  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
601  gt5_gtxtxn_out : out std_logic;
602  gt5_gtxtxp_out : out std_logic;
603  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
604  gt5_txoutclk_out : out std_logic;
605  gt5_txoutclkfabric_out : out std_logic;
606  gt5_txoutclkpcs_out : out std_logic;
607  --------------------- Transmit Ports - TX Gearbox Ports --------------------
608  gt5_txcharisk_in : in std_logic_vector(1 downto 0);
609  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
610  gt5_txresetdone_out : out std_logic;
611  ------------------ Transmit Ports - pattern Generator Ports ----------------
612  gt5_txprbssel_in : in std_logic_vector(2 downto 0);
613 
614  --GT6 (X0Y6)
615  --____________________________CHANNEL PORTS________________________________
616  ---------------------------- Channel - DRP Ports --------------------------
617  gt6_drpaddr_in : in std_logic_vector(8 downto 0);
618  gt6_drpclk_in : in std_logic;
619  gt6_drpdi_in : in std_logic_vector(15 downto 0);
620  gt6_drpdo_out : out std_logic_vector(15 downto 0);
621  gt6_drpen_in : in std_logic;
622  gt6_drprdy_out : out std_logic;
623  gt6_drpwe_in : in std_logic;
624  --------------------------- Digital Monitor Ports --------------------------
625  gt6_dmonitorout_out : out std_logic_vector(7 downto 0);
626  ------------------------------- Loopback Ports -----------------------------
627  gt6_loopback_in : in std_logic_vector(2 downto 0);
628  ------------------------------ Power-Down Ports ----------------------------
629  gt6_rxpd_in : in std_logic_vector(1 downto 0);
630  gt6_txpd_in : in std_logic_vector(1 downto 0);
631  --------------------- RX Initialization and Reset Ports --------------------
632  gt6_eyescanreset_in : in std_logic;
633  gt6_rxuserrdy_in : in std_logic;
634  -------------------------- RX Margin Analysis Ports ------------------------
635  gt6_eyescandataerror_out : out std_logic;
636  gt6_eyescantrigger_in : in std_logic;
637  ------------------- Receive Ports - Clock Correction Ports -----------------
638  gt6_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
639  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
640  gt6_rxusrclk_in : in std_logic;
641  gt6_rxusrclk2_in : in std_logic;
642  ------------------ Receive Ports - FPGA RX interface Ports -----------------
643  gt6_rxdata_out : out std_logic_vector(15 downto 0);
644  ------------------- Receive Ports - Pattern Checker Ports ------------------
645  gt6_rxprbserr_out : out std_logic;
646  gt6_rxprbssel_in : in std_logic_vector(2 downto 0);
647  ------------------- Receive Ports - Pattern Checker ports ------------------
648  gt6_rxprbscntreset_in : in std_logic;
649  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
650  gt6_rxdisperr_out : out std_logic_vector(1 downto 0);
651  gt6_rxnotintable_out : out std_logic_vector(1 downto 0);
652  --------------------------- Receive Ports - RX AFE -------------------------
653  gt6_gtxrxp_in : in std_logic;
654  ------------------------ Receive Ports - RX AFE Ports ----------------------
655  gt6_gtxrxn_in : in std_logic;
656  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
657  gt6_rxbufstatus_out : out std_logic_vector(2 downto 0);
658  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
659  gt6_rxmcommaalignen_in : in std_logic;
660  gt6_rxpcommaalignen_in : in std_logic;
661  --------------------- Receive Ports - RX Equalizer Ports -------------------
662  gt6_rxdfeagchold_in : in std_logic;
663  gt6_rxdfelfhold_in : in std_logic;
664  gt6_rxdfelpmreset_in : in std_logic;
665  gt6_rxmonitorout_out : out std_logic_vector(6 downto 0);
666  gt6_rxmonitorsel_in : in std_logic_vector(1 downto 0);
667  --------------- Receive Ports - RX Fabric Output Control Ports -------------
668  gt6_rxoutclk_out : out std_logic;
669  gt6_rxoutclkfabric_out : out std_logic;
670  ------------- Receive Ports - RX Initialization and Reset Ports ------------
671  gt6_gtrxreset_in : in std_logic;
672  gt6_rxpmareset_in : in std_logic;
673  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
674  gt6_rxchariscomma_out : out std_logic_vector(1 downto 0);
675  gt6_rxcharisk_out : out std_logic_vector(1 downto 0);
676  -------------- Receive Ports -RX Initialization and Reset Ports ------------
677  gt6_rxresetdone_out : out std_logic;
678  --------------------- TX Initialization and Reset Ports --------------------
679  gt6_gttxreset_in : in std_logic;
680  gt6_txuserrdy_in : in std_logic;
681  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
682  gt6_txusrclk_in : in std_logic;
683  gt6_txusrclk2_in : in std_logic;
684  --------------- Transmit Ports - TX Configurable Driver Ports --------------
685  gt6_txdiffctrl_in : in std_logic_vector(3 downto 0);
686  ------------------ Transmit Ports - TX Data Path interface -----------------
687  gt6_txdata_in : in std_logic_vector(15 downto 0);
688  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
689  gt6_gtxtxn_out : out std_logic;
690  gt6_gtxtxp_out : out std_logic;
691  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
692  gt6_txoutclk_out : out std_logic;
693  gt6_txoutclkfabric_out : out std_logic;
694  gt6_txoutclkpcs_out : out std_logic;
695  --------------------- Transmit Ports - TX Gearbox Ports --------------------
696  gt6_txcharisk_in : in std_logic_vector(1 downto 0);
697  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
698  gt6_txresetdone_out : out std_logic;
699  ------------------ Transmit Ports - pattern Generator Ports ----------------
700  gt6_txprbssel_in : in std_logic_vector(2 downto 0);
701 
702  --GT7 (X0Y7)
703  --____________________________CHANNEL PORTS________________________________
704  ---------------------------- Channel - DRP Ports --------------------------
705  gt7_drpaddr_in : in std_logic_vector(8 downto 0);
706  gt7_drpclk_in : in std_logic;
707  gt7_drpdi_in : in std_logic_vector(15 downto 0);
708  gt7_drpdo_out : out std_logic_vector(15 downto 0);
709  gt7_drpen_in : in std_logic;
710  gt7_drprdy_out : out std_logic;
711  gt7_drpwe_in : in std_logic;
712  --------------------------- Digital Monitor Ports --------------------------
713  gt7_dmonitorout_out : out std_logic_vector(7 downto 0);
714  ------------------------------- Loopback Ports -----------------------------
715  gt7_loopback_in : in std_logic_vector(2 downto 0);
716  ------------------------------ Power-Down Ports ----------------------------
717  gt7_rxpd_in : in std_logic_vector(1 downto 0);
718  gt7_txpd_in : in std_logic_vector(1 downto 0);
719  --------------------- RX Initialization and Reset Ports --------------------
720  gt7_eyescanreset_in : in std_logic;
721  gt7_rxuserrdy_in : in std_logic;
722  -------------------------- RX Margin Analysis Ports ------------------------
723  gt7_eyescandataerror_out : out std_logic;
724  gt7_eyescantrigger_in : in std_logic;
725  ------------------- Receive Ports - Clock Correction Ports -----------------
726  gt7_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
727  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
728  gt7_rxusrclk_in : in std_logic;
729  gt7_rxusrclk2_in : in std_logic;
730  ------------------ Receive Ports - FPGA RX interface Ports -----------------
731  gt7_rxdata_out : out std_logic_vector(15 downto 0);
732  ------------------- Receive Ports - Pattern Checker Ports ------------------
733  gt7_rxprbserr_out : out std_logic;
734  gt7_rxprbssel_in : in std_logic_vector(2 downto 0);
735  ------------------- Receive Ports - Pattern Checker ports ------------------
736  gt7_rxprbscntreset_in : in std_logic;
737  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
738  gt7_rxdisperr_out : out std_logic_vector(1 downto 0);
739  gt7_rxnotintable_out : out std_logic_vector(1 downto 0);
740  --------------------------- Receive Ports - RX AFE -------------------------
741  gt7_gtxrxp_in : in std_logic;
742  ------------------------ Receive Ports - RX AFE Ports ----------------------
743  gt7_gtxrxn_in : in std_logic;
744  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
745  gt7_rxbufstatus_out : out std_logic_vector(2 downto 0);
746  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
747  gt7_rxmcommaalignen_in : in std_logic;
748  gt7_rxpcommaalignen_in : in std_logic;
749  --------------------- Receive Ports - RX Equalizer Ports -------------------
750  gt7_rxdfeagchold_in : in std_logic;
751  gt7_rxdfelfhold_in : in std_logic;
752  gt7_rxdfelpmreset_in : in std_logic;
753  gt7_rxmonitorout_out : out std_logic_vector(6 downto 0);
754  gt7_rxmonitorsel_in : in std_logic_vector(1 downto 0);
755  --------------- Receive Ports - RX Fabric Output Control Ports -------------
756  gt7_rxoutclk_out : out std_logic;
757  gt7_rxoutclkfabric_out : out std_logic;
758  ------------- Receive Ports - RX Initialization and Reset Ports ------------
759  gt7_gtrxreset_in : in std_logic;
760  gt7_rxpmareset_in : in std_logic;
761  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
762  gt7_rxchariscomma_out : out std_logic_vector(1 downto 0);
763  gt7_rxcharisk_out : out std_logic_vector(1 downto 0);
764  -------------- Receive Ports -RX Initialization and Reset Ports ------------
765  gt7_rxresetdone_out : out std_logic;
766  --------------------- TX Initialization and Reset Ports --------------------
767  gt7_gttxreset_in : in std_logic;
768  gt7_txuserrdy_in : in std_logic;
769  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
770  gt7_txusrclk_in : in std_logic;
771  gt7_txusrclk2_in : in std_logic;
772  --------------- Transmit Ports - TX Configurable Driver Ports --------------
773  gt7_txdiffctrl_in : in std_logic_vector(3 downto 0);
774  ------------------ Transmit Ports - TX Data Path interface -----------------
775  gt7_txdata_in : in std_logic_vector(15 downto 0);
776  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
777  gt7_gtxtxn_out : out std_logic;
778  gt7_gtxtxp_out : out std_logic;
779  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
780  gt7_txoutclk_out : out std_logic;
781  gt7_txoutclkfabric_out : out std_logic;
782  gt7_txoutclkpcs_out : out std_logic;
783  --------------------- Transmit Ports - TX Gearbox Ports --------------------
784  gt7_txcharisk_in : in std_logic_vector(1 downto 0);
785  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
786  gt7_txresetdone_out : out std_logic;
787  ------------------ Transmit Ports - pattern Generator Ports ----------------
788  gt7_txprbssel_in : in std_logic_vector(2 downto 0);
789 
790  --GT8 (X0Y8)
791  --____________________________CHANNEL PORTS________________________________
792  ---------------------------- Channel - DRP Ports --------------------------
793  gt8_drpaddr_in : in std_logic_vector(8 downto 0);
794  gt8_drpclk_in : in std_logic;
795  gt8_drpdi_in : in std_logic_vector(15 downto 0);
796  gt8_drpdo_out : out std_logic_vector(15 downto 0);
797  gt8_drpen_in : in std_logic;
798  gt8_drprdy_out : out std_logic;
799  gt8_drpwe_in : in std_logic;
800  --------------------------- Digital Monitor Ports --------------------------
801  gt8_dmonitorout_out : out std_logic_vector(7 downto 0);
802  ------------------------------- Loopback Ports -----------------------------
803  gt8_loopback_in : in std_logic_vector(2 downto 0);
804  ------------------------------ Power-Down Ports ----------------------------
805  gt8_rxpd_in : in std_logic_vector(1 downto 0);
806  gt8_txpd_in : in std_logic_vector(1 downto 0);
807  --------------------- RX Initialization and Reset Ports --------------------
808  gt8_eyescanreset_in : in std_logic;
809  gt8_rxuserrdy_in : in std_logic;
810  -------------------------- RX Margin Analysis Ports ------------------------
811  gt8_eyescandataerror_out : out std_logic;
812  gt8_eyescantrigger_in : in std_logic;
813  ------------------- Receive Ports - Clock Correction Ports -----------------
814  gt8_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
815  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
816  gt8_rxusrclk_in : in std_logic;
817  gt8_rxusrclk2_in : in std_logic;
818  ------------------ Receive Ports - FPGA RX interface Ports -----------------
819  gt8_rxdata_out : out std_logic_vector(15 downto 0);
820  ------------------- Receive Ports - Pattern Checker Ports ------------------
821  gt8_rxprbserr_out : out std_logic;
822  gt8_rxprbssel_in : in std_logic_vector(2 downto 0);
823  ------------------- Receive Ports - Pattern Checker ports ------------------
824  gt8_rxprbscntreset_in : in std_logic;
825  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
826  gt8_rxdisperr_out : out std_logic_vector(1 downto 0);
827  gt8_rxnotintable_out : out std_logic_vector(1 downto 0);
828  --------------------------- Receive Ports - RX AFE -------------------------
829  gt8_gtxrxp_in : in std_logic;
830  ------------------------ Receive Ports - RX AFE Ports ----------------------
831  gt8_gtxrxn_in : in std_logic;
832  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
833  gt8_rxbufstatus_out : out std_logic_vector(2 downto 0);
834  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
835  gt8_rxmcommaalignen_in : in std_logic;
836  gt8_rxpcommaalignen_in : in std_logic;
837  --------------------- Receive Ports - RX Equalizer Ports -------------------
838  gt8_rxdfeagchold_in : in std_logic;
839  gt8_rxdfelfhold_in : in std_logic;
840  gt8_rxdfelpmreset_in : in std_logic;
841  gt8_rxmonitorout_out : out std_logic_vector(6 downto 0);
842  gt8_rxmonitorsel_in : in std_logic_vector(1 downto 0);
843  --------------- Receive Ports - RX Fabric Output Control Ports -------------
844  gt8_rxoutclk_out : out std_logic;
845  gt8_rxoutclkfabric_out : out std_logic;
846  ------------- Receive Ports - RX Initialization and Reset Ports ------------
847  gt8_gtrxreset_in : in std_logic;
848  gt8_rxpmareset_in : in std_logic;
849  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
850  gt8_rxchariscomma_out : out std_logic_vector(1 downto 0);
851  gt8_rxcharisk_out : out std_logic_vector(1 downto 0);
852  -------------- Receive Ports -RX Initialization and Reset Ports ------------
853  gt8_rxresetdone_out : out std_logic;
854  --------------------- TX Initialization and Reset Ports --------------------
855  gt8_gttxreset_in : in std_logic;
856  gt8_txuserrdy_in : in std_logic;
857  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
858  gt8_txusrclk_in : in std_logic;
859  gt8_txusrclk2_in : in std_logic;
860  --------------- Transmit Ports - TX Configurable Driver Ports --------------
861  gt8_txdiffctrl_in : in std_logic_vector(3 downto 0);
862  ------------------ Transmit Ports - TX Data Path interface -----------------
863  gt8_txdata_in : in std_logic_vector(15 downto 0);
864  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
865  gt8_gtxtxn_out : out std_logic;
866  gt8_gtxtxp_out : out std_logic;
867  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
868  gt8_txoutclk_out : out std_logic;
869  gt8_txoutclkfabric_out : out std_logic;
870  gt8_txoutclkpcs_out : out std_logic;
871  --------------------- Transmit Ports - TX Gearbox Ports --------------------
872  gt8_txcharisk_in : in std_logic_vector(1 downto 0);
873  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
874  gt8_txresetdone_out : out std_logic;
875  ------------------ Transmit Ports - pattern Generator Ports ----------------
876  gt8_txprbssel_in : in std_logic_vector(2 downto 0);
877 
878  --GT9 (X0Y9)
879  --____________________________CHANNEL PORTS________________________________
880  ---------------------------- Channel - DRP Ports --------------------------
881  gt9_drpaddr_in : in std_logic_vector(8 downto 0);
882  gt9_drpclk_in : in std_logic;
883  gt9_drpdi_in : in std_logic_vector(15 downto 0);
884  gt9_drpdo_out : out std_logic_vector(15 downto 0);
885  gt9_drpen_in : in std_logic;
886  gt9_drprdy_out : out std_logic;
887  gt9_drpwe_in : in std_logic;
888  --------------------------- Digital Monitor Ports --------------------------
889  gt9_dmonitorout_out : out std_logic_vector(7 downto 0);
890  ------------------------------- Loopback Ports -----------------------------
891  gt9_loopback_in : in std_logic_vector(2 downto 0);
892  ------------------------------ Power-Down Ports ----------------------------
893  gt9_rxpd_in : in std_logic_vector(1 downto 0);
894  gt9_txpd_in : in std_logic_vector(1 downto 0);
895  --------------------- RX Initialization and Reset Ports --------------------
896  gt9_eyescanreset_in : in std_logic;
897  gt9_rxuserrdy_in : in std_logic;
898  -------------------------- RX Margin Analysis Ports ------------------------
899  gt9_eyescandataerror_out : out std_logic;
900  gt9_eyescantrigger_in : in std_logic;
901  ------------------- Receive Ports - Clock Correction Ports -----------------
902  gt9_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
903  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
904  gt9_rxusrclk_in : in std_logic;
905  gt9_rxusrclk2_in : in std_logic;
906  ------------------ Receive Ports - FPGA RX interface Ports -----------------
907  gt9_rxdata_out : out std_logic_vector(15 downto 0);
908  ------------------- Receive Ports - Pattern Checker Ports ------------------
909  gt9_rxprbserr_out : out std_logic;
910  gt9_rxprbssel_in : in std_logic_vector(2 downto 0);
911  ------------------- Receive Ports - Pattern Checker ports ------------------
912  gt9_rxprbscntreset_in : in std_logic;
913  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
914  gt9_rxdisperr_out : out std_logic_vector(1 downto 0);
915  gt9_rxnotintable_out : out std_logic_vector(1 downto 0);
916  --------------------------- Receive Ports - RX AFE -------------------------
917  gt9_gtxrxp_in : in std_logic;
918  ------------------------ Receive Ports - RX AFE Ports ----------------------
919  gt9_gtxrxn_in : in std_logic;
920  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
921  gt9_rxbufstatus_out : out std_logic_vector(2 downto 0);
922  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
923  gt9_rxmcommaalignen_in : in std_logic;
924  gt9_rxpcommaalignen_in : in std_logic;
925  --------------------- Receive Ports - RX Equalizer Ports -------------------
926  gt9_rxdfeagchold_in : in std_logic;
927  gt9_rxdfelfhold_in : in std_logic;
928  gt9_rxdfelpmreset_in : in std_logic;
929  gt9_rxmonitorout_out : out std_logic_vector(6 downto 0);
930  gt9_rxmonitorsel_in : in std_logic_vector(1 downto 0);
931  --------------- Receive Ports - RX Fabric Output Control Ports -------------
932  gt9_rxoutclk_out : out std_logic;
933  gt9_rxoutclkfabric_out : out std_logic;
934  ------------- Receive Ports - RX Initialization and Reset Ports ------------
935  gt9_gtrxreset_in : in std_logic;
936  gt9_rxpmareset_in : in std_logic;
937  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
938  gt9_rxchariscomma_out : out std_logic_vector(1 downto 0);
939  gt9_rxcharisk_out : out std_logic_vector(1 downto 0);
940  -------------- Receive Ports -RX Initialization and Reset Ports ------------
941  gt9_rxresetdone_out : out std_logic;
942  --------------------- TX Initialization and Reset Ports --------------------
943  gt9_gttxreset_in : in std_logic;
944  gt9_txuserrdy_in : in std_logic;
945  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
946  gt9_txusrclk_in : in std_logic;
947  gt9_txusrclk2_in : in std_logic;
948  --------------- Transmit Ports - TX Configurable Driver Ports --------------
949  gt9_txdiffctrl_in : in std_logic_vector(3 downto 0);
950  ------------------ Transmit Ports - TX Data Path interface -----------------
951  gt9_txdata_in : in std_logic_vector(15 downto 0);
952  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
953  gt9_gtxtxn_out : out std_logic;
954  gt9_gtxtxp_out : out std_logic;
955  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
956  gt9_txoutclk_out : out std_logic;
957  gt9_txoutclkfabric_out : out std_logic;
958  gt9_txoutclkpcs_out : out std_logic;
959  --------------------- Transmit Ports - TX Gearbox Ports --------------------
960  gt9_txcharisk_in : in std_logic_vector(1 downto 0);
961  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
962  gt9_txresetdone_out : out std_logic;
963  ------------------ Transmit Ports - pattern Generator Ports ----------------
964  gt9_txprbssel_in : in std_logic_vector(2 downto 0);
965 
966  --GT10 (X0Y10)
967  --____________________________CHANNEL PORTS________________________________
968  ---------------------------- Channel - DRP Ports --------------------------
969  gt10_drpaddr_in : in std_logic_vector(8 downto 0);
970  gt10_drpclk_in : in std_logic;
971  gt10_drpdi_in : in std_logic_vector(15 downto 0);
972  gt10_drpdo_out : out std_logic_vector(15 downto 0);
973  gt10_drpen_in : in std_logic;
974  gt10_drprdy_out : out std_logic;
975  gt10_drpwe_in : in std_logic;
976  --------------------------- Digital Monitor Ports --------------------------
977  gt10_dmonitorout_out : out std_logic_vector(7 downto 0);
978  ------------------------------- Loopback Ports -----------------------------
979  gt10_loopback_in : in std_logic_vector(2 downto 0);
980  ------------------------------ Power-Down Ports ----------------------------
981  gt10_rxpd_in : in std_logic_vector(1 downto 0);
982  gt10_txpd_in : in std_logic_vector(1 downto 0);
983  --------------------- RX Initialization and Reset Ports --------------------
984  gt10_eyescanreset_in : in std_logic;
985  gt10_rxuserrdy_in : in std_logic;
986  -------------------------- RX Margin Analysis Ports ------------------------
987  gt10_eyescandataerror_out : out std_logic;
988  gt10_eyescantrigger_in : in std_logic;
989  ------------------- Receive Ports - Clock Correction Ports -----------------
990  gt10_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
991  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
992  gt10_rxusrclk_in : in std_logic;
993  gt10_rxusrclk2_in : in std_logic;
994  ------------------ Receive Ports - FPGA RX interface Ports -----------------
995  gt10_rxdata_out : out std_logic_vector(15 downto 0);
996  ------------------- Receive Ports - Pattern Checker Ports ------------------
997  gt10_rxprbserr_out : out std_logic;
998  gt10_rxprbssel_in : in std_logic_vector(2 downto 0);
999  ------------------- Receive Ports - Pattern Checker ports ------------------
1000  gt10_rxprbscntreset_in : in std_logic;
1001  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1002  gt10_rxdisperr_out : out std_logic_vector(1 downto 0);
1003  gt10_rxnotintable_out : out std_logic_vector(1 downto 0);
1004  --------------------------- Receive Ports - RX AFE -------------------------
1005  gt10_gtxrxp_in : in std_logic;
1006  ------------------------ Receive Ports - RX AFE Ports ----------------------
1007  gt10_gtxrxn_in : in std_logic;
1008  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1009  gt10_rxbufstatus_out : out std_logic_vector(2 downto 0);
1010  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1011  gt10_rxmcommaalignen_in : in std_logic;
1012  gt10_rxpcommaalignen_in : in std_logic;
1013  --------------------- Receive Ports - RX Equalizer Ports -------------------
1014  gt10_rxdfeagchold_in : in std_logic;
1015  gt10_rxdfelfhold_in : in std_logic;
1016  gt10_rxdfelpmreset_in : in std_logic;
1017  gt10_rxmonitorout_out : out std_logic_vector(6 downto 0);
1018  gt10_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1019  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1020  gt10_rxoutclk_out : out std_logic;
1021  gt10_rxoutclkfabric_out : out std_logic;
1022  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1023  gt10_gtrxreset_in : in std_logic;
1024  gt10_rxpmareset_in : in std_logic;
1025  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1026  gt10_rxchariscomma_out : out std_logic_vector(1 downto 0);
1027  gt10_rxcharisk_out : out std_logic_vector(1 downto 0);
1028  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1029  gt10_rxresetdone_out : out std_logic;
1030  --------------------- TX Initialization and Reset Ports --------------------
1031  gt10_gttxreset_in : in std_logic;
1032  gt10_txuserrdy_in : in std_logic;
1033  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1034  gt10_txusrclk_in : in std_logic;
1035  gt10_txusrclk2_in : in std_logic;
1036  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1037  gt10_txdiffctrl_in : in std_logic_vector(3 downto 0);
1038  ------------------ Transmit Ports - TX Data Path interface -----------------
1039  gt10_txdata_in : in std_logic_vector(15 downto 0);
1040  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1041  gt10_gtxtxn_out : out std_logic;
1042  gt10_gtxtxp_out : out std_logic;
1043  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1044  gt10_txoutclk_out : out std_logic;
1045  gt10_txoutclkfabric_out : out std_logic;
1046  gt10_txoutclkpcs_out : out std_logic;
1047  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1048  gt10_txcharisk_in : in std_logic_vector(1 downto 0);
1049  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1050  gt10_txresetdone_out : out std_logic;
1051  ------------------ Transmit Ports - pattern Generator Ports ----------------
1052  gt10_txprbssel_in : in std_logic_vector(2 downto 0);
1053 
1054  --GT11 (X0Y11)
1055  --____________________________CHANNEL PORTS________________________________
1056  ---------------------------- Channel - DRP Ports --------------------------
1057  gt11_drpaddr_in : in std_logic_vector(8 downto 0);
1058  gt11_drpclk_in : in std_logic;
1059  gt11_drpdi_in : in std_logic_vector(15 downto 0);
1060  gt11_drpdo_out : out std_logic_vector(15 downto 0);
1061  gt11_drpen_in : in std_logic;
1062  gt11_drprdy_out : out std_logic;
1063  gt11_drpwe_in : in std_logic;
1064  --------------------------- Digital Monitor Ports --------------------------
1065  gt11_dmonitorout_out : out std_logic_vector(7 downto 0);
1066  ------------------------------- Loopback Ports -----------------------------
1067  gt11_loopback_in : in std_logic_vector(2 downto 0);
1068  ------------------------------ Power-Down Ports ----------------------------
1069  gt11_rxpd_in : in std_logic_vector(1 downto 0);
1070  gt11_txpd_in : in std_logic_vector(1 downto 0);
1071  --------------------- RX Initialization and Reset Ports --------------------
1072  gt11_eyescanreset_in : in std_logic;
1073  gt11_rxuserrdy_in : in std_logic;
1074  -------------------------- RX Margin Analysis Ports ------------------------
1075  gt11_eyescandataerror_out : out std_logic;
1076  gt11_eyescantrigger_in : in std_logic;
1077  ------------------- Receive Ports - Clock Correction Ports -----------------
1078  gt11_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1079  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1080  gt11_rxusrclk_in : in std_logic;
1081  gt11_rxusrclk2_in : in std_logic;
1082  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1083  gt11_rxdata_out : out std_logic_vector(15 downto 0);
1084  ------------------- Receive Ports - Pattern Checker Ports ------------------
1085  gt11_rxprbserr_out : out std_logic;
1086  gt11_rxprbssel_in : in std_logic_vector(2 downto 0);
1087  ------------------- Receive Ports - Pattern Checker ports ------------------
1088  gt11_rxprbscntreset_in : in std_logic;
1089  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1090  gt11_rxdisperr_out : out std_logic_vector(1 downto 0);
1091  gt11_rxnotintable_out : out std_logic_vector(1 downto 0);
1092  --------------------------- Receive Ports - RX AFE -------------------------
1093  gt11_gtxrxp_in : in std_logic;
1094  ------------------------ Receive Ports - RX AFE Ports ----------------------
1095  gt11_gtxrxn_in : in std_logic;
1096  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1097  gt11_rxbufstatus_out : out std_logic_vector(2 downto 0);
1098  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1099  gt11_rxmcommaalignen_in : in std_logic;
1100  gt11_rxpcommaalignen_in : in std_logic;
1101  --------------------- Receive Ports - RX Equalizer Ports -------------------
1102  gt11_rxdfeagchold_in : in std_logic;
1103  gt11_rxdfelfhold_in : in std_logic;
1104  gt11_rxdfelpmreset_in : in std_logic;
1105  gt11_rxmonitorout_out : out std_logic_vector(6 downto 0);
1106  gt11_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1107  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1108  gt11_rxoutclk_out : out std_logic;
1109  gt11_rxoutclkfabric_out : out std_logic;
1110  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1111  gt11_gtrxreset_in : in std_logic;
1112  gt11_rxpmareset_in : in std_logic;
1113  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1114  gt11_rxchariscomma_out : out std_logic_vector(1 downto 0);
1115  gt11_rxcharisk_out : out std_logic_vector(1 downto 0);
1116  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1117  gt11_rxresetdone_out : out std_logic;
1118  --------------------- TX Initialization and Reset Ports --------------------
1119  gt11_gttxreset_in : in std_logic;
1120  gt11_txuserrdy_in : in std_logic;
1121  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1122  gt11_txusrclk_in : in std_logic;
1123  gt11_txusrclk2_in : in std_logic;
1124  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1125  gt11_txdiffctrl_in : in std_logic_vector(3 downto 0);
1126  ------------------ Transmit Ports - TX Data Path interface -----------------
1127  gt11_txdata_in : in std_logic_vector(15 downto 0);
1128  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1129  gt11_gtxtxn_out : out std_logic;
1130  gt11_gtxtxp_out : out std_logic;
1131  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1132  gt11_txoutclk_out : out std_logic;
1133  gt11_txoutclkfabric_out : out std_logic;
1134  gt11_txoutclkpcs_out : out std_logic;
1135  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1136  gt11_txcharisk_in : in std_logic_vector(1 downto 0);
1137  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1138  gt11_txresetdone_out : out std_logic;
1139  ------------------ Transmit Ports - pattern Generator Ports ----------------
1140  gt11_txprbssel_in : in std_logic_vector(2 downto 0);
1141 
1142 
1143  --____________________________COMMON PORTS________________________________
1144  GT0_QPLLOUTCLK_IN : in std_logic;
1145  GT0_QPLLOUTREFCLK_IN : in std_logic;
1146  --____________________________COMMON PORTS________________________________
1147  GT1_QPLLOUTCLK_IN : in std_logic;
1148  GT1_QPLLOUTREFCLK_IN : in std_logic;
1149  --____________________________COMMON PORTS________________________________
1150  GT2_QPLLOUTCLK_IN : in std_logic;
1151  GT2_QPLLOUTREFCLK_IN : in std_logic
1152 
1153 );
1154 
1155 
1156 end amc_gtx5Gpd_multi_gt;
1157 
1158 architecture RTL of amc_gtx5Gpd_multi_gt is
1159  attribute DowngradeIPIdentifiedWarnings: string;
1160  attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
1161 
1162  attribute CORE_GENERATION_INFO : string;
1163  attribute CORE_GENERATION_INFO of RTL : architecture is "amc_gtx5Gpd_multi_gt,gtwizard_v3_6_1,{protocol_file=Start_from_scratch}";
1164 
1165 
1166 --***********************************Parameter Declarations********************
1167 
1168  constant DLY : time := 1 ns;
1169 
1170 --***************************** Signal Declarations *****************************
1171 
1172  -- ground and tied_to_vcc_i signals
1173  signal tied_to_ground_i : std_logic;
1174  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
1175  signal tied_to_vcc_i : std_logic;
1176  signal gt0_qplloutclk_i : std_logic;
1177  signal gt0_qplloutrefclk_i : std_logic;
1178  signal gt1_qplloutclk_i : std_logic;
1179  signal gt1_qplloutrefclk_i : std_logic;
1180  signal gt2_qplloutclk_i : std_logic;
1181  signal gt2_qplloutrefclk_i : std_logic;
1182 
1183  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
1184  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1185  signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0);
1186  signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1187  signal gt2_mgtrefclktx_i : std_logic_vector(1 downto 0);
1188  signal gt2_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1189  signal gt3_mgtrefclktx_i : std_logic_vector(1 downto 0);
1190  signal gt3_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1191  signal gt4_mgtrefclktx_i : std_logic_vector(1 downto 0);
1192  signal gt4_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1193  signal gt5_mgtrefclktx_i : std_logic_vector(1 downto 0);
1194  signal gt5_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1195  signal gt6_mgtrefclktx_i : std_logic_vector(1 downto 0);
1196  signal gt6_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1197  signal gt7_mgtrefclktx_i : std_logic_vector(1 downto 0);
1198  signal gt7_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1199  signal gt8_mgtrefclktx_i : std_logic_vector(1 downto 0);
1200  signal gt8_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1201  signal gt9_mgtrefclktx_i : std_logic_vector(1 downto 0);
1202  signal gt9_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1203  signal gt10_mgtrefclktx_i : std_logic_vector(1 downto 0);
1204  signal gt10_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1205  signal gt11_mgtrefclktx_i : std_logic_vector(1 downto 0);
1206  signal gt11_mgtrefclkrx_i : std_logic_vector(1 downto 0);
1207 
1208 
1209 
1210 
1211 
1212 
1213 
1214 
1215 
1216 
1217 
1218 
1219 
1220 
1221 
1222 
1223 
1224 
1225 
1226 
1227 
1228 
1229 
1230 
1231 
1232 
1233  signal gt0_qpllclk_i : std_logic;
1234  signal gt0_qpllrefclk_i : std_logic;
1235  signal gt1_qpllclk_i : std_logic;
1236  signal gt1_qpllrefclk_i : std_logic;
1237  signal gt2_qpllclk_i : std_logic;
1238  signal gt2_qpllrefclk_i : std_logic;
1239  signal gt3_qpllclk_i : std_logic;
1240  signal gt3_qpllrefclk_i : std_logic;
1241  signal gt4_qpllclk_i : std_logic;
1242  signal gt4_qpllrefclk_i : std_logic;
1243  signal gt5_qpllclk_i : std_logic;
1244  signal gt5_qpllrefclk_i : std_logic;
1245  signal gt6_qpllclk_i : std_logic;
1246  signal gt6_qpllrefclk_i : std_logic;
1247  signal gt7_qpllclk_i : std_logic;
1248  signal gt7_qpllrefclk_i : std_logic;
1249  signal gt8_qpllclk_i : std_logic;
1250  signal gt8_qpllrefclk_i : std_logic;
1251  signal gt9_qpllclk_i : std_logic;
1252  signal gt9_qpllrefclk_i : std_logic;
1253  signal gt10_qpllclk_i : std_logic;
1254  signal gt10_qpllrefclk_i : std_logic;
1255  signal gt11_qpllclk_i : std_logic;
1256  signal gt11_qpllrefclk_i : std_logic;
1257  signal gt0_cpllreset_i : std_logic;
1258  signal gt0_cpllpd_i : std_logic;
1259  signal gt1_cpllreset_i : std_logic;
1260  signal gt1_cpllpd_i : std_logic;
1261  signal gt2_cpllreset_i : std_logic;
1262  signal gt2_cpllpd_i : std_logic;
1263  signal gt3_cpllreset_i : std_logic;
1264  signal gt3_cpllpd_i : std_logic;
1265  signal gt4_cpllreset_i : std_logic;
1266  signal gt4_cpllpd_i : std_logic;
1267  signal gt5_cpllreset_i : std_logic;
1268  signal gt5_cpllpd_i : std_logic;
1269  signal gt6_cpllreset_i : std_logic;
1270  signal gt6_cpllpd_i : std_logic;
1271  signal gt7_cpllreset_i : std_logic;
1272  signal gt7_cpllpd_i : std_logic;
1273  signal gt8_cpllreset_i : std_logic;
1274  signal gt8_cpllpd_i : std_logic;
1275  signal gt9_cpllreset_i : std_logic;
1276  signal gt9_cpllpd_i : std_logic;
1277  signal gt10_cpllreset_i : std_logic;
1278  signal gt10_cpllpd_i : std_logic;
1279  signal gt11_cpllreset_i : std_logic;
1280  signal gt11_cpllpd_i : std_logic;
1281 
1282 --*************************** Component Declarations **************************
1283 component amc_gtx5Gpd_GT
1284 generic
1285 (
1286  -- Simulation attributes
1287  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
1288  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
1289  PMA_RSV_IN : bit_vector := X"00000000";
1290  SIM_CPLLREFCLK_SEL : bit_vector := "001";
1291  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
1292 );
1293 port
1294 (
1295  cpllrefclksel_in : in std_logic_vector (2 downto 0);
1296  ---------------------------- Channel - DRP Ports --------------------------
1297  drpaddr_in : in std_logic_vector(8 downto 0);
1298  drpclk_in : in std_logic;
1299  drpdi_in : in std_logic_vector(15 downto 0);
1300  drpdo_out : out std_logic_vector(15 downto 0);
1301  drpen_in : in std_logic;
1302  drprdy_out : out std_logic;
1303  drpwe_in : in std_logic;
1304  ------------------------------- Clocking Ports -----------------------------
1305  qpllclk_in : in std_logic;
1306  qpllrefclk_in : in std_logic;
1307  --------------------------- Digital Monitor Ports --------------------------
1308  dmonitorout_out : out std_logic_vector(7 downto 0);
1309  ------------------------------- Loopback Ports -----------------------------
1310  loopback_in : in std_logic_vector(2 downto 0);
1311  ------------------------------ Power-Down Ports ----------------------------
1312  rxpd_in : in std_logic_vector(1 downto 0);
1313  txpd_in : in std_logic_vector(1 downto 0);
1314  --------------------- RX Initialization and Reset Ports --------------------
1315  eyescanreset_in : in std_logic;
1316  rxuserrdy_in : in std_logic;
1317  -------------------------- RX Margin Analysis Ports ------------------------
1318  eyescandataerror_out : out std_logic;
1319  eyescantrigger_in : in std_logic;
1320  ------------------- Receive Ports - Clock Correction Ports -----------------
1321  rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1322  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1323  rxusrclk_in : in std_logic;
1324  rxusrclk2_in : in std_logic;
1325  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1326  rxdata_out : out std_logic_vector(15 downto 0);
1327  ------------------- Receive Ports - Pattern Checker Ports ------------------
1328  rxprbserr_out : out std_logic;
1329  rxprbssel_in : in std_logic_vector(2 downto 0);
1330  ------------------- Receive Ports - Pattern Checker ports ------------------
1331  rxprbscntreset_in : in std_logic;
1332  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1333  rxdisperr_out : out std_logic_vector(1 downto 0);
1334  rxnotintable_out : out std_logic_vector(1 downto 0);
1335  --------------------------- Receive Ports - RX AFE -------------------------
1336  gtxrxp_in : in std_logic;
1337  ------------------------ Receive Ports - RX AFE Ports ----------------------
1338  gtxrxn_in : in std_logic;
1339  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1340  rxbufstatus_out : out std_logic_vector(2 downto 0);
1341  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1342  rxmcommaalignen_in : in std_logic;
1343  rxpcommaalignen_in : in std_logic;
1344  --------------------- Receive Ports - RX Equalizer Ports -------------------
1345  rxdfeagchold_in : in std_logic;
1346  rxdfelfhold_in : in std_logic;
1347  rxdfelpmreset_in : in std_logic;
1348  rxmonitorout_out : out std_logic_vector(6 downto 0);
1349  rxmonitorsel_in : in std_logic_vector(1 downto 0);
1350  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1351  rxoutclk_out : out std_logic;
1352  rxoutclkfabric_out : out std_logic;
1353  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1354  gtrxreset_in : in std_logic;
1355  rxpmareset_in : in std_logic;
1356  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1357  rxchariscomma_out : out std_logic_vector(1 downto 0);
1358  rxcharisk_out : out std_logic_vector(1 downto 0);
1359  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1360  rxresetdone_out : out std_logic;
1361  --------------------- TX Initialization and Reset Ports --------------------
1362  gttxreset_in : in std_logic;
1363  txuserrdy_in : in std_logic;
1364  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1365  txusrclk_in : in std_logic;
1366  txusrclk2_in : in std_logic;
1367  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1368  txdiffctrl_in : in std_logic_vector(3 downto 0);
1369  ------------------ Transmit Ports - TX Data Path interface -----------------
1370  txdata_in : in std_logic_vector(15 downto 0);
1371  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1372  gtxtxn_out : out std_logic;
1373  gtxtxp_out : out std_logic;
1374  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1375  txoutclk_out : out std_logic;
1376  txoutclkfabric_out : out std_logic;
1377  txoutclkpcs_out : out std_logic;
1378  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1379  txcharisk_in : in std_logic_vector(1 downto 0);
1380  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1381  txresetdone_out : out std_logic;
1382  ------------------ Transmit Ports - pattern Generator Ports ----------------
1383  txprbssel_in : in std_logic_vector(2 downto 0)
1384 
1385 
1386 );
1387 end component;
1388 
1389 
1390 
1391 --********************************* Main Body of Code**************************
1392 
1393 begin
1394 
1395  tied_to_ground_i <= '0';
1396  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
1397  tied_to_vcc_i <= '1';
1398  gt0_qpllclk_i <= GT0_QPLLOUTCLK_IN;
1399  gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN;
1400 
1401  gt1_qpllclk_i <= GT0_QPLLOUTCLK_IN;
1402  gt1_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN;
1403 
1404  gt2_qpllclk_i <= GT0_QPLLOUTCLK_IN;
1405  gt2_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN;
1406 
1407  gt3_qpllclk_i <= GT0_QPLLOUTCLK_IN;
1408  gt3_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN;
1409 
1410  gt4_qpllclk_i <= GT1_QPLLOUTCLK_IN;
1411  gt4_qpllrefclk_i <= GT1_QPLLOUTREFCLK_IN;
1412 
1413  gt5_qpllclk_i <= GT1_QPLLOUTCLK_IN;
1414  gt5_qpllrefclk_i <= GT1_QPLLOUTREFCLK_IN;
1415 
1416  gt6_qpllclk_i <= GT1_QPLLOUTCLK_IN;
1417  gt6_qpllrefclk_i <= GT1_QPLLOUTREFCLK_IN;
1418 
1419  gt7_qpllclk_i <= GT1_QPLLOUTCLK_IN;
1420  gt7_qpllrefclk_i <= GT1_QPLLOUTREFCLK_IN;
1421 
1422  gt8_qpllclk_i <= GT2_QPLLOUTCLK_IN;
1423  gt8_qpllrefclk_i <= GT2_QPLLOUTREFCLK_IN;
1424 
1425  gt9_qpllclk_i <= GT2_QPLLOUTCLK_IN;
1426  gt9_qpllrefclk_i <= GT2_QPLLOUTREFCLK_IN;
1427 
1428  gt10_qpllclk_i <= GT2_QPLLOUTCLK_IN;
1429  gt10_qpllrefclk_i <= GT2_QPLLOUTREFCLK_IN;
1430 
1431  gt11_qpllclk_i <= GT2_QPLLOUTCLK_IN;
1432  gt11_qpllrefclk_i <= GT2_QPLLOUTREFCLK_IN;
1433 
1434 
1435 
1436  --------------------------- GT Instances -------------------------------
1437 
1438 
1439  --_________________________________________________________________________
1440  --_________________________________________________________________________
1441  --GT0 (X0Y0)
1442 
1443 gt0_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
1444  generic map
1445  (
1446  -- Simulation attributes
1447  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
1448  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
1449  SIM_CPLLREFCLK_SEL => "001",
1450  PMA_RSV_IN => PMA_RSV_IN,
1451  PCS_RSVD_ATTR_IN => X"000000000000"
1452  )
1453  port map
1454  (
1455  cpllrefclksel_in => "001",
1456  ---------------------------- Channel - DRP Ports --------------------------
1457  drpaddr_in => gt0_drpaddr_in,
1458  drpclk_in => gt0_drpclk_in,
1459  drpdi_in => gt0_drpdi_in,
1460  drpdo_out => gt0_drpdo_out,
1461  drpen_in => gt0_drpen_in,
1462  drprdy_out => gt0_drprdy_out,
1463  drpwe_in => gt0_drpwe_in,
1464  ------------------------------- Clocking Ports -----------------------------
1465  qpllclk_in => gt0_qpllclk_i,
1466  qpllrefclk_in => gt0_qpllrefclk_i,
1467  --------------------------- Digital Monitor Ports --------------------------
1468  dmonitorout_out => gt0_dmonitorout_out ,
1469  ------------------------------- Loopback Ports -----------------------------
1470  loopback_in => gt0_loopback_in,
1471  ------------------------------ Power-Down Ports ----------------------------
1472  rxpd_in => gt0_rxpd_in,
1473  txpd_in => gt0_txpd_in,
1474  --------------------- RX Initialization and Reset Ports --------------------
1475  eyescanreset_in => gt0_eyescanreset_in ,
1476  rxuserrdy_in => gt0_rxuserrdy_in,
1477  -------------------------- RX Margin Analysis Ports ------------------------
1478  eyescandataerror_out => gt0_eyescandataerror_out,
1479  eyescantrigger_in => gt0_eyescantrigger_in ,
1480  ------------------- Receive Ports - Clock Correction Ports -----------------
1481  rxclkcorcnt_out => gt0_rxclkcorcnt_out ,
1482  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1483  rxusrclk_in => gt0_rxusrclk_in,
1484  rxusrclk2_in => gt0_rxusrclk2_in,
1485  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1486  rxdata_out => gt0_rxdata_out,
1487  ------------------- Receive Ports - Pattern Checker Ports ------------------
1488  rxprbserr_out => gt0_rxprbserr_out,
1489  rxprbssel_in => gt0_rxprbssel_in,
1490  ------------------- Receive Ports - Pattern Checker ports ------------------
1491  rxprbscntreset_in => gt0_rxprbscntreset_in ,
1492  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1493  rxdisperr_out => gt0_rxdisperr_out,
1494  rxnotintable_out => gt0_rxnotintable_out ,
1495  --------------------------- Receive Ports - RX AFE -------------------------
1496  gtxrxp_in => gt0_gtxrxp_in,
1497  ------------------------ Receive Ports - RX AFE Ports ----------------------
1498  gtxrxn_in => gt0_gtxrxn_in,
1499  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1500  rxbufstatus_out => gt0_rxbufstatus_out ,
1501  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1502  rxmcommaalignen_in => gt0_rxmcommaalignen_in ,
1503  rxpcommaalignen_in => gt0_rxpcommaalignen_in ,
1504  --------------------- Receive Ports - RX Equalizer Ports -------------------
1505  rxdfeagchold_in => gt0_rxdfeagchold_in ,
1506  rxdfelfhold_in => gt0_rxdfelfhold_in,
1507  rxdfelpmreset_in => gt0_rxdfelpmreset_in ,
1508  rxmonitorout_out => gt0_rxmonitorout_out ,
1509  rxmonitorsel_in => gt0_rxmonitorsel_in ,
1510  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1511  rxoutclk_out => gt0_rxoutclk_out,
1512  rxoutclkfabric_out => gt0_rxoutclkfabric_out ,
1513  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1514  gtrxreset_in => gt0_gtrxreset_in,
1515  rxpmareset_in => gt0_rxpmareset_in,
1516  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1517  rxchariscomma_out => gt0_rxchariscomma_out ,
1518  rxcharisk_out => gt0_rxcharisk_out,
1519  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1520  rxresetdone_out => gt0_rxresetdone_out ,
1521  --------------------- TX Initialization and Reset Ports --------------------
1522  gttxreset_in => gt0_gttxreset_in,
1523  txuserrdy_in => gt0_txuserrdy_in,
1524  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1525  txusrclk_in => gt0_txusrclk_in,
1526  txusrclk2_in => gt0_txusrclk2_in,
1527  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1528  txdiffctrl_in => gt0_txdiffctrl_in,
1529  ------------------ Transmit Ports - TX Data Path interface -----------------
1530  txdata_in => gt0_txdata_in,
1531  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1532  gtxtxn_out => gt0_gtxtxn_out,
1533  gtxtxp_out => gt0_gtxtxp_out,
1534  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1535  txoutclk_out => gt0_txoutclk_out,
1536  txoutclkfabric_out => gt0_txoutclkfabric_out ,
1537  txoutclkpcs_out => gt0_txoutclkpcs_out ,
1538  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1539  txcharisk_in => gt0_txcharisk_in,
1540  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1541  txresetdone_out => gt0_txresetdone_out ,
1542  ------------------ Transmit Ports - pattern Generator Ports ----------------
1543  txprbssel_in => gt0_txprbssel_in
1544 
1545  );
1546 
1547 
1548 
1549  --_________________________________________________________________________
1550  --_________________________________________________________________________
1551  --GT1 (X0Y1)
1552 
1553 gt1_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
1554  generic map
1555  (
1556  -- Simulation attributes
1557  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
1558  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
1559  SIM_CPLLREFCLK_SEL => "001",
1560  PMA_RSV_IN => PMA_RSV_IN,
1561  PCS_RSVD_ATTR_IN => X"000000000000"
1562  )
1563  port map
1564  (
1565  cpllrefclksel_in => "001",
1566  ---------------------------- Channel - DRP Ports --------------------------
1567  drpaddr_in => gt1_drpaddr_in,
1568  drpclk_in => gt1_drpclk_in,
1569  drpdi_in => gt1_drpdi_in,
1570  drpdo_out => gt1_drpdo_out,
1571  drpen_in => gt1_drpen_in,
1572  drprdy_out => gt1_drprdy_out,
1573  drpwe_in => gt1_drpwe_in,
1574  ------------------------------- Clocking Ports -----------------------------
1575  qpllclk_in => gt1_qpllclk_i,
1576  qpllrefclk_in => gt1_qpllrefclk_i,
1577  --------------------------- Digital Monitor Ports --------------------------
1578  dmonitorout_out => gt1_dmonitorout_out ,
1579  ------------------------------- Loopback Ports -----------------------------
1580  loopback_in => gt1_loopback_in,
1581  ------------------------------ Power-Down Ports ----------------------------
1582  rxpd_in => gt1_rxpd_in,
1583  txpd_in => gt1_txpd_in,
1584  --------------------- RX Initialization and Reset Ports --------------------
1585  eyescanreset_in => gt1_eyescanreset_in ,
1586  rxuserrdy_in => gt1_rxuserrdy_in,
1587  -------------------------- RX Margin Analysis Ports ------------------------
1588  eyescandataerror_out => gt1_eyescandataerror_out,
1589  eyescantrigger_in => gt1_eyescantrigger_in ,
1590  ------------------- Receive Ports - Clock Correction Ports -----------------
1591  rxclkcorcnt_out => gt1_rxclkcorcnt_out ,
1592  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1593  rxusrclk_in => gt1_rxusrclk_in,
1594  rxusrclk2_in => gt1_rxusrclk2_in,
1595  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1596  rxdata_out => gt1_rxdata_out,
1597  ------------------- Receive Ports - Pattern Checker Ports ------------------
1598  rxprbserr_out => gt1_rxprbserr_out,
1599  rxprbssel_in => gt1_rxprbssel_in,
1600  ------------------- Receive Ports - Pattern Checker ports ------------------
1601  rxprbscntreset_in => gt1_rxprbscntreset_in ,
1602  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1603  rxdisperr_out => gt1_rxdisperr_out,
1604  rxnotintable_out => gt1_rxnotintable_out ,
1605  --------------------------- Receive Ports - RX AFE -------------------------
1606  gtxrxp_in => gt1_gtxrxp_in,
1607  ------------------------ Receive Ports - RX AFE Ports ----------------------
1608  gtxrxn_in => gt1_gtxrxn_in,
1609  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1610  rxbufstatus_out => gt1_rxbufstatus_out ,
1611  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1612  rxmcommaalignen_in => gt1_rxmcommaalignen_in ,
1613  rxpcommaalignen_in => gt1_rxpcommaalignen_in ,
1614  --------------------- Receive Ports - RX Equalizer Ports -------------------
1615  rxdfeagchold_in => gt1_rxdfeagchold_in ,
1616  rxdfelfhold_in => gt1_rxdfelfhold_in,
1617  rxdfelpmreset_in => gt1_rxdfelpmreset_in ,
1618  rxmonitorout_out => gt1_rxmonitorout_out ,
1619  rxmonitorsel_in => gt1_rxmonitorsel_in ,
1620  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1621  rxoutclk_out => gt1_rxoutclk_out,
1622  rxoutclkfabric_out => gt1_rxoutclkfabric_out ,
1623  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1624  gtrxreset_in => gt1_gtrxreset_in,
1625  rxpmareset_in => gt1_rxpmareset_in,
1626  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1627  rxchariscomma_out => gt1_rxchariscomma_out ,
1628  rxcharisk_out => gt1_rxcharisk_out,
1629  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1630  rxresetdone_out => gt1_rxresetdone_out ,
1631  --------------------- TX Initialization and Reset Ports --------------------
1632  gttxreset_in => gt1_gttxreset_in,
1633  txuserrdy_in => gt1_txuserrdy_in,
1634  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1635  txusrclk_in => gt1_txusrclk_in,
1636  txusrclk2_in => gt1_txusrclk2_in,
1637  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1638  txdiffctrl_in => gt1_txdiffctrl_in,
1639  ------------------ Transmit Ports - TX Data Path interface -----------------
1640  txdata_in => gt1_txdata_in,
1641  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1642  gtxtxn_out => gt1_gtxtxn_out,
1643  gtxtxp_out => gt1_gtxtxp_out,
1644  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1645  txoutclk_out => gt1_txoutclk_out,
1646  txoutclkfabric_out => gt1_txoutclkfabric_out ,
1647  txoutclkpcs_out => gt1_txoutclkpcs_out ,
1648  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1649  txcharisk_in => gt1_txcharisk_in,
1650  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1651  txresetdone_out => gt1_txresetdone_out ,
1652  ------------------ Transmit Ports - pattern Generator Ports ----------------
1653  txprbssel_in => gt1_txprbssel_in
1654 
1655  );
1656 
1657 
1658 
1659  --_________________________________________________________________________
1660  --_________________________________________________________________________
1661  --GT2 (X0Y2)
1662 
1663 gt2_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
1664  generic map
1665  (
1666  -- Simulation attributes
1667  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
1668  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
1669  SIM_CPLLREFCLK_SEL => "001",
1670  PMA_RSV_IN => PMA_RSV_IN,
1671  PCS_RSVD_ATTR_IN => X"000000000000"
1672  )
1673  port map
1674  (
1675  cpllrefclksel_in => "001",
1676  ---------------------------- Channel - DRP Ports --------------------------
1677  drpaddr_in => gt2_drpaddr_in,
1678  drpclk_in => gt2_drpclk_in,
1679  drpdi_in => gt2_drpdi_in,
1680  drpdo_out => gt2_drpdo_out,
1681  drpen_in => gt2_drpen_in,
1682  drprdy_out => gt2_drprdy_out,
1683  drpwe_in => gt2_drpwe_in,
1684  ------------------------------- Clocking Ports -----------------------------
1685  qpllclk_in => gt2_qpllclk_i,
1686  qpllrefclk_in => gt2_qpllrefclk_i,
1687  --------------------------- Digital Monitor Ports --------------------------
1688  dmonitorout_out => gt2_dmonitorout_out ,
1689  ------------------------------- Loopback Ports -----------------------------
1690  loopback_in => gt2_loopback_in,
1691  ------------------------------ Power-Down Ports ----------------------------
1692  rxpd_in => gt2_rxpd_in,
1693  txpd_in => gt2_txpd_in,
1694  --------------------- RX Initialization and Reset Ports --------------------
1695  eyescanreset_in => gt2_eyescanreset_in ,
1696  rxuserrdy_in => gt2_rxuserrdy_in,
1697  -------------------------- RX Margin Analysis Ports ------------------------
1698  eyescandataerror_out => gt2_eyescandataerror_out,
1699  eyescantrigger_in => gt2_eyescantrigger_in ,
1700  ------------------- Receive Ports - Clock Correction Ports -----------------
1701  rxclkcorcnt_out => gt2_rxclkcorcnt_out ,
1702  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1703  rxusrclk_in => gt2_rxusrclk_in,
1704  rxusrclk2_in => gt2_rxusrclk2_in,
1705  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1706  rxdata_out => gt2_rxdata_out,
1707  ------------------- Receive Ports - Pattern Checker Ports ------------------
1708  rxprbserr_out => gt2_rxprbserr_out,
1709  rxprbssel_in => gt2_rxprbssel_in,
1710  ------------------- Receive Ports - Pattern Checker ports ------------------
1711  rxprbscntreset_in => gt2_rxprbscntreset_in ,
1712  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1713  rxdisperr_out => gt2_rxdisperr_out,
1714  rxnotintable_out => gt2_rxnotintable_out ,
1715  --------------------------- Receive Ports - RX AFE -------------------------
1716  gtxrxp_in => gt2_gtxrxp_in,
1717  ------------------------ Receive Ports - RX AFE Ports ----------------------
1718  gtxrxn_in => gt2_gtxrxn_in,
1719  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1720  rxbufstatus_out => gt2_rxbufstatus_out ,
1721  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1722  rxmcommaalignen_in => gt2_rxmcommaalignen_in ,
1723  rxpcommaalignen_in => gt2_rxpcommaalignen_in ,
1724  --------------------- Receive Ports - RX Equalizer Ports -------------------
1725  rxdfeagchold_in => gt2_rxdfeagchold_in ,
1726  rxdfelfhold_in => gt2_rxdfelfhold_in,
1727  rxdfelpmreset_in => gt2_rxdfelpmreset_in ,
1728  rxmonitorout_out => gt2_rxmonitorout_out ,
1729  rxmonitorsel_in => gt2_rxmonitorsel_in ,
1730  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1731  rxoutclk_out => gt2_rxoutclk_out,
1732  rxoutclkfabric_out => gt2_rxoutclkfabric_out ,
1733  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1734  gtrxreset_in => gt2_gtrxreset_in,
1735  rxpmareset_in => gt2_rxpmareset_in,
1736  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1737  rxchariscomma_out => gt2_rxchariscomma_out ,
1738  rxcharisk_out => gt2_rxcharisk_out,
1739  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1740  rxresetdone_out => gt2_rxresetdone_out ,
1741  --------------------- TX Initialization and Reset Ports --------------------
1742  gttxreset_in => gt2_gttxreset_in,
1743  txuserrdy_in => gt2_txuserrdy_in,
1744  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1745  txusrclk_in => gt2_txusrclk_in,
1746  txusrclk2_in => gt2_txusrclk2_in,
1747  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1748  txdiffctrl_in => gt2_txdiffctrl_in,
1749  ------------------ Transmit Ports - TX Data Path interface -----------------
1750  txdata_in => gt2_txdata_in,
1751  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1752  gtxtxn_out => gt2_gtxtxn_out,
1753  gtxtxp_out => gt2_gtxtxp_out,
1754  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1755  txoutclk_out => gt2_txoutclk_out,
1756  txoutclkfabric_out => gt2_txoutclkfabric_out ,
1757  txoutclkpcs_out => gt2_txoutclkpcs_out ,
1758  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1759  txcharisk_in => gt2_txcharisk_in,
1760  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1761  txresetdone_out => gt2_txresetdone_out ,
1762  ------------------ Transmit Ports - pattern Generator Ports ----------------
1763  txprbssel_in => gt2_txprbssel_in
1764 
1765  );
1766 
1767 
1768 
1769  --_________________________________________________________________________
1770  --_________________________________________________________________________
1771  --GT3 (X0Y3)
1772 
1773 gt3_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
1774  generic map
1775  (
1776  -- Simulation attributes
1777  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
1778  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
1779  SIM_CPLLREFCLK_SEL => "001",
1780  PMA_RSV_IN => PMA_RSV_IN,
1781  PCS_RSVD_ATTR_IN => X"000000000000"
1782  )
1783  port map
1784  (
1785  cpllrefclksel_in => "001",
1786  ---------------------------- Channel - DRP Ports --------------------------
1787  drpaddr_in => gt3_drpaddr_in,
1788  drpclk_in => gt3_drpclk_in,
1789  drpdi_in => gt3_drpdi_in,
1790  drpdo_out => gt3_drpdo_out,
1791  drpen_in => gt3_drpen_in,
1792  drprdy_out => gt3_drprdy_out,
1793  drpwe_in => gt3_drpwe_in,
1794  ------------------------------- Clocking Ports -----------------------------
1795  qpllclk_in => gt3_qpllclk_i,
1796  qpllrefclk_in => gt3_qpllrefclk_i,
1797  --------------------------- Digital Monitor Ports --------------------------
1798  dmonitorout_out => gt3_dmonitorout_out ,
1799  ------------------------------- Loopback Ports -----------------------------
1800  loopback_in => gt3_loopback_in,
1801  ------------------------------ Power-Down Ports ----------------------------
1802  rxpd_in => gt3_rxpd_in,
1803  txpd_in => gt3_txpd_in,
1804  --------------------- RX Initialization and Reset Ports --------------------
1805  eyescanreset_in => gt3_eyescanreset_in ,
1806  rxuserrdy_in => gt3_rxuserrdy_in,
1807  -------------------------- RX Margin Analysis Ports ------------------------
1808  eyescandataerror_out => gt3_eyescandataerror_out,
1809  eyescantrigger_in => gt3_eyescantrigger_in ,
1810  ------------------- Receive Ports - Clock Correction Ports -----------------
1811  rxclkcorcnt_out => gt3_rxclkcorcnt_out ,
1812  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1813  rxusrclk_in => gt3_rxusrclk_in,
1814  rxusrclk2_in => gt3_rxusrclk2_in,
1815  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1816  rxdata_out => gt3_rxdata_out,
1817  ------------------- Receive Ports - Pattern Checker Ports ------------------
1818  rxprbserr_out => gt3_rxprbserr_out,
1819  rxprbssel_in => gt3_rxprbssel_in,
1820  ------------------- Receive Ports - Pattern Checker ports ------------------
1821  rxprbscntreset_in => gt3_rxprbscntreset_in ,
1822  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1823  rxdisperr_out => gt3_rxdisperr_out,
1824  rxnotintable_out => gt3_rxnotintable_out ,
1825  --------------------------- Receive Ports - RX AFE -------------------------
1826  gtxrxp_in => gt3_gtxrxp_in,
1827  ------------------------ Receive Ports - RX AFE Ports ----------------------
1828  gtxrxn_in => gt3_gtxrxn_in,
1829  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1830  rxbufstatus_out => gt3_rxbufstatus_out ,
1831  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1832  rxmcommaalignen_in => gt3_rxmcommaalignen_in ,
1833  rxpcommaalignen_in => gt3_rxpcommaalignen_in ,
1834  --------------------- Receive Ports - RX Equalizer Ports -------------------
1835  rxdfeagchold_in => gt3_rxdfeagchold_in ,
1836  rxdfelfhold_in => gt3_rxdfelfhold_in,
1837  rxdfelpmreset_in => gt3_rxdfelpmreset_in ,
1838  rxmonitorout_out => gt3_rxmonitorout_out ,
1839  rxmonitorsel_in => gt3_rxmonitorsel_in ,
1840  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1841  rxoutclk_out => gt3_rxoutclk_out,
1842  rxoutclkfabric_out => gt3_rxoutclkfabric_out ,
1843  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1844  gtrxreset_in => gt3_gtrxreset_in,
1845  rxpmareset_in => gt3_rxpmareset_in,
1846  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1847  rxchariscomma_out => gt3_rxchariscomma_out ,
1848  rxcharisk_out => gt3_rxcharisk_out,
1849  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1850  rxresetdone_out => gt3_rxresetdone_out ,
1851  --------------------- TX Initialization and Reset Ports --------------------
1852  gttxreset_in => gt3_gttxreset_in,
1853  txuserrdy_in => gt3_txuserrdy_in,
1854  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1855  txusrclk_in => gt3_txusrclk_in,
1856  txusrclk2_in => gt3_txusrclk2_in,
1857  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1858  txdiffctrl_in => gt3_txdiffctrl_in,
1859  ------------------ Transmit Ports - TX Data Path interface -----------------
1860  txdata_in => gt3_txdata_in,
1861  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1862  gtxtxn_out => gt3_gtxtxn_out,
1863  gtxtxp_out => gt3_gtxtxp_out,
1864  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1865  txoutclk_out => gt3_txoutclk_out,
1866  txoutclkfabric_out => gt3_txoutclkfabric_out ,
1867  txoutclkpcs_out => gt3_txoutclkpcs_out ,
1868  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1869  txcharisk_in => gt3_txcharisk_in,
1870  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1871  txresetdone_out => gt3_txresetdone_out ,
1872  ------------------ Transmit Ports - pattern Generator Ports ----------------
1873  txprbssel_in => gt3_txprbssel_in
1874 
1875  );
1876 
1877 
1878 
1879  --_________________________________________________________________________
1880  --_________________________________________________________________________
1881  --GT4 (X0Y4)
1882 
1883 gt4_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
1884  generic map
1885  (
1886  -- Simulation attributes
1887  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
1888  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
1889  SIM_CPLLREFCLK_SEL => "001",
1890  PMA_RSV_IN => PMA_RSV_IN,
1891  PCS_RSVD_ATTR_IN => X"000000000000"
1892  )
1893  port map
1894  (
1895  cpllrefclksel_in => "001",
1896  ---------------------------- Channel - DRP Ports --------------------------
1897  drpaddr_in => gt4_drpaddr_in,
1898  drpclk_in => gt4_drpclk_in,
1899  drpdi_in => gt4_drpdi_in,
1900  drpdo_out => gt4_drpdo_out,
1901  drpen_in => gt4_drpen_in,
1902  drprdy_out => gt4_drprdy_out,
1903  drpwe_in => gt4_drpwe_in,
1904  ------------------------------- Clocking Ports -----------------------------
1905  qpllclk_in => gt4_qpllclk_i,
1906  qpllrefclk_in => gt4_qpllrefclk_i,
1907  --------------------------- Digital Monitor Ports --------------------------
1908  dmonitorout_out => gt4_dmonitorout_out ,
1909  ------------------------------- Loopback Ports -----------------------------
1910  loopback_in => gt4_loopback_in,
1911  ------------------------------ Power-Down Ports ----------------------------
1912  rxpd_in => gt4_rxpd_in,
1913  txpd_in => gt4_txpd_in,
1914  --------------------- RX Initialization and Reset Ports --------------------
1915  eyescanreset_in => gt4_eyescanreset_in ,
1916  rxuserrdy_in => gt4_rxuserrdy_in,
1917  -------------------------- RX Margin Analysis Ports ------------------------
1918  eyescandataerror_out => gt4_eyescandataerror_out,
1919  eyescantrigger_in => gt4_eyescantrigger_in ,
1920  ------------------- Receive Ports - Clock Correction Ports -----------------
1921  rxclkcorcnt_out => gt4_rxclkcorcnt_out ,
1922  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1923  rxusrclk_in => gt4_rxusrclk_in,
1924  rxusrclk2_in => gt4_rxusrclk2_in,
1925  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1926  rxdata_out => gt4_rxdata_out,
1927  ------------------- Receive Ports - Pattern Checker Ports ------------------
1928  rxprbserr_out => gt4_rxprbserr_out,
1929  rxprbssel_in => gt4_rxprbssel_in,
1930  ------------------- Receive Ports - Pattern Checker ports ------------------
1931  rxprbscntreset_in => gt4_rxprbscntreset_in ,
1932  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1933  rxdisperr_out => gt4_rxdisperr_out,
1934  rxnotintable_out => gt4_rxnotintable_out ,
1935  --------------------------- Receive Ports - RX AFE -------------------------
1936  gtxrxp_in => gt4_gtxrxp_in,
1937  ------------------------ Receive Ports - RX AFE Ports ----------------------
1938  gtxrxn_in => gt4_gtxrxn_in,
1939  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1940  rxbufstatus_out => gt4_rxbufstatus_out ,
1941  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1942  rxmcommaalignen_in => gt4_rxmcommaalignen_in ,
1943  rxpcommaalignen_in => gt4_rxpcommaalignen_in ,
1944  --------------------- Receive Ports - RX Equalizer Ports -------------------
1945  rxdfeagchold_in => gt4_rxdfeagchold_in ,
1946  rxdfelfhold_in => gt4_rxdfelfhold_in,
1947  rxdfelpmreset_in => gt4_rxdfelpmreset_in ,
1948  rxmonitorout_out => gt4_rxmonitorout_out ,
1949  rxmonitorsel_in => gt4_rxmonitorsel_in ,
1950  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1951  rxoutclk_out => gt4_rxoutclk_out,
1952  rxoutclkfabric_out => gt4_rxoutclkfabric_out ,
1953  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1954  gtrxreset_in => gt4_gtrxreset_in,
1955  rxpmareset_in => gt4_rxpmareset_in,
1956  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1957  rxchariscomma_out => gt4_rxchariscomma_out ,
1958  rxcharisk_out => gt4_rxcharisk_out,
1959  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1960  rxresetdone_out => gt4_rxresetdone_out ,
1961  --------------------- TX Initialization and Reset Ports --------------------
1962  gttxreset_in => gt4_gttxreset_in,
1963  txuserrdy_in => gt4_txuserrdy_in,
1964  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1965  txusrclk_in => gt4_txusrclk_in,
1966  txusrclk2_in => gt4_txusrclk2_in,
1967  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1968  txdiffctrl_in => gt4_txdiffctrl_in,
1969  ------------------ Transmit Ports - TX Data Path interface -----------------
1970  txdata_in => gt4_txdata_in,
1971  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1972  gtxtxn_out => gt4_gtxtxn_out,
1973  gtxtxp_out => gt4_gtxtxp_out,
1974  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1975  txoutclk_out => gt4_txoutclk_out,
1976  txoutclkfabric_out => gt4_txoutclkfabric_out ,
1977  txoutclkpcs_out => gt4_txoutclkpcs_out ,
1978  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1979  txcharisk_in => gt4_txcharisk_in,
1980  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1981  txresetdone_out => gt4_txresetdone_out ,
1982  ------------------ Transmit Ports - pattern Generator Ports ----------------
1983  txprbssel_in => gt4_txprbssel_in
1984 
1985  );
1986 
1987 
1988 
1989  --_________________________________________________________________________
1990  --_________________________________________________________________________
1991  --GT5 (X0Y5)
1992 
1993 gt5_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
1994  generic map
1995  (
1996  -- Simulation attributes
1997  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
1998  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
1999  SIM_CPLLREFCLK_SEL => "001",
2000  PMA_RSV_IN => PMA_RSV_IN,
2001  PCS_RSVD_ATTR_IN => X"000000000000"
2002  )
2003  port map
2004  (
2005  cpllrefclksel_in => "001",
2006  ---------------------------- Channel - DRP Ports --------------------------
2007  drpaddr_in => gt5_drpaddr_in,
2008  drpclk_in => gt5_drpclk_in,
2009  drpdi_in => gt5_drpdi_in,
2010  drpdo_out => gt5_drpdo_out,
2011  drpen_in => gt5_drpen_in,
2012  drprdy_out => gt5_drprdy_out,
2013  drpwe_in => gt5_drpwe_in,
2014  ------------------------------- Clocking Ports -----------------------------
2015  qpllclk_in => gt5_qpllclk_i,
2016  qpllrefclk_in => gt5_qpllrefclk_i,
2017  --------------------------- Digital Monitor Ports --------------------------
2018  dmonitorout_out => gt5_dmonitorout_out ,
2019  ------------------------------- Loopback Ports -----------------------------
2020  loopback_in => gt5_loopback_in,
2021  ------------------------------ Power-Down Ports ----------------------------
2022  rxpd_in => gt5_rxpd_in,
2023  txpd_in => gt5_txpd_in,
2024  --------------------- RX Initialization and Reset Ports --------------------
2025  eyescanreset_in => gt5_eyescanreset_in ,
2026  rxuserrdy_in => gt5_rxuserrdy_in,
2027  -------------------------- RX Margin Analysis Ports ------------------------
2028  eyescandataerror_out => gt5_eyescandataerror_out,
2029  eyescantrigger_in => gt5_eyescantrigger_in ,
2030  ------------------- Receive Ports - Clock Correction Ports -----------------
2031  rxclkcorcnt_out => gt5_rxclkcorcnt_out ,
2032  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2033  rxusrclk_in => gt5_rxusrclk_in,
2034  rxusrclk2_in => gt5_rxusrclk2_in,
2035  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2036  rxdata_out => gt5_rxdata_out,
2037  ------------------- Receive Ports - Pattern Checker Ports ------------------
2038  rxprbserr_out => gt5_rxprbserr_out,
2039  rxprbssel_in => gt5_rxprbssel_in,
2040  ------------------- Receive Ports - Pattern Checker ports ------------------
2041  rxprbscntreset_in => gt5_rxprbscntreset_in ,
2042  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2043  rxdisperr_out => gt5_rxdisperr_out,
2044  rxnotintable_out => gt5_rxnotintable_out ,
2045  --------------------------- Receive Ports - RX AFE -------------------------
2046  gtxrxp_in => gt5_gtxrxp_in,
2047  ------------------------ Receive Ports - RX AFE Ports ----------------------
2048  gtxrxn_in => gt5_gtxrxn_in,
2049  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2050  rxbufstatus_out => gt5_rxbufstatus_out ,
2051  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2052  rxmcommaalignen_in => gt5_rxmcommaalignen_in ,
2053  rxpcommaalignen_in => gt5_rxpcommaalignen_in ,
2054  --------------------- Receive Ports - RX Equalizer Ports -------------------
2055  rxdfeagchold_in => gt5_rxdfeagchold_in ,
2056  rxdfelfhold_in => gt5_rxdfelfhold_in,
2057  rxdfelpmreset_in => gt5_rxdfelpmreset_in ,
2058  rxmonitorout_out => gt5_rxmonitorout_out ,
2059  rxmonitorsel_in => gt5_rxmonitorsel_in ,
2060  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2061  rxoutclk_out => gt5_rxoutclk_out,
2062  rxoutclkfabric_out => gt5_rxoutclkfabric_out ,
2063  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2064  gtrxreset_in => gt5_gtrxreset_in,
2065  rxpmareset_in => gt5_rxpmareset_in,
2066  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2067  rxchariscomma_out => gt5_rxchariscomma_out ,
2068  rxcharisk_out => gt5_rxcharisk_out,
2069  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2070  rxresetdone_out => gt5_rxresetdone_out ,
2071  --------------------- TX Initialization and Reset Ports --------------------
2072  gttxreset_in => gt5_gttxreset_in,
2073  txuserrdy_in => gt5_txuserrdy_in,
2074  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2075  txusrclk_in => gt5_txusrclk_in,
2076  txusrclk2_in => gt5_txusrclk2_in,
2077  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2078  txdiffctrl_in => gt5_txdiffctrl_in,
2079  ------------------ Transmit Ports - TX Data Path interface -----------------
2080  txdata_in => gt5_txdata_in,
2081  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2082  gtxtxn_out => gt5_gtxtxn_out,
2083  gtxtxp_out => gt5_gtxtxp_out,
2084  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2085  txoutclk_out => gt5_txoutclk_out,
2086  txoutclkfabric_out => gt5_txoutclkfabric_out ,
2087  txoutclkpcs_out => gt5_txoutclkpcs_out ,
2088  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2089  txcharisk_in => gt5_txcharisk_in,
2090  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2091  txresetdone_out => gt5_txresetdone_out ,
2092  ------------------ Transmit Ports - pattern Generator Ports ----------------
2093  txprbssel_in => gt5_txprbssel_in
2094 
2095  );
2096 
2097 
2098 
2099  --_________________________________________________________________________
2100  --_________________________________________________________________________
2101  --GT6 (X0Y6)
2102 
2103 gt6_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
2104  generic map
2105  (
2106  -- Simulation attributes
2107  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
2108  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
2109  SIM_CPLLREFCLK_SEL => "001",
2110  PMA_RSV_IN => PMA_RSV_IN,
2111  PCS_RSVD_ATTR_IN => X"000000000000"
2112  )
2113  port map
2114  (
2115  cpllrefclksel_in => "001",
2116  ---------------------------- Channel - DRP Ports --------------------------
2117  drpaddr_in => gt6_drpaddr_in,
2118  drpclk_in => gt6_drpclk_in,
2119  drpdi_in => gt6_drpdi_in,
2120  drpdo_out => gt6_drpdo_out,
2121  drpen_in => gt6_drpen_in,
2122  drprdy_out => gt6_drprdy_out,
2123  drpwe_in => gt6_drpwe_in,
2124  ------------------------------- Clocking Ports -----------------------------
2125  qpllclk_in => gt6_qpllclk_i,
2126  qpllrefclk_in => gt6_qpllrefclk_i,
2127  --------------------------- Digital Monitor Ports --------------------------
2128  dmonitorout_out => gt6_dmonitorout_out ,
2129  ------------------------------- Loopback Ports -----------------------------
2130  loopback_in => gt6_loopback_in,
2131  ------------------------------ Power-Down Ports ----------------------------
2132  rxpd_in => gt6_rxpd_in,
2133  txpd_in => gt6_txpd_in,
2134  --------------------- RX Initialization and Reset Ports --------------------
2135  eyescanreset_in => gt6_eyescanreset_in ,
2136  rxuserrdy_in => gt6_rxuserrdy_in,
2137  -------------------------- RX Margin Analysis Ports ------------------------
2138  eyescandataerror_out => gt6_eyescandataerror_out,
2139  eyescantrigger_in => gt6_eyescantrigger_in ,
2140  ------------------- Receive Ports - Clock Correction Ports -----------------
2141  rxclkcorcnt_out => gt6_rxclkcorcnt_out ,
2142  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2143  rxusrclk_in => gt6_rxusrclk_in,
2144  rxusrclk2_in => gt6_rxusrclk2_in,
2145  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2146  rxdata_out => gt6_rxdata_out,
2147  ------------------- Receive Ports - Pattern Checker Ports ------------------
2148  rxprbserr_out => gt6_rxprbserr_out,
2149  rxprbssel_in => gt6_rxprbssel_in,
2150  ------------------- Receive Ports - Pattern Checker ports ------------------
2151  rxprbscntreset_in => gt6_rxprbscntreset_in ,
2152  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2153  rxdisperr_out => gt6_rxdisperr_out,
2154  rxnotintable_out => gt6_rxnotintable_out ,
2155  --------------------------- Receive Ports - RX AFE -------------------------
2156  gtxrxp_in => gt6_gtxrxp_in,
2157  ------------------------ Receive Ports - RX AFE Ports ----------------------
2158  gtxrxn_in => gt6_gtxrxn_in,
2159  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2160  rxbufstatus_out => gt6_rxbufstatus_out ,
2161  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2162  rxmcommaalignen_in => gt6_rxmcommaalignen_in ,
2163  rxpcommaalignen_in => gt6_rxpcommaalignen_in ,
2164  --------------------- Receive Ports - RX Equalizer Ports -------------------
2165  rxdfeagchold_in => gt6_rxdfeagchold_in ,
2166  rxdfelfhold_in => gt6_rxdfelfhold_in,
2167  rxdfelpmreset_in => gt6_rxdfelpmreset_in ,
2168  rxmonitorout_out => gt6_rxmonitorout_out ,
2169  rxmonitorsel_in => gt6_rxmonitorsel_in ,
2170  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2171  rxoutclk_out => gt6_rxoutclk_out,
2172  rxoutclkfabric_out => gt6_rxoutclkfabric_out ,
2173  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2174  gtrxreset_in => gt6_gtrxreset_in,
2175  rxpmareset_in => gt6_rxpmareset_in,
2176  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2177  rxchariscomma_out => gt6_rxchariscomma_out ,
2178  rxcharisk_out => gt6_rxcharisk_out,
2179  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2180  rxresetdone_out => gt6_rxresetdone_out ,
2181  --------------------- TX Initialization and Reset Ports --------------------
2182  gttxreset_in => gt6_gttxreset_in,
2183  txuserrdy_in => gt6_txuserrdy_in,
2184  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2185  txusrclk_in => gt6_txusrclk_in,
2186  txusrclk2_in => gt6_txusrclk2_in,
2187  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2188  txdiffctrl_in => gt6_txdiffctrl_in,
2189  ------------------ Transmit Ports - TX Data Path interface -----------------
2190  txdata_in => gt6_txdata_in,
2191  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2192  gtxtxn_out => gt6_gtxtxn_out,
2193  gtxtxp_out => gt6_gtxtxp_out,
2194  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2195  txoutclk_out => gt6_txoutclk_out,
2196  txoutclkfabric_out => gt6_txoutclkfabric_out ,
2197  txoutclkpcs_out => gt6_txoutclkpcs_out ,
2198  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2199  txcharisk_in => gt6_txcharisk_in,
2200  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2201  txresetdone_out => gt6_txresetdone_out ,
2202  ------------------ Transmit Ports - pattern Generator Ports ----------------
2203  txprbssel_in => gt6_txprbssel_in
2204 
2205  );
2206 
2207 
2208 
2209  --_________________________________________________________________________
2210  --_________________________________________________________________________
2211  --GT7 (X0Y7)
2212 
2213 gt7_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
2214  generic map
2215  (
2216  -- Simulation attributes
2217  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
2218  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
2219  SIM_CPLLREFCLK_SEL => "001",
2220  PMA_RSV_IN => PMA_RSV_IN,
2221  PCS_RSVD_ATTR_IN => X"000000000000"
2222  )
2223  port map
2224  (
2225  cpllrefclksel_in => "001",
2226  ---------------------------- Channel - DRP Ports --------------------------
2227  drpaddr_in => gt7_drpaddr_in,
2228  drpclk_in => gt7_drpclk_in,
2229  drpdi_in => gt7_drpdi_in,
2230  drpdo_out => gt7_drpdo_out,
2231  drpen_in => gt7_drpen_in,
2232  drprdy_out => gt7_drprdy_out,
2233  drpwe_in => gt7_drpwe_in,
2234  ------------------------------- Clocking Ports -----------------------------
2235  qpllclk_in => gt7_qpllclk_i,
2236  qpllrefclk_in => gt7_qpllrefclk_i,
2237  --------------------------- Digital Monitor Ports --------------------------
2238  dmonitorout_out => gt7_dmonitorout_out ,
2239  ------------------------------- Loopback Ports -----------------------------
2240  loopback_in => gt7_loopback_in,
2241  ------------------------------ Power-Down Ports ----------------------------
2242  rxpd_in => gt7_rxpd_in,
2243  txpd_in => gt7_txpd_in,
2244  --------------------- RX Initialization and Reset Ports --------------------
2245  eyescanreset_in => gt7_eyescanreset_in ,
2246  rxuserrdy_in => gt7_rxuserrdy_in,
2247  -------------------------- RX Margin Analysis Ports ------------------------
2248  eyescandataerror_out => gt7_eyescandataerror_out,
2249  eyescantrigger_in => gt7_eyescantrigger_in ,
2250  ------------------- Receive Ports - Clock Correction Ports -----------------
2251  rxclkcorcnt_out => gt7_rxclkcorcnt_out ,
2252  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2253  rxusrclk_in => gt7_rxusrclk_in,
2254  rxusrclk2_in => gt7_rxusrclk2_in,
2255  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2256  rxdata_out => gt7_rxdata_out,
2257  ------------------- Receive Ports - Pattern Checker Ports ------------------
2258  rxprbserr_out => gt7_rxprbserr_out,
2259  rxprbssel_in => gt7_rxprbssel_in,
2260  ------------------- Receive Ports - Pattern Checker ports ------------------
2261  rxprbscntreset_in => gt7_rxprbscntreset_in ,
2262  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2263  rxdisperr_out => gt7_rxdisperr_out,
2264  rxnotintable_out => gt7_rxnotintable_out ,
2265  --------------------------- Receive Ports - RX AFE -------------------------
2266  gtxrxp_in => gt7_gtxrxp_in,
2267  ------------------------ Receive Ports - RX AFE Ports ----------------------
2268  gtxrxn_in => gt7_gtxrxn_in,
2269  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2270  rxbufstatus_out => gt7_rxbufstatus_out ,
2271  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2272  rxmcommaalignen_in => gt7_rxmcommaalignen_in ,
2273  rxpcommaalignen_in => gt7_rxpcommaalignen_in ,
2274  --------------------- Receive Ports - RX Equalizer Ports -------------------
2275  rxdfeagchold_in => gt7_rxdfeagchold_in ,
2276  rxdfelfhold_in => gt7_rxdfelfhold_in,
2277  rxdfelpmreset_in => gt7_rxdfelpmreset_in ,
2278  rxmonitorout_out => gt7_rxmonitorout_out ,
2279  rxmonitorsel_in => gt7_rxmonitorsel_in ,
2280  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2281  rxoutclk_out => gt7_rxoutclk_out,
2282  rxoutclkfabric_out => gt7_rxoutclkfabric_out ,
2283  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2284  gtrxreset_in => gt7_gtrxreset_in,
2285  rxpmareset_in => gt7_rxpmareset_in,
2286  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2287  rxchariscomma_out => gt7_rxchariscomma_out ,
2288  rxcharisk_out => gt7_rxcharisk_out,
2289  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2290  rxresetdone_out => gt7_rxresetdone_out ,
2291  --------------------- TX Initialization and Reset Ports --------------------
2292  gttxreset_in => gt7_gttxreset_in,
2293  txuserrdy_in => gt7_txuserrdy_in,
2294  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2295  txusrclk_in => gt7_txusrclk_in,
2296  txusrclk2_in => gt7_txusrclk2_in,
2297  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2298  txdiffctrl_in => gt7_txdiffctrl_in,
2299  ------------------ Transmit Ports - TX Data Path interface -----------------
2300  txdata_in => gt7_txdata_in,
2301  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2302  gtxtxn_out => gt7_gtxtxn_out,
2303  gtxtxp_out => gt7_gtxtxp_out,
2304  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2305  txoutclk_out => gt7_txoutclk_out,
2306  txoutclkfabric_out => gt7_txoutclkfabric_out ,
2307  txoutclkpcs_out => gt7_txoutclkpcs_out ,
2308  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2309  txcharisk_in => gt7_txcharisk_in,
2310  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2311  txresetdone_out => gt7_txresetdone_out ,
2312  ------------------ Transmit Ports - pattern Generator Ports ----------------
2313  txprbssel_in => gt7_txprbssel_in
2314 
2315  );
2316 
2317 
2318 
2319  --_________________________________________________________________________
2320  --_________________________________________________________________________
2321  --GT8 (X0Y8)
2322 
2323 gt8_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
2324  generic map
2325  (
2326  -- Simulation attributes
2327  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
2328  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
2329  SIM_CPLLREFCLK_SEL => "001",
2330  PMA_RSV_IN => PMA_RSV_IN,
2331  PCS_RSVD_ATTR_IN => X"000000000000"
2332  )
2333  port map
2334  (
2335  cpllrefclksel_in => "001",
2336  ---------------------------- Channel - DRP Ports --------------------------
2337  drpaddr_in => gt8_drpaddr_in,
2338  drpclk_in => gt8_drpclk_in,
2339  drpdi_in => gt8_drpdi_in,
2340  drpdo_out => gt8_drpdo_out,
2341  drpen_in => gt8_drpen_in,
2342  drprdy_out => gt8_drprdy_out,
2343  drpwe_in => gt8_drpwe_in,
2344  ------------------------------- Clocking Ports -----------------------------
2345  qpllclk_in => gt8_qpllclk_i,
2346  qpllrefclk_in => gt8_qpllrefclk_i,
2347  --------------------------- Digital Monitor Ports --------------------------
2348  dmonitorout_out => gt8_dmonitorout_out ,
2349  ------------------------------- Loopback Ports -----------------------------
2350  loopback_in => gt8_loopback_in,
2351  ------------------------------ Power-Down Ports ----------------------------
2352  rxpd_in => gt8_rxpd_in,
2353  txpd_in => gt8_txpd_in,
2354  --------------------- RX Initialization and Reset Ports --------------------
2355  eyescanreset_in => gt8_eyescanreset_in ,
2356  rxuserrdy_in => gt8_rxuserrdy_in,
2357  -------------------------- RX Margin Analysis Ports ------------------------
2358  eyescandataerror_out => gt8_eyescandataerror_out,
2359  eyescantrigger_in => gt8_eyescantrigger_in ,
2360  ------------------- Receive Ports - Clock Correction Ports -----------------
2361  rxclkcorcnt_out => gt8_rxclkcorcnt_out ,
2362  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2363  rxusrclk_in => gt8_rxusrclk_in,
2364  rxusrclk2_in => gt8_rxusrclk2_in,
2365  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2366  rxdata_out => gt8_rxdata_out,
2367  ------------------- Receive Ports - Pattern Checker Ports ------------------
2368  rxprbserr_out => gt8_rxprbserr_out,
2369  rxprbssel_in => gt8_rxprbssel_in,
2370  ------------------- Receive Ports - Pattern Checker ports ------------------
2371  rxprbscntreset_in => gt8_rxprbscntreset_in ,
2372  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2373  rxdisperr_out => gt8_rxdisperr_out,
2374  rxnotintable_out => gt8_rxnotintable_out ,
2375  --------------------------- Receive Ports - RX AFE -------------------------
2376  gtxrxp_in => gt8_gtxrxp_in,
2377  ------------------------ Receive Ports - RX AFE Ports ----------------------
2378  gtxrxn_in => gt8_gtxrxn_in,
2379  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2380  rxbufstatus_out => gt8_rxbufstatus_out ,
2381  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2382  rxmcommaalignen_in => gt8_rxmcommaalignen_in ,
2383  rxpcommaalignen_in => gt8_rxpcommaalignen_in ,
2384  --------------------- Receive Ports - RX Equalizer Ports -------------------
2385  rxdfeagchold_in => gt8_rxdfeagchold_in ,
2386  rxdfelfhold_in => gt8_rxdfelfhold_in,
2387  rxdfelpmreset_in => gt8_rxdfelpmreset_in ,
2388  rxmonitorout_out => gt8_rxmonitorout_out ,
2389  rxmonitorsel_in => gt8_rxmonitorsel_in ,
2390  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2391  rxoutclk_out => gt8_rxoutclk_out,
2392  rxoutclkfabric_out => gt8_rxoutclkfabric_out ,
2393  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2394  gtrxreset_in => gt8_gtrxreset_in,
2395  rxpmareset_in => gt8_rxpmareset_in,
2396  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2397  rxchariscomma_out => gt8_rxchariscomma_out ,
2398  rxcharisk_out => gt8_rxcharisk_out,
2399  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2400  rxresetdone_out => gt8_rxresetdone_out ,
2401  --------------------- TX Initialization and Reset Ports --------------------
2402  gttxreset_in => gt8_gttxreset_in,
2403  txuserrdy_in => gt8_txuserrdy_in,
2404  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2405  txusrclk_in => gt8_txusrclk_in,
2406  txusrclk2_in => gt8_txusrclk2_in,
2407  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2408  txdiffctrl_in => gt8_txdiffctrl_in,
2409  ------------------ Transmit Ports - TX Data Path interface -----------------
2410  txdata_in => gt8_txdata_in,
2411  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2412  gtxtxn_out => gt8_gtxtxn_out,
2413  gtxtxp_out => gt8_gtxtxp_out,
2414  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2415  txoutclk_out => gt8_txoutclk_out,
2416  txoutclkfabric_out => gt8_txoutclkfabric_out ,
2417  txoutclkpcs_out => gt8_txoutclkpcs_out ,
2418  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2419  txcharisk_in => gt8_txcharisk_in,
2420  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2421  txresetdone_out => gt8_txresetdone_out ,
2422  ------------------ Transmit Ports - pattern Generator Ports ----------------
2423  txprbssel_in => gt8_txprbssel_in
2424 
2425  );
2426 
2427 
2428 
2429  --_________________________________________________________________________
2430  --_________________________________________________________________________
2431  --GT9 (X0Y9)
2432 
2433 gt9_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
2434  generic map
2435  (
2436  -- Simulation attributes
2437  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
2438  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
2439  SIM_CPLLREFCLK_SEL => "001",
2440  PMA_RSV_IN => PMA_RSV_IN,
2441  PCS_RSVD_ATTR_IN => X"000000000000"
2442  )
2443  port map
2444  (
2445  cpllrefclksel_in => "001",
2446  ---------------------------- Channel - DRP Ports --------------------------
2447  drpaddr_in => gt9_drpaddr_in,
2448  drpclk_in => gt9_drpclk_in,
2449  drpdi_in => gt9_drpdi_in,
2450  drpdo_out => gt9_drpdo_out,
2451  drpen_in => gt9_drpen_in,
2452  drprdy_out => gt9_drprdy_out,
2453  drpwe_in => gt9_drpwe_in,
2454  ------------------------------- Clocking Ports -----------------------------
2455  qpllclk_in => gt9_qpllclk_i,
2456  qpllrefclk_in => gt9_qpllrefclk_i,
2457  --------------------------- Digital Monitor Ports --------------------------
2458  dmonitorout_out => gt9_dmonitorout_out ,
2459  ------------------------------- Loopback Ports -----------------------------
2460  loopback_in => gt9_loopback_in,
2461  ------------------------------ Power-Down Ports ----------------------------
2462  rxpd_in => gt9_rxpd_in,
2463  txpd_in => gt9_txpd_in,
2464  --------------------- RX Initialization and Reset Ports --------------------
2465  eyescanreset_in => gt9_eyescanreset_in ,
2466  rxuserrdy_in => gt9_rxuserrdy_in,
2467  -------------------------- RX Margin Analysis Ports ------------------------
2468  eyescandataerror_out => gt9_eyescandataerror_out,
2469  eyescantrigger_in => gt9_eyescantrigger_in ,
2470  ------------------- Receive Ports - Clock Correction Ports -----------------
2471  rxclkcorcnt_out => gt9_rxclkcorcnt_out ,
2472  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2473  rxusrclk_in => gt9_rxusrclk_in,
2474  rxusrclk2_in => gt9_rxusrclk2_in,
2475  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2476  rxdata_out => gt9_rxdata_out,
2477  ------------------- Receive Ports - Pattern Checker Ports ------------------
2478  rxprbserr_out => gt9_rxprbserr_out,
2479  rxprbssel_in => gt9_rxprbssel_in,
2480  ------------------- Receive Ports - Pattern Checker ports ------------------
2481  rxprbscntreset_in => gt9_rxprbscntreset_in ,
2482  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2483  rxdisperr_out => gt9_rxdisperr_out,
2484  rxnotintable_out => gt9_rxnotintable_out ,
2485  --------------------------- Receive Ports - RX AFE -------------------------
2486  gtxrxp_in => gt9_gtxrxp_in,
2487  ------------------------ Receive Ports - RX AFE Ports ----------------------
2488  gtxrxn_in => gt9_gtxrxn_in,
2489  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2490  rxbufstatus_out => gt9_rxbufstatus_out ,
2491  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2492  rxmcommaalignen_in => gt9_rxmcommaalignen_in ,
2493  rxpcommaalignen_in => gt9_rxpcommaalignen_in ,
2494  --------------------- Receive Ports - RX Equalizer Ports -------------------
2495  rxdfeagchold_in => gt9_rxdfeagchold_in ,
2496  rxdfelfhold_in => gt9_rxdfelfhold_in,
2497  rxdfelpmreset_in => gt9_rxdfelpmreset_in ,
2498  rxmonitorout_out => gt9_rxmonitorout_out ,
2499  rxmonitorsel_in => gt9_rxmonitorsel_in ,
2500  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2501  rxoutclk_out => gt9_rxoutclk_out,
2502  rxoutclkfabric_out => gt9_rxoutclkfabric_out ,
2503  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2504  gtrxreset_in => gt9_gtrxreset_in,
2505  rxpmareset_in => gt9_rxpmareset_in,
2506  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2507  rxchariscomma_out => gt9_rxchariscomma_out ,
2508  rxcharisk_out => gt9_rxcharisk_out,
2509  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2510  rxresetdone_out => gt9_rxresetdone_out ,
2511  --------------------- TX Initialization and Reset Ports --------------------
2512  gttxreset_in => gt9_gttxreset_in,
2513  txuserrdy_in => gt9_txuserrdy_in,
2514  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2515  txusrclk_in => gt9_txusrclk_in,
2516  txusrclk2_in => gt9_txusrclk2_in,
2517  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2518  txdiffctrl_in => gt9_txdiffctrl_in,
2519  ------------------ Transmit Ports - TX Data Path interface -----------------
2520  txdata_in => gt9_txdata_in,
2521  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2522  gtxtxn_out => gt9_gtxtxn_out,
2523  gtxtxp_out => gt9_gtxtxp_out,
2524  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2525  txoutclk_out => gt9_txoutclk_out,
2526  txoutclkfabric_out => gt9_txoutclkfabric_out ,
2527  txoutclkpcs_out => gt9_txoutclkpcs_out ,
2528  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2529  txcharisk_in => gt9_txcharisk_in,
2530  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2531  txresetdone_out => gt9_txresetdone_out ,
2532  ------------------ Transmit Ports - pattern Generator Ports ----------------
2533  txprbssel_in => gt9_txprbssel_in
2534 
2535  );
2536 
2537 
2538 
2539  --_________________________________________________________________________
2540  --_________________________________________________________________________
2541  --GT10 (X0Y10)
2542 
2543 gt10_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
2544  generic map
2545  (
2546  -- Simulation attributes
2547  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
2548  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
2549  SIM_CPLLREFCLK_SEL => "001",
2550  PMA_RSV_IN => PMA_RSV_IN,
2551  PCS_RSVD_ATTR_IN => X"000000000000"
2552  )
2553  port map
2554  (
2555  cpllrefclksel_in => "001",
2556  ---------------------------- Channel - DRP Ports --------------------------
2557  drpaddr_in => gt10_drpaddr_in,
2558  drpclk_in => gt10_drpclk_in,
2559  drpdi_in => gt10_drpdi_in,
2560  drpdo_out => gt10_drpdo_out,
2561  drpen_in => gt10_drpen_in,
2562  drprdy_out => gt10_drprdy_out,
2563  drpwe_in => gt10_drpwe_in,
2564  ------------------------------- Clocking Ports -----------------------------
2565  qpllclk_in => gt10_qpllclk_i,
2566  qpllrefclk_in => gt10_qpllrefclk_i,
2567  --------------------------- Digital Monitor Ports --------------------------
2568  dmonitorout_out => gt10_dmonitorout_out ,
2569  ------------------------------- Loopback Ports -----------------------------
2570  loopback_in => gt10_loopback_in,
2571  ------------------------------ Power-Down Ports ----------------------------
2572  rxpd_in => gt10_rxpd_in,
2573  txpd_in => gt10_txpd_in,
2574  --------------------- RX Initialization and Reset Ports --------------------
2575  eyescanreset_in => gt10_eyescanreset_in ,
2576  rxuserrdy_in => gt10_rxuserrdy_in,
2577  -------------------------- RX Margin Analysis Ports ------------------------
2578  eyescandataerror_out => gt10_eyescandataerror_out ,
2579  eyescantrigger_in => gt10_eyescantrigger_in ,
2580  ------------------- Receive Ports - Clock Correction Ports -----------------
2581  rxclkcorcnt_out => gt10_rxclkcorcnt_out ,
2582  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2583  rxusrclk_in => gt10_rxusrclk_in,
2584  rxusrclk2_in => gt10_rxusrclk2_in,
2585  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2586  rxdata_out => gt10_rxdata_out,
2587  ------------------- Receive Ports - Pattern Checker Ports ------------------
2588  rxprbserr_out => gt10_rxprbserr_out,
2589  rxprbssel_in => gt10_rxprbssel_in,
2590  ------------------- Receive Ports - Pattern Checker ports ------------------
2591  rxprbscntreset_in => gt10_rxprbscntreset_in ,
2592  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2593  rxdisperr_out => gt10_rxdisperr_out,
2594  rxnotintable_out => gt10_rxnotintable_out ,
2595  --------------------------- Receive Ports - RX AFE -------------------------
2596  gtxrxp_in => gt10_gtxrxp_in,
2597  ------------------------ Receive Ports - RX AFE Ports ----------------------
2598  gtxrxn_in => gt10_gtxrxn_in,
2599  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2600  rxbufstatus_out => gt10_rxbufstatus_out ,
2601  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2602  rxmcommaalignen_in => gt10_rxmcommaalignen_in ,
2603  rxpcommaalignen_in => gt10_rxpcommaalignen_in ,
2604  --------------------- Receive Ports - RX Equalizer Ports -------------------
2605  rxdfeagchold_in => gt10_rxdfeagchold_in ,
2606  rxdfelfhold_in => gt10_rxdfelfhold_in ,
2607  rxdfelpmreset_in => gt10_rxdfelpmreset_in ,
2608  rxmonitorout_out => gt10_rxmonitorout_out ,
2609  rxmonitorsel_in => gt10_rxmonitorsel_in ,
2610  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2611  rxoutclk_out => gt10_rxoutclk_out,
2612  rxoutclkfabric_out => gt10_rxoutclkfabric_out ,
2613  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2614  gtrxreset_in => gt10_gtrxreset_in,
2615  rxpmareset_in => gt10_rxpmareset_in,
2616  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2617  rxchariscomma_out => gt10_rxchariscomma_out ,
2618  rxcharisk_out => gt10_rxcharisk_out,
2619  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2620  rxresetdone_out => gt10_rxresetdone_out ,
2621  --------------------- TX Initialization and Reset Ports --------------------
2622  gttxreset_in => gt10_gttxreset_in,
2623  txuserrdy_in => gt10_txuserrdy_in,
2624  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2625  txusrclk_in => gt10_txusrclk_in,
2626  txusrclk2_in => gt10_txusrclk2_in,
2627  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2628  txdiffctrl_in => gt10_txdiffctrl_in,
2629  ------------------ Transmit Ports - TX Data Path interface -----------------
2630  txdata_in => gt10_txdata_in,
2631  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2632  gtxtxn_out => gt10_gtxtxn_out,
2633  gtxtxp_out => gt10_gtxtxp_out,
2634  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2635  txoutclk_out => gt10_txoutclk_out,
2636  txoutclkfabric_out => gt10_txoutclkfabric_out ,
2637  txoutclkpcs_out => gt10_txoutclkpcs_out ,
2638  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2639  txcharisk_in => gt10_txcharisk_in,
2640  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2641  txresetdone_out => gt10_txresetdone_out ,
2642  ------------------ Transmit Ports - pattern Generator Ports ----------------
2643  txprbssel_in => gt10_txprbssel_in
2644 
2645  );
2646 
2647 
2648 
2649  --_________________________________________________________________________
2650  --_________________________________________________________________________
2651  --GT11 (X0Y11)
2652 
2653 gt11_amc_gtx5Gpd_i : amc_gtx5Gpd_GT
2654  generic map
2655  (
2656  -- Simulation attributes
2657  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
2658  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
2659  SIM_CPLLREFCLK_SEL => "001",
2660  PMA_RSV_IN => PMA_RSV_IN,
2661  PCS_RSVD_ATTR_IN => X"000000000000"
2662  )
2663  port map
2664  (
2665  cpllrefclksel_in => "001",
2666  ---------------------------- Channel - DRP Ports --------------------------
2667  drpaddr_in => gt11_drpaddr_in,
2668  drpclk_in => gt11_drpclk_in,
2669  drpdi_in => gt11_drpdi_in,
2670  drpdo_out => gt11_drpdo_out,
2671  drpen_in => gt11_drpen_in,
2672  drprdy_out => gt11_drprdy_out,
2673  drpwe_in => gt11_drpwe_in,
2674  ------------------------------- Clocking Ports -----------------------------
2675  qpllclk_in => gt11_qpllclk_i,
2676  qpllrefclk_in => gt11_qpllrefclk_i,
2677  --------------------------- Digital Monitor Ports --------------------------
2678  dmonitorout_out => gt11_dmonitorout_out ,
2679  ------------------------------- Loopback Ports -----------------------------
2680  loopback_in => gt11_loopback_in,
2681  ------------------------------ Power-Down Ports ----------------------------
2682  rxpd_in => gt11_rxpd_in,
2683  txpd_in => gt11_txpd_in,
2684  --------------------- RX Initialization and Reset Ports --------------------
2685  eyescanreset_in => gt11_eyescanreset_in ,
2686  rxuserrdy_in => gt11_rxuserrdy_in,
2687  -------------------------- RX Margin Analysis Ports ------------------------
2688  eyescandataerror_out => gt11_eyescandataerror_out ,
2689  eyescantrigger_in => gt11_eyescantrigger_in ,
2690  ------------------- Receive Ports - Clock Correction Ports -----------------
2691  rxclkcorcnt_out => gt11_rxclkcorcnt_out ,
2692  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2693  rxusrclk_in => gt11_rxusrclk_in,
2694  rxusrclk2_in => gt11_rxusrclk2_in,
2695  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2696  rxdata_out => gt11_rxdata_out,
2697  ------------------- Receive Ports - Pattern Checker Ports ------------------
2698  rxprbserr_out => gt11_rxprbserr_out,
2699  rxprbssel_in => gt11_rxprbssel_in,
2700  ------------------- Receive Ports - Pattern Checker ports ------------------
2701  rxprbscntreset_in => gt11_rxprbscntreset_in ,
2702  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2703  rxdisperr_out => gt11_rxdisperr_out,
2704  rxnotintable_out => gt11_rxnotintable_out ,
2705  --------------------------- Receive Ports - RX AFE -------------------------
2706  gtxrxp_in => gt11_gtxrxp_in,
2707  ------------------------ Receive Ports - RX AFE Ports ----------------------
2708  gtxrxn_in => gt11_gtxrxn_in,
2709  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2710  rxbufstatus_out => gt11_rxbufstatus_out ,
2711  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2712  rxmcommaalignen_in => gt11_rxmcommaalignen_in ,
2713  rxpcommaalignen_in => gt11_rxpcommaalignen_in ,
2714  --------------------- Receive Ports - RX Equalizer Ports -------------------
2715  rxdfeagchold_in => gt11_rxdfeagchold_in ,
2716  rxdfelfhold_in => gt11_rxdfelfhold_in ,
2717  rxdfelpmreset_in => gt11_rxdfelpmreset_in ,
2718  rxmonitorout_out => gt11_rxmonitorout_out ,
2719  rxmonitorsel_in => gt11_rxmonitorsel_in ,
2720  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2721  rxoutclk_out => gt11_rxoutclk_out,
2722  rxoutclkfabric_out => gt11_rxoutclkfabric_out ,
2723  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2724  gtrxreset_in => gt11_gtrxreset_in,
2725  rxpmareset_in => gt11_rxpmareset_in,
2726  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2727  rxchariscomma_out => gt11_rxchariscomma_out ,
2728  rxcharisk_out => gt11_rxcharisk_out,
2729  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2730  rxresetdone_out => gt11_rxresetdone_out ,
2731  --------------------- TX Initialization and Reset Ports --------------------
2732  gttxreset_in => gt11_gttxreset_in,
2733  txuserrdy_in => gt11_txuserrdy_in,
2734  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2735  txusrclk_in => gt11_txusrclk_in,
2736  txusrclk2_in => gt11_txusrclk2_in,
2737  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2738  txdiffctrl_in => gt11_txdiffctrl_in,
2739  ------------------ Transmit Ports - TX Data Path interface -----------------
2740  txdata_in => gt11_txdata_in,
2741  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2742  gtxtxn_out => gt11_gtxtxn_out,
2743  gtxtxp_out => gt11_gtxtxp_out,
2744  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2745  txoutclk_out => gt11_txoutclk_out,
2746  txoutclkfabric_out => gt11_txoutclkfabric_out ,
2747  txoutclkpcs_out => gt11_txoutclkpcs_out ,
2748  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2749  txcharisk_in => gt11_txcharisk_in,
2750  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2751  txresetdone_out => gt11_txresetdone_out ,
2752  ------------------ Transmit Ports - pattern Generator Ports ----------------
2753  txprbssel_in => gt11_txprbssel_in
2754 
2755  );
2756 
2757 
2758 end RTL;
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