AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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amc_gtx5gpd_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : amc_gtx5gpd_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module amc_gtx5Gpd_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity amc_gtx5Gpd_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80 
81 
82  STABLE_CLOCK_PERIOD : integer := 20;
83  -- Set to 1 for simulation
84  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
85 
86 );
87 port
88 (
89  SYSCLK_IN : in std_logic;
90  SOFT_RESET_IN : in std_logic;
91  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
92  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
93  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
94  GT0_DATA_VALID_IN : in std_logic;
95  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
96  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
97  GT1_DATA_VALID_IN : in std_logic;
98  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
99  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
100  GT2_DATA_VALID_IN : in std_logic;
101  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
102  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
103  GT3_DATA_VALID_IN : in std_logic;
104  GT4_TX_FSM_RESET_DONE_OUT : out std_logic;
105  GT4_RX_FSM_RESET_DONE_OUT : out std_logic;
106  GT4_DATA_VALID_IN : in std_logic;
107  GT5_TX_FSM_RESET_DONE_OUT : out std_logic;
108  GT5_RX_FSM_RESET_DONE_OUT : out std_logic;
109  GT5_DATA_VALID_IN : in std_logic;
110  GT6_TX_FSM_RESET_DONE_OUT : out std_logic;
111  GT6_RX_FSM_RESET_DONE_OUT : out std_logic;
112  GT6_DATA_VALID_IN : in std_logic;
113  GT7_TX_FSM_RESET_DONE_OUT : out std_logic;
114  GT7_RX_FSM_RESET_DONE_OUT : out std_logic;
115  GT7_DATA_VALID_IN : in std_logic;
116  GT8_TX_FSM_RESET_DONE_OUT : out std_logic;
117  GT8_RX_FSM_RESET_DONE_OUT : out std_logic;
118  GT8_DATA_VALID_IN : in std_logic;
119  GT9_TX_FSM_RESET_DONE_OUT : out std_logic;
120  GT9_RX_FSM_RESET_DONE_OUT : out std_logic;
121  GT9_DATA_VALID_IN : in std_logic;
122  GT10_TX_FSM_RESET_DONE_OUT : out std_logic;
123  GT10_RX_FSM_RESET_DONE_OUT : out std_logic;
124  GT10_DATA_VALID_IN : in std_logic;
125  GT11_TX_FSM_RESET_DONE_OUT : out std_logic;
126  GT11_RX_FSM_RESET_DONE_OUT : out std_logic;
127  GT11_DATA_VALID_IN : in std_logic;
128  --_________________________________________________________________________
129  --GT0 (X1Y0)
130  --____________________________CHANNEL PORTS________________________________
131  ---------------------------- Channel - DRP Ports --------------------------
132  gt0_drpaddr_in : in std_logic_vector(8 downto 0);
133  gt0_drpclk_in : in std_logic;
134  gt0_drpdi_in : in std_logic_vector(15 downto 0);
135  gt0_drpdo_out : out std_logic_vector(15 downto 0);
136  gt0_drpen_in : in std_logic;
137  gt0_drprdy_out : out std_logic;
138  gt0_drpwe_in : in std_logic;
139  --------------------------- Digital Monitor Ports --------------------------
140  gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
141  ------------------------------- Loopback Ports -----------------------------
142  gt0_loopback_in : in std_logic_vector(2 downto 0);
143  ------------------------------ Power-Down Ports ----------------------------
144  gt0_rxpd_in : in std_logic_vector(1 downto 0);
145  gt0_txpd_in : in std_logic_vector(1 downto 0);
146  --------------------- RX Initialization and Reset Ports --------------------
147  gt0_eyescanreset_in : in std_logic;
148  gt0_rxuserrdy_in : in std_logic;
149  -------------------------- RX Margin Analysis Ports ------------------------
150  gt0_eyescandataerror_out : out std_logic;
151  gt0_eyescantrigger_in : in std_logic;
152  ------------------- Receive Ports - Clock Correction Ports -----------------
153  gt0_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
154  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
155  gt0_rxusrclk_in : in std_logic;
156  gt0_rxusrclk2_in : in std_logic;
157  ------------------ Receive Ports - FPGA RX interface Ports -----------------
158  gt0_rxdata_out : out std_logic_vector(15 downto 0);
159  ------------------- Receive Ports - Pattern Checker Ports ------------------
160  gt0_rxprbserr_out : out std_logic;
161  gt0_rxprbssel_in : in std_logic_vector(2 downto 0);
162  ------------------- Receive Ports - Pattern Checker ports ------------------
163  gt0_rxprbscntreset_in : in std_logic;
164  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
165  gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
166  gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
167  --------------------------- Receive Ports - RX AFE -------------------------
168  gt0_gtxrxp_in : in std_logic;
169  ------------------------ Receive Ports - RX AFE Ports ----------------------
170  gt0_gtxrxn_in : in std_logic;
171  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
172  gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
173  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
174  gt0_rxmcommaalignen_in : in std_logic;
175  gt0_rxpcommaalignen_in : in std_logic;
176  --------------------- Receive Ports - RX Equalizer Ports -------------------
177  gt0_rxdfelpmreset_in : in std_logic;
178  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
179  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
180  --------------- Receive Ports - RX Fabric Output Control Ports -------------
181  gt0_rxoutclk_out : out std_logic;
182  ------------- Receive Ports - RX Initialization and Reset Ports ------------
183  gt0_gtrxreset_in : in std_logic;
184  gt0_rxpmareset_in : in std_logic;
185  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
186  gt0_rxchariscomma_out : out std_logic_vector(1 downto 0);
187  gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
188  -------------- Receive Ports -RX Initialization and Reset Ports ------------
189  gt0_rxresetdone_out : out std_logic;
190  --------------------- TX Initialization and Reset Ports --------------------
191  gt0_gttxreset_in : in std_logic;
192  gt0_txuserrdy_in : in std_logic;
193  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
194  gt0_txusrclk_in : in std_logic;
195  gt0_txusrclk2_in : in std_logic;
196  --------------- Transmit Ports - TX Configurable Driver Ports --------------
197  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
198  ------------------ Transmit Ports - TX Data Path interface -----------------
199  gt0_txdata_in : in std_logic_vector(15 downto 0);
200  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
201  gt0_gtxtxn_out : out std_logic;
202  gt0_gtxtxp_out : out std_logic;
203  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
204  gt0_txoutclk_out : out std_logic;
205  gt0_txoutclkfabric_out : out std_logic;
206  gt0_txoutclkpcs_out : out std_logic;
207  --------------------- Transmit Ports - TX Gearbox Ports --------------------
208  gt0_txcharisk_in : in std_logic_vector(1 downto 0);
209  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
210  gt0_txresetdone_out : out std_logic;
211  ------------------ Transmit Ports - pattern Generator Ports ----------------
212  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
213 
214  --GT1 (X1Y1)
215  --____________________________CHANNEL PORTS________________________________
216  ---------------------------- Channel - DRP Ports --------------------------
217  gt1_drpaddr_in : in std_logic_vector(8 downto 0);
218  gt1_drpclk_in : in std_logic;
219  gt1_drpdi_in : in std_logic_vector(15 downto 0);
220  gt1_drpdo_out : out std_logic_vector(15 downto 0);
221  gt1_drpen_in : in std_logic;
222  gt1_drprdy_out : out std_logic;
223  gt1_drpwe_in : in std_logic;
224  --------------------------- Digital Monitor Ports --------------------------
225  gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
226  ------------------------------- Loopback Ports -----------------------------
227  gt1_loopback_in : in std_logic_vector(2 downto 0);
228  ------------------------------ Power-Down Ports ----------------------------
229  gt1_rxpd_in : in std_logic_vector(1 downto 0);
230  gt1_txpd_in : in std_logic_vector(1 downto 0);
231  --------------------- RX Initialization and Reset Ports --------------------
232  gt1_eyescanreset_in : in std_logic;
233  gt1_rxuserrdy_in : in std_logic;
234  -------------------------- RX Margin Analysis Ports ------------------------
235  gt1_eyescandataerror_out : out std_logic;
236  gt1_eyescantrigger_in : in std_logic;
237  ------------------- Receive Ports - Clock Correction Ports -----------------
238  gt1_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
239  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
240  gt1_rxusrclk_in : in std_logic;
241  gt1_rxusrclk2_in : in std_logic;
242  ------------------ Receive Ports - FPGA RX interface Ports -----------------
243  gt1_rxdata_out : out std_logic_vector(15 downto 0);
244  ------------------- Receive Ports - Pattern Checker Ports ------------------
245  gt1_rxprbserr_out : out std_logic;
246  gt1_rxprbssel_in : in std_logic_vector(2 downto 0);
247  ------------------- Receive Ports - Pattern Checker ports ------------------
248  gt1_rxprbscntreset_in : in std_logic;
249  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
250  gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
251  gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
252  --------------------------- Receive Ports - RX AFE -------------------------
253  gt1_gtxrxp_in : in std_logic;
254  ------------------------ Receive Ports - RX AFE Ports ----------------------
255  gt1_gtxrxn_in : in std_logic;
256  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
257  gt1_rxbufstatus_out : out std_logic_vector(2 downto 0);
258  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
259  gt1_rxmcommaalignen_in : in std_logic;
260  gt1_rxpcommaalignen_in : in std_logic;
261  --------------------- Receive Ports - RX Equalizer Ports -------------------
262  gt1_rxdfelpmreset_in : in std_logic;
263  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
264  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
265  --------------- Receive Ports - RX Fabric Output Control Ports -------------
266  gt1_rxoutclk_out : out std_logic;
267  ------------- Receive Ports - RX Initialization and Reset Ports ------------
268  gt1_gtrxreset_in : in std_logic;
269  gt1_rxpmareset_in : in std_logic;
270  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
271  gt1_rxchariscomma_out : out std_logic_vector(1 downto 0);
272  gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
273  -------------- Receive Ports -RX Initialization and Reset Ports ------------
274  gt1_rxresetdone_out : out std_logic;
275  --------------------- TX Initialization and Reset Ports --------------------
276  gt1_gttxreset_in : in std_logic;
277  gt1_txuserrdy_in : in std_logic;
278  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
279  gt1_txusrclk_in : in std_logic;
280  gt1_txusrclk2_in : in std_logic;
281  --------------- Transmit Ports - TX Configurable Driver Ports --------------
282  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
283  ------------------ Transmit Ports - TX Data Path interface -----------------
284  gt1_txdata_in : in std_logic_vector(15 downto 0);
285  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
286  gt1_gtxtxn_out : out std_logic;
287  gt1_gtxtxp_out : out std_logic;
288  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
289  gt1_txoutclk_out : out std_logic;
290  gt1_txoutclkfabric_out : out std_logic;
291  gt1_txoutclkpcs_out : out std_logic;
292  --------------------- Transmit Ports - TX Gearbox Ports --------------------
293  gt1_txcharisk_in : in std_logic_vector(1 downto 0);
294  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
295  gt1_txresetdone_out : out std_logic;
296  ------------------ Transmit Ports - pattern Generator Ports ----------------
297  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
298 
299  --GT2 (X1Y2)
300  --____________________________CHANNEL PORTS________________________________
301  ---------------------------- Channel - DRP Ports --------------------------
302  gt2_drpaddr_in : in std_logic_vector(8 downto 0);
303  gt2_drpclk_in : in std_logic;
304  gt2_drpdi_in : in std_logic_vector(15 downto 0);
305  gt2_drpdo_out : out std_logic_vector(15 downto 0);
306  gt2_drpen_in : in std_logic;
307  gt2_drprdy_out : out std_logic;
308  gt2_drpwe_in : in std_logic;
309  --------------------------- Digital Monitor Ports --------------------------
310  gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
311  ------------------------------- Loopback Ports -----------------------------
312  gt2_loopback_in : in std_logic_vector(2 downto 0);
313  ------------------------------ Power-Down Ports ----------------------------
314  gt2_rxpd_in : in std_logic_vector(1 downto 0);
315  gt2_txpd_in : in std_logic_vector(1 downto 0);
316  --------------------- RX Initialization and Reset Ports --------------------
317  gt2_eyescanreset_in : in std_logic;
318  gt2_rxuserrdy_in : in std_logic;
319  -------------------------- RX Margin Analysis Ports ------------------------
320  gt2_eyescandataerror_out : out std_logic;
321  gt2_eyescantrigger_in : in std_logic;
322  ------------------- Receive Ports - Clock Correction Ports -----------------
323  gt2_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
324  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
325  gt2_rxusrclk_in : in std_logic;
326  gt2_rxusrclk2_in : in std_logic;
327  ------------------ Receive Ports - FPGA RX interface Ports -----------------
328  gt2_rxdata_out : out std_logic_vector(15 downto 0);
329  ------------------- Receive Ports - Pattern Checker Ports ------------------
330  gt2_rxprbserr_out : out std_logic;
331  gt2_rxprbssel_in : in std_logic_vector(2 downto 0);
332  ------------------- Receive Ports - Pattern Checker ports ------------------
333  gt2_rxprbscntreset_in : in std_logic;
334  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
335  gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
336  gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
337  --------------------------- Receive Ports - RX AFE -------------------------
338  gt2_gtxrxp_in : in std_logic;
339  ------------------------ Receive Ports - RX AFE Ports ----------------------
340  gt2_gtxrxn_in : in std_logic;
341  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
342  gt2_rxbufstatus_out : out std_logic_vector(2 downto 0);
343  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
344  gt2_rxmcommaalignen_in : in std_logic;
345  gt2_rxpcommaalignen_in : in std_logic;
346  --------------------- Receive Ports - RX Equalizer Ports -------------------
347  gt2_rxdfelpmreset_in : in std_logic;
348  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
349  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
350  --------------- Receive Ports - RX Fabric Output Control Ports -------------
351  gt2_rxoutclk_out : out std_logic;
352  ------------- Receive Ports - RX Initialization and Reset Ports ------------
353  gt2_gtrxreset_in : in std_logic;
354  gt2_rxpmareset_in : in std_logic;
355  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
356  gt2_rxchariscomma_out : out std_logic_vector(1 downto 0);
357  gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
358  -------------- Receive Ports -RX Initialization and Reset Ports ------------
359  gt2_rxresetdone_out : out std_logic;
360  --------------------- TX Initialization and Reset Ports --------------------
361  gt2_gttxreset_in : in std_logic;
362  gt2_txuserrdy_in : in std_logic;
363  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
364  gt2_txusrclk_in : in std_logic;
365  gt2_txusrclk2_in : in std_logic;
366  --------------- Transmit Ports - TX Configurable Driver Ports --------------
367  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
368  ------------------ Transmit Ports - TX Data Path interface -----------------
369  gt2_txdata_in : in std_logic_vector(15 downto 0);
370  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
371  gt2_gtxtxn_out : out std_logic;
372  gt2_gtxtxp_out : out std_logic;
373  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
374  gt2_txoutclk_out : out std_logic;
375  gt2_txoutclkfabric_out : out std_logic;
376  gt2_txoutclkpcs_out : out std_logic;
377  --------------------- Transmit Ports - TX Gearbox Ports --------------------
378  gt2_txcharisk_in : in std_logic_vector(1 downto 0);
379  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
380  gt2_txresetdone_out : out std_logic;
381  ------------------ Transmit Ports - pattern Generator Ports ----------------
382  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
383 
384  --GT3 (X1Y3)
385  --____________________________CHANNEL PORTS________________________________
386  ---------------------------- Channel - DRP Ports --------------------------
387  gt3_drpaddr_in : in std_logic_vector(8 downto 0);
388  gt3_drpclk_in : in std_logic;
389  gt3_drpdi_in : in std_logic_vector(15 downto 0);
390  gt3_drpdo_out : out std_logic_vector(15 downto 0);
391  gt3_drpen_in : in std_logic;
392  gt3_drprdy_out : out std_logic;
393  gt3_drpwe_in : in std_logic;
394  --------------------------- Digital Monitor Ports --------------------------
395  gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
396  ------------------------------- Loopback Ports -----------------------------
397  gt3_loopback_in : in std_logic_vector(2 downto 0);
398  ------------------------------ Power-Down Ports ----------------------------
399  gt3_rxpd_in : in std_logic_vector(1 downto 0);
400  gt3_txpd_in : in std_logic_vector(1 downto 0);
401  --------------------- RX Initialization and Reset Ports --------------------
402  gt3_eyescanreset_in : in std_logic;
403  gt3_rxuserrdy_in : in std_logic;
404  -------------------------- RX Margin Analysis Ports ------------------------
405  gt3_eyescandataerror_out : out std_logic;
406  gt3_eyescantrigger_in : in std_logic;
407  ------------------- Receive Ports - Clock Correction Ports -----------------
408  gt3_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
409  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
410  gt3_rxusrclk_in : in std_logic;
411  gt3_rxusrclk2_in : in std_logic;
412  ------------------ Receive Ports - FPGA RX interface Ports -----------------
413  gt3_rxdata_out : out std_logic_vector(15 downto 0);
414  ------------------- Receive Ports - Pattern Checker Ports ------------------
415  gt3_rxprbserr_out : out std_logic;
416  gt3_rxprbssel_in : in std_logic_vector(2 downto 0);
417  ------------------- Receive Ports - Pattern Checker ports ------------------
418  gt3_rxprbscntreset_in : in std_logic;
419  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
420  gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
421  gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
422  --------------------------- Receive Ports - RX AFE -------------------------
423  gt3_gtxrxp_in : in std_logic;
424  ------------------------ Receive Ports - RX AFE Ports ----------------------
425  gt3_gtxrxn_in : in std_logic;
426  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
427  gt3_rxbufstatus_out : out std_logic_vector(2 downto 0);
428  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
429  gt3_rxmcommaalignen_in : in std_logic;
430  gt3_rxpcommaalignen_in : in std_logic;
431  --------------------- Receive Ports - RX Equalizer Ports -------------------
432  gt3_rxdfelpmreset_in : in std_logic;
433  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
434  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
435  --------------- Receive Ports - RX Fabric Output Control Ports -------------
436  gt3_rxoutclk_out : out std_logic;
437  ------------- Receive Ports - RX Initialization and Reset Ports ------------
438  gt3_gtrxreset_in : in std_logic;
439  gt3_rxpmareset_in : in std_logic;
440  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
441  gt3_rxchariscomma_out : out std_logic_vector(1 downto 0);
442  gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
443  -------------- Receive Ports -RX Initialization and Reset Ports ------------
444  gt3_rxresetdone_out : out std_logic;
445  --------------------- TX Initialization and Reset Ports --------------------
446  gt3_gttxreset_in : in std_logic;
447  gt3_txuserrdy_in : in std_logic;
448  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
449  gt3_txusrclk_in : in std_logic;
450  gt3_txusrclk2_in : in std_logic;
451  --------------- Transmit Ports - TX Configurable Driver Ports --------------
452  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
453  ------------------ Transmit Ports - TX Data Path interface -----------------
454  gt3_txdata_in : in std_logic_vector(15 downto 0);
455  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
456  gt3_gtxtxn_out : out std_logic;
457  gt3_gtxtxp_out : out std_logic;
458  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
459  gt3_txoutclk_out : out std_logic;
460  gt3_txoutclkfabric_out : out std_logic;
461  gt3_txoutclkpcs_out : out std_logic;
462  --------------------- Transmit Ports - TX Gearbox Ports --------------------
463  gt3_txcharisk_in : in std_logic_vector(1 downto 0);
464  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
465  gt3_txresetdone_out : out std_logic;
466  ------------------ Transmit Ports - pattern Generator Ports ----------------
467  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
468 
469  --GT4 (X1Y4)
470  --____________________________CHANNEL PORTS________________________________
471  ---------------------------- Channel - DRP Ports --------------------------
472  gt4_drpaddr_in : in std_logic_vector(8 downto 0);
473  gt4_drpclk_in : in std_logic;
474  gt4_drpdi_in : in std_logic_vector(15 downto 0);
475  gt4_drpdo_out : out std_logic_vector(15 downto 0);
476  gt4_drpen_in : in std_logic;
477  gt4_drprdy_out : out std_logic;
478  gt4_drpwe_in : in std_logic;
479  --------------------------- Digital Monitor Ports --------------------------
480  gt4_dmonitorout_out : out std_logic_vector(7 downto 0);
481  ------------------------------- Loopback Ports -----------------------------
482  gt4_loopback_in : in std_logic_vector(2 downto 0);
483  ------------------------------ Power-Down Ports ----------------------------
484  gt4_rxpd_in : in std_logic_vector(1 downto 0);
485  gt4_txpd_in : in std_logic_vector(1 downto 0);
486  --------------------- RX Initialization and Reset Ports --------------------
487  gt4_eyescanreset_in : in std_logic;
488  gt4_rxuserrdy_in : in std_logic;
489  -------------------------- RX Margin Analysis Ports ------------------------
490  gt4_eyescandataerror_out : out std_logic;
491  gt4_eyescantrigger_in : in std_logic;
492  ------------------- Receive Ports - Clock Correction Ports -----------------
493  gt4_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
494  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
495  gt4_rxusrclk_in : in std_logic;
496  gt4_rxusrclk2_in : in std_logic;
497  ------------------ Receive Ports - FPGA RX interface Ports -----------------
498  gt4_rxdata_out : out std_logic_vector(15 downto 0);
499  ------------------- Receive Ports - Pattern Checker Ports ------------------
500  gt4_rxprbserr_out : out std_logic;
501  gt4_rxprbssel_in : in std_logic_vector(2 downto 0);
502  ------------------- Receive Ports - Pattern Checker ports ------------------
503  gt4_rxprbscntreset_in : in std_logic;
504  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
505  gt4_rxdisperr_out : out std_logic_vector(1 downto 0);
506  gt4_rxnotintable_out : out std_logic_vector(1 downto 0);
507  --------------------------- Receive Ports - RX AFE -------------------------
508  gt4_gtxrxp_in : in std_logic;
509  ------------------------ Receive Ports - RX AFE Ports ----------------------
510  gt4_gtxrxn_in : in std_logic;
511  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
512  gt4_rxbufstatus_out : out std_logic_vector(2 downto 0);
513  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
514  gt4_rxmcommaalignen_in : in std_logic;
515  gt4_rxpcommaalignen_in : in std_logic;
516  --------------------- Receive Ports - RX Equalizer Ports -------------------
517  gt4_rxdfelpmreset_in : in std_logic;
518  gt4_rxmonitorout_out : out std_logic_vector(6 downto 0);
519  gt4_rxmonitorsel_in : in std_logic_vector(1 downto 0);
520  --------------- Receive Ports - RX Fabric Output Control Ports -------------
521  gt4_rxoutclk_out : out std_logic;
522  ------------- Receive Ports - RX Initialization and Reset Ports ------------
523  gt4_gtrxreset_in : in std_logic;
524  gt4_rxpmareset_in : in std_logic;
525  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
526  gt4_rxchariscomma_out : out std_logic_vector(1 downto 0);
527  gt4_rxcharisk_out : out std_logic_vector(1 downto 0);
528  -------------- Receive Ports -RX Initialization and Reset Ports ------------
529  gt4_rxresetdone_out : out std_logic;
530  --------------------- TX Initialization and Reset Ports --------------------
531  gt4_gttxreset_in : in std_logic;
532  gt4_txuserrdy_in : in std_logic;
533  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
534  gt4_txusrclk_in : in std_logic;
535  gt4_txusrclk2_in : in std_logic;
536  --------------- Transmit Ports - TX Configurable Driver Ports --------------
537  gt4_txdiffctrl_in : in std_logic_vector(3 downto 0);
538  ------------------ Transmit Ports - TX Data Path interface -----------------
539  gt4_txdata_in : in std_logic_vector(15 downto 0);
540  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
541  gt4_gtxtxn_out : out std_logic;
542  gt4_gtxtxp_out : out std_logic;
543  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
544  gt4_txoutclk_out : out std_logic;
545  gt4_txoutclkfabric_out : out std_logic;
546  gt4_txoutclkpcs_out : out std_logic;
547  --------------------- Transmit Ports - TX Gearbox Ports --------------------
548  gt4_txcharisk_in : in std_logic_vector(1 downto 0);
549  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
550  gt4_txresetdone_out : out std_logic;
551  ------------------ Transmit Ports - pattern Generator Ports ----------------
552  gt4_txprbssel_in : in std_logic_vector(2 downto 0);
553 
554  --GT5 (X1Y5)
555  --____________________________CHANNEL PORTS________________________________
556  ---------------------------- Channel - DRP Ports --------------------------
557  gt5_drpaddr_in : in std_logic_vector(8 downto 0);
558  gt5_drpclk_in : in std_logic;
559  gt5_drpdi_in : in std_logic_vector(15 downto 0);
560  gt5_drpdo_out : out std_logic_vector(15 downto 0);
561  gt5_drpen_in : in std_logic;
562  gt5_drprdy_out : out std_logic;
563  gt5_drpwe_in : in std_logic;
564  --------------------------- Digital Monitor Ports --------------------------
565  gt5_dmonitorout_out : out std_logic_vector(7 downto 0);
566  ------------------------------- Loopback Ports -----------------------------
567  gt5_loopback_in : in std_logic_vector(2 downto 0);
568  ------------------------------ Power-Down Ports ----------------------------
569  gt5_rxpd_in : in std_logic_vector(1 downto 0);
570  gt5_txpd_in : in std_logic_vector(1 downto 0);
571  --------------------- RX Initialization and Reset Ports --------------------
572  gt5_eyescanreset_in : in std_logic;
573  gt5_rxuserrdy_in : in std_logic;
574  -------------------------- RX Margin Analysis Ports ------------------------
575  gt5_eyescandataerror_out : out std_logic;
576  gt5_eyescantrigger_in : in std_logic;
577  ------------------- Receive Ports - Clock Correction Ports -----------------
578  gt5_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
579  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
580  gt5_rxusrclk_in : in std_logic;
581  gt5_rxusrclk2_in : in std_logic;
582  ------------------ Receive Ports - FPGA RX interface Ports -----------------
583  gt5_rxdata_out : out std_logic_vector(15 downto 0);
584  ------------------- Receive Ports - Pattern Checker Ports ------------------
585  gt5_rxprbserr_out : out std_logic;
586  gt5_rxprbssel_in : in std_logic_vector(2 downto 0);
587  ------------------- Receive Ports - Pattern Checker ports ------------------
588  gt5_rxprbscntreset_in : in std_logic;
589  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
590  gt5_rxdisperr_out : out std_logic_vector(1 downto 0);
591  gt5_rxnotintable_out : out std_logic_vector(1 downto 0);
592  --------------------------- Receive Ports - RX AFE -------------------------
593  gt5_gtxrxp_in : in std_logic;
594  ------------------------ Receive Ports - RX AFE Ports ----------------------
595  gt5_gtxrxn_in : in std_logic;
596  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
597  gt5_rxbufstatus_out : out std_logic_vector(2 downto 0);
598  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
599  gt5_rxmcommaalignen_in : in std_logic;
600  gt5_rxpcommaalignen_in : in std_logic;
601  --------------------- Receive Ports - RX Equalizer Ports -------------------
602  gt5_rxdfelpmreset_in : in std_logic;
603  gt5_rxmonitorout_out : out std_logic_vector(6 downto 0);
604  gt5_rxmonitorsel_in : in std_logic_vector(1 downto 0);
605  --------------- Receive Ports - RX Fabric Output Control Ports -------------
606  gt5_rxoutclk_out : out std_logic;
607  ------------- Receive Ports - RX Initialization and Reset Ports ------------
608  gt5_gtrxreset_in : in std_logic;
609  gt5_rxpmareset_in : in std_logic;
610  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
611  gt5_rxchariscomma_out : out std_logic_vector(1 downto 0);
612  gt5_rxcharisk_out : out std_logic_vector(1 downto 0);
613  -------------- Receive Ports -RX Initialization and Reset Ports ------------
614  gt5_rxresetdone_out : out std_logic;
615  --------------------- TX Initialization and Reset Ports --------------------
616  gt5_gttxreset_in : in std_logic;
617  gt5_txuserrdy_in : in std_logic;
618  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
619  gt5_txusrclk_in : in std_logic;
620  gt5_txusrclk2_in : in std_logic;
621  --------------- Transmit Ports - TX Configurable Driver Ports --------------
622  gt5_txdiffctrl_in : in std_logic_vector(3 downto 0);
623  ------------------ Transmit Ports - TX Data Path interface -----------------
624  gt5_txdata_in : in std_logic_vector(15 downto 0);
625  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
626  gt5_gtxtxn_out : out std_logic;
627  gt5_gtxtxp_out : out std_logic;
628  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
629  gt5_txoutclk_out : out std_logic;
630  gt5_txoutclkfabric_out : out std_logic;
631  gt5_txoutclkpcs_out : out std_logic;
632  --------------------- Transmit Ports - TX Gearbox Ports --------------------
633  gt5_txcharisk_in : in std_logic_vector(1 downto 0);
634  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
635  gt5_txresetdone_out : out std_logic;
636  ------------------ Transmit Ports - pattern Generator Ports ----------------
637  gt5_txprbssel_in : in std_logic_vector(2 downto 0);
638 
639  --GT6 (X1Y6)
640  --____________________________CHANNEL PORTS________________________________
641  ---------------------------- Channel - DRP Ports --------------------------
642  gt6_drpaddr_in : in std_logic_vector(8 downto 0);
643  gt6_drpclk_in : in std_logic;
644  gt6_drpdi_in : in std_logic_vector(15 downto 0);
645  gt6_drpdo_out : out std_logic_vector(15 downto 0);
646  gt6_drpen_in : in std_logic;
647  gt6_drprdy_out : out std_logic;
648  gt6_drpwe_in : in std_logic;
649  --------------------------- Digital Monitor Ports --------------------------
650  gt6_dmonitorout_out : out std_logic_vector(7 downto 0);
651  ------------------------------- Loopback Ports -----------------------------
652  gt6_loopback_in : in std_logic_vector(2 downto 0);
653  ------------------------------ Power-Down Ports ----------------------------
654  gt6_rxpd_in : in std_logic_vector(1 downto 0);
655  gt6_txpd_in : in std_logic_vector(1 downto 0);
656  --------------------- RX Initialization and Reset Ports --------------------
657  gt6_eyescanreset_in : in std_logic;
658  gt6_rxuserrdy_in : in std_logic;
659  -------------------------- RX Margin Analysis Ports ------------------------
660  gt6_eyescandataerror_out : out std_logic;
661  gt6_eyescantrigger_in : in std_logic;
662  ------------------- Receive Ports - Clock Correction Ports -----------------
663  gt6_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
664  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
665  gt6_rxusrclk_in : in std_logic;
666  gt6_rxusrclk2_in : in std_logic;
667  ------------------ Receive Ports - FPGA RX interface Ports -----------------
668  gt6_rxdata_out : out std_logic_vector(15 downto 0);
669  ------------------- Receive Ports - Pattern Checker Ports ------------------
670  gt6_rxprbserr_out : out std_logic;
671  gt6_rxprbssel_in : in std_logic_vector(2 downto 0);
672  ------------------- Receive Ports - Pattern Checker ports ------------------
673  gt6_rxprbscntreset_in : in std_logic;
674  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
675  gt6_rxdisperr_out : out std_logic_vector(1 downto 0);
676  gt6_rxnotintable_out : out std_logic_vector(1 downto 0);
677  --------------------------- Receive Ports - RX AFE -------------------------
678  gt6_gtxrxp_in : in std_logic;
679  ------------------------ Receive Ports - RX AFE Ports ----------------------
680  gt6_gtxrxn_in : in std_logic;
681  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
682  gt6_rxbufstatus_out : out std_logic_vector(2 downto 0);
683  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
684  gt6_rxmcommaalignen_in : in std_logic;
685  gt6_rxpcommaalignen_in : in std_logic;
686  --------------------- Receive Ports - RX Equalizer Ports -------------------
687  gt6_rxdfelpmreset_in : in std_logic;
688  gt6_rxmonitorout_out : out std_logic_vector(6 downto 0);
689  gt6_rxmonitorsel_in : in std_logic_vector(1 downto 0);
690  --------------- Receive Ports - RX Fabric Output Control Ports -------------
691  gt6_rxoutclk_out : out std_logic;
692  ------------- Receive Ports - RX Initialization and Reset Ports ------------
693  gt6_gtrxreset_in : in std_logic;
694  gt6_rxpmareset_in : in std_logic;
695  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
696  gt6_rxchariscomma_out : out std_logic_vector(1 downto 0);
697  gt6_rxcharisk_out : out std_logic_vector(1 downto 0);
698  -------------- Receive Ports -RX Initialization and Reset Ports ------------
699  gt6_rxresetdone_out : out std_logic;
700  --------------------- TX Initialization and Reset Ports --------------------
701  gt6_gttxreset_in : in std_logic;
702  gt6_txuserrdy_in : in std_logic;
703  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
704  gt6_txusrclk_in : in std_logic;
705  gt6_txusrclk2_in : in std_logic;
706  --------------- Transmit Ports - TX Configurable Driver Ports --------------
707  gt6_txdiffctrl_in : in std_logic_vector(3 downto 0);
708  ------------------ Transmit Ports - TX Data Path interface -----------------
709  gt6_txdata_in : in std_logic_vector(15 downto 0);
710  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
711  gt6_gtxtxn_out : out std_logic;
712  gt6_gtxtxp_out : out std_logic;
713  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
714  gt6_txoutclk_out : out std_logic;
715  gt6_txoutclkfabric_out : out std_logic;
716  gt6_txoutclkpcs_out : out std_logic;
717  --------------------- Transmit Ports - TX Gearbox Ports --------------------
718  gt6_txcharisk_in : in std_logic_vector(1 downto 0);
719  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
720  gt6_txresetdone_out : out std_logic;
721  ------------------ Transmit Ports - pattern Generator Ports ----------------
722  gt6_txprbssel_in : in std_logic_vector(2 downto 0);
723 
724  --GT7 (X1Y7)
725  --____________________________CHANNEL PORTS________________________________
726  ---------------------------- Channel - DRP Ports --------------------------
727  gt7_drpaddr_in : in std_logic_vector(8 downto 0);
728  gt7_drpclk_in : in std_logic;
729  gt7_drpdi_in : in std_logic_vector(15 downto 0);
730  gt7_drpdo_out : out std_logic_vector(15 downto 0);
731  gt7_drpen_in : in std_logic;
732  gt7_drprdy_out : out std_logic;
733  gt7_drpwe_in : in std_logic;
734  --------------------------- Digital Monitor Ports --------------------------
735  gt7_dmonitorout_out : out std_logic_vector(7 downto 0);
736  ------------------------------- Loopback Ports -----------------------------
737  gt7_loopback_in : in std_logic_vector(2 downto 0);
738  ------------------------------ Power-Down Ports ----------------------------
739  gt7_rxpd_in : in std_logic_vector(1 downto 0);
740  gt7_txpd_in : in std_logic_vector(1 downto 0);
741  --------------------- RX Initialization and Reset Ports --------------------
742  gt7_eyescanreset_in : in std_logic;
743  gt7_rxuserrdy_in : in std_logic;
744  -------------------------- RX Margin Analysis Ports ------------------------
745  gt7_eyescandataerror_out : out std_logic;
746  gt7_eyescantrigger_in : in std_logic;
747  ------------------- Receive Ports - Clock Correction Ports -----------------
748  gt7_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
749  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
750  gt7_rxusrclk_in : in std_logic;
751  gt7_rxusrclk2_in : in std_logic;
752  ------------------ Receive Ports - FPGA RX interface Ports -----------------
753  gt7_rxdata_out : out std_logic_vector(15 downto 0);
754  ------------------- Receive Ports - Pattern Checker Ports ------------------
755  gt7_rxprbserr_out : out std_logic;
756  gt7_rxprbssel_in : in std_logic_vector(2 downto 0);
757  ------------------- Receive Ports - Pattern Checker ports ------------------
758  gt7_rxprbscntreset_in : in std_logic;
759  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
760  gt7_rxdisperr_out : out std_logic_vector(1 downto 0);
761  gt7_rxnotintable_out : out std_logic_vector(1 downto 0);
762  --------------------------- Receive Ports - RX AFE -------------------------
763  gt7_gtxrxp_in : in std_logic;
764  ------------------------ Receive Ports - RX AFE Ports ----------------------
765  gt7_gtxrxn_in : in std_logic;
766  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
767  gt7_rxbufstatus_out : out std_logic_vector(2 downto 0);
768  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
769  gt7_rxmcommaalignen_in : in std_logic;
770  gt7_rxpcommaalignen_in : in std_logic;
771  --------------------- Receive Ports - RX Equalizer Ports -------------------
772  gt7_rxdfelpmreset_in : in std_logic;
773  gt7_rxmonitorout_out : out std_logic_vector(6 downto 0);
774  gt7_rxmonitorsel_in : in std_logic_vector(1 downto 0);
775  --------------- Receive Ports - RX Fabric Output Control Ports -------------
776  gt7_rxoutclk_out : out std_logic;
777  ------------- Receive Ports - RX Initialization and Reset Ports ------------
778  gt7_gtrxreset_in : in std_logic;
779  gt7_rxpmareset_in : in std_logic;
780  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
781  gt7_rxchariscomma_out : out std_logic_vector(1 downto 0);
782  gt7_rxcharisk_out : out std_logic_vector(1 downto 0);
783  -------------- Receive Ports -RX Initialization and Reset Ports ------------
784  gt7_rxresetdone_out : out std_logic;
785  --------------------- TX Initialization and Reset Ports --------------------
786  gt7_gttxreset_in : in std_logic;
787  gt7_txuserrdy_in : in std_logic;
788  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
789  gt7_txusrclk_in : in std_logic;
790  gt7_txusrclk2_in : in std_logic;
791  --------------- Transmit Ports - TX Configurable Driver Ports --------------
792  gt7_txdiffctrl_in : in std_logic_vector(3 downto 0);
793  ------------------ Transmit Ports - TX Data Path interface -----------------
794  gt7_txdata_in : in std_logic_vector(15 downto 0);
795  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
796  gt7_gtxtxn_out : out std_logic;
797  gt7_gtxtxp_out : out std_logic;
798  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
799  gt7_txoutclk_out : out std_logic;
800  gt7_txoutclkfabric_out : out std_logic;
801  gt7_txoutclkpcs_out : out std_logic;
802  --------------------- Transmit Ports - TX Gearbox Ports --------------------
803  gt7_txcharisk_in : in std_logic_vector(1 downto 0);
804  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
805  gt7_txresetdone_out : out std_logic;
806  ------------------ Transmit Ports - pattern Generator Ports ----------------
807  gt7_txprbssel_in : in std_logic_vector(2 downto 0);
808 
809  --GT8 (X1Y8)
810  --____________________________CHANNEL PORTS________________________________
811  ---------------------------- Channel - DRP Ports --------------------------
812  gt8_drpaddr_in : in std_logic_vector(8 downto 0);
813  gt8_drpclk_in : in std_logic;
814  gt8_drpdi_in : in std_logic_vector(15 downto 0);
815  gt8_drpdo_out : out std_logic_vector(15 downto 0);
816  gt8_drpen_in : in std_logic;
817  gt8_drprdy_out : out std_logic;
818  gt8_drpwe_in : in std_logic;
819  --------------------------- Digital Monitor Ports --------------------------
820  gt8_dmonitorout_out : out std_logic_vector(7 downto 0);
821  ------------------------------- Loopback Ports -----------------------------
822  gt8_loopback_in : in std_logic_vector(2 downto 0);
823  ------------------------------ Power-Down Ports ----------------------------
824  gt8_rxpd_in : in std_logic_vector(1 downto 0);
825  gt8_txpd_in : in std_logic_vector(1 downto 0);
826  --------------------- RX Initialization and Reset Ports --------------------
827  gt8_eyescanreset_in : in std_logic;
828  gt8_rxuserrdy_in : in std_logic;
829  -------------------------- RX Margin Analysis Ports ------------------------
830  gt8_eyescandataerror_out : out std_logic;
831  gt8_eyescantrigger_in : in std_logic;
832  ------------------- Receive Ports - Clock Correction Ports -----------------
833  gt8_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
834  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
835  gt8_rxusrclk_in : in std_logic;
836  gt8_rxusrclk2_in : in std_logic;
837  ------------------ Receive Ports - FPGA RX interface Ports -----------------
838  gt8_rxdata_out : out std_logic_vector(15 downto 0);
839  ------------------- Receive Ports - Pattern Checker Ports ------------------
840  gt8_rxprbserr_out : out std_logic;
841  gt8_rxprbssel_in : in std_logic_vector(2 downto 0);
842  ------------------- Receive Ports - Pattern Checker ports ------------------
843  gt8_rxprbscntreset_in : in std_logic;
844  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
845  gt8_rxdisperr_out : out std_logic_vector(1 downto 0);
846  gt8_rxnotintable_out : out std_logic_vector(1 downto 0);
847  --------------------------- Receive Ports - RX AFE -------------------------
848  gt8_gtxrxp_in : in std_logic;
849  ------------------------ Receive Ports - RX AFE Ports ----------------------
850  gt8_gtxrxn_in : in std_logic;
851  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
852  gt8_rxbufstatus_out : out std_logic_vector(2 downto 0);
853  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
854  gt8_rxmcommaalignen_in : in std_logic;
855  gt8_rxpcommaalignen_in : in std_logic;
856  --------------------- Receive Ports - RX Equalizer Ports -------------------
857  gt8_rxdfelpmreset_in : in std_logic;
858  gt8_rxmonitorout_out : out std_logic_vector(6 downto 0);
859  gt8_rxmonitorsel_in : in std_logic_vector(1 downto 0);
860  --------------- Receive Ports - RX Fabric Output Control Ports -------------
861  gt8_rxoutclk_out : out std_logic;
862  ------------- Receive Ports - RX Initialization and Reset Ports ------------
863  gt8_gtrxreset_in : in std_logic;
864  gt8_rxpmareset_in : in std_logic;
865  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
866  gt8_rxchariscomma_out : out std_logic_vector(1 downto 0);
867  gt8_rxcharisk_out : out std_logic_vector(1 downto 0);
868  -------------- Receive Ports -RX Initialization and Reset Ports ------------
869  gt8_rxresetdone_out : out std_logic;
870  --------------------- TX Initialization and Reset Ports --------------------
871  gt8_gttxreset_in : in std_logic;
872  gt8_txuserrdy_in : in std_logic;
873  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
874  gt8_txusrclk_in : in std_logic;
875  gt8_txusrclk2_in : in std_logic;
876  --------------- Transmit Ports - TX Configurable Driver Ports --------------
877  gt8_txdiffctrl_in : in std_logic_vector(3 downto 0);
878  ------------------ Transmit Ports - TX Data Path interface -----------------
879  gt8_txdata_in : in std_logic_vector(15 downto 0);
880  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
881  gt8_gtxtxn_out : out std_logic;
882  gt8_gtxtxp_out : out std_logic;
883  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
884  gt8_txoutclk_out : out std_logic;
885  gt8_txoutclkfabric_out : out std_logic;
886  gt8_txoutclkpcs_out : out std_logic;
887  --------------------- Transmit Ports - TX Gearbox Ports --------------------
888  gt8_txcharisk_in : in std_logic_vector(1 downto 0);
889  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
890  gt8_txresetdone_out : out std_logic;
891  ------------------ Transmit Ports - pattern Generator Ports ----------------
892  gt8_txprbssel_in : in std_logic_vector(2 downto 0);
893 
894  --GT9 (X1Y9)
895  --____________________________CHANNEL PORTS________________________________
896  ---------------------------- Channel - DRP Ports --------------------------
897  gt9_drpaddr_in : in std_logic_vector(8 downto 0);
898  gt9_drpclk_in : in std_logic;
899  gt9_drpdi_in : in std_logic_vector(15 downto 0);
900  gt9_drpdo_out : out std_logic_vector(15 downto 0);
901  gt9_drpen_in : in std_logic;
902  gt9_drprdy_out : out std_logic;
903  gt9_drpwe_in : in std_logic;
904  --------------------------- Digital Monitor Ports --------------------------
905  gt9_dmonitorout_out : out std_logic_vector(7 downto 0);
906  ------------------------------- Loopback Ports -----------------------------
907  gt9_loopback_in : in std_logic_vector(2 downto 0);
908  ------------------------------ Power-Down Ports ----------------------------
909  gt9_rxpd_in : in std_logic_vector(1 downto 0);
910  gt9_txpd_in : in std_logic_vector(1 downto 0);
911  --------------------- RX Initialization and Reset Ports --------------------
912  gt9_eyescanreset_in : in std_logic;
913  gt9_rxuserrdy_in : in std_logic;
914  -------------------------- RX Margin Analysis Ports ------------------------
915  gt9_eyescandataerror_out : out std_logic;
916  gt9_eyescantrigger_in : in std_logic;
917  ------------------- Receive Ports - Clock Correction Ports -----------------
918  gt9_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
919  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
920  gt9_rxusrclk_in : in std_logic;
921  gt9_rxusrclk2_in : in std_logic;
922  ------------------ Receive Ports - FPGA RX interface Ports -----------------
923  gt9_rxdata_out : out std_logic_vector(15 downto 0);
924  ------------------- Receive Ports - Pattern Checker Ports ------------------
925  gt9_rxprbserr_out : out std_logic;
926  gt9_rxprbssel_in : in std_logic_vector(2 downto 0);
927  ------------------- Receive Ports - Pattern Checker ports ------------------
928  gt9_rxprbscntreset_in : in std_logic;
929  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
930  gt9_rxdisperr_out : out std_logic_vector(1 downto 0);
931  gt9_rxnotintable_out : out std_logic_vector(1 downto 0);
932  --------------------------- Receive Ports - RX AFE -------------------------
933  gt9_gtxrxp_in : in std_logic;
934  ------------------------ Receive Ports - RX AFE Ports ----------------------
935  gt9_gtxrxn_in : in std_logic;
936  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
937  gt9_rxbufstatus_out : out std_logic_vector(2 downto 0);
938  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
939  gt9_rxmcommaalignen_in : in std_logic;
940  gt9_rxpcommaalignen_in : in std_logic;
941  --------------------- Receive Ports - RX Equalizer Ports -------------------
942  gt9_rxdfelpmreset_in : in std_logic;
943  gt9_rxmonitorout_out : out std_logic_vector(6 downto 0);
944  gt9_rxmonitorsel_in : in std_logic_vector(1 downto 0);
945  --------------- Receive Ports - RX Fabric Output Control Ports -------------
946  gt9_rxoutclk_out : out std_logic;
947  ------------- Receive Ports - RX Initialization and Reset Ports ------------
948  gt9_gtrxreset_in : in std_logic;
949  gt9_rxpmareset_in : in std_logic;
950  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
951  gt9_rxchariscomma_out : out std_logic_vector(1 downto 0);
952  gt9_rxcharisk_out : out std_logic_vector(1 downto 0);
953  -------------- Receive Ports -RX Initialization and Reset Ports ------------
954  gt9_rxresetdone_out : out std_logic;
955  --------------------- TX Initialization and Reset Ports --------------------
956  gt9_gttxreset_in : in std_logic;
957  gt9_txuserrdy_in : in std_logic;
958  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
959  gt9_txusrclk_in : in std_logic;
960  gt9_txusrclk2_in : in std_logic;
961  --------------- Transmit Ports - TX Configurable Driver Ports --------------
962  gt9_txdiffctrl_in : in std_logic_vector(3 downto 0);
963  ------------------ Transmit Ports - TX Data Path interface -----------------
964  gt9_txdata_in : in std_logic_vector(15 downto 0);
965  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
966  gt9_gtxtxn_out : out std_logic;
967  gt9_gtxtxp_out : out std_logic;
968  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
969  gt9_txoutclk_out : out std_logic;
970  gt9_txoutclkfabric_out : out std_logic;
971  gt9_txoutclkpcs_out : out std_logic;
972  --------------------- Transmit Ports - TX Gearbox Ports --------------------
973  gt9_txcharisk_in : in std_logic_vector(1 downto 0);
974  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
975  gt9_txresetdone_out : out std_logic;
976  ------------------ Transmit Ports - pattern Generator Ports ----------------
977  gt9_txprbssel_in : in std_logic_vector(2 downto 0);
978 
979  --GT10 (X1Y10)
980  --____________________________CHANNEL PORTS________________________________
981  ---------------------------- Channel - DRP Ports --------------------------
982  gt10_drpaddr_in : in std_logic_vector(8 downto 0);
983  gt10_drpclk_in : in std_logic;
984  gt10_drpdi_in : in std_logic_vector(15 downto 0);
985  gt10_drpdo_out : out std_logic_vector(15 downto 0);
986  gt10_drpen_in : in std_logic;
987  gt10_drprdy_out : out std_logic;
988  gt10_drpwe_in : in std_logic;
989  --------------------------- Digital Monitor Ports --------------------------
990  gt10_dmonitorout_out : out std_logic_vector(7 downto 0);
991  ------------------------------- Loopback Ports -----------------------------
992  gt10_loopback_in : in std_logic_vector(2 downto 0);
993  ------------------------------ Power-Down Ports ----------------------------
994  gt10_rxpd_in : in std_logic_vector(1 downto 0);
995  gt10_txpd_in : in std_logic_vector(1 downto 0);
996  --------------------- RX Initialization and Reset Ports --------------------
997  gt10_eyescanreset_in : in std_logic;
998  gt10_rxuserrdy_in : in std_logic;
999  -------------------------- RX Margin Analysis Ports ------------------------
1000  gt10_eyescandataerror_out : out std_logic;
1001  gt10_eyescantrigger_in : in std_logic;
1002  ------------------- Receive Ports - Clock Correction Ports -----------------
1003  gt10_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1004  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1005  gt10_rxusrclk_in : in std_logic;
1006  gt10_rxusrclk2_in : in std_logic;
1007  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1008  gt10_rxdata_out : out std_logic_vector(15 downto 0);
1009  ------------------- Receive Ports - Pattern Checker Ports ------------------
1010  gt10_rxprbserr_out : out std_logic;
1011  gt10_rxprbssel_in : in std_logic_vector(2 downto 0);
1012  ------------------- Receive Ports - Pattern Checker ports ------------------
1013  gt10_rxprbscntreset_in : in std_logic;
1014  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1015  gt10_rxdisperr_out : out std_logic_vector(1 downto 0);
1016  gt10_rxnotintable_out : out std_logic_vector(1 downto 0);
1017  --------------------------- Receive Ports - RX AFE -------------------------
1018  gt10_gtxrxp_in : in std_logic;
1019  ------------------------ Receive Ports - RX AFE Ports ----------------------
1020  gt10_gtxrxn_in : in std_logic;
1021  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1022  gt10_rxbufstatus_out : out std_logic_vector(2 downto 0);
1023  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1024  gt10_rxmcommaalignen_in : in std_logic;
1025  gt10_rxpcommaalignen_in : in std_logic;
1026  --------------------- Receive Ports - RX Equalizer Ports -------------------
1027  gt10_rxdfelpmreset_in : in std_logic;
1028  gt10_rxmonitorout_out : out std_logic_vector(6 downto 0);
1029  gt10_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1030  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1031  gt10_rxoutclk_out : out std_logic;
1032  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1033  gt10_gtrxreset_in : in std_logic;
1034  gt10_rxpmareset_in : in std_logic;
1035  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1036  gt10_rxchariscomma_out : out std_logic_vector(1 downto 0);
1037  gt10_rxcharisk_out : out std_logic_vector(1 downto 0);
1038  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1039  gt10_rxresetdone_out : out std_logic;
1040  --------------------- TX Initialization and Reset Ports --------------------
1041  gt10_gttxreset_in : in std_logic;
1042  gt10_txuserrdy_in : in std_logic;
1043  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1044  gt10_txusrclk_in : in std_logic;
1045  gt10_txusrclk2_in : in std_logic;
1046  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1047  gt10_txdiffctrl_in : in std_logic_vector(3 downto 0);
1048  ------------------ Transmit Ports - TX Data Path interface -----------------
1049  gt10_txdata_in : in std_logic_vector(15 downto 0);
1050  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1051  gt10_gtxtxn_out : out std_logic;
1052  gt10_gtxtxp_out : out std_logic;
1053  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1054  gt10_txoutclk_out : out std_logic;
1055  gt10_txoutclkfabric_out : out std_logic;
1056  gt10_txoutclkpcs_out : out std_logic;
1057  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1058  gt10_txcharisk_in : in std_logic_vector(1 downto 0);
1059  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1060  gt10_txresetdone_out : out std_logic;
1061  ------------------ Transmit Ports - pattern Generator Ports ----------------
1062  gt10_txprbssel_in : in std_logic_vector(2 downto 0);
1063 
1064  --GT11 (X1Y11)
1065  --____________________________CHANNEL PORTS________________________________
1066  ---------------------------- Channel - DRP Ports --------------------------
1067  gt11_drpaddr_in : in std_logic_vector(8 downto 0);
1068  gt11_drpclk_in : in std_logic;
1069  gt11_drpdi_in : in std_logic_vector(15 downto 0);
1070  gt11_drpdo_out : out std_logic_vector(15 downto 0);
1071  gt11_drpen_in : in std_logic;
1072  gt11_drprdy_out : out std_logic;
1073  gt11_drpwe_in : in std_logic;
1074  --------------------------- Digital Monitor Ports --------------------------
1075  gt11_dmonitorout_out : out std_logic_vector(7 downto 0);
1076  ------------------------------- Loopback Ports -----------------------------
1077  gt11_loopback_in : in std_logic_vector(2 downto 0);
1078  ------------------------------ Power-Down Ports ----------------------------
1079  gt11_rxpd_in : in std_logic_vector(1 downto 0);
1080  gt11_txpd_in : in std_logic_vector(1 downto 0);
1081  --------------------- RX Initialization and Reset Ports --------------------
1082  gt11_eyescanreset_in : in std_logic;
1083  gt11_rxuserrdy_in : in std_logic;
1084  -------------------------- RX Margin Analysis Ports ------------------------
1085  gt11_eyescandataerror_out : out std_logic;
1086  gt11_eyescantrigger_in : in std_logic;
1087  ------------------- Receive Ports - Clock Correction Ports -----------------
1088  gt11_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1089  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1090  gt11_rxusrclk_in : in std_logic;
1091  gt11_rxusrclk2_in : in std_logic;
1092  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1093  gt11_rxdata_out : out std_logic_vector(15 downto 0);
1094  ------------------- Receive Ports - Pattern Checker Ports ------------------
1095  gt11_rxprbserr_out : out std_logic;
1096  gt11_rxprbssel_in : in std_logic_vector(2 downto 0);
1097  ------------------- Receive Ports - Pattern Checker ports ------------------
1098  gt11_rxprbscntreset_in : in std_logic;
1099  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1100  gt11_rxdisperr_out : out std_logic_vector(1 downto 0);
1101  gt11_rxnotintable_out : out std_logic_vector(1 downto 0);
1102  --------------------------- Receive Ports - RX AFE -------------------------
1103  gt11_gtxrxp_in : in std_logic;
1104  ------------------------ Receive Ports - RX AFE Ports ----------------------
1105  gt11_gtxrxn_in : in std_logic;
1106  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1107  gt11_rxbufstatus_out : out std_logic_vector(2 downto 0);
1108  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1109  gt11_rxmcommaalignen_in : in std_logic;
1110  gt11_rxpcommaalignen_in : in std_logic;
1111  --------------------- Receive Ports - RX Equalizer Ports -------------------
1112  gt11_rxdfelpmreset_in : in std_logic;
1113  gt11_rxmonitorout_out : out std_logic_vector(6 downto 0);
1114  gt11_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1115  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1116  gt11_rxoutclk_out : out std_logic;
1117  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1118  gt11_gtrxreset_in : in std_logic;
1119  gt11_rxpmareset_in : in std_logic;
1120  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1121  gt11_rxchariscomma_out : out std_logic_vector(1 downto 0);
1122  gt11_rxcharisk_out : out std_logic_vector(1 downto 0);
1123  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1124  gt11_rxresetdone_out : out std_logic;
1125  --------------------- TX Initialization and Reset Ports --------------------
1126  gt11_gttxreset_in : in std_logic;
1127  gt11_txuserrdy_in : in std_logic;
1128  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1129  gt11_txusrclk_in : in std_logic;
1130  gt11_txusrclk2_in : in std_logic;
1131  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1132  gt11_txdiffctrl_in : in std_logic_vector(3 downto 0);
1133  ------------------ Transmit Ports - TX Data Path interface -----------------
1134  gt11_txdata_in : in std_logic_vector(15 downto 0);
1135  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1136  gt11_gtxtxn_out : out std_logic;
1137  gt11_gtxtxp_out : out std_logic;
1138  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1139  gt11_txoutclk_out : out std_logic;
1140  gt11_txoutclkfabric_out : out std_logic;
1141  gt11_txoutclkpcs_out : out std_logic;
1142  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1143  gt11_txcharisk_in : in std_logic_vector(1 downto 0);
1144  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1145  gt11_txresetdone_out : out std_logic;
1146  ------------------ Transmit Ports - pattern Generator Ports ----------------
1147  gt11_txprbssel_in : in std_logic_vector(2 downto 0);
1148 
1149 
1150  --____________________________COMMON PORTS________________________________
1151  GT0_QPLLLOCK_IN : in std_logic;
1152  GT0_QPLLREFCLKLOST_IN : in std_logic;
1153  GT0_QPLLRESET_OUT : out std_logic;
1154  GT0_QPLLOUTCLK_IN : in std_logic;
1155  GT0_QPLLOUTREFCLK_IN : in std_logic;
1156  --____________________________COMMON PORTS________________________________
1157  GT1_QPLLLOCK_IN : in std_logic;
1158  GT1_QPLLREFCLKLOST_IN : in std_logic;
1159  GT1_QPLLRESET_OUT : out std_logic;
1160  GT1_QPLLOUTCLK_IN : in std_logic;
1161  GT1_QPLLOUTREFCLK_IN : in std_logic;
1162  --____________________________COMMON PORTS________________________________
1163  GT2_QPLLLOCK_IN : in std_logic;
1164  GT2_QPLLREFCLKLOST_IN : in std_logic;
1165  GT2_QPLLRESET_OUT : out std_logic;
1166  GT2_QPLLOUTCLK_IN : in std_logic;
1167  GT2_QPLLOUTREFCLK_IN : in std_logic
1168 
1169 );
1170 
1171 end amc_gtx5Gpd_init;
1172 
1173 architecture RTL of amc_gtx5Gpd_init is
1174 attribute DowngradeIPIdentifiedWarnings: string;
1175 attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
1176 
1177 --**************************Component Declarations*****************************
1178 
1179 
1180 component amc_gtx5Gpd_multi_gt
1181 generic
1182 (
1183  -- Simulation attributes
1184  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
1185 
1186 );
1187 port
1188 (
1189 
1190  --_________________________________________________________________________
1191  --_________________________________________________________________________
1192  --GT0 (X1Y0)
1193  --____________________________CHANNEL PORTS________________________________
1194 
1195  ---------------------------- Channel - DRP Ports --------------------------
1196  gt0_drpaddr_in : in std_logic_vector(8 downto 0);
1197  gt0_drpclk_in : in std_logic;
1198  gt0_drpdi_in : in std_logic_vector(15 downto 0);
1199  gt0_drpdo_out : out std_logic_vector(15 downto 0);
1200  gt0_drpen_in : in std_logic;
1201  gt0_drprdy_out : out std_logic;
1202  gt0_drpwe_in : in std_logic;
1203  --------------------------- Digital Monitor Ports --------------------------
1204  gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
1205  ------------------------------- Loopback Ports -----------------------------
1206  gt0_loopback_in : in std_logic_vector(2 downto 0);
1207  ------------------------------ Power-Down Ports ----------------------------
1208  gt0_rxpd_in : in std_logic_vector(1 downto 0);
1209  gt0_txpd_in : in std_logic_vector(1 downto 0);
1210  --------------------- RX Initialization and Reset Ports --------------------
1211  gt0_eyescanreset_in : in std_logic;
1212  gt0_rxuserrdy_in : in std_logic;
1213  -------------------------- RX Margin Analysis Ports ------------------------
1214  gt0_eyescandataerror_out : out std_logic;
1215  gt0_eyescantrigger_in : in std_logic;
1216  ------------------- Receive Ports - Clock Correction Ports -----------------
1217  gt0_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1218  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1219  gt0_rxusrclk_in : in std_logic;
1220  gt0_rxusrclk2_in : in std_logic;
1221  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1222  gt0_rxdata_out : out std_logic_vector(15 downto 0);
1223  ------------------- Receive Ports - Pattern Checker Ports ------------------
1224  gt0_rxprbserr_out : out std_logic;
1225  gt0_rxprbssel_in : in std_logic_vector(2 downto 0);
1226  ------------------- Receive Ports - Pattern Checker ports ------------------
1227  gt0_rxprbscntreset_in : in std_logic;
1228  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1229  gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
1230  gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
1231  --------------------------- Receive Ports - RX AFE -------------------------
1232  gt0_gtxrxp_in : in std_logic;
1233  ------------------------ Receive Ports - RX AFE Ports ----------------------
1234  gt0_gtxrxn_in : in std_logic;
1235  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1236  gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
1237  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1238  gt0_rxmcommaalignen_in : in std_logic;
1239  gt0_rxpcommaalignen_in : in std_logic;
1240  --------------------- Receive Ports - RX Equalizer Ports -------------------
1241  gt0_rxdfeagchold_in : in std_logic;
1242  gt0_rxdfelfhold_in : in std_logic;
1243  gt0_rxdfelpmreset_in : in std_logic;
1244  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
1245  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1246  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1247  gt0_rxoutclk_out : out std_logic;
1248  gt0_rxoutclkfabric_out : out std_logic;
1249  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1250  gt0_gtrxreset_in : in std_logic;
1251  gt0_rxpmareset_in : in std_logic;
1252  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1253  gt0_rxchariscomma_out : out std_logic_vector(1 downto 0);
1254  gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
1255  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1256  gt0_rxresetdone_out : out std_logic;
1257  --------------------- TX Initialization and Reset Ports --------------------
1258  gt0_gttxreset_in : in std_logic;
1259  gt0_txuserrdy_in : in std_logic;
1260  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1261  gt0_txusrclk_in : in std_logic;
1262  gt0_txusrclk2_in : in std_logic;
1263  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1264  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
1265  ------------------ Transmit Ports - TX Data Path interface -----------------
1266  gt0_txdata_in : in std_logic_vector(15 downto 0);
1267  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1268  gt0_gtxtxn_out : out std_logic;
1269  gt0_gtxtxp_out : out std_logic;
1270  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1271  gt0_txoutclk_out : out std_logic;
1272  gt0_txoutclkfabric_out : out std_logic;
1273  gt0_txoutclkpcs_out : out std_logic;
1274  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1275  gt0_txcharisk_in : in std_logic_vector(1 downto 0);
1276  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1277  gt0_txresetdone_out : out std_logic;
1278  ------------------ Transmit Ports - pattern Generator Ports ----------------
1279  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
1280 
1281  --_________________________________________________________________________
1282  --_________________________________________________________________________
1283  --GT1 (X1Y1)
1284  --____________________________CHANNEL PORTS________________________________
1285 
1286  ---------------------------- Channel - DRP Ports --------------------------
1287  gt1_drpaddr_in : in std_logic_vector(8 downto 0);
1288  gt1_drpclk_in : in std_logic;
1289  gt1_drpdi_in : in std_logic_vector(15 downto 0);
1290  gt1_drpdo_out : out std_logic_vector(15 downto 0);
1291  gt1_drpen_in : in std_logic;
1292  gt1_drprdy_out : out std_logic;
1293  gt1_drpwe_in : in std_logic;
1294  --------------------------- Digital Monitor Ports --------------------------
1295  gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
1296  ------------------------------- Loopback Ports -----------------------------
1297  gt1_loopback_in : in std_logic_vector(2 downto 0);
1298  ------------------------------ Power-Down Ports ----------------------------
1299  gt1_rxpd_in : in std_logic_vector(1 downto 0);
1300  gt1_txpd_in : in std_logic_vector(1 downto 0);
1301  --------------------- RX Initialization and Reset Ports --------------------
1302  gt1_eyescanreset_in : in std_logic;
1303  gt1_rxuserrdy_in : in std_logic;
1304  -------------------------- RX Margin Analysis Ports ------------------------
1305  gt1_eyescandataerror_out : out std_logic;
1306  gt1_eyescantrigger_in : in std_logic;
1307  ------------------- Receive Ports - Clock Correction Ports -----------------
1308  gt1_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1309  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1310  gt1_rxusrclk_in : in std_logic;
1311  gt1_rxusrclk2_in : in std_logic;
1312  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1313  gt1_rxdata_out : out std_logic_vector(15 downto 0);
1314  ------------------- Receive Ports - Pattern Checker Ports ------------------
1315  gt1_rxprbserr_out : out std_logic;
1316  gt1_rxprbssel_in : in std_logic_vector(2 downto 0);
1317  ------------------- Receive Ports - Pattern Checker ports ------------------
1318  gt1_rxprbscntreset_in : in std_logic;
1319  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1320  gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
1321  gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
1322  --------------------------- Receive Ports - RX AFE -------------------------
1323  gt1_gtxrxp_in : in std_logic;
1324  ------------------------ Receive Ports - RX AFE Ports ----------------------
1325  gt1_gtxrxn_in : in std_logic;
1326  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1327  gt1_rxbufstatus_out : out std_logic_vector(2 downto 0);
1328  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1329  gt1_rxmcommaalignen_in : in std_logic;
1330  gt1_rxpcommaalignen_in : in std_logic;
1331  --------------------- Receive Ports - RX Equalizer Ports -------------------
1332  gt1_rxdfeagchold_in : in std_logic;
1333  gt1_rxdfelfhold_in : in std_logic;
1334  gt1_rxdfelpmreset_in : in std_logic;
1335  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
1336  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1337  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1338  gt1_rxoutclk_out : out std_logic;
1339  gt1_rxoutclkfabric_out : out std_logic;
1340  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1341  gt1_gtrxreset_in : in std_logic;
1342  gt1_rxpmareset_in : in std_logic;
1343  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1344  gt1_rxchariscomma_out : out std_logic_vector(1 downto 0);
1345  gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
1346  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1347  gt1_rxresetdone_out : out std_logic;
1348  --------------------- TX Initialization and Reset Ports --------------------
1349  gt1_gttxreset_in : in std_logic;
1350  gt1_txuserrdy_in : in std_logic;
1351  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1352  gt1_txusrclk_in : in std_logic;
1353  gt1_txusrclk2_in : in std_logic;
1354  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1355  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
1356  ------------------ Transmit Ports - TX Data Path interface -----------------
1357  gt1_txdata_in : in std_logic_vector(15 downto 0);
1358  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1359  gt1_gtxtxn_out : out std_logic;
1360  gt1_gtxtxp_out : out std_logic;
1361  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1362  gt1_txoutclk_out : out std_logic;
1363  gt1_txoutclkfabric_out : out std_logic;
1364  gt1_txoutclkpcs_out : out std_logic;
1365  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1366  gt1_txcharisk_in : in std_logic_vector(1 downto 0);
1367  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1368  gt1_txresetdone_out : out std_logic;
1369  ------------------ Transmit Ports - pattern Generator Ports ----------------
1370  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
1371 
1372  --_________________________________________________________________________
1373  --_________________________________________________________________________
1374  --GT2 (X1Y2)
1375  --____________________________CHANNEL PORTS________________________________
1376 
1377  ---------------------------- Channel - DRP Ports --------------------------
1378  gt2_drpaddr_in : in std_logic_vector(8 downto 0);
1379  gt2_drpclk_in : in std_logic;
1380  gt2_drpdi_in : in std_logic_vector(15 downto 0);
1381  gt2_drpdo_out : out std_logic_vector(15 downto 0);
1382  gt2_drpen_in : in std_logic;
1383  gt2_drprdy_out : out std_logic;
1384  gt2_drpwe_in : in std_logic;
1385  --------------------------- Digital Monitor Ports --------------------------
1386  gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
1387  ------------------------------- Loopback Ports -----------------------------
1388  gt2_loopback_in : in std_logic_vector(2 downto 0);
1389  ------------------------------ Power-Down Ports ----------------------------
1390  gt2_rxpd_in : in std_logic_vector(1 downto 0);
1391  gt2_txpd_in : in std_logic_vector(1 downto 0);
1392  --------------------- RX Initialization and Reset Ports --------------------
1393  gt2_eyescanreset_in : in std_logic;
1394  gt2_rxuserrdy_in : in std_logic;
1395  -------------------------- RX Margin Analysis Ports ------------------------
1396  gt2_eyescandataerror_out : out std_logic;
1397  gt2_eyescantrigger_in : in std_logic;
1398  ------------------- Receive Ports - Clock Correction Ports -----------------
1399  gt2_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1400  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1401  gt2_rxusrclk_in : in std_logic;
1402  gt2_rxusrclk2_in : in std_logic;
1403  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1404  gt2_rxdata_out : out std_logic_vector(15 downto 0);
1405  ------------------- Receive Ports - Pattern Checker Ports ------------------
1406  gt2_rxprbserr_out : out std_logic;
1407  gt2_rxprbssel_in : in std_logic_vector(2 downto 0);
1408  ------------------- Receive Ports - Pattern Checker ports ------------------
1409  gt2_rxprbscntreset_in : in std_logic;
1410  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1411  gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
1412  gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
1413  --------------------------- Receive Ports - RX AFE -------------------------
1414  gt2_gtxrxp_in : in std_logic;
1415  ------------------------ Receive Ports - RX AFE Ports ----------------------
1416  gt2_gtxrxn_in : in std_logic;
1417  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1418  gt2_rxbufstatus_out : out std_logic_vector(2 downto 0);
1419  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1420  gt2_rxmcommaalignen_in : in std_logic;
1421  gt2_rxpcommaalignen_in : in std_logic;
1422  --------------------- Receive Ports - RX Equalizer Ports -------------------
1423  gt2_rxdfeagchold_in : in std_logic;
1424  gt2_rxdfelfhold_in : in std_logic;
1425  gt2_rxdfelpmreset_in : in std_logic;
1426  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
1427  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1428  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1429  gt2_rxoutclk_out : out std_logic;
1430  gt2_rxoutclkfabric_out : out std_logic;
1431  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1432  gt2_gtrxreset_in : in std_logic;
1433  gt2_rxpmareset_in : in std_logic;
1434  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1435  gt2_rxchariscomma_out : out std_logic_vector(1 downto 0);
1436  gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
1437  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1438  gt2_rxresetdone_out : out std_logic;
1439  --------------------- TX Initialization and Reset Ports --------------------
1440  gt2_gttxreset_in : in std_logic;
1441  gt2_txuserrdy_in : in std_logic;
1442  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1443  gt2_txusrclk_in : in std_logic;
1444  gt2_txusrclk2_in : in std_logic;
1445  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1446  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
1447  ------------------ Transmit Ports - TX Data Path interface -----------------
1448  gt2_txdata_in : in std_logic_vector(15 downto 0);
1449  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1450  gt2_gtxtxn_out : out std_logic;
1451  gt2_gtxtxp_out : out std_logic;
1452  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1453  gt2_txoutclk_out : out std_logic;
1454  gt2_txoutclkfabric_out : out std_logic;
1455  gt2_txoutclkpcs_out : out std_logic;
1456  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1457  gt2_txcharisk_in : in std_logic_vector(1 downto 0);
1458  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1459  gt2_txresetdone_out : out std_logic;
1460  ------------------ Transmit Ports - pattern Generator Ports ----------------
1461  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
1462 
1463  --_________________________________________________________________________
1464  --_________________________________________________________________________
1465  --GT3 (X1Y3)
1466  --____________________________CHANNEL PORTS________________________________
1467 
1468  ---------------------------- Channel - DRP Ports --------------------------
1469  gt3_drpaddr_in : in std_logic_vector(8 downto 0);
1470  gt3_drpclk_in : in std_logic;
1471  gt3_drpdi_in : in std_logic_vector(15 downto 0);
1472  gt3_drpdo_out : out std_logic_vector(15 downto 0);
1473  gt3_drpen_in : in std_logic;
1474  gt3_drprdy_out : out std_logic;
1475  gt3_drpwe_in : in std_logic;
1476  --------------------------- Digital Monitor Ports --------------------------
1477  gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
1478  ------------------------------- Loopback Ports -----------------------------
1479  gt3_loopback_in : in std_logic_vector(2 downto 0);
1480  ------------------------------ Power-Down Ports ----------------------------
1481  gt3_rxpd_in : in std_logic_vector(1 downto 0);
1482  gt3_txpd_in : in std_logic_vector(1 downto 0);
1483  --------------------- RX Initialization and Reset Ports --------------------
1484  gt3_eyescanreset_in : in std_logic;
1485  gt3_rxuserrdy_in : in std_logic;
1486  -------------------------- RX Margin Analysis Ports ------------------------
1487  gt3_eyescandataerror_out : out std_logic;
1488  gt3_eyescantrigger_in : in std_logic;
1489  ------------------- Receive Ports - Clock Correction Ports -----------------
1490  gt3_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1491  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1492  gt3_rxusrclk_in : in std_logic;
1493  gt3_rxusrclk2_in : in std_logic;
1494  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1495  gt3_rxdata_out : out std_logic_vector(15 downto 0);
1496  ------------------- Receive Ports - Pattern Checker Ports ------------------
1497  gt3_rxprbserr_out : out std_logic;
1498  gt3_rxprbssel_in : in std_logic_vector(2 downto 0);
1499  ------------------- Receive Ports - Pattern Checker ports ------------------
1500  gt3_rxprbscntreset_in : in std_logic;
1501  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1502  gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
1503  gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
1504  --------------------------- Receive Ports - RX AFE -------------------------
1505  gt3_gtxrxp_in : in std_logic;
1506  ------------------------ Receive Ports - RX AFE Ports ----------------------
1507  gt3_gtxrxn_in : in std_logic;
1508  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1509  gt3_rxbufstatus_out : out std_logic_vector(2 downto 0);
1510  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1511  gt3_rxmcommaalignen_in : in std_logic;
1512  gt3_rxpcommaalignen_in : in std_logic;
1513  --------------------- Receive Ports - RX Equalizer Ports -------------------
1514  gt3_rxdfeagchold_in : in std_logic;
1515  gt3_rxdfelfhold_in : in std_logic;
1516  gt3_rxdfelpmreset_in : in std_logic;
1517  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
1518  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1519  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1520  gt3_rxoutclk_out : out std_logic;
1521  gt3_rxoutclkfabric_out : out std_logic;
1522  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1523  gt3_gtrxreset_in : in std_logic;
1524  gt3_rxpmareset_in : in std_logic;
1525  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1526  gt3_rxchariscomma_out : out std_logic_vector(1 downto 0);
1527  gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
1528  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1529  gt3_rxresetdone_out : out std_logic;
1530  --------------------- TX Initialization and Reset Ports --------------------
1531  gt3_gttxreset_in : in std_logic;
1532  gt3_txuserrdy_in : in std_logic;
1533  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1534  gt3_txusrclk_in : in std_logic;
1535  gt3_txusrclk2_in : in std_logic;
1536  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1537  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
1538  ------------------ Transmit Ports - TX Data Path interface -----------------
1539  gt3_txdata_in : in std_logic_vector(15 downto 0);
1540  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1541  gt3_gtxtxn_out : out std_logic;
1542  gt3_gtxtxp_out : out std_logic;
1543  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1544  gt3_txoutclk_out : out std_logic;
1545  gt3_txoutclkfabric_out : out std_logic;
1546  gt3_txoutclkpcs_out : out std_logic;
1547  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1548  gt3_txcharisk_in : in std_logic_vector(1 downto 0);
1549  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1550  gt3_txresetdone_out : out std_logic;
1551  ------------------ Transmit Ports - pattern Generator Ports ----------------
1552  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
1553 
1554  --_________________________________________________________________________
1555  --_________________________________________________________________________
1556  --GT4 (X1Y4)
1557  --____________________________CHANNEL PORTS________________________________
1558 
1559  ---------------------------- Channel - DRP Ports --------------------------
1560  gt4_drpaddr_in : in std_logic_vector(8 downto 0);
1561  gt4_drpclk_in : in std_logic;
1562  gt4_drpdi_in : in std_logic_vector(15 downto 0);
1563  gt4_drpdo_out : out std_logic_vector(15 downto 0);
1564  gt4_drpen_in : in std_logic;
1565  gt4_drprdy_out : out std_logic;
1566  gt4_drpwe_in : in std_logic;
1567  --------------------------- Digital Monitor Ports --------------------------
1568  gt4_dmonitorout_out : out std_logic_vector(7 downto 0);
1569  ------------------------------- Loopback Ports -----------------------------
1570  gt4_loopback_in : in std_logic_vector(2 downto 0);
1571  ------------------------------ Power-Down Ports ----------------------------
1572  gt4_rxpd_in : in std_logic_vector(1 downto 0);
1573  gt4_txpd_in : in std_logic_vector(1 downto 0);
1574  --------------------- RX Initialization and Reset Ports --------------------
1575  gt4_eyescanreset_in : in std_logic;
1576  gt4_rxuserrdy_in : in std_logic;
1577  -------------------------- RX Margin Analysis Ports ------------------------
1578  gt4_eyescandataerror_out : out std_logic;
1579  gt4_eyescantrigger_in : in std_logic;
1580  ------------------- Receive Ports - Clock Correction Ports -----------------
1581  gt4_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1582  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1583  gt4_rxusrclk_in : in std_logic;
1584  gt4_rxusrclk2_in : in std_logic;
1585  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1586  gt4_rxdata_out : out std_logic_vector(15 downto 0);
1587  ------------------- Receive Ports - Pattern Checker Ports ------------------
1588  gt4_rxprbserr_out : out std_logic;
1589  gt4_rxprbssel_in : in std_logic_vector(2 downto 0);
1590  ------------------- Receive Ports - Pattern Checker ports ------------------
1591  gt4_rxprbscntreset_in : in std_logic;
1592  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1593  gt4_rxdisperr_out : out std_logic_vector(1 downto 0);
1594  gt4_rxnotintable_out : out std_logic_vector(1 downto 0);
1595  --------------------------- Receive Ports - RX AFE -------------------------
1596  gt4_gtxrxp_in : in std_logic;
1597  ------------------------ Receive Ports - RX AFE Ports ----------------------
1598  gt4_gtxrxn_in : in std_logic;
1599  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1600  gt4_rxbufstatus_out : out std_logic_vector(2 downto 0);
1601  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1602  gt4_rxmcommaalignen_in : in std_logic;
1603  gt4_rxpcommaalignen_in : in std_logic;
1604  --------------------- Receive Ports - RX Equalizer Ports -------------------
1605  gt4_rxdfeagchold_in : in std_logic;
1606  gt4_rxdfelfhold_in : in std_logic;
1607  gt4_rxdfelpmreset_in : in std_logic;
1608  gt4_rxmonitorout_out : out std_logic_vector(6 downto 0);
1609  gt4_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1610  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1611  gt4_rxoutclk_out : out std_logic;
1612  gt4_rxoutclkfabric_out : out std_logic;
1613  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1614  gt4_gtrxreset_in : in std_logic;
1615  gt4_rxpmareset_in : in std_logic;
1616  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1617  gt4_rxchariscomma_out : out std_logic_vector(1 downto 0);
1618  gt4_rxcharisk_out : out std_logic_vector(1 downto 0);
1619  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1620  gt4_rxresetdone_out : out std_logic;
1621  --------------------- TX Initialization and Reset Ports --------------------
1622  gt4_gttxreset_in : in std_logic;
1623  gt4_txuserrdy_in : in std_logic;
1624  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1625  gt4_txusrclk_in : in std_logic;
1626  gt4_txusrclk2_in : in std_logic;
1627  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1628  gt4_txdiffctrl_in : in std_logic_vector(3 downto 0);
1629  ------------------ Transmit Ports - TX Data Path interface -----------------
1630  gt4_txdata_in : in std_logic_vector(15 downto 0);
1631  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1632  gt4_gtxtxn_out : out std_logic;
1633  gt4_gtxtxp_out : out std_logic;
1634  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1635  gt4_txoutclk_out : out std_logic;
1636  gt4_txoutclkfabric_out : out std_logic;
1637  gt4_txoutclkpcs_out : out std_logic;
1638  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1639  gt4_txcharisk_in : in std_logic_vector(1 downto 0);
1640  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1641  gt4_txresetdone_out : out std_logic;
1642  ------------------ Transmit Ports - pattern Generator Ports ----------------
1643  gt4_txprbssel_in : in std_logic_vector(2 downto 0);
1644 
1645  --_________________________________________________________________________
1646  --_________________________________________________________________________
1647  --GT5 (X1Y5)
1648  --____________________________CHANNEL PORTS________________________________
1649 
1650  ---------------------------- Channel - DRP Ports --------------------------
1651  gt5_drpaddr_in : in std_logic_vector(8 downto 0);
1652  gt5_drpclk_in : in std_logic;
1653  gt5_drpdi_in : in std_logic_vector(15 downto 0);
1654  gt5_drpdo_out : out std_logic_vector(15 downto 0);
1655  gt5_drpen_in : in std_logic;
1656  gt5_drprdy_out : out std_logic;
1657  gt5_drpwe_in : in std_logic;
1658  --------------------------- Digital Monitor Ports --------------------------
1659  gt5_dmonitorout_out : out std_logic_vector(7 downto 0);
1660  ------------------------------- Loopback Ports -----------------------------
1661  gt5_loopback_in : in std_logic_vector(2 downto 0);
1662  ------------------------------ Power-Down Ports ----------------------------
1663  gt5_rxpd_in : in std_logic_vector(1 downto 0);
1664  gt5_txpd_in : in std_logic_vector(1 downto 0);
1665  --------------------- RX Initialization and Reset Ports --------------------
1666  gt5_eyescanreset_in : in std_logic;
1667  gt5_rxuserrdy_in : in std_logic;
1668  -------------------------- RX Margin Analysis Ports ------------------------
1669  gt5_eyescandataerror_out : out std_logic;
1670  gt5_eyescantrigger_in : in std_logic;
1671  ------------------- Receive Ports - Clock Correction Ports -----------------
1672  gt5_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1673  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1674  gt5_rxusrclk_in : in std_logic;
1675  gt5_rxusrclk2_in : in std_logic;
1676  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1677  gt5_rxdata_out : out std_logic_vector(15 downto 0);
1678  ------------------- Receive Ports - Pattern Checker Ports ------------------
1679  gt5_rxprbserr_out : out std_logic;
1680  gt5_rxprbssel_in : in std_logic_vector(2 downto 0);
1681  ------------------- Receive Ports - Pattern Checker ports ------------------
1682  gt5_rxprbscntreset_in : in std_logic;
1683  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1684  gt5_rxdisperr_out : out std_logic_vector(1 downto 0);
1685  gt5_rxnotintable_out : out std_logic_vector(1 downto 0);
1686  --------------------------- Receive Ports - RX AFE -------------------------
1687  gt5_gtxrxp_in : in std_logic;
1688  ------------------------ Receive Ports - RX AFE Ports ----------------------
1689  gt5_gtxrxn_in : in std_logic;
1690  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1691  gt5_rxbufstatus_out : out std_logic_vector(2 downto 0);
1692  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1693  gt5_rxmcommaalignen_in : in std_logic;
1694  gt5_rxpcommaalignen_in : in std_logic;
1695  --------------------- Receive Ports - RX Equalizer Ports -------------------
1696  gt5_rxdfeagchold_in : in std_logic;
1697  gt5_rxdfelfhold_in : in std_logic;
1698  gt5_rxdfelpmreset_in : in std_logic;
1699  gt5_rxmonitorout_out : out std_logic_vector(6 downto 0);
1700  gt5_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1701  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1702  gt5_rxoutclk_out : out std_logic;
1703  gt5_rxoutclkfabric_out : out std_logic;
1704  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1705  gt5_gtrxreset_in : in std_logic;
1706  gt5_rxpmareset_in : in std_logic;
1707  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1708  gt5_rxchariscomma_out : out std_logic_vector(1 downto 0);
1709  gt5_rxcharisk_out : out std_logic_vector(1 downto 0);
1710  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1711  gt5_rxresetdone_out : out std_logic;
1712  --------------------- TX Initialization and Reset Ports --------------------
1713  gt5_gttxreset_in : in std_logic;
1714  gt5_txuserrdy_in : in std_logic;
1715  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1716  gt5_txusrclk_in : in std_logic;
1717  gt5_txusrclk2_in : in std_logic;
1718  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1719  gt5_txdiffctrl_in : in std_logic_vector(3 downto 0);
1720  ------------------ Transmit Ports - TX Data Path interface -----------------
1721  gt5_txdata_in : in std_logic_vector(15 downto 0);
1722  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1723  gt5_gtxtxn_out : out std_logic;
1724  gt5_gtxtxp_out : out std_logic;
1725  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1726  gt5_txoutclk_out : out std_logic;
1727  gt5_txoutclkfabric_out : out std_logic;
1728  gt5_txoutclkpcs_out : out std_logic;
1729  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1730  gt5_txcharisk_in : in std_logic_vector(1 downto 0);
1731  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1732  gt5_txresetdone_out : out std_logic;
1733  ------------------ Transmit Ports - pattern Generator Ports ----------------
1734  gt5_txprbssel_in : in std_logic_vector(2 downto 0);
1735 
1736  --_________________________________________________________________________
1737  --_________________________________________________________________________
1738  --GT6 (X1Y6)
1739  --____________________________CHANNEL PORTS________________________________
1740 
1741  ---------------------------- Channel - DRP Ports --------------------------
1742  gt6_drpaddr_in : in std_logic_vector(8 downto 0);
1743  gt6_drpclk_in : in std_logic;
1744  gt6_drpdi_in : in std_logic_vector(15 downto 0);
1745  gt6_drpdo_out : out std_logic_vector(15 downto 0);
1746  gt6_drpen_in : in std_logic;
1747  gt6_drprdy_out : out std_logic;
1748  gt6_drpwe_in : in std_logic;
1749  --------------------------- Digital Monitor Ports --------------------------
1750  gt6_dmonitorout_out : out std_logic_vector(7 downto 0);
1751  ------------------------------- Loopback Ports -----------------------------
1752  gt6_loopback_in : in std_logic_vector(2 downto 0);
1753  ------------------------------ Power-Down Ports ----------------------------
1754  gt6_rxpd_in : in std_logic_vector(1 downto 0);
1755  gt6_txpd_in : in std_logic_vector(1 downto 0);
1756  --------------------- RX Initialization and Reset Ports --------------------
1757  gt6_eyescanreset_in : in std_logic;
1758  gt6_rxuserrdy_in : in std_logic;
1759  -------------------------- RX Margin Analysis Ports ------------------------
1760  gt6_eyescandataerror_out : out std_logic;
1761  gt6_eyescantrigger_in : in std_logic;
1762  ------------------- Receive Ports - Clock Correction Ports -----------------
1763  gt6_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1764  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1765  gt6_rxusrclk_in : in std_logic;
1766  gt6_rxusrclk2_in : in std_logic;
1767  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1768  gt6_rxdata_out : out std_logic_vector(15 downto 0);
1769  ------------------- Receive Ports - Pattern Checker Ports ------------------
1770  gt6_rxprbserr_out : out std_logic;
1771  gt6_rxprbssel_in : in std_logic_vector(2 downto 0);
1772  ------------------- Receive Ports - Pattern Checker ports ------------------
1773  gt6_rxprbscntreset_in : in std_logic;
1774  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1775  gt6_rxdisperr_out : out std_logic_vector(1 downto 0);
1776  gt6_rxnotintable_out : out std_logic_vector(1 downto 0);
1777  --------------------------- Receive Ports - RX AFE -------------------------
1778  gt6_gtxrxp_in : in std_logic;
1779  ------------------------ Receive Ports - RX AFE Ports ----------------------
1780  gt6_gtxrxn_in : in std_logic;
1781  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1782  gt6_rxbufstatus_out : out std_logic_vector(2 downto 0);
1783  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1784  gt6_rxmcommaalignen_in : in std_logic;
1785  gt6_rxpcommaalignen_in : in std_logic;
1786  --------------------- Receive Ports - RX Equalizer Ports -------------------
1787  gt6_rxdfeagchold_in : in std_logic;
1788  gt6_rxdfelfhold_in : in std_logic;
1789  gt6_rxdfelpmreset_in : in std_logic;
1790  gt6_rxmonitorout_out : out std_logic_vector(6 downto 0);
1791  gt6_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1792  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1793  gt6_rxoutclk_out : out std_logic;
1794  gt6_rxoutclkfabric_out : out std_logic;
1795  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1796  gt6_gtrxreset_in : in std_logic;
1797  gt6_rxpmareset_in : in std_logic;
1798  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1799  gt6_rxchariscomma_out : out std_logic_vector(1 downto 0);
1800  gt6_rxcharisk_out : out std_logic_vector(1 downto 0);
1801  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1802  gt6_rxresetdone_out : out std_logic;
1803  --------------------- TX Initialization and Reset Ports --------------------
1804  gt6_gttxreset_in : in std_logic;
1805  gt6_txuserrdy_in : in std_logic;
1806  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1807  gt6_txusrclk_in : in std_logic;
1808  gt6_txusrclk2_in : in std_logic;
1809  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1810  gt6_txdiffctrl_in : in std_logic_vector(3 downto 0);
1811  ------------------ Transmit Ports - TX Data Path interface -----------------
1812  gt6_txdata_in : in std_logic_vector(15 downto 0);
1813  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1814  gt6_gtxtxn_out : out std_logic;
1815  gt6_gtxtxp_out : out std_logic;
1816  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1817  gt6_txoutclk_out : out std_logic;
1818  gt6_txoutclkfabric_out : out std_logic;
1819  gt6_txoutclkpcs_out : out std_logic;
1820  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1821  gt6_txcharisk_in : in std_logic_vector(1 downto 0);
1822  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1823  gt6_txresetdone_out : out std_logic;
1824  ------------------ Transmit Ports - pattern Generator Ports ----------------
1825  gt6_txprbssel_in : in std_logic_vector(2 downto 0);
1826 
1827  --_________________________________________________________________________
1828  --_________________________________________________________________________
1829  --GT7 (X1Y7)
1830  --____________________________CHANNEL PORTS________________________________
1831 
1832  ---------------------------- Channel - DRP Ports --------------------------
1833  gt7_drpaddr_in : in std_logic_vector(8 downto 0);
1834  gt7_drpclk_in : in std_logic;
1835  gt7_drpdi_in : in std_logic_vector(15 downto 0);
1836  gt7_drpdo_out : out std_logic_vector(15 downto 0);
1837  gt7_drpen_in : in std_logic;
1838  gt7_drprdy_out : out std_logic;
1839  gt7_drpwe_in : in std_logic;
1840  --------------------------- Digital Monitor Ports --------------------------
1841  gt7_dmonitorout_out : out std_logic_vector(7 downto 0);
1842  ------------------------------- Loopback Ports -----------------------------
1843  gt7_loopback_in : in std_logic_vector(2 downto 0);
1844  ------------------------------ Power-Down Ports ----------------------------
1845  gt7_rxpd_in : in std_logic_vector(1 downto 0);
1846  gt7_txpd_in : in std_logic_vector(1 downto 0);
1847  --------------------- RX Initialization and Reset Ports --------------------
1848  gt7_eyescanreset_in : in std_logic;
1849  gt7_rxuserrdy_in : in std_logic;
1850  -------------------------- RX Margin Analysis Ports ------------------------
1851  gt7_eyescandataerror_out : out std_logic;
1852  gt7_eyescantrigger_in : in std_logic;
1853  ------------------- Receive Ports - Clock Correction Ports -----------------
1854  gt7_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1855  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1856  gt7_rxusrclk_in : in std_logic;
1857  gt7_rxusrclk2_in : in std_logic;
1858  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1859  gt7_rxdata_out : out std_logic_vector(15 downto 0);
1860  ------------------- Receive Ports - Pattern Checker Ports ------------------
1861  gt7_rxprbserr_out : out std_logic;
1862  gt7_rxprbssel_in : in std_logic_vector(2 downto 0);
1863  ------------------- Receive Ports - Pattern Checker ports ------------------
1864  gt7_rxprbscntreset_in : in std_logic;
1865  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1866  gt7_rxdisperr_out : out std_logic_vector(1 downto 0);
1867  gt7_rxnotintable_out : out std_logic_vector(1 downto 0);
1868  --------------------------- Receive Ports - RX AFE -------------------------
1869  gt7_gtxrxp_in : in std_logic;
1870  ------------------------ Receive Ports - RX AFE Ports ----------------------
1871  gt7_gtxrxn_in : in std_logic;
1872  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1873  gt7_rxbufstatus_out : out std_logic_vector(2 downto 0);
1874  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1875  gt7_rxmcommaalignen_in : in std_logic;
1876  gt7_rxpcommaalignen_in : in std_logic;
1877  --------------------- Receive Ports - RX Equalizer Ports -------------------
1878  gt7_rxdfeagchold_in : in std_logic;
1879  gt7_rxdfelfhold_in : in std_logic;
1880  gt7_rxdfelpmreset_in : in std_logic;
1881  gt7_rxmonitorout_out : out std_logic_vector(6 downto 0);
1882  gt7_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1883  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1884  gt7_rxoutclk_out : out std_logic;
1885  gt7_rxoutclkfabric_out : out std_logic;
1886  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1887  gt7_gtrxreset_in : in std_logic;
1888  gt7_rxpmareset_in : in std_logic;
1889  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1890  gt7_rxchariscomma_out : out std_logic_vector(1 downto 0);
1891  gt7_rxcharisk_out : out std_logic_vector(1 downto 0);
1892  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1893  gt7_rxresetdone_out : out std_logic;
1894  --------------------- TX Initialization and Reset Ports --------------------
1895  gt7_gttxreset_in : in std_logic;
1896  gt7_txuserrdy_in : in std_logic;
1897  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1898  gt7_txusrclk_in : in std_logic;
1899  gt7_txusrclk2_in : in std_logic;
1900  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1901  gt7_txdiffctrl_in : in std_logic_vector(3 downto 0);
1902  ------------------ Transmit Ports - TX Data Path interface -----------------
1903  gt7_txdata_in : in std_logic_vector(15 downto 0);
1904  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1905  gt7_gtxtxn_out : out std_logic;
1906  gt7_gtxtxp_out : out std_logic;
1907  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1908  gt7_txoutclk_out : out std_logic;
1909  gt7_txoutclkfabric_out : out std_logic;
1910  gt7_txoutclkpcs_out : out std_logic;
1911  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1912  gt7_txcharisk_in : in std_logic_vector(1 downto 0);
1913  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1914  gt7_txresetdone_out : out std_logic;
1915  ------------------ Transmit Ports - pattern Generator Ports ----------------
1916  gt7_txprbssel_in : in std_logic_vector(2 downto 0);
1917 
1918  --_________________________________________________________________________
1919  --_________________________________________________________________________
1920  --GT8 (X1Y8)
1921  --____________________________CHANNEL PORTS________________________________
1922 
1923  ---------------------------- Channel - DRP Ports --------------------------
1924  gt8_drpaddr_in : in std_logic_vector(8 downto 0);
1925  gt8_drpclk_in : in std_logic;
1926  gt8_drpdi_in : in std_logic_vector(15 downto 0);
1927  gt8_drpdo_out : out std_logic_vector(15 downto 0);
1928  gt8_drpen_in : in std_logic;
1929  gt8_drprdy_out : out std_logic;
1930  gt8_drpwe_in : in std_logic;
1931  --------------------------- Digital Monitor Ports --------------------------
1932  gt8_dmonitorout_out : out std_logic_vector(7 downto 0);
1933  ------------------------------- Loopback Ports -----------------------------
1934  gt8_loopback_in : in std_logic_vector(2 downto 0);
1935  ------------------------------ Power-Down Ports ----------------------------
1936  gt8_rxpd_in : in std_logic_vector(1 downto 0);
1937  gt8_txpd_in : in std_logic_vector(1 downto 0);
1938  --------------------- RX Initialization and Reset Ports --------------------
1939  gt8_eyescanreset_in : in std_logic;
1940  gt8_rxuserrdy_in : in std_logic;
1941  -------------------------- RX Margin Analysis Ports ------------------------
1942  gt8_eyescandataerror_out : out std_logic;
1943  gt8_eyescantrigger_in : in std_logic;
1944  ------------------- Receive Ports - Clock Correction Ports -----------------
1945  gt8_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
1946  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1947  gt8_rxusrclk_in : in std_logic;
1948  gt8_rxusrclk2_in : in std_logic;
1949  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1950  gt8_rxdata_out : out std_logic_vector(15 downto 0);
1951  ------------------- Receive Ports - Pattern Checker Ports ------------------
1952  gt8_rxprbserr_out : out std_logic;
1953  gt8_rxprbssel_in : in std_logic_vector(2 downto 0);
1954  ------------------- Receive Ports - Pattern Checker ports ------------------
1955  gt8_rxprbscntreset_in : in std_logic;
1956  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1957  gt8_rxdisperr_out : out std_logic_vector(1 downto 0);
1958  gt8_rxnotintable_out : out std_logic_vector(1 downto 0);
1959  --------------------------- Receive Ports - RX AFE -------------------------
1960  gt8_gtxrxp_in : in std_logic;
1961  ------------------------ Receive Ports - RX AFE Ports ----------------------
1962  gt8_gtxrxn_in : in std_logic;
1963  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1964  gt8_rxbufstatus_out : out std_logic_vector(2 downto 0);
1965  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1966  gt8_rxmcommaalignen_in : in std_logic;
1967  gt8_rxpcommaalignen_in : in std_logic;
1968  --------------------- Receive Ports - RX Equalizer Ports -------------------
1969  gt8_rxdfeagchold_in : in std_logic;
1970  gt8_rxdfelfhold_in : in std_logic;
1971  gt8_rxdfelpmreset_in : in std_logic;
1972  gt8_rxmonitorout_out : out std_logic_vector(6 downto 0);
1973  gt8_rxmonitorsel_in : in std_logic_vector(1 downto 0);
1974  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1975  gt8_rxoutclk_out : out std_logic;
1976  gt8_rxoutclkfabric_out : out std_logic;
1977  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1978  gt8_gtrxreset_in : in std_logic;
1979  gt8_rxpmareset_in : in std_logic;
1980  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1981  gt8_rxchariscomma_out : out std_logic_vector(1 downto 0);
1982  gt8_rxcharisk_out : out std_logic_vector(1 downto 0);
1983  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1984  gt8_rxresetdone_out : out std_logic;
1985  --------------------- TX Initialization and Reset Ports --------------------
1986  gt8_gttxreset_in : in std_logic;
1987  gt8_txuserrdy_in : in std_logic;
1988  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1989  gt8_txusrclk_in : in std_logic;
1990  gt8_txusrclk2_in : in std_logic;
1991  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1992  gt8_txdiffctrl_in : in std_logic_vector(3 downto 0);
1993  ------------------ Transmit Ports - TX Data Path interface -----------------
1994  gt8_txdata_in : in std_logic_vector(15 downto 0);
1995  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1996  gt8_gtxtxn_out : out std_logic;
1997  gt8_gtxtxp_out : out std_logic;
1998  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1999  gt8_txoutclk_out : out std_logic;
2000  gt8_txoutclkfabric_out : out std_logic;
2001  gt8_txoutclkpcs_out : out std_logic;
2002  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2003  gt8_txcharisk_in : in std_logic_vector(1 downto 0);
2004  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2005  gt8_txresetdone_out : out std_logic;
2006  ------------------ Transmit Ports - pattern Generator Ports ----------------
2007  gt8_txprbssel_in : in std_logic_vector(2 downto 0);
2008 
2009  --_________________________________________________________________________
2010  --_________________________________________________________________________
2011  --GT9 (X1Y9)
2012  --____________________________CHANNEL PORTS________________________________
2013 
2014  ---------------------------- Channel - DRP Ports --------------------------
2015  gt9_drpaddr_in : in std_logic_vector(8 downto 0);
2016  gt9_drpclk_in : in std_logic;
2017  gt9_drpdi_in : in std_logic_vector(15 downto 0);
2018  gt9_drpdo_out : out std_logic_vector(15 downto 0);
2019  gt9_drpen_in : in std_logic;
2020  gt9_drprdy_out : out std_logic;
2021  gt9_drpwe_in : in std_logic;
2022  --------------------------- Digital Monitor Ports --------------------------
2023  gt9_dmonitorout_out : out std_logic_vector(7 downto 0);
2024  ------------------------------- Loopback Ports -----------------------------
2025  gt9_loopback_in : in std_logic_vector(2 downto 0);
2026  ------------------------------ Power-Down Ports ----------------------------
2027  gt9_rxpd_in : in std_logic_vector(1 downto 0);
2028  gt9_txpd_in : in std_logic_vector(1 downto 0);
2029  --------------------- RX Initialization and Reset Ports --------------------
2030  gt9_eyescanreset_in : in std_logic;
2031  gt9_rxuserrdy_in : in std_logic;
2032  -------------------------- RX Margin Analysis Ports ------------------------
2033  gt9_eyescandataerror_out : out std_logic;
2034  gt9_eyescantrigger_in : in std_logic;
2035  ------------------- Receive Ports - Clock Correction Ports -----------------
2036  gt9_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
2037  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2038  gt9_rxusrclk_in : in std_logic;
2039  gt9_rxusrclk2_in : in std_logic;
2040  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2041  gt9_rxdata_out : out std_logic_vector(15 downto 0);
2042  ------------------- Receive Ports - Pattern Checker Ports ------------------
2043  gt9_rxprbserr_out : out std_logic;
2044  gt9_rxprbssel_in : in std_logic_vector(2 downto 0);
2045  ------------------- Receive Ports - Pattern Checker ports ------------------
2046  gt9_rxprbscntreset_in : in std_logic;
2047  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2048  gt9_rxdisperr_out : out std_logic_vector(1 downto 0);
2049  gt9_rxnotintable_out : out std_logic_vector(1 downto 0);
2050  --------------------------- Receive Ports - RX AFE -------------------------
2051  gt9_gtxrxp_in : in std_logic;
2052  ------------------------ Receive Ports - RX AFE Ports ----------------------
2053  gt9_gtxrxn_in : in std_logic;
2054  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2055  gt9_rxbufstatus_out : out std_logic_vector(2 downto 0);
2056  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2057  gt9_rxmcommaalignen_in : in std_logic;
2058  gt9_rxpcommaalignen_in : in std_logic;
2059  --------------------- Receive Ports - RX Equalizer Ports -------------------
2060  gt9_rxdfeagchold_in : in std_logic;
2061  gt9_rxdfelfhold_in : in std_logic;
2062  gt9_rxdfelpmreset_in : in std_logic;
2063  gt9_rxmonitorout_out : out std_logic_vector(6 downto 0);
2064  gt9_rxmonitorsel_in : in std_logic_vector(1 downto 0);
2065  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2066  gt9_rxoutclk_out : out std_logic;
2067  gt9_rxoutclkfabric_out : out std_logic;
2068  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2069  gt9_gtrxreset_in : in std_logic;
2070  gt9_rxpmareset_in : in std_logic;
2071  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2072  gt9_rxchariscomma_out : out std_logic_vector(1 downto 0);
2073  gt9_rxcharisk_out : out std_logic_vector(1 downto 0);
2074  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2075  gt9_rxresetdone_out : out std_logic;
2076  --------------------- TX Initialization and Reset Ports --------------------
2077  gt9_gttxreset_in : in std_logic;
2078  gt9_txuserrdy_in : in std_logic;
2079  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2080  gt9_txusrclk_in : in std_logic;
2081  gt9_txusrclk2_in : in std_logic;
2082  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2083  gt9_txdiffctrl_in : in std_logic_vector(3 downto 0);
2084  ------------------ Transmit Ports - TX Data Path interface -----------------
2085  gt9_txdata_in : in std_logic_vector(15 downto 0);
2086  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2087  gt9_gtxtxn_out : out std_logic;
2088  gt9_gtxtxp_out : out std_logic;
2089  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2090  gt9_txoutclk_out : out std_logic;
2091  gt9_txoutclkfabric_out : out std_logic;
2092  gt9_txoutclkpcs_out : out std_logic;
2093  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2094  gt9_txcharisk_in : in std_logic_vector(1 downto 0);
2095  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2096  gt9_txresetdone_out : out std_logic;
2097  ------------------ Transmit Ports - pattern Generator Ports ----------------
2098  gt9_txprbssel_in : in std_logic_vector(2 downto 0);
2099 
2100  --_________________________________________________________________________
2101  --_________________________________________________________________________
2102  --GT10 (X1Y10)
2103  --____________________________CHANNEL PORTS________________________________
2104 
2105  ---------------------------- Channel - DRP Ports --------------------------
2106  gt10_drpaddr_in : in std_logic_vector(8 downto 0);
2107  gt10_drpclk_in : in std_logic;
2108  gt10_drpdi_in : in std_logic_vector(15 downto 0);
2109  gt10_drpdo_out : out std_logic_vector(15 downto 0);
2110  gt10_drpen_in : in std_logic;
2111  gt10_drprdy_out : out std_logic;
2112  gt10_drpwe_in : in std_logic;
2113  --------------------------- Digital Monitor Ports --------------------------
2114  gt10_dmonitorout_out : out std_logic_vector(7 downto 0);
2115  ------------------------------- Loopback Ports -----------------------------
2116  gt10_loopback_in : in std_logic_vector(2 downto 0);
2117  ------------------------------ Power-Down Ports ----------------------------
2118  gt10_rxpd_in : in std_logic_vector(1 downto 0);
2119  gt10_txpd_in : in std_logic_vector(1 downto 0);
2120  --------------------- RX Initialization and Reset Ports --------------------
2121  gt10_eyescanreset_in : in std_logic;
2122  gt10_rxuserrdy_in : in std_logic;
2123  -------------------------- RX Margin Analysis Ports ------------------------
2124  gt10_eyescandataerror_out : out std_logic;
2125  gt10_eyescantrigger_in : in std_logic;
2126  ------------------- Receive Ports - Clock Correction Ports -----------------
2127  gt10_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
2128  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2129  gt10_rxusrclk_in : in std_logic;
2130  gt10_rxusrclk2_in : in std_logic;
2131  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2132  gt10_rxdata_out : out std_logic_vector(15 downto 0);
2133  ------------------- Receive Ports - Pattern Checker Ports ------------------
2134  gt10_rxprbserr_out : out std_logic;
2135  gt10_rxprbssel_in : in std_logic_vector(2 downto 0);
2136  ------------------- Receive Ports - Pattern Checker ports ------------------
2137  gt10_rxprbscntreset_in : in std_logic;
2138  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2139  gt10_rxdisperr_out : out std_logic_vector(1 downto 0);
2140  gt10_rxnotintable_out : out std_logic_vector(1 downto 0);
2141  --------------------------- Receive Ports - RX AFE -------------------------
2142  gt10_gtxrxp_in : in std_logic;
2143  ------------------------ Receive Ports - RX AFE Ports ----------------------
2144  gt10_gtxrxn_in : in std_logic;
2145  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2146  gt10_rxbufstatus_out : out std_logic_vector(2 downto 0);
2147  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2148  gt10_rxmcommaalignen_in : in std_logic;
2149  gt10_rxpcommaalignen_in : in std_logic;
2150  --------------------- Receive Ports - RX Equalizer Ports -------------------
2151  gt10_rxdfeagchold_in : in std_logic;
2152  gt10_rxdfelfhold_in : in std_logic;
2153  gt10_rxdfelpmreset_in : in std_logic;
2154  gt10_rxmonitorout_out : out std_logic_vector(6 downto 0);
2155  gt10_rxmonitorsel_in : in std_logic_vector(1 downto 0);
2156  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2157  gt10_rxoutclk_out : out std_logic;
2158  gt10_rxoutclkfabric_out : out std_logic;
2159  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2160  gt10_gtrxreset_in : in std_logic;
2161  gt10_rxpmareset_in : in std_logic;
2162  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2163  gt10_rxchariscomma_out : out std_logic_vector(1 downto 0);
2164  gt10_rxcharisk_out : out std_logic_vector(1 downto 0);
2165  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2166  gt10_rxresetdone_out : out std_logic;
2167  --------------------- TX Initialization and Reset Ports --------------------
2168  gt10_gttxreset_in : in std_logic;
2169  gt10_txuserrdy_in : in std_logic;
2170  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2171  gt10_txusrclk_in : in std_logic;
2172  gt10_txusrclk2_in : in std_logic;
2173  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2174  gt10_txdiffctrl_in : in std_logic_vector(3 downto 0);
2175  ------------------ Transmit Ports - TX Data Path interface -----------------
2176  gt10_txdata_in : in std_logic_vector(15 downto 0);
2177  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2178  gt10_gtxtxn_out : out std_logic;
2179  gt10_gtxtxp_out : out std_logic;
2180  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2181  gt10_txoutclk_out : out std_logic;
2182  gt10_txoutclkfabric_out : out std_logic;
2183  gt10_txoutclkpcs_out : out std_logic;
2184  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2185  gt10_txcharisk_in : in std_logic_vector(1 downto 0);
2186  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2187  gt10_txresetdone_out : out std_logic;
2188  ------------------ Transmit Ports - pattern Generator Ports ----------------
2189  gt10_txprbssel_in : in std_logic_vector(2 downto 0);
2190 
2191  --_________________________________________________________________________
2192  --_________________________________________________________________________
2193  --GT11 (X1Y11)
2194  --____________________________CHANNEL PORTS________________________________
2195 
2196  ---------------------------- Channel - DRP Ports --------------------------
2197  gt11_drpaddr_in : in std_logic_vector(8 downto 0);
2198  gt11_drpclk_in : in std_logic;
2199  gt11_drpdi_in : in std_logic_vector(15 downto 0);
2200  gt11_drpdo_out : out std_logic_vector(15 downto 0);
2201  gt11_drpen_in : in std_logic;
2202  gt11_drprdy_out : out std_logic;
2203  gt11_drpwe_in : in std_logic;
2204  --------------------------- Digital Monitor Ports --------------------------
2205  gt11_dmonitorout_out : out std_logic_vector(7 downto 0);
2206  ------------------------------- Loopback Ports -----------------------------
2207  gt11_loopback_in : in std_logic_vector(2 downto 0);
2208  ------------------------------ Power-Down Ports ----------------------------
2209  gt11_rxpd_in : in std_logic_vector(1 downto 0);
2210  gt11_txpd_in : in std_logic_vector(1 downto 0);
2211  --------------------- RX Initialization and Reset Ports --------------------
2212  gt11_eyescanreset_in : in std_logic;
2213  gt11_rxuserrdy_in : in std_logic;
2214  -------------------------- RX Margin Analysis Ports ------------------------
2215  gt11_eyescandataerror_out : out std_logic;
2216  gt11_eyescantrigger_in : in std_logic;
2217  ------------------- Receive Ports - Clock Correction Ports -----------------
2218  gt11_rxclkcorcnt_out : out std_logic_vector(1 downto 0);
2219  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2220  gt11_rxusrclk_in : in std_logic;
2221  gt11_rxusrclk2_in : in std_logic;
2222  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2223  gt11_rxdata_out : out std_logic_vector(15 downto 0);
2224  ------------------- Receive Ports - Pattern Checker Ports ------------------
2225  gt11_rxprbserr_out : out std_logic;
2226  gt11_rxprbssel_in : in std_logic_vector(2 downto 0);
2227  ------------------- Receive Ports - Pattern Checker ports ------------------
2228  gt11_rxprbscntreset_in : in std_logic;
2229  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2230  gt11_rxdisperr_out : out std_logic_vector(1 downto 0);
2231  gt11_rxnotintable_out : out std_logic_vector(1 downto 0);
2232  --------------------------- Receive Ports - RX AFE -------------------------
2233  gt11_gtxrxp_in : in std_logic;
2234  ------------------------ Receive Ports - RX AFE Ports ----------------------
2235  gt11_gtxrxn_in : in std_logic;
2236  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2237  gt11_rxbufstatus_out : out std_logic_vector(2 downto 0);
2238  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2239  gt11_rxmcommaalignen_in : in std_logic;
2240  gt11_rxpcommaalignen_in : in std_logic;
2241  --------------------- Receive Ports - RX Equalizer Ports -------------------
2242  gt11_rxdfeagchold_in : in std_logic;
2243  gt11_rxdfelfhold_in : in std_logic;
2244  gt11_rxdfelpmreset_in : in std_logic;
2245  gt11_rxmonitorout_out : out std_logic_vector(6 downto 0);
2246  gt11_rxmonitorsel_in : in std_logic_vector(1 downto 0);
2247  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2248  gt11_rxoutclk_out : out std_logic;
2249  gt11_rxoutclkfabric_out : out std_logic;
2250  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2251  gt11_gtrxreset_in : in std_logic;
2252  gt11_rxpmareset_in : in std_logic;
2253  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2254  gt11_rxchariscomma_out : out std_logic_vector(1 downto 0);
2255  gt11_rxcharisk_out : out std_logic_vector(1 downto 0);
2256  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2257  gt11_rxresetdone_out : out std_logic;
2258  --------------------- TX Initialization and Reset Ports --------------------
2259  gt11_gttxreset_in : in std_logic;
2260  gt11_txuserrdy_in : in std_logic;
2261  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2262  gt11_txusrclk_in : in std_logic;
2263  gt11_txusrclk2_in : in std_logic;
2264  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2265  gt11_txdiffctrl_in : in std_logic_vector(3 downto 0);
2266  ------------------ Transmit Ports - TX Data Path interface -----------------
2267  gt11_txdata_in : in std_logic_vector(15 downto 0);
2268  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2269  gt11_gtxtxn_out : out std_logic;
2270  gt11_gtxtxp_out : out std_logic;
2271  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2272  gt11_txoutclk_out : out std_logic;
2273  gt11_txoutclkfabric_out : out std_logic;
2274  gt11_txoutclkpcs_out : out std_logic;
2275  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2276  gt11_txcharisk_in : in std_logic_vector(1 downto 0);
2277  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2278  gt11_txresetdone_out : out std_logic;
2279  ------------------ Transmit Ports - pattern Generator Ports ----------------
2280  gt11_txprbssel_in : in std_logic_vector(2 downto 0);
2281 
2282 
2283  --____________________________COMMON PORTS________________________________
2284  GT0_QPLLOUTCLK_IN : in std_logic;
2285  GT0_QPLLOUTREFCLK_IN : in std_logic ;
2286  --____________________________COMMON PORTS________________________________
2287  GT1_QPLLOUTCLK_IN : in std_logic;
2288  GT1_QPLLOUTREFCLK_IN : in std_logic ;
2289  --____________________________COMMON PORTS________________________________
2290  GT2_QPLLOUTCLK_IN : in std_logic;
2291  GT2_QPLLOUTREFCLK_IN : in std_logic
2292 
2293 );
2294 end component;
2295 
2296 component amc_gtx5Gpd_TX_STARTUP_FSM
2297  Generic(
2298  EXAMPLE_SIMULATION : integer := 0;
2299  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
2300  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
2301  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
2302  RX_QPLL_USED : boolean := False; -- share these two generic values
2303  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
2304  -- is enough. For single-lane applications the automatic alignment is
2305  -- sufficient
2306  );
2307  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
2308  --or reference-clock present at startup.
2309  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
2310  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
2311  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
2312  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
2313  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
2314  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
2315  TXRESETDONE : in STD_LOGIC;
2316  MMCM_LOCK : in STD_LOGIC;
2317  GTTXRESET : out STD_LOGIC:='0';
2318  MMCM_RESET : out STD_LOGIC:='0';
2319  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
2320  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
2321  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
2322  TXUSERRDY : out STD_LOGIC:='0';
2323  RUN_PHALIGNMENT : out STD_LOGIC:='0';
2324  RESET_PHALIGNMENT : out STD_LOGIC:='0';
2325  PHALIGNMENT_DONE : in STD_LOGIC;
2326 
2327  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
2328  -- Retries it took to get the transceiver up and running
2329  );
2330 end component;
2331 
2332 component amc_gtx5Gpd_RX_STARTUP_FSM
2333  Generic(
2334  EXAMPLE_SIMULATION : integer := 0;
2335  EQ_MODE : string := "DFE";
2336  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
2337  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
2338  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
2339  RX_QPLL_USED : boolean := False; -- share these two generic values
2340  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
2341  -- is enough. For single-lane applications the automatic alignment is
2342  -- sufficient
2343  );
2344  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
2345  --or reference-clock present at startup.
2346  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
2347  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
2348  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
2349  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
2350  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
2351  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
2352  RXRESETDONE : in STD_LOGIC;
2353  MMCM_LOCK : in STD_LOGIC;
2354  RECCLK_STABLE : in STD_LOGIC;
2355  RECCLK_MONITOR_RESTART : in STD_LOGIC;
2356  DATA_VALID : in STD_LOGIC;
2357  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
2358  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
2359  GTRXRESET : out STD_LOGIC:='0';
2360  MMCM_RESET : out STD_LOGIC:='0';
2361  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
2362  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
2363  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
2364  RXUSERRDY : out STD_LOGIC:='0';
2365  RUN_PHALIGNMENT : out STD_LOGIC;
2366  PHALIGNMENT_DONE : in STD_LOGIC;
2367  RESET_PHALIGNMENT : out STD_LOGIC:='0';
2368  RXDFEAGCHOLD : out STD_LOGIC;
2369  RXDFELFHOLD : out STD_LOGIC;
2370  RXLPMLFHOLD : out STD_LOGIC;
2371  RXLPMHFHOLD : out STD_LOGIC;
2372  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
2373  -- Retries it took to get the transceiver up and running
2374  );
2375 end component;
2376 
2377 
2378 
2379 
2380 
2381 
2382  function get_cdrlock_time(is_sim : in integer) return integer is
2383  variable lock_time: integer;
2384  begin
2385  if (is_sim = 1) then
2386  lock_time := 1000;
2387  else
2388  lock_time := 100000 / integer(5.0); --Typical CDR lock time is 50,000UI as per DS183
2389  end if;
2390  return lock_time;
2391  end function;
2392 
2393 
2394 --***********************************Parameter Declarations********************
2395 
2396  constant DLY : time := 1 ns;
2397  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
2398  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
2399 
2400 
2401 
2402  -------------------------- GT Wrapper Wires ------------------------------
2403  signal gt0_txpmaresetdone_i : std_logic;
2404  signal gt0_rxpmaresetdone_i : std_logic;
2405  signal gt0_txresetdone_i : std_logic;
2406  signal gt0_rxresetdone_i : std_logic;
2407  signal gt0_gttxreset_i : std_logic;
2408  signal gt0_gttxreset_t : std_logic;
2409  signal gt0_gtrxreset_i : std_logic;
2410  signal gt0_gtrxreset_t : std_logic;
2411  signal gt0_rxdfelpmreset_i : std_logic;
2412  signal gt0_txuserrdy_i : std_logic;
2413  signal gt0_txuserrdy_t : std_logic;
2414  signal gt0_rxuserrdy_i : std_logic;
2415  signal gt0_rxuserrdy_t : std_logic;
2416 
2417  signal gt0_rxdfeagchold_i : std_logic;
2418  signal gt0_rxdfelfhold_i : std_logic;
2419  signal gt0_rxlpmlfhold_i : std_logic;
2420  signal gt0_rxlpmhfhold_i : std_logic;
2421 
2422 
2423  signal gt1_txpmaresetdone_i : std_logic;
2424  signal gt1_rxpmaresetdone_i : std_logic;
2425  signal gt1_txresetdone_i : std_logic;
2426  signal gt1_rxresetdone_i : std_logic;
2427  signal gt1_gttxreset_i : std_logic;
2428  signal gt1_gttxreset_t : std_logic;
2429  signal gt1_gtrxreset_i : std_logic;
2430  signal gt1_gtrxreset_t : std_logic;
2431  signal gt1_rxdfelpmreset_i : std_logic;
2432  signal gt1_txuserrdy_i : std_logic;
2433  signal gt1_txuserrdy_t : std_logic;
2434  signal gt1_rxuserrdy_i : std_logic;
2435  signal gt1_rxuserrdy_t : std_logic;
2436 
2437  signal gt1_rxdfeagchold_i : std_logic;
2438  signal gt1_rxdfelfhold_i : std_logic;
2439  signal gt1_rxlpmlfhold_i : std_logic;
2440  signal gt1_rxlpmhfhold_i : std_logic;
2441 
2442 
2443  signal gt2_txpmaresetdone_i : std_logic;
2444  signal gt2_rxpmaresetdone_i : std_logic;
2445  signal gt2_txresetdone_i : std_logic;
2446  signal gt2_rxresetdone_i : std_logic;
2447  signal gt2_gttxreset_i : std_logic;
2448  signal gt2_gttxreset_t : std_logic;
2449  signal gt2_gtrxreset_i : std_logic;
2450  signal gt2_gtrxreset_t : std_logic;
2451  signal gt2_rxdfelpmreset_i : std_logic;
2452  signal gt2_txuserrdy_i : std_logic;
2453  signal gt2_txuserrdy_t : std_logic;
2454  signal gt2_rxuserrdy_i : std_logic;
2455  signal gt2_rxuserrdy_t : std_logic;
2456 
2457  signal gt2_rxdfeagchold_i : std_logic;
2458  signal gt2_rxdfelfhold_i : std_logic;
2459  signal gt2_rxlpmlfhold_i : std_logic;
2460  signal gt2_rxlpmhfhold_i : std_logic;
2461 
2462 
2463  signal gt3_txpmaresetdone_i : std_logic;
2464  signal gt3_rxpmaresetdone_i : std_logic;
2465  signal gt3_txresetdone_i : std_logic;
2466  signal gt3_rxresetdone_i : std_logic;
2467  signal gt3_gttxreset_i : std_logic;
2468  signal gt3_gttxreset_t : std_logic;
2469  signal gt3_gtrxreset_i : std_logic;
2470  signal gt3_gtrxreset_t : std_logic;
2471  signal gt3_rxdfelpmreset_i : std_logic;
2472  signal gt3_txuserrdy_i : std_logic;
2473  signal gt3_txuserrdy_t : std_logic;
2474  signal gt3_rxuserrdy_i : std_logic;
2475  signal gt3_rxuserrdy_t : std_logic;
2476 
2477  signal gt3_rxdfeagchold_i : std_logic;
2478  signal gt3_rxdfelfhold_i : std_logic;
2479  signal gt3_rxlpmlfhold_i : std_logic;
2480  signal gt3_rxlpmhfhold_i : std_logic;
2481 
2482 
2483  signal gt4_txpmaresetdone_i : std_logic;
2484  signal gt4_rxpmaresetdone_i : std_logic;
2485  signal gt4_txresetdone_i : std_logic;
2486  signal gt4_rxresetdone_i : std_logic;
2487  signal gt4_gttxreset_i : std_logic;
2488  signal gt4_gttxreset_t : std_logic;
2489  signal gt4_gtrxreset_i : std_logic;
2490  signal gt4_gtrxreset_t : std_logic;
2491  signal gt4_rxdfelpmreset_i : std_logic;
2492  signal gt4_txuserrdy_i : std_logic;
2493  signal gt4_txuserrdy_t : std_logic;
2494  signal gt4_rxuserrdy_i : std_logic;
2495  signal gt4_rxuserrdy_t : std_logic;
2496 
2497  signal gt4_rxdfeagchold_i : std_logic;
2498  signal gt4_rxdfelfhold_i : std_logic;
2499  signal gt4_rxlpmlfhold_i : std_logic;
2500  signal gt4_rxlpmhfhold_i : std_logic;
2501 
2502 
2503  signal gt5_txpmaresetdone_i : std_logic;
2504  signal gt5_rxpmaresetdone_i : std_logic;
2505  signal gt5_txresetdone_i : std_logic;
2506  signal gt5_rxresetdone_i : std_logic;
2507  signal gt5_gttxreset_i : std_logic;
2508  signal gt5_gttxreset_t : std_logic;
2509  signal gt5_gtrxreset_i : std_logic;
2510  signal gt5_gtrxreset_t : std_logic;
2511  signal gt5_rxdfelpmreset_i : std_logic;
2512  signal gt5_txuserrdy_i : std_logic;
2513  signal gt5_txuserrdy_t : std_logic;
2514  signal gt5_rxuserrdy_i : std_logic;
2515  signal gt5_rxuserrdy_t : std_logic;
2516 
2517  signal gt5_rxdfeagchold_i : std_logic;
2518  signal gt5_rxdfelfhold_i : std_logic;
2519  signal gt5_rxlpmlfhold_i : std_logic;
2520  signal gt5_rxlpmhfhold_i : std_logic;
2521 
2522 
2523  signal gt6_txpmaresetdone_i : std_logic;
2524  signal gt6_rxpmaresetdone_i : std_logic;
2525  signal gt6_txresetdone_i : std_logic;
2526  signal gt6_rxresetdone_i : std_logic;
2527  signal gt6_gttxreset_i : std_logic;
2528  signal gt6_gttxreset_t : std_logic;
2529  signal gt6_gtrxreset_i : std_logic;
2530  signal gt6_gtrxreset_t : std_logic;
2531  signal gt6_rxdfelpmreset_i : std_logic;
2532  signal gt6_txuserrdy_i : std_logic;
2533  signal gt6_txuserrdy_t : std_logic;
2534  signal gt6_rxuserrdy_i : std_logic;
2535  signal gt6_rxuserrdy_t : std_logic;
2536 
2537  signal gt6_rxdfeagchold_i : std_logic;
2538  signal gt6_rxdfelfhold_i : std_logic;
2539  signal gt6_rxlpmlfhold_i : std_logic;
2540  signal gt6_rxlpmhfhold_i : std_logic;
2541 
2542 
2543  signal gt7_txpmaresetdone_i : std_logic;
2544  signal gt7_rxpmaresetdone_i : std_logic;
2545  signal gt7_txresetdone_i : std_logic;
2546  signal gt7_rxresetdone_i : std_logic;
2547  signal gt7_gttxreset_i : std_logic;
2548  signal gt7_gttxreset_t : std_logic;
2549  signal gt7_gtrxreset_i : std_logic;
2550  signal gt7_gtrxreset_t : std_logic;
2551  signal gt7_rxdfelpmreset_i : std_logic;
2552  signal gt7_txuserrdy_i : std_logic;
2553  signal gt7_txuserrdy_t : std_logic;
2554  signal gt7_rxuserrdy_i : std_logic;
2555  signal gt7_rxuserrdy_t : std_logic;
2556 
2557  signal gt7_rxdfeagchold_i : std_logic;
2558  signal gt7_rxdfelfhold_i : std_logic;
2559  signal gt7_rxlpmlfhold_i : std_logic;
2560  signal gt7_rxlpmhfhold_i : std_logic;
2561 
2562 
2563  signal gt8_txpmaresetdone_i : std_logic;
2564  signal gt8_rxpmaresetdone_i : std_logic;
2565  signal gt8_txresetdone_i : std_logic;
2566  signal gt8_rxresetdone_i : std_logic;
2567  signal gt8_gttxreset_i : std_logic;
2568  signal gt8_gttxreset_t : std_logic;
2569  signal gt8_gtrxreset_i : std_logic;
2570  signal gt8_gtrxreset_t : std_logic;
2571  signal gt8_rxdfelpmreset_i : std_logic;
2572  signal gt8_txuserrdy_i : std_logic;
2573  signal gt8_txuserrdy_t : std_logic;
2574  signal gt8_rxuserrdy_i : std_logic;
2575  signal gt8_rxuserrdy_t : std_logic;
2576 
2577  signal gt8_rxdfeagchold_i : std_logic;
2578  signal gt8_rxdfelfhold_i : std_logic;
2579  signal gt8_rxlpmlfhold_i : std_logic;
2580  signal gt8_rxlpmhfhold_i : std_logic;
2581 
2582 
2583  signal gt9_txpmaresetdone_i : std_logic;
2584  signal gt9_rxpmaresetdone_i : std_logic;
2585  signal gt9_txresetdone_i : std_logic;
2586  signal gt9_rxresetdone_i : std_logic;
2587  signal gt9_gttxreset_i : std_logic;
2588  signal gt9_gttxreset_t : std_logic;
2589  signal gt9_gtrxreset_i : std_logic;
2590  signal gt9_gtrxreset_t : std_logic;
2591  signal gt9_rxdfelpmreset_i : std_logic;
2592  signal gt9_txuserrdy_i : std_logic;
2593  signal gt9_txuserrdy_t : std_logic;
2594  signal gt9_rxuserrdy_i : std_logic;
2595  signal gt9_rxuserrdy_t : std_logic;
2596 
2597  signal gt9_rxdfeagchold_i : std_logic;
2598  signal gt9_rxdfelfhold_i : std_logic;
2599  signal gt9_rxlpmlfhold_i : std_logic;
2600  signal gt9_rxlpmhfhold_i : std_logic;
2601 
2602 
2603  signal gt10_txpmaresetdone_i : std_logic;
2604  signal gt10_rxpmaresetdone_i : std_logic;
2605  signal gt10_txresetdone_i : std_logic;
2606  signal gt10_rxresetdone_i : std_logic;
2607  signal gt10_gttxreset_i : std_logic;
2608  signal gt10_gttxreset_t : std_logic;
2609  signal gt10_gtrxreset_i : std_logic;
2610  signal gt10_gtrxreset_t : std_logic;
2611  signal gt10_rxdfelpmreset_i : std_logic;
2612  signal gt10_txuserrdy_i : std_logic;
2613  signal gt10_txuserrdy_t : std_logic;
2614  signal gt10_rxuserrdy_i : std_logic;
2615  signal gt10_rxuserrdy_t : std_logic;
2616 
2617  signal gt10_rxdfeagchold_i : std_logic;
2618  signal gt10_rxdfelfhold_i : std_logic;
2619  signal gt10_rxlpmlfhold_i : std_logic;
2620  signal gt10_rxlpmhfhold_i : std_logic;
2621 
2622 
2623  signal gt11_txpmaresetdone_i : std_logic;
2624  signal gt11_rxpmaresetdone_i : std_logic;
2625  signal gt11_txresetdone_i : std_logic;
2626  signal gt11_rxresetdone_i : std_logic;
2627  signal gt11_gttxreset_i : std_logic;
2628  signal gt11_gttxreset_t : std_logic;
2629  signal gt11_gtrxreset_i : std_logic;
2630  signal gt11_gtrxreset_t : std_logic;
2631  signal gt11_rxdfelpmreset_i : std_logic;
2632  signal gt11_txuserrdy_i : std_logic;
2633  signal gt11_txuserrdy_t : std_logic;
2634  signal gt11_rxuserrdy_i : std_logic;
2635  signal gt11_rxuserrdy_t : std_logic;
2636 
2637  signal gt11_rxdfeagchold_i : std_logic;
2638  signal gt11_rxdfelfhold_i : std_logic;
2639  signal gt11_rxlpmlfhold_i : std_logic;
2640  signal gt11_rxlpmhfhold_i : std_logic;
2641 
2642 
2643 
2644  signal gt0_qpllreset_i : std_logic;
2645  signal gt0_qpllreset_t : std_logic;
2646  signal gt0_qpllrefclklost_i : std_logic;
2647  signal gt0_qplllock_i : std_logic;
2648  signal gt1_qpllreset_i : std_logic;
2649  signal gt1_qpllreset_t : std_logic;
2650  signal gt1_qpllrefclklost_i : std_logic;
2651  signal gt1_qplllock_i : std_logic;
2652  signal gt2_qpllreset_i : std_logic;
2653  signal gt2_qpllreset_t : std_logic;
2654  signal gt2_qpllrefclklost_i : std_logic;
2655  signal gt2_qplllock_i : std_logic;
2656 
2657 
2658  ------------------------------- Global Signals -----------------------------
2659  signal tied_to_ground_i : std_logic;
2660  signal tied_to_vcc_i : std_logic;
2661 
2662  signal gt0_txoutclk_i : std_logic;
2663  signal gt0_rxoutclk_i : std_logic;
2664  signal gt0_rxoutclkfabric_out : std_logic;
2665  signal gt0_txoutclk_i2 : std_logic;
2666  signal gt0_recclk_stable_i : std_logic;
2667  signal gt0_rx_cdrlocked : std_logic;
2668  signal gt0_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2669 
2670  signal gt1_txoutclk_i : std_logic;
2671  signal gt1_rxoutclk_i : std_logic;
2672  signal gt1_rxoutclkfabric_out : std_logic;
2673  signal gt1_txoutclk_i2 : std_logic;
2674  signal gt1_recclk_stable_i : std_logic;
2675  signal gt1_rx_cdrlocked : std_logic;
2676  signal gt1_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2677 
2678  signal gt2_txoutclk_i : std_logic;
2679  signal gt2_rxoutclk_i : std_logic;
2680  signal gt2_rxoutclkfabric_out : std_logic;
2681  signal gt2_txoutclk_i2 : std_logic;
2682  signal gt2_recclk_stable_i : std_logic;
2683  signal gt2_rx_cdrlocked : std_logic;
2684  signal gt2_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2685 
2686  signal gt3_txoutclk_i : std_logic;
2687  signal gt3_rxoutclk_i : std_logic;
2688  signal gt3_rxoutclkfabric_out : std_logic;
2689  signal gt3_txoutclk_i2 : std_logic;
2690  signal gt3_recclk_stable_i : std_logic;
2691  signal gt3_rx_cdrlocked : std_logic;
2692  signal gt3_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2693 
2694  signal gt4_txoutclk_i : std_logic;
2695  signal gt4_rxoutclk_i : std_logic;
2696  signal gt4_rxoutclkfabric_out : std_logic;
2697  signal gt4_txoutclk_i2 : std_logic;
2698  signal gt4_recclk_stable_i : std_logic;
2699  signal gt4_rx_cdrlocked : std_logic;
2700  signal gt4_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2701 
2702  signal gt5_txoutclk_i : std_logic;
2703  signal gt5_rxoutclk_i : std_logic;
2704  signal gt5_rxoutclkfabric_out : std_logic;
2705  signal gt5_txoutclk_i2 : std_logic;
2706  signal gt5_recclk_stable_i : std_logic;
2707  signal gt5_rx_cdrlocked : std_logic;
2708  signal gt5_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2709 
2710  signal gt6_txoutclk_i : std_logic;
2711  signal gt6_rxoutclk_i : std_logic;
2712  signal gt6_rxoutclkfabric_out : std_logic;
2713  signal gt6_txoutclk_i2 : std_logic;
2714  signal gt6_recclk_stable_i : std_logic;
2715  signal gt6_rx_cdrlocked : std_logic;
2716  signal gt6_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2717 
2718  signal gt7_txoutclk_i : std_logic;
2719  signal gt7_rxoutclk_i : std_logic;
2720  signal gt7_rxoutclkfabric_out : std_logic;
2721  signal gt7_txoutclk_i2 : std_logic;
2722  signal gt7_recclk_stable_i : std_logic;
2723  signal gt7_rx_cdrlocked : std_logic;
2724  signal gt7_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2725 
2726  signal gt8_txoutclk_i : std_logic;
2727  signal gt8_rxoutclk_i : std_logic;
2728  signal gt8_rxoutclkfabric_out : std_logic;
2729  signal gt8_txoutclk_i2 : std_logic;
2730  signal gt8_recclk_stable_i : std_logic;
2731  signal gt8_rx_cdrlocked : std_logic;
2732  signal gt8_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2733 
2734  signal gt9_txoutclk_i : std_logic;
2735  signal gt9_rxoutclk_i : std_logic;
2736  signal gt9_rxoutclkfabric_out : std_logic;
2737  signal gt9_txoutclk_i2 : std_logic;
2738  signal gt9_recclk_stable_i : std_logic;
2739  signal gt9_rx_cdrlocked : std_logic;
2740  signal gt9_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2741 
2742  signal gt10_txoutclk_i : std_logic;
2743  signal gt10_rxoutclk_i : std_logic;
2744  signal gt10_rxoutclkfabric_out : std_logic;
2745  signal gt10_txoutclk_i2 : std_logic;
2746  signal gt10_recclk_stable_i : std_logic;
2747  signal gt10_rx_cdrlocked : std_logic;
2748  signal gt10_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2749 
2750  signal gt11_txoutclk_i : std_logic;
2751  signal gt11_rxoutclk_i : std_logic;
2752  signal gt11_rxoutclkfabric_out : std_logic;
2753  signal gt11_txoutclk_i2 : std_logic;
2754  signal gt11_recclk_stable_i : std_logic;
2755  signal gt11_rx_cdrlocked : std_logic;
2756  signal gt11_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
2757 
2758 
2759 
2760 
2761 
2762 
2763  signal rx_cdrlocked : std_logic;
2764 
2765 
2766 
2767 
2768 
2769 --**************************** Main Body of Code *******************************
2770 begin
2771  -- Static signal Assigments
2772  tied_to_ground_i <= '0';
2773  tied_to_vcc_i <= '1';
2774 
2775  ----------------------------- The GT Wrapper -----------------------------
2776 
2777  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
2778  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
2779  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
2780  -- enabled, bonding should occur after alignment.
2781 
2782 
2783  amc_gtx5Gpd_i : amc_gtx5Gpd_multi_gt
2784  generic map
2785  (
2786  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
2787  )
2788  port map
2789  (
2790  --_____________________________________________________________________
2791  --_____________________________________________________________________
2792  --GT0 (X1Y0)
2793 
2794  ---------------------------- Channel - DRP Ports --------------------------
2795  gt0_drpaddr_in => gt0_drpaddr_in,
2796  gt0_drpclk_in => gt0_drpclk_in,
2797  gt0_drpdi_in => gt0_drpdi_in,
2798  gt0_drpdo_out => gt0_drpdo_out,
2799  gt0_drpen_in => gt0_drpen_in,
2800  gt0_drprdy_out => gt0_drprdy_out,
2801  gt0_drpwe_in => gt0_drpwe_in,
2802  --------------------------- Digital Monitor Ports --------------------------
2803  gt0_dmonitorout_out => gt0_dmonitorout_out ,
2804  ------------------------------- Loopback Ports -----------------------------
2805  gt0_loopback_in => gt0_loopback_in,
2806  ------------------------------ Power-Down Ports ----------------------------
2807  gt0_rxpd_in => gt0_rxpd_in,
2808  gt0_txpd_in => gt0_txpd_in,
2809  --------------------- RX Initialization and Reset Ports --------------------
2810  gt0_eyescanreset_in => gt0_eyescanreset_in ,
2811  gt0_rxuserrdy_in => gt0_rxuserrdy_i,
2812  -------------------------- RX Margin Analysis Ports ------------------------
2813  gt0_eyescandataerror_out => gt0_eyescandataerror_out,
2814  gt0_eyescantrigger_in => gt0_eyescantrigger_in ,
2815  ------------------- Receive Ports - Clock Correction Ports -----------------
2816  gt0_rxclkcorcnt_out => gt0_rxclkcorcnt_out ,
2817  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2818  gt0_rxusrclk_in => gt0_rxusrclk_in,
2819  gt0_rxusrclk2_in => gt0_rxusrclk2_in,
2820  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2821  gt0_rxdata_out => gt0_rxdata_out,
2822  ------------------- Receive Ports - Pattern Checker Ports ------------------
2823  gt0_rxprbserr_out => gt0_rxprbserr_out,
2824  gt0_rxprbssel_in => gt0_rxprbssel_in,
2825  ------------------- Receive Ports - Pattern Checker ports ------------------
2826  gt0_rxprbscntreset_in => gt0_rxprbscntreset_in ,
2827  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2828  gt0_rxdisperr_out => gt0_rxdisperr_out,
2829  gt0_rxnotintable_out => gt0_rxnotintable_out ,
2830  --------------------------- Receive Ports - RX AFE -------------------------
2831  gt0_gtxrxp_in => gt0_gtxrxp_in,
2832  ------------------------ Receive Ports - RX AFE Ports ----------------------
2833  gt0_gtxrxn_in => gt0_gtxrxn_in,
2834  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2835  gt0_rxbufstatus_out => gt0_rxbufstatus_out ,
2836  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2837  gt0_rxmcommaalignen_in => gt0_rxmcommaalignen_in ,
2838  gt0_rxpcommaalignen_in => gt0_rxpcommaalignen_in ,
2839  --------------------- Receive Ports - RX Equalizer Ports -------------------
2840  gt0_rxdfeagchold_in => gt0_rxdfeagchold_i,
2841  gt0_rxdfelfhold_in => gt0_rxdfelfhold_i,
2842  gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in ,
2843  gt0_rxmonitorout_out => gt0_rxmonitorout_out ,
2844  gt0_rxmonitorsel_in => gt0_rxmonitorsel_in ,
2845  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2846  gt0_rxoutclk_out => gt0_rxoutclk_out,
2847  gt0_rxoutclkfabric_out => gt0_rxoutclkfabric_out ,
2848  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2849  gt0_gtrxreset_in => gt0_gtrxreset_i,
2850  gt0_rxpmareset_in => gt0_rxpmareset_in,
2851  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2852  gt0_rxchariscomma_out => gt0_rxchariscomma_out ,
2853  gt0_rxcharisk_out => gt0_rxcharisk_out,
2854  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2855  gt0_rxresetdone_out => gt0_rxresetdone_i,
2856  --------------------- TX Initialization and Reset Ports --------------------
2857  gt0_gttxreset_in => gt0_gttxreset_i,
2858  gt0_txuserrdy_in => gt0_txuserrdy_i,
2859  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2860  gt0_txusrclk_in => gt0_txusrclk_in,
2861  gt0_txusrclk2_in => gt0_txusrclk2_in,
2862  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2863  gt0_txdiffctrl_in => gt0_txdiffctrl_in,
2864  ------------------ Transmit Ports - TX Data Path interface -----------------
2865  gt0_txdata_in => gt0_txdata_in,
2866  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2867  gt0_gtxtxn_out => gt0_gtxtxn_out,
2868  gt0_gtxtxp_out => gt0_gtxtxp_out,
2869  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2870  gt0_txoutclk_out => gt0_txoutclk_i,
2871  gt0_txoutclkfabric_out => gt0_txoutclkfabric_out ,
2872  gt0_txoutclkpcs_out => gt0_txoutclkpcs_out ,
2873  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2874  gt0_txcharisk_in => gt0_txcharisk_in,
2875  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2876  gt0_txresetdone_out => gt0_txresetdone_i,
2877  ------------------ Transmit Ports - pattern Generator Ports ----------------
2878  gt0_txprbssel_in => gt0_txprbssel_in,
2879 
2880 
2881  --_____________________________________________________________________
2882  --_____________________________________________________________________
2883  --GT1 (X1Y1)
2884 
2885  ---------------------------- Channel - DRP Ports --------------------------
2886  gt1_drpaddr_in => gt1_drpaddr_in,
2887  gt1_drpclk_in => gt1_drpclk_in,
2888  gt1_drpdi_in => gt1_drpdi_in,
2889  gt1_drpdo_out => gt1_drpdo_out,
2890  gt1_drpen_in => gt1_drpen_in,
2891  gt1_drprdy_out => gt1_drprdy_out,
2892  gt1_drpwe_in => gt1_drpwe_in,
2893  --------------------------- Digital Monitor Ports --------------------------
2894  gt1_dmonitorout_out => gt1_dmonitorout_out ,
2895  ------------------------------- Loopback Ports -----------------------------
2896  gt1_loopback_in => gt1_loopback_in,
2897  ------------------------------ Power-Down Ports ----------------------------
2898  gt1_rxpd_in => gt1_rxpd_in,
2899  gt1_txpd_in => gt1_txpd_in,
2900  --------------------- RX Initialization and Reset Ports --------------------
2901  gt1_eyescanreset_in => gt1_eyescanreset_in ,
2902  gt1_rxuserrdy_in => gt1_rxuserrdy_i,
2903  -------------------------- RX Margin Analysis Ports ------------------------
2904  gt1_eyescandataerror_out => gt1_eyescandataerror_out,
2905  gt1_eyescantrigger_in => gt1_eyescantrigger_in ,
2906  ------------------- Receive Ports - Clock Correction Ports -----------------
2907  gt1_rxclkcorcnt_out => gt1_rxclkcorcnt_out ,
2908  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2909  gt1_rxusrclk_in => gt1_rxusrclk_in,
2910  gt1_rxusrclk2_in => gt1_rxusrclk2_in,
2911  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2912  gt1_rxdata_out => gt1_rxdata_out,
2913  ------------------- Receive Ports - Pattern Checker Ports ------------------
2914  gt1_rxprbserr_out => gt1_rxprbserr_out,
2915  gt1_rxprbssel_in => gt1_rxprbssel_in,
2916  ------------------- Receive Ports - Pattern Checker ports ------------------
2917  gt1_rxprbscntreset_in => gt1_rxprbscntreset_in ,
2918  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2919  gt1_rxdisperr_out => gt1_rxdisperr_out,
2920  gt1_rxnotintable_out => gt1_rxnotintable_out ,
2921  --------------------------- Receive Ports - RX AFE -------------------------
2922  gt1_gtxrxp_in => gt1_gtxrxp_in,
2923  ------------------------ Receive Ports - RX AFE Ports ----------------------
2924  gt1_gtxrxn_in => gt1_gtxrxn_in,
2925  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2926  gt1_rxbufstatus_out => gt1_rxbufstatus_out ,
2927  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2928  gt1_rxmcommaalignen_in => gt1_rxmcommaalignen_in ,
2929  gt1_rxpcommaalignen_in => gt1_rxpcommaalignen_in ,
2930  --------------------- Receive Ports - RX Equalizer Ports -------------------
2931  gt1_rxdfeagchold_in => gt1_rxdfeagchold_i,
2932  gt1_rxdfelfhold_in => gt1_rxdfelfhold_i,
2933  gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in ,
2934  gt1_rxmonitorout_out => gt1_rxmonitorout_out ,
2935  gt1_rxmonitorsel_in => gt1_rxmonitorsel_in ,
2936  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2937  gt1_rxoutclk_out => gt1_rxoutclk_out,
2938  gt1_rxoutclkfabric_out => gt1_rxoutclkfabric_out ,
2939  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2940  gt1_gtrxreset_in => gt1_gtrxreset_i,
2941  gt1_rxpmareset_in => gt1_rxpmareset_in,
2942  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2943  gt1_rxchariscomma_out => gt1_rxchariscomma_out ,
2944  gt1_rxcharisk_out => gt1_rxcharisk_out,
2945  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2946  gt1_rxresetdone_out => gt1_rxresetdone_i,
2947  --------------------- TX Initialization and Reset Ports --------------------
2948  gt1_gttxreset_in => gt1_gttxreset_i,
2949  gt1_txuserrdy_in => gt1_txuserrdy_i,
2950  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2951  gt1_txusrclk_in => gt1_txusrclk_in,
2952  gt1_txusrclk2_in => gt1_txusrclk2_in,
2953  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2954  gt1_txdiffctrl_in => gt1_txdiffctrl_in,
2955  ------------------ Transmit Ports - TX Data Path interface -----------------
2956  gt1_txdata_in => gt1_txdata_in,
2957  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2958  gt1_gtxtxn_out => gt1_gtxtxn_out,
2959  gt1_gtxtxp_out => gt1_gtxtxp_out,
2960  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2961  gt1_txoutclk_out => gt1_txoutclk_i,
2962  gt1_txoutclkfabric_out => gt1_txoutclkfabric_out ,
2963  gt1_txoutclkpcs_out => gt1_txoutclkpcs_out ,
2964  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2965  gt1_txcharisk_in => gt1_txcharisk_in,
2966  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2967  gt1_txresetdone_out => gt1_txresetdone_i,
2968  ------------------ Transmit Ports - pattern Generator Ports ----------------
2969  gt1_txprbssel_in => gt1_txprbssel_in,
2970 
2971 
2972  --_____________________________________________________________________
2973  --_____________________________________________________________________
2974  --GT2 (X1Y2)
2975 
2976  ---------------------------- Channel - DRP Ports --------------------------
2977  gt2_drpaddr_in => gt2_drpaddr_in,
2978  gt2_drpclk_in => gt2_drpclk_in,
2979  gt2_drpdi_in => gt2_drpdi_in,
2980  gt2_drpdo_out => gt2_drpdo_out,
2981  gt2_drpen_in => gt2_drpen_in,
2982  gt2_drprdy_out => gt2_drprdy_out,
2983  gt2_drpwe_in => gt2_drpwe_in,
2984  --------------------------- Digital Monitor Ports --------------------------
2985  gt2_dmonitorout_out => gt2_dmonitorout_out ,
2986  ------------------------------- Loopback Ports -----------------------------
2987  gt2_loopback_in => gt2_loopback_in,
2988  ------------------------------ Power-Down Ports ----------------------------
2989  gt2_rxpd_in => gt2_rxpd_in,
2990  gt2_txpd_in => gt2_txpd_in,
2991  --------------------- RX Initialization and Reset Ports --------------------
2992  gt2_eyescanreset_in => gt2_eyescanreset_in ,
2993  gt2_rxuserrdy_in => gt2_rxuserrdy_i,
2994  -------------------------- RX Margin Analysis Ports ------------------------
2995  gt2_eyescandataerror_out => gt2_eyescandataerror_out ,
2996  gt2_eyescantrigger_in => gt2_eyescantrigger_in ,
2997  ------------------- Receive Ports - Clock Correction Ports -----------------
2998  gt2_rxclkcorcnt_out => gt2_rxclkcorcnt_out ,
2999  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3000  gt2_rxusrclk_in => gt2_rxusrclk_in,
3001  gt2_rxusrclk2_in => gt2_rxusrclk2_in,
3002  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3003  gt2_rxdata_out => gt2_rxdata_out,
3004  ------------------- Receive Ports - Pattern Checker Ports ------------------
3005  gt2_rxprbserr_out => gt2_rxprbserr_out,
3006  gt2_rxprbssel_in => gt2_rxprbssel_in,
3007  ------------------- Receive Ports - Pattern Checker ports ------------------
3008  gt2_rxprbscntreset_in => gt2_rxprbscntreset_in ,
3009  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3010  gt2_rxdisperr_out => gt2_rxdisperr_out,
3011  gt2_rxnotintable_out => gt2_rxnotintable_out ,
3012  --------------------------- Receive Ports - RX AFE -------------------------
3013  gt2_gtxrxp_in => gt2_gtxrxp_in,
3014  ------------------------ Receive Ports - RX AFE Ports ----------------------
3015  gt2_gtxrxn_in => gt2_gtxrxn_in,
3016  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3017  gt2_rxbufstatus_out => gt2_rxbufstatus_out ,
3018  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3019  gt2_rxmcommaalignen_in => gt2_rxmcommaalignen_in ,
3020  gt2_rxpcommaalignen_in => gt2_rxpcommaalignen_in ,
3021  --------------------- Receive Ports - RX Equalizer Ports -------------------
3022  gt2_rxdfeagchold_in => gt2_rxdfeagchold_i,
3023  gt2_rxdfelfhold_in => gt2_rxdfelfhold_i,
3024  gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in ,
3025  gt2_rxmonitorout_out => gt2_rxmonitorout_out ,
3026  gt2_rxmonitorsel_in => gt2_rxmonitorsel_in ,
3027  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3028  gt2_rxoutclk_out => gt2_rxoutclk_out,
3029  gt2_rxoutclkfabric_out => gt2_rxoutclkfabric_out ,
3030  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3031  gt2_gtrxreset_in => gt2_gtrxreset_i,
3032  gt2_rxpmareset_in => gt2_rxpmareset_in,
3033  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3034  gt2_rxchariscomma_out => gt2_rxchariscomma_out ,
3035  gt2_rxcharisk_out => gt2_rxcharisk_out,
3036  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3037  gt2_rxresetdone_out => gt2_rxresetdone_i,
3038  --------------------- TX Initialization and Reset Ports --------------------
3039  gt2_gttxreset_in => gt2_gttxreset_i,
3040  gt2_txuserrdy_in => gt2_txuserrdy_i,
3041  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3042  gt2_txusrclk_in => gt2_txusrclk_in,
3043  gt2_txusrclk2_in => gt2_txusrclk2_in,
3044  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3045  gt2_txdiffctrl_in => gt2_txdiffctrl_in,
3046  ------------------ Transmit Ports - TX Data Path interface -----------------
3047  gt2_txdata_in => gt2_txdata_in,
3048  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3049  gt2_gtxtxn_out => gt2_gtxtxn_out,
3050  gt2_gtxtxp_out => gt2_gtxtxp_out,
3051  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3052  gt2_txoutclk_out => gt2_txoutclk_i,
3053  gt2_txoutclkfabric_out => gt2_txoutclkfabric_out ,
3054  gt2_txoutclkpcs_out => gt2_txoutclkpcs_out ,
3055  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3056  gt2_txcharisk_in => gt2_txcharisk_in,
3057  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3058  gt2_txresetdone_out => gt2_txresetdone_i,
3059  ------------------ Transmit Ports - pattern Generator Ports ----------------
3060  gt2_txprbssel_in => gt2_txprbssel_in,
3061 
3062 
3063  --_____________________________________________________________________
3064  --_____________________________________________________________________
3065  --GT3 (X1Y3)
3066 
3067  ---------------------------- Channel - DRP Ports --------------------------
3068  gt3_drpaddr_in => gt3_drpaddr_in,
3069  gt3_drpclk_in => gt3_drpclk_in,
3070  gt3_drpdi_in => gt3_drpdi_in,
3071  gt3_drpdo_out => gt3_drpdo_out,
3072  gt3_drpen_in => gt3_drpen_in,
3073  gt3_drprdy_out => gt3_drprdy_out,
3074  gt3_drpwe_in => gt3_drpwe_in,
3075  --------------------------- Digital Monitor Ports --------------------------
3076  gt3_dmonitorout_out => gt3_dmonitorout_out ,
3077  ------------------------------- Loopback Ports -----------------------------
3078  gt3_loopback_in => gt3_loopback_in,
3079  ------------------------------ Power-Down Ports ----------------------------
3080  gt3_rxpd_in => gt3_rxpd_in,
3081  gt3_txpd_in => gt3_txpd_in,
3082  --------------------- RX Initialization and Reset Ports --------------------
3083  gt3_eyescanreset_in => gt3_eyescanreset_in ,
3084  gt3_rxuserrdy_in => gt3_rxuserrdy_i,
3085  -------------------------- RX Margin Analysis Ports ------------------------
3086  gt3_eyescandataerror_out => gt3_eyescandataerror_out,
3087  gt3_eyescantrigger_in => gt3_eyescantrigger_in ,
3088  ------------------- Receive Ports - Clock Correction Ports -----------------
3089  gt3_rxclkcorcnt_out => gt3_rxclkcorcnt_out ,
3090  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3091  gt3_rxusrclk_in => gt3_rxusrclk_in,
3092  gt3_rxusrclk2_in => gt3_rxusrclk2_in,
3093  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3094  gt3_rxdata_out => gt3_rxdata_out,
3095  ------------------- Receive Ports - Pattern Checker Ports ------------------
3096  gt3_rxprbserr_out => gt3_rxprbserr_out,
3097  gt3_rxprbssel_in => gt3_rxprbssel_in,
3098  ------------------- Receive Ports - Pattern Checker ports ------------------
3099  gt3_rxprbscntreset_in => gt3_rxprbscntreset_in ,
3100  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3101  gt3_rxdisperr_out => gt3_rxdisperr_out,
3102  gt3_rxnotintable_out => gt3_rxnotintable_out ,
3103  --------------------------- Receive Ports - RX AFE -------------------------
3104  gt3_gtxrxp_in => gt3_gtxrxp_in,
3105  ------------------------ Receive Ports - RX AFE Ports ----------------------
3106  gt3_gtxrxn_in => gt3_gtxrxn_in,
3107  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3108  gt3_rxbufstatus_out => gt3_rxbufstatus_out ,
3109  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3110  gt3_rxmcommaalignen_in => gt3_rxmcommaalignen_in ,
3111  gt3_rxpcommaalignen_in => gt3_rxpcommaalignen_in ,
3112  --------------------- Receive Ports - RX Equalizer Ports -------------------
3113  gt3_rxdfeagchold_in => gt3_rxdfeagchold_i,
3114  gt3_rxdfelfhold_in => gt3_rxdfelfhold_i,
3115  gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in ,
3116  gt3_rxmonitorout_out => gt3_rxmonitorout_out ,
3117  gt3_rxmonitorsel_in => gt3_rxmonitorsel_in ,
3118  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3119  gt3_rxoutclk_out => gt3_rxoutclk_out,
3120  gt3_rxoutclkfabric_out => gt3_rxoutclkfabric_out ,
3121  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3122  gt3_gtrxreset_in => gt3_gtrxreset_i,
3123  gt3_rxpmareset_in => gt3_rxpmareset_in,
3124  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3125  gt3_rxchariscomma_out => gt3_rxchariscomma_out ,
3126  gt3_rxcharisk_out => gt3_rxcharisk_out,
3127  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3128  gt3_rxresetdone_out => gt3_rxresetdone_i,
3129  --------------------- TX Initialization and Reset Ports --------------------
3130  gt3_gttxreset_in => gt3_gttxreset_i,
3131  gt3_txuserrdy_in => gt3_txuserrdy_i,
3132  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3133  gt3_txusrclk_in => gt3_txusrclk_in,
3134  gt3_txusrclk2_in => gt3_txusrclk2_in,
3135  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3136  gt3_txdiffctrl_in => gt3_txdiffctrl_in,
3137  ------------------ Transmit Ports - TX Data Path interface -----------------
3138  gt3_txdata_in => gt3_txdata_in,
3139  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3140  gt3_gtxtxn_out => gt3_gtxtxn_out,
3141  gt3_gtxtxp_out => gt3_gtxtxp_out,
3142  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3143  gt3_txoutclk_out => gt3_txoutclk_i,
3144  gt3_txoutclkfabric_out => gt3_txoutclkfabric_out ,
3145  gt3_txoutclkpcs_out => gt3_txoutclkpcs_out ,
3146  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3147  gt3_txcharisk_in => gt3_txcharisk_in,
3148  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3149  gt3_txresetdone_out => gt3_txresetdone_i,
3150  ------------------ Transmit Ports - pattern Generator Ports ----------------
3151  gt3_txprbssel_in => gt3_txprbssel_in,
3152 
3153 
3154  --_____________________________________________________________________
3155  --_____________________________________________________________________
3156  --GT4 (X1Y4)
3157 
3158  ---------------------------- Channel - DRP Ports --------------------------
3159  gt4_drpaddr_in => gt4_drpaddr_in,
3160  gt4_drpclk_in => gt4_drpclk_in,
3161  gt4_drpdi_in => gt4_drpdi_in,
3162  gt4_drpdo_out => gt4_drpdo_out,
3163  gt4_drpen_in => gt4_drpen_in,
3164  gt4_drprdy_out => gt4_drprdy_out,
3165  gt4_drpwe_in => gt4_drpwe_in,
3166  --------------------------- Digital Monitor Ports --------------------------
3167  gt4_dmonitorout_out => gt4_dmonitorout_out ,
3168  ------------------------------- Loopback Ports -----------------------------
3169  gt4_loopback_in => gt4_loopback_in,
3170  ------------------------------ Power-Down Ports ----------------------------
3171  gt4_rxpd_in => gt4_rxpd_in,
3172  gt4_txpd_in => gt4_txpd_in,
3173  --------------------- RX Initialization and Reset Ports --------------------
3174  gt4_eyescanreset_in => gt4_eyescanreset_in ,
3175  gt4_rxuserrdy_in => gt4_rxuserrdy_i,
3176  -------------------------- RX Margin Analysis Ports ------------------------
3177  gt4_eyescandataerror_out => gt4_eyescandataerror_out,
3178  gt4_eyescantrigger_in => gt4_eyescantrigger_in ,
3179  ------------------- Receive Ports - Clock Correction Ports -----------------
3180  gt4_rxclkcorcnt_out => gt4_rxclkcorcnt_out ,
3181  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3182  gt4_rxusrclk_in => gt4_rxusrclk_in,
3183  gt4_rxusrclk2_in => gt4_rxusrclk2_in,
3184  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3185  gt4_rxdata_out => gt4_rxdata_out,
3186  ------------------- Receive Ports - Pattern Checker Ports ------------------
3187  gt4_rxprbserr_out => gt4_rxprbserr_out,
3188  gt4_rxprbssel_in => gt4_rxprbssel_in,
3189  ------------------- Receive Ports - Pattern Checker ports ------------------
3190  gt4_rxprbscntreset_in => gt4_rxprbscntreset_in ,
3191  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3192  gt4_rxdisperr_out => gt4_rxdisperr_out,
3193  gt4_rxnotintable_out => gt4_rxnotintable_out ,
3194  --------------------------- Receive Ports - RX AFE -------------------------
3195  gt4_gtxrxp_in => gt4_gtxrxp_in,
3196  ------------------------ Receive Ports - RX AFE Ports ----------------------
3197  gt4_gtxrxn_in => gt4_gtxrxn_in,
3198  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3199  gt4_rxbufstatus_out => gt4_rxbufstatus_out ,
3200  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3201  gt4_rxmcommaalignen_in => gt4_rxmcommaalignen_in ,
3202  gt4_rxpcommaalignen_in => gt4_rxpcommaalignen_in ,
3203  --------------------- Receive Ports - RX Equalizer Ports -------------------
3204  gt4_rxdfeagchold_in => gt4_rxdfeagchold_i,
3205  gt4_rxdfelfhold_in => gt4_rxdfelfhold_i,
3206  gt4_rxdfelpmreset_in => gt4_rxdfelpmreset_in ,
3207  gt4_rxmonitorout_out => gt4_rxmonitorout_out ,
3208  gt4_rxmonitorsel_in => gt4_rxmonitorsel_in ,
3209  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3210  gt4_rxoutclk_out => gt4_rxoutclk_out,
3211  gt4_rxoutclkfabric_out => gt4_rxoutclkfabric_out ,
3212  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3213  gt4_gtrxreset_in => gt4_gtrxreset_i,
3214  gt4_rxpmareset_in => gt4_rxpmareset_in,
3215  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3216  gt4_rxchariscomma_out => gt4_rxchariscomma_out ,
3217  gt4_rxcharisk_out => gt4_rxcharisk_out,
3218  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3219  gt4_rxresetdone_out => gt4_rxresetdone_i,
3220  --------------------- TX Initialization and Reset Ports --------------------
3221  gt4_gttxreset_in => gt4_gttxreset_i,
3222  gt4_txuserrdy_in => gt4_txuserrdy_i,
3223  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3224  gt4_txusrclk_in => gt4_txusrclk_in,
3225  gt4_txusrclk2_in => gt4_txusrclk2_in,
3226  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3227  gt4_txdiffctrl_in => gt4_txdiffctrl_in,
3228  ------------------ Transmit Ports - TX Data Path interface -----------------
3229  gt4_txdata_in => gt4_txdata_in,
3230  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3231  gt4_gtxtxn_out => gt4_gtxtxn_out,
3232  gt4_gtxtxp_out => gt4_gtxtxp_out,
3233  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3234  gt4_txoutclk_out => gt4_txoutclk_i,
3235  gt4_txoutclkfabric_out => gt4_txoutclkfabric_out ,
3236  gt4_txoutclkpcs_out => gt4_txoutclkpcs_out ,
3237  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3238  gt4_txcharisk_in => gt4_txcharisk_in,
3239  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3240  gt4_txresetdone_out => gt4_txresetdone_i,
3241  ------------------ Transmit Ports - pattern Generator Ports ----------------
3242  gt4_txprbssel_in => gt4_txprbssel_in,
3243 
3244 
3245  --_____________________________________________________________________
3246  --_____________________________________________________________________
3247  --GT5 (X1Y5)
3248 
3249  ---------------------------- Channel - DRP Ports --------------------------
3250  gt5_drpaddr_in => gt5_drpaddr_in,
3251  gt5_drpclk_in => gt5_drpclk_in,
3252  gt5_drpdi_in => gt5_drpdi_in,
3253  gt5_drpdo_out => gt5_drpdo_out,
3254  gt5_drpen_in => gt5_drpen_in,
3255  gt5_drprdy_out => gt5_drprdy_out,
3256  gt5_drpwe_in => gt5_drpwe_in,
3257  --------------------------- Digital Monitor Ports --------------------------
3258  gt5_dmonitorout_out => gt5_dmonitorout_out ,
3259  ------------------------------- Loopback Ports -----------------------------
3260  gt5_loopback_in => gt5_loopback_in,
3261  ------------------------------ Power-Down Ports ----------------------------
3262  gt5_rxpd_in => gt5_rxpd_in,
3263  gt5_txpd_in => gt5_txpd_in,
3264  --------------------- RX Initialization and Reset Ports --------------------
3265  gt5_eyescanreset_in => gt5_eyescanreset_in ,
3266  gt5_rxuserrdy_in => gt5_rxuserrdy_i,
3267  -------------------------- RX Margin Analysis Ports ------------------------
3268  gt5_eyescandataerror_out => gt5_eyescandataerror_out,
3269  gt5_eyescantrigger_in => gt5_eyescantrigger_in ,
3270  ------------------- Receive Ports - Clock Correction Ports -----------------
3271  gt5_rxclkcorcnt_out => gt5_rxclkcorcnt_out ,
3272  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3273  gt5_rxusrclk_in => gt5_rxusrclk_in,
3274  gt5_rxusrclk2_in => gt5_rxusrclk2_in,
3275  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3276  gt5_rxdata_out => gt5_rxdata_out,
3277  ------------------- Receive Ports - Pattern Checker Ports ------------------
3278  gt5_rxprbserr_out => gt5_rxprbserr_out,
3279  gt5_rxprbssel_in => gt5_rxprbssel_in,
3280  ------------------- Receive Ports - Pattern Checker ports ------------------
3281  gt5_rxprbscntreset_in => gt5_rxprbscntreset_in ,
3282  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3283  gt5_rxdisperr_out => gt5_rxdisperr_out,
3284  gt5_rxnotintable_out => gt5_rxnotintable_out ,
3285  --------------------------- Receive Ports - RX AFE -------------------------
3286  gt5_gtxrxp_in => gt5_gtxrxp_in,
3287  ------------------------ Receive Ports - RX AFE Ports ----------------------
3288  gt5_gtxrxn_in => gt5_gtxrxn_in,
3289  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3290  gt5_rxbufstatus_out => gt5_rxbufstatus_out ,
3291  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3292  gt5_rxmcommaalignen_in => gt5_rxmcommaalignen_in ,
3293  gt5_rxpcommaalignen_in => gt5_rxpcommaalignen_in ,
3294  --------------------- Receive Ports - RX Equalizer Ports -------------------
3295  gt5_rxdfeagchold_in => gt5_rxdfeagchold_i,
3296  gt5_rxdfelfhold_in => gt5_rxdfelfhold_i,
3297  gt5_rxdfelpmreset_in => gt5_rxdfelpmreset_in ,
3298  gt5_rxmonitorout_out => gt5_rxmonitorout_out ,
3299  gt5_rxmonitorsel_in => gt5_rxmonitorsel_in ,
3300  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3301  gt5_rxoutclk_out => gt5_rxoutclk_out,
3302  gt5_rxoutclkfabric_out => gt5_rxoutclkfabric_out ,
3303  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3304  gt5_gtrxreset_in => gt5_gtrxreset_i,
3305  gt5_rxpmareset_in => gt5_rxpmareset_in,
3306  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3307  gt5_rxchariscomma_out => gt5_rxchariscomma_out ,
3308  gt5_rxcharisk_out => gt5_rxcharisk_out,
3309  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3310  gt5_rxresetdone_out => gt5_rxresetdone_i,
3311  --------------------- TX Initialization and Reset Ports --------------------
3312  gt5_gttxreset_in => gt5_gttxreset_i,
3313  gt5_txuserrdy_in => gt5_txuserrdy_i,
3314  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3315  gt5_txusrclk_in => gt5_txusrclk_in,
3316  gt5_txusrclk2_in => gt5_txusrclk2_in,
3317  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3318  gt5_txdiffctrl_in => gt5_txdiffctrl_in,
3319  ------------------ Transmit Ports - TX Data Path interface -----------------
3320  gt5_txdata_in => gt5_txdata_in,
3321  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3322  gt5_gtxtxn_out => gt5_gtxtxn_out,
3323  gt5_gtxtxp_out => gt5_gtxtxp_out,
3324  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3325  gt5_txoutclk_out => gt5_txoutclk_i,
3326  gt5_txoutclkfabric_out => gt5_txoutclkfabric_out ,
3327  gt5_txoutclkpcs_out => gt5_txoutclkpcs_out ,
3328  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3329  gt5_txcharisk_in => gt5_txcharisk_in,
3330  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3331  gt5_txresetdone_out => gt5_txresetdone_i,
3332  ------------------ Transmit Ports - pattern Generator Ports ----------------
3333  gt5_txprbssel_in => gt5_txprbssel_in,
3334 
3335 
3336  --_____________________________________________________________________
3337  --_____________________________________________________________________
3338  --GT6 (X1Y6)
3339 
3340  ---------------------------- Channel - DRP Ports --------------------------
3341  gt6_drpaddr_in => gt6_drpaddr_in,
3342  gt6_drpclk_in => gt6_drpclk_in,
3343  gt6_drpdi_in => gt6_drpdi_in,
3344  gt6_drpdo_out => gt6_drpdo_out,
3345  gt6_drpen_in => gt6_drpen_in,
3346  gt6_drprdy_out => gt6_drprdy_out,
3347  gt6_drpwe_in => gt6_drpwe_in,
3348  --------------------------- Digital Monitor Ports --------------------------
3349  gt6_dmonitorout_out => gt6_dmonitorout_out ,
3350  ------------------------------- Loopback Ports -----------------------------
3351  gt6_loopback_in => gt6_loopback_in,
3352  ------------------------------ Power-Down Ports ----------------------------
3353  gt6_rxpd_in => gt6_rxpd_in,
3354  gt6_txpd_in => gt6_txpd_in,
3355  --------------------- RX Initialization and Reset Ports --------------------
3356  gt6_eyescanreset_in => gt6_eyescanreset_in ,
3357  gt6_rxuserrdy_in => gt6_rxuserrdy_i,
3358  -------------------------- RX Margin Analysis Ports ------------------------
3359  gt6_eyescandataerror_out => gt6_eyescandataerror_out,
3360  gt6_eyescantrigger_in => gt6_eyescantrigger_in ,
3361  ------------------- Receive Ports - Clock Correction Ports -----------------
3362  gt6_rxclkcorcnt_out => gt6_rxclkcorcnt_out ,
3363  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3364  gt6_rxusrclk_in => gt6_rxusrclk_in,
3365  gt6_rxusrclk2_in => gt6_rxusrclk2_in,
3366  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3367  gt6_rxdata_out => gt6_rxdata_out,
3368  ------------------- Receive Ports - Pattern Checker Ports ------------------
3369  gt6_rxprbserr_out => gt6_rxprbserr_out,
3370  gt6_rxprbssel_in => gt6_rxprbssel_in,
3371  ------------------- Receive Ports - Pattern Checker ports ------------------
3372  gt6_rxprbscntreset_in => gt6_rxprbscntreset_in ,
3373  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3374  gt6_rxdisperr_out => gt6_rxdisperr_out,
3375  gt6_rxnotintable_out => gt6_rxnotintable_out ,
3376  --------------------------- Receive Ports - RX AFE -------------------------
3377  gt6_gtxrxp_in => gt6_gtxrxp_in,
3378  ------------------------ Receive Ports - RX AFE Ports ----------------------
3379  gt6_gtxrxn_in => gt6_gtxrxn_in,
3380  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3381  gt6_rxbufstatus_out => gt6_rxbufstatus_out ,
3382  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3383  gt6_rxmcommaalignen_in => gt6_rxmcommaalignen_in ,
3384  gt6_rxpcommaalignen_in => gt6_rxpcommaalignen_in ,
3385  --------------------- Receive Ports - RX Equalizer Ports -------------------
3386  gt6_rxdfeagchold_in => gt6_rxdfeagchold_i,
3387  gt6_rxdfelfhold_in => gt6_rxdfelfhold_i,
3388  gt6_rxdfelpmreset_in => gt6_rxdfelpmreset_in ,
3389  gt6_rxmonitorout_out => gt6_rxmonitorout_out ,
3390  gt6_rxmonitorsel_in => gt6_rxmonitorsel_in ,
3391  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3392  gt6_rxoutclk_out => gt6_rxoutclk_out,
3393  gt6_rxoutclkfabric_out => gt6_rxoutclkfabric_out ,
3394  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3395  gt6_gtrxreset_in => gt6_gtrxreset_i,
3396  gt6_rxpmareset_in => gt6_rxpmareset_in,
3397  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3398  gt6_rxchariscomma_out => gt6_rxchariscomma_out ,
3399  gt6_rxcharisk_out => gt6_rxcharisk_out,
3400  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3401  gt6_rxresetdone_out => gt6_rxresetdone_i,
3402  --------------------- TX Initialization and Reset Ports --------------------
3403  gt6_gttxreset_in => gt6_gttxreset_i,
3404  gt6_txuserrdy_in => gt6_txuserrdy_i,
3405  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3406  gt6_txusrclk_in => gt6_txusrclk_in,
3407  gt6_txusrclk2_in => gt6_txusrclk2_in,
3408  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3409  gt6_txdiffctrl_in => gt6_txdiffctrl_in,
3410  ------------------ Transmit Ports - TX Data Path interface -----------------
3411  gt6_txdata_in => gt6_txdata_in,
3412  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3413  gt6_gtxtxn_out => gt6_gtxtxn_out,
3414  gt6_gtxtxp_out => gt6_gtxtxp_out,
3415  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3416  gt6_txoutclk_out => gt6_txoutclk_i,
3417  gt6_txoutclkfabric_out => gt6_txoutclkfabric_out ,
3418  gt6_txoutclkpcs_out => gt6_txoutclkpcs_out ,
3419  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3420  gt6_txcharisk_in => gt6_txcharisk_in,
3421  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3422  gt6_txresetdone_out => gt6_txresetdone_i,
3423  ------------------ Transmit Ports - pattern Generator Ports ----------------
3424  gt6_txprbssel_in => gt6_txprbssel_in,
3425 
3426 
3427  --_____________________________________________________________________
3428  --_____________________________________________________________________
3429  --GT7 (X1Y7)
3430 
3431  ---------------------------- Channel - DRP Ports --------------------------
3432  gt7_drpaddr_in => gt7_drpaddr_in,
3433  gt7_drpclk_in => gt7_drpclk_in,
3434  gt7_drpdi_in => gt7_drpdi_in,
3435  gt7_drpdo_out => gt7_drpdo_out,
3436  gt7_drpen_in => gt7_drpen_in,
3437  gt7_drprdy_out => gt7_drprdy_out,
3438  gt7_drpwe_in => gt7_drpwe_in,
3439  --------------------------- Digital Monitor Ports --------------------------
3440  gt7_dmonitorout_out => gt7_dmonitorout_out ,
3441  ------------------------------- Loopback Ports -----------------------------
3442  gt7_loopback_in => gt7_loopback_in,
3443  ------------------------------ Power-Down Ports ----------------------------
3444  gt7_rxpd_in => gt7_rxpd_in,
3445  gt7_txpd_in => gt7_txpd_in,
3446  --------------------- RX Initialization and Reset Ports --------------------
3447  gt7_eyescanreset_in => gt7_eyescanreset_in ,
3448  gt7_rxuserrdy_in => gt7_rxuserrdy_i,
3449  -------------------------- RX Margin Analysis Ports ------------------------
3450  gt7_eyescandataerror_out => gt7_eyescandataerror_out,
3451  gt7_eyescantrigger_in => gt7_eyescantrigger_in ,
3452  ------------------- Receive Ports - Clock Correction Ports -----------------
3453  gt7_rxclkcorcnt_out => gt7_rxclkcorcnt_out ,
3454  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3455  gt7_rxusrclk_in => gt7_rxusrclk_in,
3456  gt7_rxusrclk2_in => gt7_rxusrclk2_in,
3457  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3458  gt7_rxdata_out => gt7_rxdata_out,
3459  ------------------- Receive Ports - Pattern Checker Ports ------------------
3460  gt7_rxprbserr_out => gt7_rxprbserr_out,
3461  gt7_rxprbssel_in => gt7_rxprbssel_in,
3462  ------------------- Receive Ports - Pattern Checker ports ------------------
3463  gt7_rxprbscntreset_in => gt7_rxprbscntreset_in ,
3464  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3465  gt7_rxdisperr_out => gt7_rxdisperr_out,
3466  gt7_rxnotintable_out => gt7_rxnotintable_out ,
3467  --------------------------- Receive Ports - RX AFE -------------------------
3468  gt7_gtxrxp_in => gt7_gtxrxp_in,
3469  ------------------------ Receive Ports - RX AFE Ports ----------------------
3470  gt7_gtxrxn_in => gt7_gtxrxn_in,
3471  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3472  gt7_rxbufstatus_out => gt7_rxbufstatus_out ,
3473  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3474  gt7_rxmcommaalignen_in => gt7_rxmcommaalignen_in ,
3475  gt7_rxpcommaalignen_in => gt7_rxpcommaalignen_in ,
3476  --------------------- Receive Ports - RX Equalizer Ports -------------------
3477  gt7_rxdfeagchold_in => gt7_rxdfeagchold_i,
3478  gt7_rxdfelfhold_in => gt7_rxdfelfhold_i,
3479  gt7_rxdfelpmreset_in => gt7_rxdfelpmreset_in ,
3480  gt7_rxmonitorout_out => gt7_rxmonitorout_out ,
3481  gt7_rxmonitorsel_in => gt7_rxmonitorsel_in ,
3482  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3483  gt7_rxoutclk_out => gt7_rxoutclk_out,
3484  gt7_rxoutclkfabric_out => gt7_rxoutclkfabric_out ,
3485  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3486  gt7_gtrxreset_in => gt7_gtrxreset_i,
3487  gt7_rxpmareset_in => gt7_rxpmareset_in,
3488  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3489  gt7_rxchariscomma_out => gt7_rxchariscomma_out ,
3490  gt7_rxcharisk_out => gt7_rxcharisk_out,
3491  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3492  gt7_rxresetdone_out => gt7_rxresetdone_i,
3493  --------------------- TX Initialization and Reset Ports --------------------
3494  gt7_gttxreset_in => gt7_gttxreset_i,
3495  gt7_txuserrdy_in => gt7_txuserrdy_i,
3496  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3497  gt7_txusrclk_in => gt7_txusrclk_in,
3498  gt7_txusrclk2_in => gt7_txusrclk2_in,
3499  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3500  gt7_txdiffctrl_in => gt7_txdiffctrl_in,
3501  ------------------ Transmit Ports - TX Data Path interface -----------------
3502  gt7_txdata_in => gt7_txdata_in,
3503  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3504  gt7_gtxtxn_out => gt7_gtxtxn_out,
3505  gt7_gtxtxp_out => gt7_gtxtxp_out,
3506  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3507  gt7_txoutclk_out => gt7_txoutclk_i,
3508  gt7_txoutclkfabric_out => gt7_txoutclkfabric_out ,
3509  gt7_txoutclkpcs_out => gt7_txoutclkpcs_out ,
3510  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3511  gt7_txcharisk_in => gt7_txcharisk_in,
3512  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3513  gt7_txresetdone_out => gt7_txresetdone_i,
3514  ------------------ Transmit Ports - pattern Generator Ports ----------------
3515  gt7_txprbssel_in => gt7_txprbssel_in,
3516 
3517 
3518  --_____________________________________________________________________
3519  --_____________________________________________________________________
3520  --GT8 (X1Y8)
3521 
3522  ---------------------------- Channel - DRP Ports --------------------------
3523  gt8_drpaddr_in => gt8_drpaddr_in,
3524  gt8_drpclk_in => gt8_drpclk_in,
3525  gt8_drpdi_in => gt8_drpdi_in,
3526  gt8_drpdo_out => gt8_drpdo_out,
3527  gt8_drpen_in => gt8_drpen_in,
3528  gt8_drprdy_out => gt8_drprdy_out,
3529  gt8_drpwe_in => gt8_drpwe_in,
3530  --------------------------- Digital Monitor Ports --------------------------
3531  gt8_dmonitorout_out => gt8_dmonitorout_out ,
3532  ------------------------------- Loopback Ports -----------------------------
3533  gt8_loopback_in => gt8_loopback_in,
3534  ------------------------------ Power-Down Ports ----------------------------
3535  gt8_rxpd_in => gt8_rxpd_in,
3536  gt8_txpd_in => gt8_txpd_in,
3537  --------------------- RX Initialization and Reset Ports --------------------
3538  gt8_eyescanreset_in => gt8_eyescanreset_in ,
3539  gt8_rxuserrdy_in => gt8_rxuserrdy_i,
3540  -------------------------- RX Margin Analysis Ports ------------------------
3541  gt8_eyescandataerror_out => gt8_eyescandataerror_out,
3542  gt8_eyescantrigger_in => gt8_eyescantrigger_in ,
3543  ------------------- Receive Ports - Clock Correction Ports -----------------
3544  gt8_rxclkcorcnt_out => gt8_rxclkcorcnt_out ,
3545  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3546  gt8_rxusrclk_in => gt8_rxusrclk_in,
3547  gt8_rxusrclk2_in => gt8_rxusrclk2_in,
3548  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3549  gt8_rxdata_out => gt8_rxdata_out,
3550  ------------------- Receive Ports - Pattern Checker Ports ------------------
3551  gt8_rxprbserr_out => gt8_rxprbserr_out,
3552  gt8_rxprbssel_in => gt8_rxprbssel_in,
3553  ------------------- Receive Ports - Pattern Checker ports ------------------
3554  gt8_rxprbscntreset_in => gt8_rxprbscntreset_in ,
3555  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3556  gt8_rxdisperr_out => gt8_rxdisperr_out,
3557  gt8_rxnotintable_out => gt8_rxnotintable_out ,
3558  --------------------------- Receive Ports - RX AFE -------------------------
3559  gt8_gtxrxp_in => gt8_gtxrxp_in,
3560  ------------------------ Receive Ports - RX AFE Ports ----------------------
3561  gt8_gtxrxn_in => gt8_gtxrxn_in,
3562  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3563  gt8_rxbufstatus_out => gt8_rxbufstatus_out ,
3564  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3565  gt8_rxmcommaalignen_in => gt8_rxmcommaalignen_in ,
3566  gt8_rxpcommaalignen_in => gt8_rxpcommaalignen_in ,
3567  --------------------- Receive Ports - RX Equalizer Ports -------------------
3568  gt8_rxdfeagchold_in => gt8_rxdfeagchold_i,
3569  gt8_rxdfelfhold_in => gt8_rxdfelfhold_i,
3570  gt8_rxdfelpmreset_in => gt8_rxdfelpmreset_in ,
3571  gt8_rxmonitorout_out => gt8_rxmonitorout_out ,
3572  gt8_rxmonitorsel_in => gt8_rxmonitorsel_in ,
3573  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3574  gt8_rxoutclk_out => gt8_rxoutclk_out,
3575  gt8_rxoutclkfabric_out => gt8_rxoutclkfabric_out ,
3576  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3577  gt8_gtrxreset_in => gt8_gtrxreset_i,
3578  gt8_rxpmareset_in => gt8_rxpmareset_in,
3579  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3580  gt8_rxchariscomma_out => gt8_rxchariscomma_out ,
3581  gt8_rxcharisk_out => gt8_rxcharisk_out,
3582  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3583  gt8_rxresetdone_out => gt8_rxresetdone_i,
3584  --------------------- TX Initialization and Reset Ports --------------------
3585  gt8_gttxreset_in => gt8_gttxreset_i,
3586  gt8_txuserrdy_in => gt8_txuserrdy_i,
3587  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3588  gt8_txusrclk_in => gt8_txusrclk_in,
3589  gt8_txusrclk2_in => gt8_txusrclk2_in,
3590  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3591  gt8_txdiffctrl_in => gt8_txdiffctrl_in,
3592  ------------------ Transmit Ports - TX Data Path interface -----------------
3593  gt8_txdata_in => gt8_txdata_in,
3594  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3595  gt8_gtxtxn_out => gt8_gtxtxn_out,
3596  gt8_gtxtxp_out => gt8_gtxtxp_out,
3597  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3598  gt8_txoutclk_out => gt8_txoutclk_i,
3599  gt8_txoutclkfabric_out => gt8_txoutclkfabric_out ,
3600  gt8_txoutclkpcs_out => gt8_txoutclkpcs_out ,
3601  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3602  gt8_txcharisk_in => gt8_txcharisk_in,
3603  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3604  gt8_txresetdone_out => gt8_txresetdone_i,
3605  ------------------ Transmit Ports - pattern Generator Ports ----------------
3606  gt8_txprbssel_in => gt8_txprbssel_in,
3607 
3608 
3609  --_____________________________________________________________________
3610  --_____________________________________________________________________
3611  --GT9 (X1Y9)
3612 
3613  ---------------------------- Channel - DRP Ports --------------------------
3614  gt9_drpaddr_in => gt9_drpaddr_in,
3615  gt9_drpclk_in => gt9_drpclk_in,
3616  gt9_drpdi_in => gt9_drpdi_in,
3617  gt9_drpdo_out => gt9_drpdo_out,
3618  gt9_drpen_in => gt9_drpen_in,
3619  gt9_drprdy_out => gt9_drprdy_out,
3620  gt9_drpwe_in => gt9_drpwe_in,
3621  --------------------------- Digital Monitor Ports --------------------------
3622  gt9_dmonitorout_out => gt9_dmonitorout_out ,
3623  ------------------------------- Loopback Ports -----------------------------
3624  gt9_loopback_in => gt9_loopback_in,
3625  ------------------------------ Power-Down Ports ----------------------------
3626  gt9_rxpd_in => gt9_rxpd_in,
3627  gt9_txpd_in => gt9_txpd_in,
3628  --------------------- RX Initialization and Reset Ports --------------------
3629  gt9_eyescanreset_in => gt9_eyescanreset_in ,
3630  gt9_rxuserrdy_in => gt9_rxuserrdy_i,
3631  -------------------------- RX Margin Analysis Ports ------------------------
3632  gt9_eyescandataerror_out => gt9_eyescandataerror_out,
3633  gt9_eyescantrigger_in => gt9_eyescantrigger_in ,
3634  ------------------- Receive Ports - Clock Correction Ports -----------------
3635  gt9_rxclkcorcnt_out => gt9_rxclkcorcnt_out ,
3636  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3637  gt9_rxusrclk_in => gt9_rxusrclk_in,
3638  gt9_rxusrclk2_in => gt9_rxusrclk2_in,
3639  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3640  gt9_rxdata_out => gt9_rxdata_out,
3641  ------------------- Receive Ports - Pattern Checker Ports ------------------
3642  gt9_rxprbserr_out => gt9_rxprbserr_out,
3643  gt9_rxprbssel_in => gt9_rxprbssel_in,
3644  ------------------- Receive Ports - Pattern Checker ports ------------------
3645  gt9_rxprbscntreset_in => gt9_rxprbscntreset_in ,
3646  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3647  gt9_rxdisperr_out => gt9_rxdisperr_out,
3648  gt9_rxnotintable_out => gt9_rxnotintable_out ,
3649  --------------------------- Receive Ports - RX AFE -------------------------
3650  gt9_gtxrxp_in => gt9_gtxrxp_in,
3651  ------------------------ Receive Ports - RX AFE Ports ----------------------
3652  gt9_gtxrxn_in => gt9_gtxrxn_in,
3653  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3654  gt9_rxbufstatus_out => gt9_rxbufstatus_out ,
3655  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3656  gt9_rxmcommaalignen_in => gt9_rxmcommaalignen_in ,
3657  gt9_rxpcommaalignen_in => gt9_rxpcommaalignen_in ,
3658  --------------------- Receive Ports - RX Equalizer Ports -------------------
3659  gt9_rxdfeagchold_in => gt9_rxdfeagchold_i,
3660  gt9_rxdfelfhold_in => gt9_rxdfelfhold_i,
3661  gt9_rxdfelpmreset_in => gt9_rxdfelpmreset_in ,
3662  gt9_rxmonitorout_out => gt9_rxmonitorout_out ,
3663  gt9_rxmonitorsel_in => gt9_rxmonitorsel_in ,
3664  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3665  gt9_rxoutclk_out => gt9_rxoutclk_out,
3666  gt9_rxoutclkfabric_out => gt9_rxoutclkfabric_out ,
3667  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3668  gt9_gtrxreset_in => gt9_gtrxreset_i,
3669  gt9_rxpmareset_in => gt9_rxpmareset_in,
3670  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3671  gt9_rxchariscomma_out => gt9_rxchariscomma_out ,
3672  gt9_rxcharisk_out => gt9_rxcharisk_out,
3673  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3674  gt9_rxresetdone_out => gt9_rxresetdone_i,
3675  --------------------- TX Initialization and Reset Ports --------------------
3676  gt9_gttxreset_in => gt9_gttxreset_i,
3677  gt9_txuserrdy_in => gt9_txuserrdy_i,
3678  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3679  gt9_txusrclk_in => gt9_txusrclk_in,
3680  gt9_txusrclk2_in => gt9_txusrclk2_in,
3681  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3682  gt9_txdiffctrl_in => gt9_txdiffctrl_in,
3683  ------------------ Transmit Ports - TX Data Path interface -----------------
3684  gt9_txdata_in => gt9_txdata_in,
3685  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3686  gt9_gtxtxn_out => gt9_gtxtxn_out,
3687  gt9_gtxtxp_out => gt9_gtxtxp_out,
3688  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3689  gt9_txoutclk_out => gt9_txoutclk_i,
3690  gt9_txoutclkfabric_out => gt9_txoutclkfabric_out ,
3691  gt9_txoutclkpcs_out => gt9_txoutclkpcs_out ,
3692  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3693  gt9_txcharisk_in => gt9_txcharisk_in,
3694  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3695  gt9_txresetdone_out => gt9_txresetdone_i,
3696  ------------------ Transmit Ports - pattern Generator Ports ----------------
3697  gt9_txprbssel_in => gt9_txprbssel_in,
3698 
3699 
3700  --_____________________________________________________________________
3701  --_____________________________________________________________________
3702  --GT10 (X1Y10)
3703 
3704  ---------------------------- Channel - DRP Ports --------------------------
3705  gt10_drpaddr_in => gt10_drpaddr_in,
3706  gt10_drpclk_in => gt10_drpclk_in,
3707  gt10_drpdi_in => gt10_drpdi_in,
3708  gt10_drpdo_out => gt10_drpdo_out,
3709  gt10_drpen_in => gt10_drpen_in,
3710  gt10_drprdy_out => gt10_drprdy_out,
3711  gt10_drpwe_in => gt10_drpwe_in,
3712  --------------------------- Digital Monitor Ports --------------------------
3713  gt10_dmonitorout_out => gt10_dmonitorout_out ,
3714  ------------------------------- Loopback Ports -----------------------------
3715  gt10_loopback_in => gt10_loopback_in,
3716  ------------------------------ Power-Down Ports ----------------------------
3717  gt10_rxpd_in => gt10_rxpd_in,
3718  gt10_txpd_in => gt10_txpd_in,
3719  --------------------- RX Initialization and Reset Ports --------------------
3720  gt10_eyescanreset_in => gt10_eyescanreset_in ,
3721  gt10_rxuserrdy_in => gt10_rxuserrdy_i,
3722  -------------------------- RX Margin Analysis Ports ------------------------
3723  gt10_eyescandataerror_out => gt10_eyescandataerror_out,
3724  gt10_eyescantrigger_in => gt10_eyescantrigger_in ,
3725  ------------------- Receive Ports - Clock Correction Ports -----------------
3726  gt10_rxclkcorcnt_out => gt10_rxclkcorcnt_out ,
3727  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3728  gt10_rxusrclk_in => gt10_rxusrclk_in,
3729  gt10_rxusrclk2_in => gt10_rxusrclk2_in,
3730  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3731  gt10_rxdata_out => gt10_rxdata_out,
3732  ------------------- Receive Ports - Pattern Checker Ports ------------------
3733  gt10_rxprbserr_out => gt10_rxprbserr_out,
3734  gt10_rxprbssel_in => gt10_rxprbssel_in,
3735  ------------------- Receive Ports - Pattern Checker ports ------------------
3736  gt10_rxprbscntreset_in => gt10_rxprbscntreset_in ,
3737  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3738  gt10_rxdisperr_out => gt10_rxdisperr_out,
3739  gt10_rxnotintable_out => gt10_rxnotintable_out ,
3740  --------------------------- Receive Ports - RX AFE -------------------------
3741  gt10_gtxrxp_in => gt10_gtxrxp_in,
3742  ------------------------ Receive Ports - RX AFE Ports ----------------------
3743  gt10_gtxrxn_in => gt10_gtxrxn_in,
3744  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3745  gt10_rxbufstatus_out => gt10_rxbufstatus_out ,
3746  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3747  gt10_rxmcommaalignen_in => gt10_rxmcommaalignen_in ,
3748  gt10_rxpcommaalignen_in => gt10_rxpcommaalignen_in ,
3749  --------------------- Receive Ports - RX Equalizer Ports -------------------
3750  gt10_rxdfeagchold_in => gt10_rxdfeagchold_i ,
3751  gt10_rxdfelfhold_in => gt10_rxdfelfhold_i,
3752  gt10_rxdfelpmreset_in => gt10_rxdfelpmreset_in ,
3753  gt10_rxmonitorout_out => gt10_rxmonitorout_out ,
3754  gt10_rxmonitorsel_in => gt10_rxmonitorsel_in ,
3755  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3756  gt10_rxoutclk_out => gt10_rxoutclk_out,
3757  gt10_rxoutclkfabric_out => gt10_rxoutclkfabric_out ,
3758  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3759  gt10_gtrxreset_in => gt10_gtrxreset_i,
3760  gt10_rxpmareset_in => gt10_rxpmareset_in,
3761  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3762  gt10_rxchariscomma_out => gt10_rxchariscomma_out ,
3763  gt10_rxcharisk_out => gt10_rxcharisk_out,
3764  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3765  gt10_rxresetdone_out => gt10_rxresetdone_i,
3766  --------------------- TX Initialization and Reset Ports --------------------
3767  gt10_gttxreset_in => gt10_gttxreset_i,
3768  gt10_txuserrdy_in => gt10_txuserrdy_i,
3769  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3770  gt10_txusrclk_in => gt10_txusrclk_in,
3771  gt10_txusrclk2_in => gt10_txusrclk2_in,
3772  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3773  gt10_txdiffctrl_in => gt10_txdiffctrl_in,
3774  ------------------ Transmit Ports - TX Data Path interface -----------------
3775  gt10_txdata_in => gt10_txdata_in,
3776  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3777  gt10_gtxtxn_out => gt10_gtxtxn_out,
3778  gt10_gtxtxp_out => gt10_gtxtxp_out,
3779  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3780  gt10_txoutclk_out => gt10_txoutclk_i,
3781  gt10_txoutclkfabric_out => gt10_txoutclkfabric_out ,
3782  gt10_txoutclkpcs_out => gt10_txoutclkpcs_out ,
3783  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3784  gt10_txcharisk_in => gt10_txcharisk_in,
3785  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3786  gt10_txresetdone_out => gt10_txresetdone_i,
3787  ------------------ Transmit Ports - pattern Generator Ports ----------------
3788  gt10_txprbssel_in => gt10_txprbssel_in,
3789 
3790 
3791  --_____________________________________________________________________
3792  --_____________________________________________________________________
3793  --GT11 (X1Y11)
3794 
3795  ---------------------------- Channel - DRP Ports --------------------------
3796  gt11_drpaddr_in => gt11_drpaddr_in,
3797  gt11_drpclk_in => gt11_drpclk_in,
3798  gt11_drpdi_in => gt11_drpdi_in,
3799  gt11_drpdo_out => gt11_drpdo_out,
3800  gt11_drpen_in => gt11_drpen_in,
3801  gt11_drprdy_out => gt11_drprdy_out,
3802  gt11_drpwe_in => gt11_drpwe_in,
3803  --------------------------- Digital Monitor Ports --------------------------
3804  gt11_dmonitorout_out => gt11_dmonitorout_out ,
3805  ------------------------------- Loopback Ports -----------------------------
3806  gt11_loopback_in => gt11_loopback_in,
3807  ------------------------------ Power-Down Ports ----------------------------
3808  gt11_rxpd_in => gt11_rxpd_in,
3809  gt11_txpd_in => gt11_txpd_in,
3810  --------------------- RX Initialization and Reset Ports --------------------
3811  gt11_eyescanreset_in => gt11_eyescanreset_in ,
3812  gt11_rxuserrdy_in => gt11_rxuserrdy_i,
3813  -------------------------- RX Margin Analysis Ports ------------------------
3814  gt11_eyescandataerror_out => gt11_eyescandataerror_out,
3815  gt11_eyescantrigger_in => gt11_eyescantrigger_in ,
3816  ------------------- Receive Ports - Clock Correction Ports -----------------
3817  gt11_rxclkcorcnt_out => gt11_rxclkcorcnt_out ,
3818  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
3819  gt11_rxusrclk_in => gt11_rxusrclk_in,
3820  gt11_rxusrclk2_in => gt11_rxusrclk2_in,
3821  ------------------ Receive Ports - FPGA RX interface Ports -----------------
3822  gt11_rxdata_out => gt11_rxdata_out,
3823  ------------------- Receive Ports - Pattern Checker Ports ------------------
3824  gt11_rxprbserr_out => gt11_rxprbserr_out,
3825  gt11_rxprbssel_in => gt11_rxprbssel_in,
3826  ------------------- Receive Ports - Pattern Checker ports ------------------
3827  gt11_rxprbscntreset_in => gt11_rxprbscntreset_in ,
3828  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
3829  gt11_rxdisperr_out => gt11_rxdisperr_out,
3830  gt11_rxnotintable_out => gt11_rxnotintable_out ,
3831  --------------------------- Receive Ports - RX AFE -------------------------
3832  gt11_gtxrxp_in => gt11_gtxrxp_in,
3833  ------------------------ Receive Ports - RX AFE Ports ----------------------
3834  gt11_gtxrxn_in => gt11_gtxrxn_in,
3835  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
3836  gt11_rxbufstatus_out => gt11_rxbufstatus_out ,
3837  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
3838  gt11_rxmcommaalignen_in => gt11_rxmcommaalignen_in ,
3839  gt11_rxpcommaalignen_in => gt11_rxpcommaalignen_in ,
3840  --------------------- Receive Ports - RX Equalizer Ports -------------------
3841  gt11_rxdfeagchold_in => gt11_rxdfeagchold_i ,
3842  gt11_rxdfelfhold_in => gt11_rxdfelfhold_i,
3843  gt11_rxdfelpmreset_in => gt11_rxdfelpmreset_in ,
3844  gt11_rxmonitorout_out => gt11_rxmonitorout_out ,
3845  gt11_rxmonitorsel_in => gt11_rxmonitorsel_in ,
3846  --------------- Receive Ports - RX Fabric Output Control Ports -------------
3847  gt11_rxoutclk_out => gt11_rxoutclk_out,
3848  gt11_rxoutclkfabric_out => gt11_rxoutclkfabric_out ,
3849  ------------- Receive Ports - RX Initialization and Reset Ports ------------
3850  gt11_gtrxreset_in => gt11_gtrxreset_i,
3851  gt11_rxpmareset_in => gt11_rxpmareset_in,
3852  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
3853  gt11_rxchariscomma_out => gt11_rxchariscomma_out ,
3854  gt11_rxcharisk_out => gt11_rxcharisk_out,
3855  -------------- Receive Ports -RX Initialization and Reset Ports ------------
3856  gt11_rxresetdone_out => gt11_rxresetdone_i,
3857  --------------------- TX Initialization and Reset Ports --------------------
3858  gt11_gttxreset_in => gt11_gttxreset_i,
3859  gt11_txuserrdy_in => gt11_txuserrdy_i,
3860  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
3861  gt11_txusrclk_in => gt11_txusrclk_in,
3862  gt11_txusrclk2_in => gt11_txusrclk2_in,
3863  --------------- Transmit Ports - TX Configurable Driver Ports --------------
3864  gt11_txdiffctrl_in => gt11_txdiffctrl_in,
3865  ------------------ Transmit Ports - TX Data Path interface -----------------
3866  gt11_txdata_in => gt11_txdata_in,
3867  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
3868  gt11_gtxtxn_out => gt11_gtxtxn_out,
3869  gt11_gtxtxp_out => gt11_gtxtxp_out,
3870  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
3871  gt11_txoutclk_out => gt11_txoutclk_i,
3872  gt11_txoutclkfabric_out => gt11_txoutclkfabric_out ,
3873  gt11_txoutclkpcs_out => gt11_txoutclkpcs_out ,
3874  --------------------- Transmit Ports - TX Gearbox Ports --------------------
3875  gt11_txcharisk_in => gt11_txcharisk_in,
3876  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
3877  gt11_txresetdone_out => gt11_txresetdone_i,
3878  ------------------ Transmit Ports - pattern Generator Ports ----------------
3879  gt11_txprbssel_in => gt11_txprbssel_in,
3880 
3881 
3882 
3883 
3884  --____________________________COMMON PORTS________________________________
3885  gt0_qplloutclk_in => gt0_qplloutclk_in,
3886  gt0_qplloutrefclk_in => gt0_qplloutrefclk_in ,
3887 
3888  --____________________________COMMON PORTS________________________________
3889  gt1_qplloutclk_in => gt1_qplloutclk_in,
3890  gt1_qplloutrefclk_in => gt1_qplloutrefclk_in ,
3891 
3892  --____________________________COMMON PORTS________________________________
3893  gt2_qplloutclk_in => gt2_qplloutclk_in,
3894  gt2_qplloutrefclk_in => gt2_qplloutrefclk_in
3895  );
3896 
3897 
3898 gt0_rxdfelpmreset_i <= tied_to_ground_i;
3899 gt1_rxdfelpmreset_i <= tied_to_ground_i;
3900 gt2_rxdfelpmreset_i <= tied_to_ground_i;
3901 gt3_rxdfelpmreset_i <= tied_to_ground_i;
3902 gt4_rxdfelpmreset_i <= tied_to_ground_i;
3903 gt5_rxdfelpmreset_i <= tied_to_ground_i;
3904 gt6_rxdfelpmreset_i <= tied_to_ground_i;
3905 gt7_rxdfelpmreset_i <= tied_to_ground_i;
3906 gt8_rxdfelpmreset_i <= tied_to_ground_i;
3907 gt9_rxdfelpmreset_i <= tied_to_ground_i;
3908 gt10_rxdfelpmreset_i <= tied_to_ground_i;
3909 gt11_rxdfelpmreset_i <= tied_to_ground_i;
3910 
3911 
3912 GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
3913 GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
3914 GT0_TXOUTCLK_OUT <= gt0_txoutclk_i;
3915 GT1_TXRESETDONE_OUT <= gt1_txresetdone_i;
3916 GT1_RXRESETDONE_OUT <= gt1_rxresetdone_i;
3917 GT1_TXOUTCLK_OUT <= gt1_txoutclk_i;
3918 GT2_TXRESETDONE_OUT <= gt2_txresetdone_i;
3919 GT2_RXRESETDONE_OUT <= gt2_rxresetdone_i;
3920 GT2_TXOUTCLK_OUT <= gt2_txoutclk_i;
3921 GT3_TXRESETDONE_OUT <= gt3_txresetdone_i;
3922 GT3_RXRESETDONE_OUT <= gt3_rxresetdone_i;
3923 GT3_TXOUTCLK_OUT <= gt3_txoutclk_i;
3924 GT4_TXRESETDONE_OUT <= gt4_txresetdone_i;
3925 GT4_RXRESETDONE_OUT <= gt4_rxresetdone_i;
3926 GT4_TXOUTCLK_OUT <= gt4_txoutclk_i;
3927 GT5_TXRESETDONE_OUT <= gt5_txresetdone_i;
3928 GT5_RXRESETDONE_OUT <= gt5_rxresetdone_i;
3929 GT5_TXOUTCLK_OUT <= gt5_txoutclk_i;
3930 GT6_TXRESETDONE_OUT <= gt6_txresetdone_i;
3931 GT6_RXRESETDONE_OUT <= gt6_rxresetdone_i;
3932 GT6_TXOUTCLK_OUT <= gt6_txoutclk_i;
3933 GT7_TXRESETDONE_OUT <= gt7_txresetdone_i;
3934 GT7_RXRESETDONE_OUT <= gt7_rxresetdone_i;
3935 GT7_TXOUTCLK_OUT <= gt7_txoutclk_i;
3936 GT8_TXRESETDONE_OUT <= gt8_txresetdone_i;
3937 GT8_RXRESETDONE_OUT <= gt8_rxresetdone_i;
3938 GT8_TXOUTCLK_OUT <= gt8_txoutclk_i;
3939 GT9_TXRESETDONE_OUT <= gt9_txresetdone_i;
3940 GT9_RXRESETDONE_OUT <= gt9_rxresetdone_i;
3941 GT9_TXOUTCLK_OUT <= gt9_txoutclk_i;
3942 GT10_TXRESETDONE_OUT <= gt10_txresetdone_i;
3943 GT10_RXRESETDONE_OUT <= gt10_rxresetdone_i;
3944 GT10_TXOUTCLK_OUT <= gt10_txoutclk_i;
3945 GT11_TXRESETDONE_OUT <= gt11_txresetdone_i;
3946 GT11_RXRESETDONE_OUT <= gt11_rxresetdone_i;
3947 GT11_TXOUTCLK_OUT <= gt11_txoutclk_i;
3948  GT0_QPLLRESET_OUT <= gt0_qpllreset_t;
3949  GT1_QPLLRESET_OUT <= gt1_qpllreset_t;
3950  GT2_QPLLRESET_OUT <= gt2_qpllreset_t;
3951 
3952 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
3953  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
3954  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
3955  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
3956  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
3957  gt1_gttxreset_i <= GT1_GTTXRESET_IN or gt1_gttxreset_t;
3958  gt1_gtrxreset_i <= GT1_GTRXRESET_IN or gt1_gtrxreset_t;
3959  gt1_txuserrdy_i <= GT1_TXUSERRDY_IN or gt1_txuserrdy_t;
3960  gt1_rxuserrdy_i <= GT1_RXUSERRDY_IN or gt1_rxuserrdy_t;
3961  gt2_gttxreset_i <= GT2_GTTXRESET_IN or gt2_gttxreset_t;
3962  gt2_gtrxreset_i <= GT2_GTRXRESET_IN or gt2_gtrxreset_t;
3963  gt2_txuserrdy_i <= GT2_TXUSERRDY_IN or gt2_txuserrdy_t;
3964  gt2_rxuserrdy_i <= GT2_RXUSERRDY_IN or gt2_rxuserrdy_t;
3965  gt3_gttxreset_i <= GT3_GTTXRESET_IN or gt3_gttxreset_t;
3966  gt3_gtrxreset_i <= GT3_GTRXRESET_IN or gt3_gtrxreset_t;
3967  gt3_txuserrdy_i <= GT3_TXUSERRDY_IN or gt3_txuserrdy_t;
3968  gt3_rxuserrdy_i <= GT3_RXUSERRDY_IN or gt3_rxuserrdy_t;
3969  gt4_gttxreset_i <= GT4_GTTXRESET_IN or gt4_gttxreset_t;
3970  gt4_gtrxreset_i <= GT4_GTRXRESET_IN or gt4_gtrxreset_t;
3971  gt4_txuserrdy_i <= GT4_TXUSERRDY_IN or gt4_txuserrdy_t;
3972  gt4_rxuserrdy_i <= GT4_RXUSERRDY_IN or gt4_rxuserrdy_t;
3973  gt5_gttxreset_i <= GT5_GTTXRESET_IN or gt5_gttxreset_t;
3974  gt5_gtrxreset_i <= GT5_GTRXRESET_IN or gt5_gtrxreset_t;
3975  gt5_txuserrdy_i <= GT5_TXUSERRDY_IN or gt5_txuserrdy_t;
3976  gt5_rxuserrdy_i <= GT5_RXUSERRDY_IN or gt5_rxuserrdy_t;
3977  gt6_gttxreset_i <= GT6_GTTXRESET_IN or gt6_gttxreset_t;
3978  gt6_gtrxreset_i <= GT6_GTRXRESET_IN or gt6_gtrxreset_t;
3979  gt6_txuserrdy_i <= GT6_TXUSERRDY_IN or gt6_txuserrdy_t;
3980  gt6_rxuserrdy_i <= GT6_RXUSERRDY_IN or gt6_rxuserrdy_t;
3981  gt7_gttxreset_i <= GT7_GTTXRESET_IN or gt7_gttxreset_t;
3982  gt7_gtrxreset_i <= GT7_GTRXRESET_IN or gt7_gtrxreset_t;
3983  gt7_txuserrdy_i <= GT7_TXUSERRDY_IN or gt7_txuserrdy_t;
3984  gt7_rxuserrdy_i <= GT7_RXUSERRDY_IN or gt7_rxuserrdy_t;
3985  gt8_gttxreset_i <= GT8_GTTXRESET_IN or gt8_gttxreset_t;
3986  gt8_gtrxreset_i <= GT8_GTRXRESET_IN or gt8_gtrxreset_t;
3987  gt8_txuserrdy_i <= GT8_TXUSERRDY_IN or gt8_txuserrdy_t;
3988  gt8_rxuserrdy_i <= GT8_RXUSERRDY_IN or gt8_rxuserrdy_t;
3989  gt9_gttxreset_i <= GT9_GTTXRESET_IN or gt9_gttxreset_t;
3990  gt9_gtrxreset_i <= GT9_GTRXRESET_IN or gt9_gtrxreset_t;
3991  gt9_txuserrdy_i <= GT9_TXUSERRDY_IN or gt9_txuserrdy_t;
3992  gt9_rxuserrdy_i <= GT9_RXUSERRDY_IN or gt9_rxuserrdy_t;
3993  gt10_gttxreset_i <= GT10_GTTXRESET_IN or gt10_gttxreset_t;
3994  gt10_gtrxreset_i <= GT10_GTRXRESET_IN or gt10_gtrxreset_t;
3995  gt10_txuserrdy_i <= GT10_TXUSERRDY_IN or gt10_txuserrdy_t;
3996  gt10_rxuserrdy_i <= GT10_RXUSERRDY_IN or gt10_rxuserrdy_t;
3997  gt11_gttxreset_i <= GT11_GTTXRESET_IN or gt11_gttxreset_t;
3998  gt11_gtrxreset_i <= GT11_GTRXRESET_IN or gt11_gtrxreset_t;
3999  gt11_txuserrdy_i <= GT11_TXUSERRDY_IN or gt11_txuserrdy_t;
4000  gt11_rxuserrdy_i <= GT11_RXUSERRDY_IN or gt11_rxuserrdy_t;
4001 end generate chipscope;
4002 
4003 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
4004 gt0_gttxreset_i <= gt0_gttxreset_t;
4005 gt0_gtrxreset_i <= gt0_gtrxreset_t;
4006 gt0_txuserrdy_i <= gt0_txuserrdy_t;
4007 gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
4008 gt1_gttxreset_i <= gt1_gttxreset_t;
4009 gt1_gtrxreset_i <= gt1_gtrxreset_t;
4010 gt1_txuserrdy_i <= gt1_txuserrdy_t;
4011 gt1_rxuserrdy_i <= gt1_rxuserrdy_t;
4012 gt2_gttxreset_i <= gt2_gttxreset_t;
4013 gt2_gtrxreset_i <= gt2_gtrxreset_t;
4014 gt2_txuserrdy_i <= gt2_txuserrdy_t;
4015 gt2_rxuserrdy_i <= gt2_rxuserrdy_t;
4016 gt3_gttxreset_i <= gt3_gttxreset_t;
4017 gt3_gtrxreset_i <= gt3_gtrxreset_t;
4018 gt3_txuserrdy_i <= gt3_txuserrdy_t;
4019 gt3_rxuserrdy_i <= gt3_rxuserrdy_t;
4020 gt4_gttxreset_i <= gt4_gttxreset_t;
4021 gt4_gtrxreset_i <= gt4_gtrxreset_t;
4022 gt4_txuserrdy_i <= gt4_txuserrdy_t;
4023 gt4_rxuserrdy_i <= gt4_rxuserrdy_t;
4024 gt5_gttxreset_i <= gt5_gttxreset_t;
4025 gt5_gtrxreset_i <= gt5_gtrxreset_t;
4026 gt5_txuserrdy_i <= gt5_txuserrdy_t;
4027 gt5_rxuserrdy_i <= gt5_rxuserrdy_t;
4028 gt6_gttxreset_i <= gt6_gttxreset_t;
4029 gt6_gtrxreset_i <= gt6_gtrxreset_t;
4030 gt6_txuserrdy_i <= gt6_txuserrdy_t;
4031 gt6_rxuserrdy_i <= gt6_rxuserrdy_t;
4032 gt7_gttxreset_i <= gt7_gttxreset_t;
4033 gt7_gtrxreset_i <= gt7_gtrxreset_t;
4034 gt7_txuserrdy_i <= gt7_txuserrdy_t;
4035 gt7_rxuserrdy_i <= gt7_rxuserrdy_t;
4036 gt8_gttxreset_i <= gt8_gttxreset_t;
4037 gt8_gtrxreset_i <= gt8_gtrxreset_t;
4038 gt8_txuserrdy_i <= gt8_txuserrdy_t;
4039 gt8_rxuserrdy_i <= gt8_rxuserrdy_t;
4040 gt9_gttxreset_i <= gt9_gttxreset_t;
4041 gt9_gtrxreset_i <= gt9_gtrxreset_t;
4042 gt9_txuserrdy_i <= gt9_txuserrdy_t;
4043 gt9_rxuserrdy_i <= gt9_rxuserrdy_t;
4044 gt10_gttxreset_i <= gt10_gttxreset_t;
4045 gt10_gtrxreset_i <= gt10_gtrxreset_t;
4046 gt10_txuserrdy_i <= gt10_txuserrdy_t;
4047 gt10_rxuserrdy_i <= gt10_rxuserrdy_t;
4048 gt11_gttxreset_i <= gt11_gttxreset_t;
4049 gt11_gtrxreset_i <= gt11_gtrxreset_t;
4050 gt11_txuserrdy_i <= gt11_txuserrdy_t;
4051 gt11_rxuserrdy_i <= gt11_rxuserrdy_t;
4052 end generate no_chipscope;
4053 
4054 
4055 gt0_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4056 
4057  generic map(
4058  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4059  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4060  RETRY_COUNTER_BITWIDTH => 8,
4061  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4062  RX_QPLL_USED => TRUE, -- share these two generic values
4063  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4064  -- is enough. For single-lane applications the automatic alignment is
4065  -- sufficient
4066  )
4067  port map (
4068  STABLE_CLOCK => SYSCLK_IN,
4069  TXUSERCLK => GT0_TXUSRCLK_IN,
4070  SOFT_RESET => SOFT_RESET_IN,
4071  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4072  CPLLREFCLKLOST => tied_to_ground_i,
4073  QPLLLOCK => GT0_QPLLLOCK_IN,
4074  CPLLLOCK => tied_to_vcc_i,
4075  TXRESETDONE => gt0_txresetdone_i,
4076  MMCM_LOCK => tied_to_vcc_i,
4077  GTTXRESET => gt0_gttxreset_t,
4078  MMCM_RESET => open,
4079  QPLL_RESET => gt0_qpllreset_t,
4080  CPLL_RESET => open,
4081  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
4082  TXUSERRDY => gt0_txuserrdy_t,
4083  RUN_PHALIGNMENT => open,
4084  RESET_PHALIGNMENT => open,
4085  PHALIGNMENT_DONE => tied_to_vcc_i,
4086  RETRY_COUNTER => open
4087  );
4088 
4089 gt1_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4090 
4091  generic map(
4092  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4093  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4094  RETRY_COUNTER_BITWIDTH => 8,
4095  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4096  RX_QPLL_USED => TRUE, -- share these two generic values
4097  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4098  -- is enough. For single-lane applications the automatic alignment is
4099  -- sufficient
4100  )
4101  port map (
4102  STABLE_CLOCK => SYSCLK_IN,
4103  TXUSERCLK => GT1_TXUSRCLK_IN,
4104  SOFT_RESET => SOFT_RESET_IN,
4105  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4106  CPLLREFCLKLOST => tied_to_ground_i,
4107  QPLLLOCK => GT0_QPLLLOCK_IN,
4108  CPLLLOCK => tied_to_vcc_i,
4109  TXRESETDONE => gt1_txresetdone_i,
4110  MMCM_LOCK => tied_to_vcc_i,
4111  GTTXRESET => gt1_gttxreset_t,
4112  MMCM_RESET => open,
4113  QPLL_RESET => open,
4114  CPLL_RESET => open,
4115  TX_FSM_RESET_DONE => GT1_TX_FSM_RESET_DONE_OUT,
4116  TXUSERRDY => gt1_txuserrdy_t,
4117  RUN_PHALIGNMENT => open,
4118  RESET_PHALIGNMENT => open,
4119  PHALIGNMENT_DONE => tied_to_vcc_i,
4120  RETRY_COUNTER => open
4121  );
4122 
4123 gt2_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4124 
4125  generic map(
4126  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4127  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4128  RETRY_COUNTER_BITWIDTH => 8,
4129  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4130  RX_QPLL_USED => TRUE, -- share these two generic values
4131  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4132  -- is enough. For single-lane applications the automatic alignment is
4133  -- sufficient
4134  )
4135  port map (
4136  STABLE_CLOCK => SYSCLK_IN,
4137  TXUSERCLK => GT2_TXUSRCLK_IN,
4138  SOFT_RESET => SOFT_RESET_IN,
4139  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4140  CPLLREFCLKLOST => tied_to_ground_i,
4141  QPLLLOCK => GT0_QPLLLOCK_IN,
4142  CPLLLOCK => tied_to_vcc_i,
4143  TXRESETDONE => gt2_txresetdone_i,
4144  MMCM_LOCK => tied_to_vcc_i,
4145  GTTXRESET => gt2_gttxreset_t,
4146  MMCM_RESET => open,
4147  QPLL_RESET => open,
4148  CPLL_RESET => open,
4149  TX_FSM_RESET_DONE => GT2_TX_FSM_RESET_DONE_OUT,
4150  TXUSERRDY => gt2_txuserrdy_t,
4151  RUN_PHALIGNMENT => open,
4152  RESET_PHALIGNMENT => open,
4153  PHALIGNMENT_DONE => tied_to_vcc_i,
4154  RETRY_COUNTER => open
4155  );
4156 
4157 gt3_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4158 
4159  generic map(
4160  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4161  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4162  RETRY_COUNTER_BITWIDTH => 8,
4163  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4164  RX_QPLL_USED => TRUE, -- share these two generic values
4165  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4166  -- is enough. For single-lane applications the automatic alignment is
4167  -- sufficient
4168  )
4169  port map (
4170  STABLE_CLOCK => SYSCLK_IN,
4171  TXUSERCLK => GT3_TXUSRCLK_IN,
4172  SOFT_RESET => SOFT_RESET_IN,
4173  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4174  CPLLREFCLKLOST => tied_to_ground_i,
4175  QPLLLOCK => GT0_QPLLLOCK_IN,
4176  CPLLLOCK => tied_to_vcc_i,
4177  TXRESETDONE => gt3_txresetdone_i,
4178  MMCM_LOCK => tied_to_vcc_i,
4179  GTTXRESET => gt3_gttxreset_t,
4180  MMCM_RESET => open,
4181  QPLL_RESET => open,
4182  CPLL_RESET => open,
4183  TX_FSM_RESET_DONE => GT3_TX_FSM_RESET_DONE_OUT,
4184  TXUSERRDY => gt3_txuserrdy_t,
4185  RUN_PHALIGNMENT => open,
4186  RESET_PHALIGNMENT => open,
4187  PHALIGNMENT_DONE => tied_to_vcc_i,
4188  RETRY_COUNTER => open
4189  );
4190 
4191 gt4_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4192 
4193  generic map(
4194  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4195  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4196  RETRY_COUNTER_BITWIDTH => 8,
4197  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4198  RX_QPLL_USED => TRUE, -- share these two generic values
4199  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4200  -- is enough. For single-lane applications the automatic alignment is
4201  -- sufficient
4202  )
4203  port map (
4204  STABLE_CLOCK => SYSCLK_IN,
4205  TXUSERCLK => GT4_TXUSRCLK_IN,
4206  SOFT_RESET => SOFT_RESET_IN,
4207  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4208  CPLLREFCLKLOST => tied_to_ground_i,
4209  QPLLLOCK => GT1_QPLLLOCK_IN,
4210  CPLLLOCK => tied_to_vcc_i,
4211  TXRESETDONE => gt4_txresetdone_i,
4212  MMCM_LOCK => tied_to_vcc_i,
4213  GTTXRESET => gt4_gttxreset_t,
4214  MMCM_RESET => open,
4215  QPLL_RESET => gt1_qpllreset_t,
4216  CPLL_RESET => open,
4217  TX_FSM_RESET_DONE => GT4_TX_FSM_RESET_DONE_OUT,
4218  TXUSERRDY => gt4_txuserrdy_t,
4219  RUN_PHALIGNMENT => open,
4220  RESET_PHALIGNMENT => open,
4221  PHALIGNMENT_DONE => tied_to_vcc_i,
4222  RETRY_COUNTER => open
4223  );
4224 
4225 gt5_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4226 
4227  generic map(
4228  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4229  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4230  RETRY_COUNTER_BITWIDTH => 8,
4231  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4232  RX_QPLL_USED => TRUE, -- share these two generic values
4233  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4234  -- is enough. For single-lane applications the automatic alignment is
4235  -- sufficient
4236  )
4237  port map (
4238  STABLE_CLOCK => SYSCLK_IN,
4239  TXUSERCLK => GT5_TXUSRCLK_IN,
4240  SOFT_RESET => SOFT_RESET_IN,
4241  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4242  CPLLREFCLKLOST => tied_to_ground_i,
4243  QPLLLOCK => GT1_QPLLLOCK_IN,
4244  CPLLLOCK => tied_to_vcc_i,
4245  TXRESETDONE => gt5_txresetdone_i,
4246  MMCM_LOCK => tied_to_vcc_i,
4247  GTTXRESET => gt5_gttxreset_t,
4248  MMCM_RESET => open,
4249  QPLL_RESET => open,
4250  CPLL_RESET => open,
4251  TX_FSM_RESET_DONE => GT5_TX_FSM_RESET_DONE_OUT,
4252  TXUSERRDY => gt5_txuserrdy_t,
4253  RUN_PHALIGNMENT => open,
4254  RESET_PHALIGNMENT => open,
4255  PHALIGNMENT_DONE => tied_to_vcc_i,
4256  RETRY_COUNTER => open
4257  );
4258 
4259 gt6_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4260 
4261  generic map(
4262  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4263  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4264  RETRY_COUNTER_BITWIDTH => 8,
4265  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4266  RX_QPLL_USED => TRUE, -- share these two generic values
4267  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4268  -- is enough. For single-lane applications the automatic alignment is
4269  -- sufficient
4270  )
4271  port map (
4272  STABLE_CLOCK => SYSCLK_IN,
4273  TXUSERCLK => GT6_TXUSRCLK_IN,
4274  SOFT_RESET => SOFT_RESET_IN,
4275  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4276  CPLLREFCLKLOST => tied_to_ground_i,
4277  QPLLLOCK => GT1_QPLLLOCK_IN,
4278  CPLLLOCK => tied_to_vcc_i,
4279  TXRESETDONE => gt6_txresetdone_i,
4280  MMCM_LOCK => tied_to_vcc_i,
4281  GTTXRESET => gt6_gttxreset_t,
4282  MMCM_RESET => open,
4283  QPLL_RESET => open,
4284  CPLL_RESET => open,
4285  TX_FSM_RESET_DONE => GT6_TX_FSM_RESET_DONE_OUT,
4286  TXUSERRDY => gt6_txuserrdy_t,
4287  RUN_PHALIGNMENT => open,
4288  RESET_PHALIGNMENT => open,
4289  PHALIGNMENT_DONE => tied_to_vcc_i,
4290  RETRY_COUNTER => open
4291  );
4292 
4293 gt7_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4294 
4295  generic map(
4296  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4297  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4298  RETRY_COUNTER_BITWIDTH => 8,
4299  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4300  RX_QPLL_USED => TRUE, -- share these two generic values
4301  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4302  -- is enough. For single-lane applications the automatic alignment is
4303  -- sufficient
4304  )
4305  port map (
4306  STABLE_CLOCK => SYSCLK_IN,
4307  TXUSERCLK => GT7_TXUSRCLK_IN,
4308  SOFT_RESET => SOFT_RESET_IN,
4309  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4310  CPLLREFCLKLOST => tied_to_ground_i,
4311  QPLLLOCK => GT1_QPLLLOCK_IN,
4312  CPLLLOCK => tied_to_vcc_i,
4313  TXRESETDONE => gt7_txresetdone_i,
4314  MMCM_LOCK => tied_to_vcc_i,
4315  GTTXRESET => gt7_gttxreset_t,
4316  MMCM_RESET => open,
4317  QPLL_RESET => open,
4318  CPLL_RESET => open,
4319  TX_FSM_RESET_DONE => GT7_TX_FSM_RESET_DONE_OUT,
4320  TXUSERRDY => gt7_txuserrdy_t,
4321  RUN_PHALIGNMENT => open,
4322  RESET_PHALIGNMENT => open,
4323  PHALIGNMENT_DONE => tied_to_vcc_i,
4324  RETRY_COUNTER => open
4325  );
4326 
4327 gt8_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4328 
4329  generic map(
4330  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4331  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4332  RETRY_COUNTER_BITWIDTH => 8,
4333  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4334  RX_QPLL_USED => TRUE, -- share these two generic values
4335  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4336  -- is enough. For single-lane applications the automatic alignment is
4337  -- sufficient
4338  )
4339  port map (
4340  STABLE_CLOCK => SYSCLK_IN,
4341  TXUSERCLK => GT8_TXUSRCLK_IN,
4342  SOFT_RESET => SOFT_RESET_IN,
4343  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4344  CPLLREFCLKLOST => tied_to_ground_i,
4345  QPLLLOCK => GT2_QPLLLOCK_IN,
4346  CPLLLOCK => tied_to_vcc_i,
4347  TXRESETDONE => gt8_txresetdone_i,
4348  MMCM_LOCK => tied_to_vcc_i,
4349  GTTXRESET => gt8_gttxreset_t,
4350  MMCM_RESET => open,
4351  QPLL_RESET => gt2_qpllreset_t,
4352  CPLL_RESET => open,
4353  TX_FSM_RESET_DONE => GT8_TX_FSM_RESET_DONE_OUT,
4354  TXUSERRDY => gt8_txuserrdy_t,
4355  RUN_PHALIGNMENT => open,
4356  RESET_PHALIGNMENT => open,
4357  PHALIGNMENT_DONE => tied_to_vcc_i,
4358  RETRY_COUNTER => open
4359  );
4360 
4361 gt9_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4362 
4363  generic map(
4364  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4365  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4366  RETRY_COUNTER_BITWIDTH => 8,
4367  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4368  RX_QPLL_USED => TRUE, -- share these two generic values
4369  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4370  -- is enough. For single-lane applications the automatic alignment is
4371  -- sufficient
4372  )
4373  port map (
4374  STABLE_CLOCK => SYSCLK_IN,
4375  TXUSERCLK => GT9_TXUSRCLK_IN,
4376  SOFT_RESET => SOFT_RESET_IN,
4377  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4378  CPLLREFCLKLOST => tied_to_ground_i,
4379  QPLLLOCK => GT2_QPLLLOCK_IN,
4380  CPLLLOCK => tied_to_vcc_i,
4381  TXRESETDONE => gt9_txresetdone_i,
4382  MMCM_LOCK => tied_to_vcc_i,
4383  GTTXRESET => gt9_gttxreset_t,
4384  MMCM_RESET => open,
4385  QPLL_RESET => open,
4386  CPLL_RESET => open,
4387  TX_FSM_RESET_DONE => GT9_TX_FSM_RESET_DONE_OUT,
4388  TXUSERRDY => gt9_txuserrdy_t,
4389  RUN_PHALIGNMENT => open,
4390  RESET_PHALIGNMENT => open,
4391  PHALIGNMENT_DONE => tied_to_vcc_i,
4392  RETRY_COUNTER => open
4393  );
4394 
4395 gt10_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4396 
4397  generic map(
4398  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4399  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4400  RETRY_COUNTER_BITWIDTH => 8,
4401  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4402  RX_QPLL_USED => TRUE, -- share these two generic values
4403  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4404  -- is enough. For single-lane applications the automatic alignment is
4405  -- sufficient
4406  )
4407  port map (
4408  STABLE_CLOCK => SYSCLK_IN,
4409  TXUSERCLK => GT10_TXUSRCLK_IN,
4410  SOFT_RESET => SOFT_RESET_IN,
4411  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4412  CPLLREFCLKLOST => tied_to_ground_i,
4413  QPLLLOCK => GT2_QPLLLOCK_IN,
4414  CPLLLOCK => tied_to_vcc_i,
4415  TXRESETDONE => gt10_txresetdone_i ,
4416  MMCM_LOCK => tied_to_vcc_i,
4417  GTTXRESET => gt10_gttxreset_t,
4418  MMCM_RESET => open,
4419  QPLL_RESET => open,
4420  CPLL_RESET => open,
4421  TX_FSM_RESET_DONE => GT10_TX_FSM_RESET_DONE_OUT,
4422  TXUSERRDY => gt10_txuserrdy_t,
4423  RUN_PHALIGNMENT => open,
4424  RESET_PHALIGNMENT => open,
4425  PHALIGNMENT_DONE => tied_to_vcc_i,
4426  RETRY_COUNTER => open
4427  );
4428 
4429 gt11_txresetfsm_i: amc_gtx5Gpd_TX_STARTUP_FSM
4430 
4431  generic map(
4432  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4433  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
4434  RETRY_COUNTER_BITWIDTH => 8,
4435  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4436  RX_QPLL_USED => TRUE, -- share these two generic values
4437  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4438  -- is enough. For single-lane applications the automatic alignment is
4439  -- sufficient
4440  )
4441  port map (
4442  STABLE_CLOCK => SYSCLK_IN,
4443  TXUSERCLK => GT11_TXUSRCLK_IN,
4444  SOFT_RESET => SOFT_RESET_IN,
4445  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4446  CPLLREFCLKLOST => tied_to_ground_i,
4447  QPLLLOCK => GT2_QPLLLOCK_IN,
4448  CPLLLOCK => tied_to_vcc_i,
4449  TXRESETDONE => gt11_txresetdone_i,
4450  MMCM_LOCK => tied_to_vcc_i,
4451  GTTXRESET => gt11_gttxreset_t,
4452  MMCM_RESET => open,
4453  QPLL_RESET => open,
4454  CPLL_RESET => open,
4455  TX_FSM_RESET_DONE => GT11_TX_FSM_RESET_DONE_OUT,
4456  TXUSERRDY => gt11_txuserrdy_t,
4457  RUN_PHALIGNMENT => open,
4458  RESET_PHALIGNMENT => open,
4459  PHALIGNMENT_DONE => tied_to_vcc_i,
4460  RETRY_COUNTER => open
4461  );
4462 
4463 
4464 
4465 
4466 
4467 
4468 
4469 
4470 gt0_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4471 
4472  generic map(
4473  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4474  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4475  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4476  RETRY_COUNTER_BITWIDTH => 8,
4477  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4478  RX_QPLL_USED => TRUE, -- share these two generic values
4479  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4480  -- is enough. For single-lane applications the automatic alignment is
4481  -- sufficient
4482  )
4483  port map (
4484  STABLE_CLOCK => SYSCLK_IN,
4485  RXUSERCLK => GT0_RXUSRCLK_IN,
4486  SOFT_RESET => SOFT_RESET_IN,
4487  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4488  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4489  CPLLREFCLKLOST => tied_to_ground_i,
4490  QPLLLOCK => GT0_QPLLLOCK_IN,
4491  CPLLLOCK => tied_to_vcc_i,
4492  RXRESETDONE => gt0_rxresetdone_i,
4493  MMCM_LOCK => tied_to_vcc_i,
4494  RECCLK_STABLE => gt0_recclk_stable_i ,
4495  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4496  DATA_VALID => GT0_DATA_VALID_IN,
4497  TXUSERRDY => gt0_txuserrdy_i,
4498  GTRXRESET => gt0_gtrxreset_t,
4499  MMCM_RESET => open,
4500  QPLL_RESET => open,
4501  CPLL_RESET => open,
4502  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT ,
4503  RXUSERRDY => gt0_rxuserrdy_t,
4504  RUN_PHALIGNMENT => open,
4505  RESET_PHALIGNMENT => open,
4506  PHALIGNMENT_DONE => tied_to_vcc_i,
4507  RXDFEAGCHOLD => gt0_rxdfeagchold_i,
4508  RXDFELFHOLD => gt0_rxdfelfhold_i,
4509  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
4510  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
4511  RETRY_COUNTER => open
4512  );
4513 
4514 
4515 gt1_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4516 
4517  generic map(
4518  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4519  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4520  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4521  RETRY_COUNTER_BITWIDTH => 8,
4522  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4523  RX_QPLL_USED => TRUE, -- share these two generic values
4524  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4525  -- is enough. For single-lane applications the automatic alignment is
4526  -- sufficient
4527  )
4528  port map (
4529  STABLE_CLOCK => SYSCLK_IN,
4530  RXUSERCLK => GT1_RXUSRCLK_IN,
4531  SOFT_RESET => SOFT_RESET_IN,
4532  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4533  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4534  CPLLREFCLKLOST => tied_to_ground_i,
4535  QPLLLOCK => GT0_QPLLLOCK_IN,
4536  CPLLLOCK => tied_to_vcc_i,
4537  RXRESETDONE => gt1_rxresetdone_i,
4538  MMCM_LOCK => tied_to_vcc_i,
4539  RECCLK_STABLE => gt1_recclk_stable_i ,
4540  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4541  DATA_VALID => GT1_DATA_VALID_IN,
4542  TXUSERRDY => gt1_txuserrdy_i,
4543  GTRXRESET => gt1_gtrxreset_t,
4544  MMCM_RESET => open,
4545  QPLL_RESET => open,
4546  CPLL_RESET => open,
4547  RX_FSM_RESET_DONE => GT1_RX_FSM_RESET_DONE_OUT ,
4548  RXUSERRDY => gt1_rxuserrdy_t,
4549  RUN_PHALIGNMENT => open,
4550  RESET_PHALIGNMENT => open,
4551  PHALIGNMENT_DONE => tied_to_vcc_i,
4552  RXDFEAGCHOLD => gt1_rxdfeagchold_i ,
4553  RXDFELFHOLD => gt1_rxdfelfhold_i,
4554  RXLPMLFHOLD => gt1_rxlpmlfhold_i,
4555  RXLPMHFHOLD => gt1_rxlpmhfhold_i,
4556  RETRY_COUNTER => open
4557  );
4558 
4559 
4560 gt2_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4561 
4562  generic map(
4563  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4564  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4565  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4566  RETRY_COUNTER_BITWIDTH => 8,
4567  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4568  RX_QPLL_USED => TRUE, -- share these two generic values
4569  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4570  -- is enough. For single-lane applications the automatic alignment is
4571  -- sufficient
4572  )
4573  port map (
4574  STABLE_CLOCK => SYSCLK_IN,
4575  RXUSERCLK => GT2_RXUSRCLK_IN,
4576  SOFT_RESET => SOFT_RESET_IN,
4577  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4578  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4579  CPLLREFCLKLOST => tied_to_ground_i,
4580  QPLLLOCK => GT0_QPLLLOCK_IN,
4581  CPLLLOCK => tied_to_vcc_i,
4582  RXRESETDONE => gt2_rxresetdone_i,
4583  MMCM_LOCK => tied_to_vcc_i,
4584  RECCLK_STABLE => gt2_recclk_stable_i ,
4585  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4586  DATA_VALID => GT2_DATA_VALID_IN,
4587  TXUSERRDY => gt2_txuserrdy_i,
4588  GTRXRESET => gt2_gtrxreset_t,
4589  MMCM_RESET => open,
4590  QPLL_RESET => open,
4591  CPLL_RESET => open,
4592  RX_FSM_RESET_DONE => GT2_RX_FSM_RESET_DONE_OUT ,
4593  RXUSERRDY => gt2_rxuserrdy_t,
4594  RUN_PHALIGNMENT => open,
4595  RESET_PHALIGNMENT => open,
4596  PHALIGNMENT_DONE => tied_to_vcc_i,
4597  RXDFEAGCHOLD => gt2_rxdfeagchold_i ,
4598  RXDFELFHOLD => gt2_rxdfelfhold_i,
4599  RXLPMLFHOLD => gt2_rxlpmlfhold_i,
4600  RXLPMHFHOLD => gt2_rxlpmhfhold_i,
4601  RETRY_COUNTER => open
4602  );
4603 
4604 
4605 gt3_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4606 
4607  generic map(
4608  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4609  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4610  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4611  RETRY_COUNTER_BITWIDTH => 8,
4612  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4613  RX_QPLL_USED => TRUE, -- share these two generic values
4614  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4615  -- is enough. For single-lane applications the automatic alignment is
4616  -- sufficient
4617  )
4618  port map (
4619  STABLE_CLOCK => SYSCLK_IN,
4620  RXUSERCLK => GT3_RXUSRCLK_IN,
4621  SOFT_RESET => SOFT_RESET_IN,
4622  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4623  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_IN ,
4624  CPLLREFCLKLOST => tied_to_ground_i,
4625  QPLLLOCK => GT0_QPLLLOCK_IN,
4626  CPLLLOCK => tied_to_vcc_i,
4627  RXRESETDONE => gt3_rxresetdone_i,
4628  MMCM_LOCK => tied_to_vcc_i,
4629  RECCLK_STABLE => gt3_recclk_stable_i ,
4630  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4631  DATA_VALID => GT3_DATA_VALID_IN,
4632  TXUSERRDY => gt3_txuserrdy_i,
4633  GTRXRESET => gt3_gtrxreset_t,
4634  MMCM_RESET => open,
4635  QPLL_RESET => open,
4636  CPLL_RESET => open,
4637  RX_FSM_RESET_DONE => GT3_RX_FSM_RESET_DONE_OUT ,
4638  RXUSERRDY => gt3_rxuserrdy_t,
4639  RUN_PHALIGNMENT => open,
4640  RESET_PHALIGNMENT => open,
4641  PHALIGNMENT_DONE => tied_to_vcc_i,
4642  RXDFEAGCHOLD => gt3_rxdfeagchold_i ,
4643  RXDFELFHOLD => gt3_rxdfelfhold_i,
4644  RXLPMLFHOLD => gt3_rxlpmlfhold_i,
4645  RXLPMHFHOLD => gt3_rxlpmhfhold_i,
4646  RETRY_COUNTER => open
4647  );
4648 
4649 
4650 gt4_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4651 
4652  generic map(
4653  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4654  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4655  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4656  RETRY_COUNTER_BITWIDTH => 8,
4657  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4658  RX_QPLL_USED => TRUE, -- share these two generic values
4659  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4660  -- is enough. For single-lane applications the automatic alignment is
4661  -- sufficient
4662  )
4663  port map (
4664  STABLE_CLOCK => SYSCLK_IN,
4665  RXUSERCLK => GT4_RXUSRCLK_IN,
4666  SOFT_RESET => SOFT_RESET_IN,
4667  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4668  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4669  CPLLREFCLKLOST => tied_to_ground_i,
4670  QPLLLOCK => GT1_QPLLLOCK_IN,
4671  CPLLLOCK => tied_to_vcc_i,
4672  RXRESETDONE => gt4_rxresetdone_i,
4673  MMCM_LOCK => tied_to_vcc_i,
4674  RECCLK_STABLE => gt4_recclk_stable_i ,
4675  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4676  DATA_VALID => GT4_DATA_VALID_IN,
4677  TXUSERRDY => gt4_txuserrdy_i,
4678  GTRXRESET => gt4_gtrxreset_t,
4679  MMCM_RESET => open,
4680  QPLL_RESET => open,
4681  CPLL_RESET => open,
4682  RX_FSM_RESET_DONE => GT4_RX_FSM_RESET_DONE_OUT ,
4683  RXUSERRDY => gt4_rxuserrdy_t,
4684  RUN_PHALIGNMENT => open,
4685  RESET_PHALIGNMENT => open,
4686  PHALIGNMENT_DONE => tied_to_vcc_i,
4687  RXDFEAGCHOLD => gt4_rxdfeagchold_i ,
4688  RXDFELFHOLD => gt4_rxdfelfhold_i,
4689  RXLPMLFHOLD => gt4_rxlpmlfhold_i,
4690  RXLPMHFHOLD => gt4_rxlpmhfhold_i,
4691  RETRY_COUNTER => open
4692  );
4693 
4694 
4695 gt5_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4696 
4697  generic map(
4698  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4699  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4700  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4701  RETRY_COUNTER_BITWIDTH => 8,
4702  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4703  RX_QPLL_USED => TRUE, -- share these two generic values
4704  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4705  -- is enough. For single-lane applications the automatic alignment is
4706  -- sufficient
4707  )
4708  port map (
4709  STABLE_CLOCK => SYSCLK_IN,
4710  RXUSERCLK => GT5_RXUSRCLK_IN,
4711  SOFT_RESET => SOFT_RESET_IN,
4712  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4713  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4714  CPLLREFCLKLOST => tied_to_ground_i,
4715  QPLLLOCK => GT1_QPLLLOCK_IN,
4716  CPLLLOCK => tied_to_vcc_i,
4717  RXRESETDONE => gt5_rxresetdone_i,
4718  MMCM_LOCK => tied_to_vcc_i,
4719  RECCLK_STABLE => gt5_recclk_stable_i ,
4720  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4721  DATA_VALID => GT5_DATA_VALID_IN,
4722  TXUSERRDY => gt5_txuserrdy_i,
4723  GTRXRESET => gt5_gtrxreset_t,
4724  MMCM_RESET => open,
4725  QPLL_RESET => open,
4726  CPLL_RESET => open,
4727  RX_FSM_RESET_DONE => GT5_RX_FSM_RESET_DONE_OUT ,
4728  RXUSERRDY => gt5_rxuserrdy_t,
4729  RUN_PHALIGNMENT => open,
4730  RESET_PHALIGNMENT => open,
4731  PHALIGNMENT_DONE => tied_to_vcc_i,
4732  RXDFEAGCHOLD => gt5_rxdfeagchold_i ,
4733  RXDFELFHOLD => gt5_rxdfelfhold_i,
4734  RXLPMLFHOLD => gt5_rxlpmlfhold_i,
4735  RXLPMHFHOLD => gt5_rxlpmhfhold_i,
4736  RETRY_COUNTER => open
4737  );
4738 
4739 
4740 gt6_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4741 
4742  generic map(
4743  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4744  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4745  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4746  RETRY_COUNTER_BITWIDTH => 8,
4747  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4748  RX_QPLL_USED => TRUE, -- share these two generic values
4749  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4750  -- is enough. For single-lane applications the automatic alignment is
4751  -- sufficient
4752  )
4753  port map (
4754  STABLE_CLOCK => SYSCLK_IN,
4755  RXUSERCLK => GT6_RXUSRCLK_IN,
4756  SOFT_RESET => SOFT_RESET_IN,
4757  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4758  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4759  CPLLREFCLKLOST => tied_to_ground_i,
4760  QPLLLOCK => GT1_QPLLLOCK_IN,
4761  CPLLLOCK => tied_to_vcc_i,
4762  RXRESETDONE => gt6_rxresetdone_i,
4763  MMCM_LOCK => tied_to_vcc_i,
4764  RECCLK_STABLE => gt6_recclk_stable_i ,
4765  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4766  DATA_VALID => GT6_DATA_VALID_IN,
4767  TXUSERRDY => gt6_txuserrdy_i,
4768  GTRXRESET => gt6_gtrxreset_t,
4769  MMCM_RESET => open,
4770  QPLL_RESET => open,
4771  CPLL_RESET => open,
4772  RX_FSM_RESET_DONE => GT6_RX_FSM_RESET_DONE_OUT ,
4773  RXUSERRDY => gt6_rxuserrdy_t,
4774  RUN_PHALIGNMENT => open,
4775  RESET_PHALIGNMENT => open,
4776  PHALIGNMENT_DONE => tied_to_vcc_i,
4777  RXDFEAGCHOLD => gt6_rxdfeagchold_i,
4778  RXDFELFHOLD => gt6_rxdfelfhold_i,
4779  RXLPMLFHOLD => gt6_rxlpmlfhold_i,
4780  RXLPMHFHOLD => gt6_rxlpmhfhold_i,
4781  RETRY_COUNTER => open
4782  );
4783 
4784 
4785 gt7_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4786 
4787  generic map(
4788  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4789  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4790  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4791  RETRY_COUNTER_BITWIDTH => 8,
4792  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4793  RX_QPLL_USED => TRUE, -- share these two generic values
4794  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4795  -- is enough. For single-lane applications the automatic alignment is
4796  -- sufficient
4797  )
4798  port map (
4799  STABLE_CLOCK => SYSCLK_IN,
4800  RXUSERCLK => GT7_RXUSRCLK_IN,
4801  SOFT_RESET => SOFT_RESET_IN,
4802  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4803  QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_IN ,
4804  CPLLREFCLKLOST => tied_to_ground_i,
4805  QPLLLOCK => GT1_QPLLLOCK_IN,
4806  CPLLLOCK => tied_to_vcc_i,
4807  RXRESETDONE => gt7_rxresetdone_i,
4808  MMCM_LOCK => tied_to_vcc_i,
4809  RECCLK_STABLE => gt7_recclk_stable_i ,
4810  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4811  DATA_VALID => GT7_DATA_VALID_IN,
4812  TXUSERRDY => gt7_txuserrdy_i,
4813  GTRXRESET => gt7_gtrxreset_t,
4814  MMCM_RESET => open,
4815  QPLL_RESET => open,
4816  CPLL_RESET => open,
4817  RX_FSM_RESET_DONE => GT7_RX_FSM_RESET_DONE_OUT ,
4818  RXUSERRDY => gt7_rxuserrdy_t,
4819  RUN_PHALIGNMENT => open,
4820  RESET_PHALIGNMENT => open,
4821  PHALIGNMENT_DONE => tied_to_vcc_i,
4822  RXDFEAGCHOLD => gt7_rxdfeagchold_i ,
4823  RXDFELFHOLD => gt7_rxdfelfhold_i,
4824  RXLPMLFHOLD => gt7_rxlpmlfhold_i,
4825  RXLPMHFHOLD => gt7_rxlpmhfhold_i,
4826  RETRY_COUNTER => open
4827  );
4828 
4829 
4830 gt8_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4831 
4832  generic map(
4833  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4834  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4835  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4836  RETRY_COUNTER_BITWIDTH => 8,
4837  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4838  RX_QPLL_USED => TRUE, -- share these two generic values
4839  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4840  -- is enough. For single-lane applications the automatic alignment is
4841  -- sufficient
4842  )
4843  port map (
4844  STABLE_CLOCK => SYSCLK_IN,
4845  RXUSERCLK => GT8_RXUSRCLK_IN,
4846  SOFT_RESET => SOFT_RESET_IN,
4847  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4848  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4849  CPLLREFCLKLOST => tied_to_ground_i,
4850  QPLLLOCK => GT2_QPLLLOCK_IN,
4851  CPLLLOCK => tied_to_vcc_i,
4852  RXRESETDONE => gt8_rxresetdone_i,
4853  MMCM_LOCK => tied_to_vcc_i,
4854  RECCLK_STABLE => gt8_recclk_stable_i ,
4855  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4856  DATA_VALID => GT8_DATA_VALID_IN,
4857  TXUSERRDY => gt8_txuserrdy_i,
4858  GTRXRESET => gt8_gtrxreset_t,
4859  MMCM_RESET => open,
4860  QPLL_RESET => open,
4861  CPLL_RESET => open,
4862  RX_FSM_RESET_DONE => GT8_RX_FSM_RESET_DONE_OUT ,
4863  RXUSERRDY => gt8_rxuserrdy_t,
4864  RUN_PHALIGNMENT => open,
4865  RESET_PHALIGNMENT => open,
4866  PHALIGNMENT_DONE => tied_to_vcc_i,
4867  RXDFEAGCHOLD => gt8_rxdfeagchold_i ,
4868  RXDFELFHOLD => gt8_rxdfelfhold_i,
4869  RXLPMLFHOLD => gt8_rxlpmlfhold_i,
4870  RXLPMHFHOLD => gt8_rxlpmhfhold_i,
4871  RETRY_COUNTER => open
4872  );
4873 
4874 
4875 gt9_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4876 
4877  generic map(
4878  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4879  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4880  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4881  RETRY_COUNTER_BITWIDTH => 8,
4882  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4883  RX_QPLL_USED => TRUE, -- share these two generic values
4884  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4885  -- is enough. For single-lane applications the automatic alignment is
4886  -- sufficient
4887  )
4888  port map (
4889  STABLE_CLOCK => SYSCLK_IN,
4890  RXUSERCLK => GT9_RXUSRCLK_IN,
4891  SOFT_RESET => SOFT_RESET_IN,
4892  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4893  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4894  CPLLREFCLKLOST => tied_to_ground_i,
4895  QPLLLOCK => GT2_QPLLLOCK_IN,
4896  CPLLLOCK => tied_to_vcc_i,
4897  RXRESETDONE => gt9_rxresetdone_i,
4898  MMCM_LOCK => tied_to_vcc_i,
4899  RECCLK_STABLE => gt9_recclk_stable_i ,
4900  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4901  DATA_VALID => GT9_DATA_VALID_IN,
4902  TXUSERRDY => gt9_txuserrdy_i,
4903  GTRXRESET => gt9_gtrxreset_t,
4904  MMCM_RESET => open,
4905  QPLL_RESET => open,
4906  CPLL_RESET => open,
4907  RX_FSM_RESET_DONE => GT9_RX_FSM_RESET_DONE_OUT ,
4908  RXUSERRDY => gt9_rxuserrdy_t,
4909  RUN_PHALIGNMENT => open,
4910  RESET_PHALIGNMENT => open,
4911  PHALIGNMENT_DONE => tied_to_vcc_i,
4912  RXDFEAGCHOLD => gt9_rxdfeagchold_i ,
4913  RXDFELFHOLD => gt9_rxdfelfhold_i,
4914  RXLPMLFHOLD => gt9_rxlpmlfhold_i,
4915  RXLPMHFHOLD => gt9_rxlpmhfhold_i,
4916  RETRY_COUNTER => open
4917  );
4918 
4919 
4920 gt10_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4921 
4922  generic map(
4923  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4924  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4925  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4926  RETRY_COUNTER_BITWIDTH => 8,
4927  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4928  RX_QPLL_USED => TRUE, -- share these two generic values
4929  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4930  -- is enough. For single-lane applications the automatic alignment is
4931  -- sufficient
4932  )
4933  port map (
4934  STABLE_CLOCK => SYSCLK_IN,
4935  RXUSERCLK => GT10_RXUSRCLK_IN,
4936  SOFT_RESET => SOFT_RESET_IN,
4937  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4938  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4939  CPLLREFCLKLOST => tied_to_ground_i,
4940  QPLLLOCK => GT2_QPLLLOCK_IN,
4941  CPLLLOCK => tied_to_vcc_i,
4942  RXRESETDONE => gt10_rxresetdone_i,
4943  MMCM_LOCK => tied_to_vcc_i,
4944  RECCLK_STABLE => gt10_recclk_stable_i ,
4945  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4946  DATA_VALID => GT10_DATA_VALID_IN,
4947  TXUSERRDY => gt10_txuserrdy_i,
4948  GTRXRESET => gt10_gtrxreset_t,
4949  MMCM_RESET => open,
4950  QPLL_RESET => open,
4951  CPLL_RESET => open,
4952  RX_FSM_RESET_DONE => GT10_RX_FSM_RESET_DONE_OUT ,
4953  RXUSERRDY => gt10_rxuserrdy_t,
4954  RUN_PHALIGNMENT => open,
4955  RESET_PHALIGNMENT => open,
4956  PHALIGNMENT_DONE => tied_to_vcc_i,
4957  RXDFEAGCHOLD => gt10_rxdfeagchold_i ,
4958  RXDFELFHOLD => gt10_rxdfelfhold_i,
4959  RXLPMLFHOLD => gt10_rxlpmlfhold_i,
4960  RXLPMHFHOLD => gt10_rxlpmhfhold_i,
4961  RETRY_COUNTER => open
4962  );
4963 
4964 
4965 gt11_rxresetfsm_i: amc_gtx5Gpd_RX_STARTUP_FSM
4966 
4967  generic map(
4968  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
4969  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
4970  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
4971  RETRY_COUNTER_BITWIDTH => 8,
4972  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
4973  RX_QPLL_USED => TRUE, -- share these two generic values
4974  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
4975  -- is enough. For single-lane applications the automatic alignment is
4976  -- sufficient
4977  )
4978  port map (
4979  STABLE_CLOCK => SYSCLK_IN,
4980  RXUSERCLK => GT11_RXUSRCLK_IN,
4981  SOFT_RESET => SOFT_RESET_IN,
4982  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
4983  QPLLREFCLKLOST => GT2_QPLLREFCLKLOST_IN ,
4984  CPLLREFCLKLOST => tied_to_ground_i,
4985  QPLLLOCK => GT2_QPLLLOCK_IN,
4986  CPLLLOCK => tied_to_vcc_i,
4987  RXRESETDONE => gt11_rxresetdone_i,
4988  MMCM_LOCK => tied_to_vcc_i,
4989  RECCLK_STABLE => gt11_recclk_stable_i ,
4990  RECCLK_MONITOR_RESTART => tied_to_ground_i,
4991  DATA_VALID => GT11_DATA_VALID_IN,
4992  TXUSERRDY => gt11_txuserrdy_i,
4993  GTRXRESET => gt11_gtrxreset_t,
4994  MMCM_RESET => open,
4995  QPLL_RESET => open,
4996  CPLL_RESET => open,
4997  RX_FSM_RESET_DONE => GT11_RX_FSM_RESET_DONE_OUT ,
4998  RXUSERRDY => gt11_rxuserrdy_t,
4999  RUN_PHALIGNMENT => open,
5000  RESET_PHALIGNMENT => open,
5001  PHALIGNMENT_DONE => tied_to_vcc_i,
5002  RXDFEAGCHOLD => gt11_rxdfeagchold_i ,
5003  RXDFELFHOLD => gt11_rxdfelfhold_i ,
5004  RXLPMLFHOLD => gt11_rxlpmlfhold_i ,
5005  RXLPMHFHOLD => gt11_rxlpmhfhold_i,
5006  RETRY_COUNTER => open
5007  );
5008 
5009 
5010 
5011  gt0_cdrlock_timeout:process(SYSCLK_IN)
5012  begin
5013  if rising_edge(SYSCLK_IN) then
5014  if(gt0_gtrxreset_i = '1') then
5015  gt0_rx_cdrlocked <= '0';
5016  gt0_rx_cdrlock_counter <= 0 after DLY;
5017  elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5018  gt0_rx_cdrlocked <= '1';
5019  gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter after DLY;
5020  else
5021  gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1 after DLY;
5022  end if;
5023  end if;
5024  end process;
5025 
5026  gt1_cdrlock_timeout:process(SYSCLK_IN)
5027  begin
5028  if rising_edge(SYSCLK_IN) then
5029  if(gt1_gtrxreset_i = '1') then
5030  gt1_rx_cdrlocked <= '0';
5031  gt1_rx_cdrlock_counter <= 0 after DLY;
5032  elsif (gt1_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5033  gt1_rx_cdrlocked <= '1';
5034  gt1_rx_cdrlock_counter <= gt1_rx_cdrlock_counter after DLY;
5035  else
5036  gt1_rx_cdrlock_counter <= gt1_rx_cdrlock_counter + 1 after DLY;
5037  end if;
5038  end if;
5039  end process;
5040 
5041  gt2_cdrlock_timeout:process(SYSCLK_IN)
5042  begin
5043  if rising_edge(SYSCLK_IN) then
5044  if(gt2_gtrxreset_i = '1') then
5045  gt2_rx_cdrlocked <= '0';
5046  gt2_rx_cdrlock_counter <= 0 after DLY;
5047  elsif (gt2_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5048  gt2_rx_cdrlocked <= '1';
5049  gt2_rx_cdrlock_counter <= gt2_rx_cdrlock_counter after DLY;
5050  else
5051  gt2_rx_cdrlock_counter <= gt2_rx_cdrlock_counter + 1 after DLY;
5052  end if;
5053  end if;
5054  end process;
5055 
5056  gt3_cdrlock_timeout:process(SYSCLK_IN)
5057  begin
5058  if rising_edge(SYSCLK_IN) then
5059  if(gt3_gtrxreset_i = '1') then
5060  gt3_rx_cdrlocked <= '0';
5061  gt3_rx_cdrlock_counter <= 0 after DLY;
5062  elsif (gt3_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5063  gt3_rx_cdrlocked <= '1';
5064  gt3_rx_cdrlock_counter <= gt3_rx_cdrlock_counter after DLY;
5065  else
5066  gt3_rx_cdrlock_counter <= gt3_rx_cdrlock_counter + 1 after DLY;
5067  end if;
5068  end if;
5069  end process;
5070 
5071  gt4_cdrlock_timeout:process(SYSCLK_IN)
5072  begin
5073  if rising_edge(SYSCLK_IN) then
5074  if(gt4_gtrxreset_i = '1') then
5075  gt4_rx_cdrlocked <= '0';
5076  gt4_rx_cdrlock_counter <= 0 after DLY;
5077  elsif (gt4_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5078  gt4_rx_cdrlocked <= '1';
5079  gt4_rx_cdrlock_counter <= gt4_rx_cdrlock_counter after DLY;
5080  else
5081  gt4_rx_cdrlock_counter <= gt4_rx_cdrlock_counter + 1 after DLY;
5082  end if;
5083  end if;
5084  end process;
5085 
5086  gt5_cdrlock_timeout:process(SYSCLK_IN)
5087  begin
5088  if rising_edge(SYSCLK_IN) then
5089  if(gt5_gtrxreset_i = '1') then
5090  gt5_rx_cdrlocked <= '0';
5091  gt5_rx_cdrlock_counter <= 0 after DLY;
5092  elsif (gt5_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5093  gt5_rx_cdrlocked <= '1';
5094  gt5_rx_cdrlock_counter <= gt5_rx_cdrlock_counter after DLY;
5095  else
5096  gt5_rx_cdrlock_counter <= gt5_rx_cdrlock_counter + 1 after DLY;
5097  end if;
5098  end if;
5099  end process;
5100 
5101  gt6_cdrlock_timeout:process(SYSCLK_IN)
5102  begin
5103  if rising_edge(SYSCLK_IN) then
5104  if(gt6_gtrxreset_i = '1') then
5105  gt6_rx_cdrlocked <= '0';
5106  gt6_rx_cdrlock_counter <= 0 after DLY;
5107  elsif (gt6_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5108  gt6_rx_cdrlocked <= '1';
5109  gt6_rx_cdrlock_counter <= gt6_rx_cdrlock_counter after DLY;
5110  else
5111  gt6_rx_cdrlock_counter <= gt6_rx_cdrlock_counter + 1 after DLY;
5112  end if;
5113  end if;
5114  end process;
5115 
5116  gt7_cdrlock_timeout:process(SYSCLK_IN)
5117  begin
5118  if rising_edge(SYSCLK_IN) then
5119  if(gt7_gtrxreset_i = '1') then
5120  gt7_rx_cdrlocked <= '0';
5121  gt7_rx_cdrlock_counter <= 0 after DLY;
5122  elsif (gt7_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5123  gt7_rx_cdrlocked <= '1';
5124  gt7_rx_cdrlock_counter <= gt7_rx_cdrlock_counter after DLY;
5125  else
5126  gt7_rx_cdrlock_counter <= gt7_rx_cdrlock_counter + 1 after DLY;
5127  end if;
5128  end if;
5129  end process;
5130 
5131  gt8_cdrlock_timeout:process(SYSCLK_IN)
5132  begin
5133  if rising_edge(SYSCLK_IN) then
5134  if(gt8_gtrxreset_i = '1') then
5135  gt8_rx_cdrlocked <= '0';
5136  gt8_rx_cdrlock_counter <= 0 after DLY;
5137  elsif (gt8_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5138  gt8_rx_cdrlocked <= '1';
5139  gt8_rx_cdrlock_counter <= gt8_rx_cdrlock_counter after DLY;
5140  else
5141  gt8_rx_cdrlock_counter <= gt8_rx_cdrlock_counter + 1 after DLY;
5142  end if;
5143  end if;
5144  end process;
5145 
5146  gt9_cdrlock_timeout:process(SYSCLK_IN)
5147  begin
5148  if rising_edge(SYSCLK_IN) then
5149  if(gt9_gtrxreset_i = '1') then
5150  gt9_rx_cdrlocked <= '0';
5151  gt9_rx_cdrlock_counter <= 0 after DLY;
5152  elsif (gt9_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5153  gt9_rx_cdrlocked <= '1';
5154  gt9_rx_cdrlock_counter <= gt9_rx_cdrlock_counter after DLY;
5155  else
5156  gt9_rx_cdrlock_counter <= gt9_rx_cdrlock_counter + 1 after DLY;
5157  end if;
5158  end if;
5159  end process;
5160 
5161  gt10_cdrlock_timeout:process(SYSCLK_IN)
5162  begin
5163  if rising_edge(SYSCLK_IN) then
5164  if(gt10_gtrxreset_i = '1') then
5165  gt10_rx_cdrlocked <= '0';
5166  gt10_rx_cdrlock_counter <= 0 after DLY;
5167  elsif (gt10_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5168  gt10_rx_cdrlocked <= '1';
5169  gt10_rx_cdrlock_counter <= gt10_rx_cdrlock_counter after DLY;
5170  else
5171  gt10_rx_cdrlock_counter <= gt10_rx_cdrlock_counter + 1 after DLY;
5172  end if;
5173  end if;
5174  end process;
5175 
5176  gt11_cdrlock_timeout:process(SYSCLK_IN)
5177  begin
5178  if rising_edge(SYSCLK_IN) then
5179  if(gt11_gtrxreset_i = '1') then
5180  gt11_rx_cdrlocked <= '0';
5181  gt11_rx_cdrlock_counter <= 0 after DLY;
5182  elsif (gt11_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
5183  gt11_rx_cdrlocked <= '1';
5184  gt11_rx_cdrlock_counter <= gt11_rx_cdrlock_counter after DLY;
5185  else
5186  gt11_rx_cdrlock_counter <= gt11_rx_cdrlock_counter + 1 after DLY;
5187  end if;
5188  end if;
5189  end process;
5190 
5191 gt0_recclk_stable_i <= gt0_rx_cdrlocked;
5192 gt1_recclk_stable_i <= gt1_rx_cdrlocked;
5193 gt2_recclk_stable_i <= gt2_rx_cdrlocked;
5194 gt3_recclk_stable_i <= gt3_rx_cdrlocked;
5195 gt4_recclk_stable_i <= gt4_rx_cdrlocked;
5196 gt5_recclk_stable_i <= gt5_rx_cdrlocked;
5197 gt6_recclk_stable_i <= gt6_rx_cdrlocked;
5198 gt7_recclk_stable_i <= gt7_rx_cdrlocked;
5199 gt8_recclk_stable_i <= gt8_rx_cdrlocked;
5200 gt9_recclk_stable_i <= gt9_rx_cdrlocked;
5201 gt10_recclk_stable_i <= gt10_rx_cdrlocked;
5202 gt11_recclk_stable_i <= gt11_rx_cdrlocked;
5203 
5204 
5205 
5206 
5207 
5208 
5209 end RTL;
5210 
5211 
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