AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
amc_gtx5gpd_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : amc_gtx5gpd_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module amc_gtx5Gpd_GT (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 --***************************** Entity Declaration ****************************
71 
72 entity amc_gtx5Gpd_GT is
73 generic
74 (
75  -- Simulation attributes
76  GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
77  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
78  SIM_CPLLREFCLK_SEL : bit_vector := "001";
79  PMA_RSV_IN : bit_vector := x"001E7080";
80  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
81 );
82 port
83 (
84  cpllrefclksel_in : in std_logic_vector(2 downto 0);
85  ---------------------------- Channel - DRP Ports --------------------------
86  drpaddr_in : in std_logic_vector(8 downto 0);
87  drpclk_in : in std_logic;
88  drpdi_in : in std_logic_vector(15 downto 0);
89  drpdo_out : out std_logic_vector(15 downto 0);
90  drpen_in : in std_logic;
91  drprdy_out : out std_logic;
92  drpwe_in : in std_logic;
93  ------------------------------- Clocking Ports -----------------------------
94  qpllclk_in : in std_logic;
95  qpllrefclk_in : in std_logic;
96  --------------------------- Digital Monitor Ports --------------------------
97  dmonitorout_out : out std_logic_vector(7 downto 0);
98  ------------------------------- Loopback Ports -----------------------------
99  loopback_in : in std_logic_vector(2 downto 0);
100  ------------------------------ Power-Down Ports ----------------------------
101  rxpd_in : in std_logic_vector(1 downto 0);
102  txpd_in : in std_logic_vector(1 downto 0);
103  --------------------- RX Initialization and Reset Ports --------------------
104  eyescanreset_in : in std_logic;
105  rxuserrdy_in : in std_logic;
106  -------------------------- RX Margin Analysis Ports ------------------------
107  eyescandataerror_out : out std_logic;
108  eyescantrigger_in : in std_logic;
109  ------------------- Receive Ports - Clock Correction Ports -----------------
110  rxclkcorcnt_out : out std_logic_vector(1 downto 0);
111  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
112  rxusrclk_in : in std_logic;
113  rxusrclk2_in : in std_logic;
114  ------------------ Receive Ports - FPGA RX interface Ports -----------------
115  rxdata_out : out std_logic_vector(15 downto 0);
116  ------------------- Receive Ports - Pattern Checker Ports ------------------
117  rxprbserr_out : out std_logic;
118  rxprbssel_in : in std_logic_vector(2 downto 0);
119  ------------------- Receive Ports - Pattern Checker ports ------------------
120  rxprbscntreset_in : in std_logic;
121  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
122  rxdisperr_out : out std_logic_vector(1 downto 0);
123  rxnotintable_out : out std_logic_vector(1 downto 0);
124  --------------------------- Receive Ports - RX AFE -------------------------
125  gtxrxp_in : in std_logic;
126  ------------------------ Receive Ports - RX AFE Ports ----------------------
127  gtxrxn_in : in std_logic;
128  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
129  rxbufstatus_out : out std_logic_vector(2 downto 0);
130  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
131  rxmcommaalignen_in : in std_logic;
132  rxpcommaalignen_in : in std_logic;
133  --------------------- Receive Ports - RX Equalizer Ports -------------------
134  rxdfeagchold_in : in std_logic;
135  rxdfelfhold_in : in std_logic;
136  rxdfelpmreset_in : in std_logic;
137  rxmonitorout_out : out std_logic_vector(6 downto 0);
138  rxmonitorsel_in : in std_logic_vector(1 downto 0);
139  --------------- Receive Ports - RX Fabric Output Control Ports -------------
140  rxoutclk_out : out std_logic;
141  rxoutclkfabric_out : out std_logic;
142  ------------- Receive Ports - RX Initialization and Reset Ports ------------
143  gtrxreset_in : in std_logic;
144  rxpmareset_in : in std_logic;
145  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
146  rxchariscomma_out : out std_logic_vector(1 downto 0);
147  rxcharisk_out : out std_logic_vector(1 downto 0);
148  -------------- Receive Ports -RX Initialization and Reset Ports ------------
149  rxresetdone_out : out std_logic;
150  --------------------- TX Initialization and Reset Ports --------------------
151  gttxreset_in : in std_logic;
152  txuserrdy_in : in std_logic;
153  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
154  txusrclk_in : in std_logic;
155  txusrclk2_in : in std_logic;
156  --------------- Transmit Ports - TX Configurable Driver Ports --------------
157  txdiffctrl_in : in std_logic_vector(3 downto 0);
158  ------------------ Transmit Ports - TX Data Path interface -----------------
159  txdata_in : in std_logic_vector(15 downto 0);
160  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
161  gtxtxn_out : out std_logic;
162  gtxtxp_out : out std_logic;
163  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
164  txoutclk_out : out std_logic;
165  txoutclkfabric_out : out std_logic;
166  txoutclkpcs_out : out std_logic;
167  --------------------- Transmit Ports - TX Gearbox Ports --------------------
168  txcharisk_in : in std_logic_vector(1 downto 0);
169  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
170  txresetdone_out : out std_logic;
171  ------------------ Transmit Ports - pattern Generator Ports ----------------
172  txprbssel_in : in std_logic_vector(2 downto 0)
173 
174 
175 );
176 
177 
178 end amc_gtx5Gpd_GT;
179 
180 architecture RTL of amc_gtx5Gpd_GT is
181 
182 --**************************** Signal Declarations ****************************
183 
184  -- ground and tied_to_vcc_i signals
185  signal tied_to_ground_i : std_logic;
186  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
187  signal tied_to_vcc_i : std_logic;
188 
189 
190 
191  -- RX Datapath signals
192  signal rxdata_i : std_logic_vector(63 downto 0);
193  signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
194  signal rxcharisk_float_i : std_logic_vector(5 downto 0);
195  signal rxdisperr_float_i : std_logic_vector(5 downto 0);
196  signal rxnotintable_float_i : std_logic_vector(5 downto 0);
197  signal rxrundisp_float_i : std_logic_vector(5 downto 0);
198 
199 
200  -- TX Datapath signals
201  signal txdata_i : std_logic_vector(63 downto 0);
202  signal txkerr_float_i : std_logic_vector(5 downto 0);
203  signal txrundisp_float_i : std_logic_vector(5 downto 0);
204  signal rxstartofseq_float_i : std_logic;
205 --******************************** Main Body of Code***************************
206 
207 begin
208 
209  --------------------------- Static signal Assignments ---------------------
210 
211  tied_to_ground_i <= '0';
212  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
213  tied_to_vcc_i <= '1';
214 
215  ------------------- GT Datapath byte mapping -----------------
216  RXDATA_OUT <= rxdata_i(15 downto 0);
217 
218  txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
219 
220 
221 
222  ----------------------------- GTXE2 Instance --------------------------
223 
224  gtxe2_i :GTXE2_CHANNEL
225  generic map
226  (
227 
228  --_______________________ Simulation-Only Attributes ___________________
229 
230  SIM_RECEIVER_DETECT_PASS => ("TRUE"),
231  SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
232  SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
233  SIM_CPLLREFCLK_SEL => (SIM_CPLLREFCLK_SEL),
234  SIM_VERSION => ("4.0"),
235 
236 
237  ------------------RX Byte and Word Alignment Attributes---------------
238  ALIGN_COMMA_DOUBLE => ("FALSE"),
239  ALIGN_COMMA_ENABLE => ("1111111111"),
240  ALIGN_COMMA_WORD => (2),
241  ALIGN_MCOMMA_DET => ("TRUE"),
242  ALIGN_MCOMMA_VALUE => ("1010000011"),
243  ALIGN_PCOMMA_DET => ("TRUE"),
244  ALIGN_PCOMMA_VALUE => ("0101111100"),
245  SHOW_REALIGN_COMMA => ("TRUE"),
246  RXSLIDE_AUTO_WAIT => (7),
247  RXSLIDE_MODE => ("OFF"),
248  RX_SIG_VALID_DLY => (10),
249 
250  ------------------RX 8B/10B Decoder Attributes---------------
251  RX_DISPERR_SEQ_MATCH => ("TRUE"),
252  DEC_MCOMMA_DETECT => ("TRUE"),
253  DEC_PCOMMA_DETECT => ("TRUE"),
254  DEC_VALID_COMMA_ONLY => ("TRUE"),
255 
256  ------------------------RX Clock Correction Attributes----------------------
257  CBCC_DATA_SOURCE_SEL => ("DECODED"),
258  CLK_COR_SEQ_2_USE => ("FALSE"),
259  CLK_COR_KEEP_IDLE => ("FALSE"),
260  CLK_COR_MAX_LAT => (15),
261  CLK_COR_MIN_LAT => (12),
262  CLK_COR_PRECEDENCE => ("TRUE"),
263  CLK_COR_REPEAT_WAIT => (0),
264  CLK_COR_SEQ_LEN => (2),
265  CLK_COR_SEQ_1_ENABLE => ("1111"),
266  CLK_COR_SEQ_1_1 => ("0111111011"),
267  CLK_COR_SEQ_1_2 => ("0111011100"),
268  CLK_COR_SEQ_1_3 => ("0000000000"),
269  CLK_COR_SEQ_1_4 => ("0000000000"),
270  CLK_CORRECT_USE => ("TRUE"),
271  CLK_COR_SEQ_2_ENABLE => ("1111"),
272  CLK_COR_SEQ_2_1 => ("0000000000"),
273  CLK_COR_SEQ_2_2 => ("0000000000"),
274  CLK_COR_SEQ_2_3 => ("0000000000"),
275  CLK_COR_SEQ_2_4 => ("0000000000"),
276 
277  ------------------------RX Channel Bonding Attributes----------------------
278  CHAN_BOND_KEEP_ALIGN => ("FALSE"),
279  CHAN_BOND_MAX_SKEW => (1),
280  CHAN_BOND_SEQ_LEN => (1),
281  CHAN_BOND_SEQ_1_1 => ("0000000000"),
282  CHAN_BOND_SEQ_1_2 => ("0000000000"),
283  CHAN_BOND_SEQ_1_3 => ("0000000000"),
284  CHAN_BOND_SEQ_1_4 => ("0000000000"),
285  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
286  CHAN_BOND_SEQ_2_1 => ("0000000000"),
287  CHAN_BOND_SEQ_2_2 => ("0000000000"),
288  CHAN_BOND_SEQ_2_3 => ("0000000000"),
289  CHAN_BOND_SEQ_2_4 => ("0000000000"),
290  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
291  CHAN_BOND_SEQ_2_USE => ("FALSE"),
292  FTS_DESKEW_SEQ_ENABLE => ("1111"),
293  FTS_LANE_DESKEW_CFG => ("1111"),
294  FTS_LANE_DESKEW_EN => ("FALSE"),
295 
296  ---------------------------RX Margin Analysis Attributes----------------------------
297  ES_CONTROL => ("000000"),
298  ES_ERRDET_EN => ("FALSE"),
299  ES_EYE_SCAN_EN => ("TRUE"),
300  ES_HORZ_OFFSET => (x"000"),
301  ES_PMA_CFG => ("0000000000"),
302  ES_PRESCALE => ("00000"),
303  ES_QUALIFIER => (x"00000000000000000000"),
304  ES_QUAL_MASK => (x"00000000000000000000"),
305  ES_SDATA_MASK => (x"00000000000000000000"),
306  ES_VERT_OFFSET => ("000000000"),
307 
308  -------------------------FPGA RX Interface Attributes-------------------------
309  RX_DATA_WIDTH => (20),
310 
311  ---------------------------PMA Attributes----------------------------
312  OUTREFCLK_SEL_INV => ("11"),
313  PMA_RSV => (PMA_RSV_IN),
314  PMA_RSV2 => (x"2050"),
315  PMA_RSV3 => ("00"),
316  PMA_RSV4 => (x"00000000"),
317  RX_BIAS_CFG => ("000000000100"),
318  DMONITOR_CFG => (x"000A00"),
319  RX_CM_SEL => ("11"),
320  RX_CM_TRIM => ("010"),
321  RX_DEBUG_CFG => ("000000000000"),
322  RX_OS_CFG => ("0000010000000"),
323  TERM_RCAL_CFG => ("10000"),
324  TERM_RCAL_OVRD => ('0'),
325  TST_RSV => (x"00000000"),
326  RX_CLK25_DIV => (10),
327  TX_CLK25_DIV => (10),
328  UCODEER_CLR => ('0'),
329 
330  ---------------------------PCI Express Attributes----------------------------
331  PCS_PCIE_EN => ("FALSE"),
332 
333  ---------------------------PCS Attributes----------------------------
334  PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
335 
336  -------------RX Buffer Attributes------------
337  RXBUF_ADDR_MODE => ("FULL"),
338  RXBUF_EIDLE_HI_CNT => ("1000"),
339  RXBUF_EIDLE_LO_CNT => ("0000"),
340  RXBUF_EN => ("TRUE"),
341  RX_BUFFER_CFG => ("000000"),
342  RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
343  RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
344  RXBUF_RESET_ON_EIDLE => ("FALSE"),
345  RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
346  RXBUFRESET_TIME => ("00001"),
347  RXBUF_THRESH_OVFLW => (61),
348  RXBUF_THRESH_OVRD => ("FALSE"),
349  RXBUF_THRESH_UNDFLW => (4),
350  RXDLY_CFG => (x"001F"),
351  RXDLY_LCFG => (x"030"),
352  RXDLY_TAP_CFG => (x"0000"),
353  RXPH_CFG => (x"000000"),
354  RXPHDLY_CFG => (x"084020"),
355  RXPH_MONITOR_SEL => ("00000"),
356  RX_XCLK_SEL => ("RXREC"),
357  RX_DDI_SEL => ("000000"),
358  RX_DEFER_RESET_BUF_EN => ("TRUE"),
359 
360  -----------------------CDR Attributes-------------------------
361 
362  --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
363 
364  --For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010
365 
366  --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
367 
368  --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
369 
370  --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
371 
372  --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
373 
374  --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
375 
376  --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
377  RXCDR_CFG => (x"03000023ff10200020"),
378  RXCDR_FR_RESET_ON_EIDLE => ('0'),
379  RXCDR_HOLD_DURING_EIDLE => ('0'),
380  RXCDR_PH_RESET_ON_EIDLE => ('0'),
381  RXCDR_LOCK_CFG => ("010101"),
382 
383  -------------------RX Initialization and Reset Attributes-------------------
384  RXCDRFREQRESET_TIME => ("00001"),
385  RXCDRPHRESET_TIME => ("00001"),
386  RXISCANRESET_TIME => ("00001"),
387  RXPCSRESET_TIME => ("00001"),
388  RXPMARESET_TIME => ("00011"),
389 
390  -------------------RX OOB Signaling Attributes-------------------
391  RXOOB_CFG => ("0000110"),
392 
393  -------------------------RX Gearbox Attributes---------------------------
394  RXGEARBOX_EN => ("FALSE"),
395  GEARBOX_MODE => ("000"),
396 
397  -------------------------PRBS Detection Attribute-----------------------
398  RXPRBS_ERR_LOOPBACK => ('0'),
399 
400  -------------Power-Down Attributes----------
401  PD_TRANS_TIME_FROM_P2 => (x"03c"),
402  PD_TRANS_TIME_NONE_P2 => (x"3c"),
403  PD_TRANS_TIME_TO_P2 => (x"64"),
404 
405  -------------RX OOB Signaling Attributes----------
406  SAS_MAX_COM => (64),
407  SAS_MIN_COM => (36),
408  SATA_BURST_SEQ_LEN => ("0101"),
409  SATA_BURST_VAL => ("111"),
410  SATA_EIDLE_VAL => ("111"),
411  SATA_MAX_BURST => (8),
412  SATA_MAX_INIT => (21),
413  SATA_MAX_WAKE => (7),
414  SATA_MIN_BURST => (4),
415  SATA_MIN_INIT => (12),
416  SATA_MIN_WAKE => (4),
417 
418  -------------RX Fabric Clock Output Control Attributes----------
419  TRANS_TIME_RATE => (x"0E"),
420 
421  --------------TX Buffer Attributes----------------
422  TXBUF_EN => ("TRUE"),
423  TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
424  TXDLY_CFG => (x"001F"),
425  TXDLY_LCFG => (x"030"),
426  TXDLY_TAP_CFG => (x"0000"),
427  TXPH_CFG => (x"0780"),
428  TXPHDLY_CFG => (x"084020"),
429  TXPH_MONITOR_SEL => ("00000"),
430  TX_XCLK_SEL => ("TXOUT"),
431 
432  -------------------------FPGA TX Interface Attributes-------------------------
433  TX_DATA_WIDTH => (20),
434 
435  -------------------------TX Configurable Driver Attributes-------------------------
436  TX_DEEMPH0 => ("00000"),
437  TX_DEEMPH1 => ("00000"),
438  TX_EIDLE_ASSERT_DELAY => ("110"),
439  TX_EIDLE_DEASSERT_DELAY => ("100"),
440  TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
441  TX_MAINCURSOR_SEL => ('0'),
442  TX_DRIVE_MODE => ("DIRECT"),
443  TX_MARGIN_FULL_0 => ("1001110"),
444  TX_MARGIN_FULL_1 => ("1001001"),
445  TX_MARGIN_FULL_2 => ("1000101"),
446  TX_MARGIN_FULL_3 => ("1000010"),
447  TX_MARGIN_FULL_4 => ("1000000"),
448  TX_MARGIN_LOW_0 => ("1000110"),
449  TX_MARGIN_LOW_1 => ("1000100"),
450  TX_MARGIN_LOW_2 => ("1000010"),
451  TX_MARGIN_LOW_3 => ("1000000"),
452  TX_MARGIN_LOW_4 => ("1000000"),
453 
454  -------------------------TX Gearbox Attributes--------------------------
455  TXGEARBOX_EN => ("FALSE"),
456 
457  -------------------------TX Initialization and Reset Attributes--------------------------
458  TXPCSRESET_TIME => ("00001"),
459  TXPMARESET_TIME => ("00001"),
460 
461  -------------------------TX Receiver Detection Attributes--------------------------
462  TX_RXDETECT_CFG => (x"1832"),
463  TX_RXDETECT_REF => ("100"),
464 
465  ----------------------------CPLL Attributes----------------------------
466  CPLL_CFG => (x"BC07DC"),
467  CPLL_FBDIV => (4),
468  CPLL_FBDIV_45 => (4),
469  CPLL_INIT_CFG => (x"00001E"),
470  CPLL_LOCK_CFG => (x"01E8"),
471  CPLL_REFCLK_DIV => (1),
472  RXOUT_DIV => (2),
473  TXOUT_DIV => (2),
474  SATA_CPLL_CFG => ("VCO_3000MHZ"),
475 
476  --------------RX Initialization and Reset Attributes-------------
477  RXDFELPMRESET_TIME => ("0001111"),
478 
479  --------------RX Equalizer Attributes-------------
480  RXLPM_HF_CFG => ("00000011110000"),
481  RXLPM_LF_CFG => ("00000011110000"),
482  RX_DFE_GAIN_CFG => (x"020FEA"),
483  RX_DFE_H2_CFG => ("000000000000"),
484  RX_DFE_H3_CFG => ("000001000000"),
485  RX_DFE_H4_CFG => ("00011110000"),
486  RX_DFE_H5_CFG => ("00011100000"),
487  RX_DFE_KL_CFG => ("0000011111110"),
488  RX_DFE_LPM_CFG => (x"0954"),
489  RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
490  RX_DFE_UT_CFG => ("10001111000000000"),
491  RX_DFE_VP_CFG => ("00011111100000011"),
492 
493  -------------------------Power-Down Attributes-------------------------
494  RX_CLKMUX_PD => ('1'),
495  TX_CLKMUX_PD => ('1'),
496 
497  -------------------------FPGA RX Interface Attribute-------------------------
498  RX_INT_DATAWIDTH => (0),
499 
500  -------------------------FPGA TX Interface Attribute-------------------------
501  TX_INT_DATAWIDTH => (0),
502 
503  ------------------TX Configurable Driver Attributes---------------
504  TX_QPI_STATUS_EN => ('0'),
505 
506  -------------------------RX Equalizer Attributes--------------------------
507  RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
508  RX_DFE_XYD_CFG => ("0000000000000"),
509 
510  -------------------------TX Configurable Driver Attributes--------------------------
511  TX_PREDRIVER_MODE => ('0')
512 
513 
514  )
515  port map
516  (
517  --------------------------------- CPLL Ports -------------------------------
518  CPLLFBCLKLOST => open,
519  CPLLLOCK => open,
520  CPLLLOCKDETCLK => tied_to_ground_i,
521  CPLLLOCKEN => tied_to_vcc_i,
522  CPLLPD => tied_to_vcc_i,
523  CPLLREFCLKLOST => open,
524  CPLLREFCLKSEL => cpllrefclksel_in,
525  CPLLRESET => tied_to_ground_i,
526  GTRSVD => "0000000000000000",
527  PCSRSVDIN => "0000000000000000",
528  PCSRSVDIN2 => "00000",
529  PMARSVDIN => "00000",
530  PMARSVDIN2 => "00000",
531  TSTIN => "11111111111111111111" ,
532  TSTOUT => open,
533  ---------------------------------- Channel ---------------------------------
534  CLKRSVD => tied_to_ground_vec_i (3 downto 0),
535  -------------------------- Channel - Clocking Ports ------------------------
536  GTGREFCLK => tied_to_ground_i,
537  GTNORTHREFCLK0 => tied_to_ground_i,
538  GTNORTHREFCLK1 => tied_to_ground_i,
539  GTREFCLK0 => tied_to_ground_i,
540  GTREFCLK1 => tied_to_ground_i,
541  GTSOUTHREFCLK0 => tied_to_ground_i,
542  GTSOUTHREFCLK1 => tied_to_ground_i,
543  ---------------------------- Channel - DRP Ports --------------------------
544  DRPADDR => drpaddr_in,
545  DRPCLK => drpclk_in ,
546  DRPDI => drpdi_in,
547  DRPDO => drpdo_out ,
548  DRPEN => drpen_in,
549  DRPRDY => drprdy_out,
550  DRPWE => drpwe_in,
551  ------------------------------- Clocking Ports -----------------------------
552  GTREFCLKMONITOR => open,
553  QPLLCLK => qpllclk_in,
554  QPLLREFCLK => qpllrefclk_in,
555  RXSYSCLKSEL => "11",
556  TXSYSCLKSEL => "11",
557  --------------------------- Digital Monitor Ports --------------------------
558  DMONITOROUT => dmonitorout_out,
559  ----------------- FPGA TX Interface Datapath Configuration ----------------
560  TX8B10BEN => tied_to_vcc_i,
561  ------------------------------- Loopback Ports -----------------------------
562  LOOPBACK => loopback_in,
563  ----------------------------- PCI Express Ports ----------------------------
564  PHYSTATUS => open,
565  RXRATE => tied_to_ground_vec_i (2 downto 0),
566  RXVALID => open,
567  ------------------------------ Power-Down Ports ----------------------------
568  RXPD => rxpd_in,
569  TXPD => txpd_in,
570  -------------------------- RX 8B/10B Decoder Ports -------------------------
571  SETERRSTATUS => tied_to_ground_i,
572  --------------------- RX Initialization and Reset Ports --------------------
573  EYESCANRESET => eyescanreset_in,
574  RXUSERRDY => rxuserrdy_in,
575  -------------------------- RX Margin Analysis Ports ------------------------
576  EYESCANDATAERROR => eyescandataerror_out ,
577  EYESCANMODE => tied_to_ground_i,
578  EYESCANTRIGGER => eyescantrigger_in,
579  ------------------------- Receive Ports - CDR Ports ------------------------
580  RXCDRFREQRESET => tied_to_ground_i,
581  RXCDRHOLD => tied_to_ground_i,
582  RXCDRLOCK => open,
583  RXCDROVRDEN => tied_to_ground_i,
584  RXCDRRESET => tied_to_ground_i,
585  RXCDRRESETRSV => tied_to_ground_i,
586  ------------------- Receive Ports - Clock Correction Ports -----------------
587  RXCLKCORCNT => rxclkcorcnt_out,
588  ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
589  RX8B10BEN => tied_to_vcc_i,
590  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
591  RXUSRCLK => rxusrclk_in,
592  RXUSRCLK2 => rxusrclk2_in,
593  ------------------ Receive Ports - FPGA RX interface Ports -----------------
594  RXDATA => rxdata_i,
595  ------------------- Receive Ports - Pattern Checker Ports ------------------
596  RXPRBSERR => rxprbserr_out,
597  RXPRBSSEL => rxprbssel_in,
598  ------------------- Receive Ports - Pattern Checker ports ------------------
599  RXPRBSCNTRESET => rxprbscntreset_in,
600  -------------------- Receive Ports - RX Equalizer Ports -------------------
601  RXDFEXYDEN => tied_to_vcc_i,
602  RXDFEXYDHOLD => tied_to_ground_i,
603  RXDFEXYDOVRDEN => tied_to_ground_i,
604  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
605  RXDISPERR(7 downto 2) => rxdisperr_float_i,
606  RXDISPERR(1 downto 0) => rxdisperr_out,
607  RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
608  RXNOTINTABLE(1 downto 0) => rxnotintable_out,
609  --------------------------- Receive Ports - RX AFE -------------------------
610  GTXRXP => gtxrxp_in ,
611  ------------------------ Receive Ports - RX AFE Ports ----------------------
612  GTXRXN => gtxrxn_in ,
613  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
614  RXBUFRESET => tied_to_ground_i,
615  RXBUFSTATUS => rxbufstatus_out,
616  RXDDIEN => tied_to_ground_i,
617  RXDLYBYPASS => tied_to_vcc_i,
618  RXDLYEN => tied_to_ground_i,
619  RXDLYOVRDEN => tied_to_ground_i,
620  RXDLYSRESET => tied_to_ground_i,
621  RXDLYSRESETDONE => open,
622  RXPHALIGN => tied_to_ground_i,
623  RXPHALIGNDONE => open,
624  RXPHALIGNEN => tied_to_ground_i,
625  RXPHDLYPD => tied_to_ground_i,
626  RXPHDLYRESET => tied_to_ground_i,
627  RXPHMONITOR => open,
628  RXPHOVRDEN => tied_to_ground_i,
629  RXPHSLIPMONITOR => open,
630  RXSTATUS => open,
631  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
632  RXBYTEISALIGNED => open,
633  RXBYTEREALIGN => open,
634  RXCOMMADET => open,
635  RXCOMMADETEN => tied_to_vcc_i,
636  RXMCOMMAALIGNEN => rxmcommaalignen_in,
637  RXPCOMMAALIGNEN => rxpcommaalignen_in,
638  ------------------ Receive Ports - RX Channel Bonding Ports ----------------
639  RXCHANBONDSEQ => open,
640  RXCHBONDEN => tied_to_ground_i,
641  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
642  RXCHBONDMASTER => tied_to_ground_i,
643  RXCHBONDO => open,
644  RXCHBONDSLAVE => tied_to_ground_i,
645  ----------------- Receive Ports - RX Channel Bonding Ports ----------------
646  RXCHANISALIGNED => open,
647  RXCHANREALIGN => open,
648  -------------------- Receive Ports - RX Equailizer Ports -------------------
649  RXLPMHFHOLD => tied_to_ground_i,
650  RXLPMHFOVRDEN => tied_to_ground_i,
651  RXLPMLFHOLD => tied_to_ground_i,
652  --------------------- Receive Ports - RX Equalizer Ports -------------------
653  RXDFEAGCHOLD => rxdfeagchold_in,
654  RXDFEAGCOVRDEN => tied_to_ground_i,
655  RXDFECM1EN => tied_to_ground_i,
656  RXDFELFHOLD => rxdfelfhold_in,
657  RXDFELFOVRDEN => tied_to_vcc_i,
658  RXDFELPMRESET => rxdfelpmreset_in,
659  RXDFETAP2HOLD => tied_to_ground_i,
660  RXDFETAP2OVRDEN => tied_to_ground_i,
661  RXDFETAP3HOLD => tied_to_ground_i,
662  RXDFETAP3OVRDEN => tied_to_ground_i,
663  RXDFETAP4HOLD => tied_to_ground_i,
664  RXDFETAP4OVRDEN => tied_to_ground_i,
665  RXDFETAP5HOLD => tied_to_ground_i,
666  RXDFETAP5OVRDEN => tied_to_ground_i,
667  RXDFEUTHOLD => tied_to_ground_i,
668  RXDFEUTOVRDEN => tied_to_ground_i,
669  RXDFEVPHOLD => tied_to_ground_i,
670  RXDFEVPOVRDEN => tied_to_ground_i,
671  RXDFEVSEN => tied_to_ground_i,
672  RXLPMLFKLOVRDEN => tied_to_ground_i,
673  RXMONITOROUT => rxmonitorout_out,
674  RXMONITORSEL => rxmonitorsel_in,
675  RXOSHOLD => tied_to_ground_i,
676  RXOSOVRDEN => tied_to_ground_i,
677  ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
678  RXRATEDONE => open,
679  --------------- Receive Ports - RX Fabric Output Control Ports -------------
680  RXOUTCLK => rxoutclk_out,
681  RXOUTCLKFABRIC => rxoutclkfabric_out,
682  RXOUTCLKPCS => open,
683  RXOUTCLKSEL => "010",
684  ---------------------- Receive Ports - RX Gearbox Ports --------------------
685  RXDATAVALID => open,
686  RXHEADER => open,
687  RXHEADERVALID => open,
688  RXSTARTOFSEQ => open,
689  --------------------- Receive Ports - RX Gearbox Ports --------------------
690  RXGEARBOXSLIP => tied_to_ground_i,
691  ------------- Receive Ports - RX Initialization and Reset Ports ------------
692  GTRXRESET => gtrxreset_in,
693  RXOOBRESET => tied_to_ground_i,
694  RXPCSRESET => tied_to_ground_i,
695  RXPMARESET => rxpmareset_in,
696  ------------------ Receive Ports - RX Margin Analysis ports ----------------
697  RXLPMEN => tied_to_ground_i,
698  ------------------- Receive Ports - RX OOB Signaling ports -----------------
699  RXCOMSASDET => open,
700  RXCOMWAKEDET => open,
701  ------------------ Receive Ports - RX OOB Signaling ports -----------------
702  RXCOMINITDET => open,
703  ------------------ Receive Ports - RX OOB signalling Ports -----------------
704  RXELECIDLE => open,
705  RXELECIDLEMODE => "11",
706  ----------------- Receive Ports - RX Polarity Control Ports ----------------
707  RXPOLARITY => tied_to_ground_i,
708  ---------------------- Receive Ports - RX gearbox ports --------------------
709  RXSLIDE => tied_to_ground_i,
710  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
711  RXCHARISCOMMA(7 downto 2) => rxchariscomma_float_i ,
712  RXCHARISCOMMA(1 downto 0) => rxchariscomma_out,
713  RXCHARISK(7 downto 2) => rxcharisk_float_i,
714  RXCHARISK(1 downto 0) => rxcharisk_out,
715  ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
716  RXCHBONDI => "00000",
717  -------------- Receive Ports -RX Initialization and Reset Ports ------------
718  RXRESETDONE => rxresetdone_out,
719  -------------------------------- Rx AFE Ports ------------------------------
720  RXQPIEN => tied_to_ground_i,
721  RXQPISENN => open,
722  RXQPISENP => open,
723  --------------------------- TX Buffer Bypass Ports -------------------------
724  TXPHDLYTSTCLK => tied_to_ground_i,
725  ------------------------ TX Configurable Driver Ports ----------------------
726  TXPOSTCURSOR => "00000",
727  TXPOSTCURSORINV => tied_to_ground_i,
728  TXPRECURSOR => tied_to_ground_vec_i (4 downto 0),
729  TXPRECURSORINV => tied_to_ground_i,
730  TXQPIBIASEN => tied_to_ground_i,
731  TXQPISTRONGPDOWN => tied_to_ground_i,
732  TXQPIWEAKPUP => tied_to_ground_i,
733  --------------------- TX Initialization and Reset Ports --------------------
734  CFGRESET => tied_to_ground_i,
735  GTTXRESET => gttxreset_in,
736  PCSRSVDOUT => open,
737  TXUSERRDY => txuserrdy_in,
738  ---------------------- Transceiver Reset Mode Operation --------------------
739  GTRESETSEL => tied_to_ground_i,
740  RESETOVRD => tied_to_ground_i,
741  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
742  TXCHARDISPMODE => tied_to_ground_vec_i (7 downto 0),
743  TXCHARDISPVAL => tied_to_ground_vec_i (7 downto 0),
744  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
745  TXUSRCLK => txusrclk_in,
746  TXUSRCLK2 => txusrclk2_in,
747  --------------------- Transmit Ports - PCI Express Ports -------------------
748  TXELECIDLE => tied_to_ground_i,
749  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
750  TXRATE => tied_to_ground_vec_i (2 downto 0),
751  TXSWING => tied_to_ground_i,
752  ------------------ Transmit Ports - Pattern Generator Ports ----------------
753  TXPRBSFORCEERR => tied_to_ground_i,
754  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
755  TXDLYBYPASS => tied_to_vcc_i,
756  TXDLYEN => tied_to_ground_i,
757  TXDLYHOLD => tied_to_ground_i,
758  TXDLYOVRDEN => tied_to_ground_i,
759  TXDLYSRESET => tied_to_ground_i,
760  TXDLYSRESETDONE => open,
761  TXDLYUPDOWN => tied_to_ground_i,
762  TXPHALIGN => tied_to_ground_i,
763  TXPHALIGNDONE => open,
764  TXPHALIGNEN => tied_to_ground_i,
765  TXPHDLYPD => tied_to_ground_i,
766  TXPHDLYRESET => tied_to_ground_i,
767  TXPHINIT => tied_to_ground_i,
768  TXPHINITDONE => open,
769  TXPHOVRDEN => tied_to_ground_i,
770  ---------------------- Transmit Ports - TX Buffer Ports --------------------
771  TXBUFSTATUS => open,
772  --------------- Transmit Ports - TX Configurable Driver Ports --------------
773  TXBUFDIFFCTRL => "100",
774  TXDEEMPH => tied_to_ground_i,
775  TXDIFFCTRL => txdiffctrl_in,
776  TXDIFFPD => tied_to_ground_i,
777  TXINHIBIT => tied_to_ground_i,
778  TXMAINCURSOR => "0000000" ,
779  TXPISOPD => tied_to_ground_i,
780  ------------------ Transmit Ports - TX Data Path interface -----------------
781  TXDATA => txdata_i,
782  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
783  GTXTXN => gtxtxn_out,
784  GTXTXP => gtxtxp_out,
785  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
786  TXOUTCLK => txoutclk_out,
787  TXOUTCLKFABRIC => txoutclkfabric_out ,
788  TXOUTCLKPCS => txoutclkpcs_out,
789  TXOUTCLKSEL => "011",
790  TXRATEDONE => open,
791  --------------------- Transmit Ports - TX Gearbox Ports --------------------
792  TXCHARISK(7 downto 2) => tied_to_ground_vec_i (5 downto 0),
793  TXCHARISK(1 downto 0) => txcharisk_in,
794  TXGEARBOXREADY => open,
795  TXHEADER => tied_to_ground_vec_i (2 downto 0),
796  TXSEQUENCE => tied_to_ground_vec_i (6 downto 0),
797  TXSTARTSEQ => tied_to_ground_i,
798  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
799  TXPCSRESET => tied_to_ground_i,
800  TXPMARESET => tied_to_ground_i,
801  TXRESETDONE => txresetdone_out,
802  ------------------ Transmit Ports - TX OOB signalling Ports ----------------
803  TXCOMFINISH => open,
804  TXCOMINIT => tied_to_ground_i,
805  TXCOMSAS => tied_to_ground_i,
806  TXCOMWAKE => tied_to_ground_i,
807  TXPDELECIDLEMODE => tied_to_ground_i,
808  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
809  TXPOLARITY => tied_to_ground_i,
810  --------------- Transmit Ports - TX Receiver Detection Ports --------------
811  TXDETECTRX => tied_to_ground_i,
812  ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
813  TX8B10BBYPASS => tied_to_ground_vec_i (7 downto 0),
814  ------------------ Transmit Ports - pattern Generator Ports ----------------
815  TXPRBSSEL => txprbssel_in,
816  ----------------------- Tx Configurable Driver Ports ----------------------
817  TXQPISENN => open,
818  TXQPISENP => open
819 
820  );
821 
822 
823  end RTL;
824 
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