AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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TTC_trigger.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 09:29:47 08/28/2015
6 -- Design Name:
7 -- Module Name: TTC_trigger - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 
35 entity TTC_trigger is
36  generic(simulation : boolean := false);
37  Port ( reset : in STD_LOGIC; -- async reset
38  UsrClk : in STD_LOGIC;
39  TTCclk : in STD_LOGIC;
40  HammingData_in : in STD_LOGIC_VECTOR (17 downto 0);
41  HammingDataValid : in STD_LOGIC;
42  BC0 : in STD_LOGIC;
43  BcntMm : out STD_LOGIC;
44  TTC_lock : out STD_LOGIC;
45  BC0_lock : out STD_LOGIC;
46  TrigData : out STD_LOGIC_VECTOR (7 downto 0));
47 end TTC_trigger;
48 
49 architecture Behavioral of TTC_trigger is
50 signal TTC_lock_i : std_logic := '0';
51 signal BC0_lock_i : std_logic := '0';
52 signal Toggle : std_logic := '0';
53 signal ToggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
54 signal TTC_edge : std_logic_vector(6 downto 0) := (others => '0');
55 signal HammingDataValid_dl3 : std_logic := '0';
56 signal chk_HammingData : std_logic := '0';
57 signal OutStrobe : std_logic := '0';
58 signal rd_enable : std_logic := '0';
59 signal rd_TTC_data : std_logic := '0';
60 signal BC0_l : std_logic := '0';
61 signal BcntMm_i : std_logic := '0';
62 signal BC0_matchCntr : std_logic_vector(8 downto 0) := (others => '0');
63 signal HammingData : std_logic_vector(17 downto 0) := (others => '0');
64 signal TTC_data_we : std_logic := '0';
65 signal TTC_data_in : std_logic_vector(8 downto 0) := (others => '0');
66 signal TTC_data : std_logic_vector(8 downto 0) := (others => '0');
67 signal TTC_data_a : std_logic_vector(2 downto 0) := (others => '1');
68 signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
69 signal MmCntr : std_logic_vector(3 downto 0) := (others => '0');
70 signal GoodBcnt : std_logic_vector(3 downto 0) := (others => '0');
71 --signal BC0_link : std_logic := '0';
72 signal TrigData_d : std_logic_vector(8 downto 0) := (others => '0');
73 signal TrigData_i : std_logic_vector(8 downto 0) := (others => '0');
74 signal BC0_offset : std_logic_vector(3 downto 0) := (others => '0');
75 signal ec_delta_BC0 : std_logic := '0';
76 signal delta_BC0 : std_logic_vector(3 downto 0) := (others => '0');
77 signal sel_TTC_edge : std_logic_vector(2 downto 0) := (others => '0');
78 type array6x9 is array(0 to 5) of std_logic_vector(8 downto 0);
79 signal MatchCntr : array6x9 := (others => (others => '0'));
80 begin
81 TrigData <= TrigData_i(7 downto 0);
82 TTC_lock <= TTC_lock_i;
83 BC0_lock <= BC0_lock_i;
84 BcntMm <= BcntMm_i;
85 process(TTCclk)
86 begin
87  if(TTCclk'event and TTCclk = '1')then
88  Toggle <= not Toggle;
89  end if;
90 end process;
91 process(UsrClk,reset)
92 begin
93  if(reset = '1' or TTC_lock_i = '0')then
94  TTC_data_a <= (others => '1');
95  rd_enable <= '0';
96  rd_TTC_data <= '0';
97  elsif(UsrClk'event and UsrClk = '1')then
98  if(TTC_data_we = '1' and rd_TTC_data = '0')then
99  TTC_data_a <= TTC_data_a + 1;
100  elsif(TTC_data_we = '0' and rd_TTC_data = '1' and TTC_data_a /= "111")then
101  TTC_data_a <= TTC_data_a - 1;
102  end if;
103  if(TTC_data_a = "001")then
104  rd_enable <= '1';
105  end if;
106  if(TTC_edge(3) = '1' and rd_enable = '1')then
107  rd_TTC_data <= '1';
108  else
109  rd_TTC_data <= '0';
110  end if;
111  end if;
112 end process;
113 OutStrobe <= TTC_edge(4);
114 process(UsrClk)
115 variable reached256 : std_logic;
116 variable MatchCntr_MSB : std_logic_vector(5 downto 0);
117 begin
118  if(simulation)then
119  reached256 := MatchCntr(5)(4) or MatchCntr(4)(4) or MatchCntr(3)(4) or MatchCntr(2)(4) or MatchCntr(1)(4) or MatchCntr(0)(4);
120  MatchCntr_MSB := MatchCntr(5)(4) & MatchCntr(4)(4) & MatchCntr(3)(4) & MatchCntr(2)(4) & MatchCntr(1)(4) & MatchCntr(0)(4);
121  else
122  reached256 := MatchCntr(5)(8) or MatchCntr(4)(8) or MatchCntr(3)(8) or MatchCntr(2)(8) or MatchCntr(1)(8) or MatchCntr(0)(8);
123  MatchCntr_MSB := MatchCntr(5)(8) & MatchCntr(4)(8) & MatchCntr(3)(8) & MatchCntr(2)(8) & MatchCntr(1)(8) & MatchCntr(0)(8);
124  end if;
125  if(UsrClk'event and UsrClk = '1')then
126  ToggleSyncRegs <= ToggleSyncRegs(2 downto 0) & Toggle;
127  TTC_edge <= TTC_edge(5 downto 0) & (ToggleSyncRegs(3) xor ToggleSyncRegs(2));
128  if(TTC_lock_i = '0')then
129  chk_HammingData <= HammingDataValid_dl3;
130  else
131  chk_HammingData <= TTC_edge(conv_integer(sel_TTC_edge));
132  end if;
133  if((chk_HammingData = '1' and BC0_l = '1') or TTC_lock_i = '1')then
134  MatchCntr <= (others => (others => '0'));
135  elsif(chk_HammingData = '1' and reached256 = '0')then
136  for i in 0 to 5 loop
137  if(TTC_edge(i+1) = '1')then
138  MatchCntr(i) <= MatchCntr(i) + 1;
139  end if;
140  end loop;
141  end if;
142  if(chk_HammingData = '1' and BC0_l = '1' and TTC_lock_i = '0')then
143  sel_TTC_edge(2) <= MatchCntr_MSB(4) or MatchCntr_MSB(5);
144  sel_TTC_edge(1) <= not MatchCntr_MSB(5) and (MatchCntr_MSB(2) or MatchCntr_MSB(3));
145  sel_TTC_edge(0) <= MatchCntr_MSB(5) or (not MatchCntr_MSB(4) and (MatchCntr_MSB(3) or (not MatchCntr_MSB(2) and MatchCntr_MSB(1))));
146  end if;
147  if(chk_HammingData = '1')then
148  if(TTC_lock_i = '0' and HammingData(17 downto 16) = "11")then
149  bcnt <= x"001";
150  BC0_l <= '0';
151  elsif(simulation and bcnt = x"10f")then
152  bcnt <= x"cd0";
153  elsif(bcnt = x"deb")then
154  bcnt <= x"000";
155  BC0_l <= '1';
156  else
157  bcnt <= bcnt + 1;
158  BC0_l <= '0';
159  end if;
160  end if;
161 -- if(OutStrobe = '1')then
162 -- TrigData <= TTC_data(7 downto 0);
163 -- BC0_link <= TTC_data(8);
164 -- end if;
165  if(OutStrobe = '1')then
166  TrigData_d <= TTC_data;
167  end if;
168  if(chk_HammingData = '1' and bcnt(3 downto 0) /= HammingData(15 downto 12))then
169  BcntMm_i <= '1';
170  else
171  BcntMm_i <= '0';
172  end if;
173  if(TTC_lock_i = '1')then
174  BC0_matchCntr <= (others => '0');
175  elsif(chk_HammingData = '1' and HammingData(17 downto 16) = "11")then
176  if(BC0_l = '0')then
177  BC0_matchCntr <= (others => '0');
178  else
179  BC0_matchCntr <= BC0_matchCntr + 1;
180  end if;
181  end if;
182  if(TTC_lock_i = '0')then
183  MmCntr <= (others => '0');
184  elsif(BcntMm_i = '1')then
185  MmCntr <= MmCntr + 1;
186  elsif(GoodBcnt(3) = '1')then
187  MmCntr <= MmCntr - 1;
188  end if;
189  if(or_reduce(MmCntr) = '0' or GoodBcnt(3) = '1' or BcntMm_i = '1')then
190  GoodBcnt <= (others => '0');
191  elsif(chk_HammingData = '1')then
192  GoodBcnt <= GoodBcnt + 1;
193  end if;
194  if(MmCntr(3) = '1')then
195  TTC_lock_i <= '0';
196  elsif(BC0_matchCntr(8) = '1' or (simulation and BC0_matchCntr(2) = '1'))then
197  TTC_lock_i <= '1';
198  end if;
199  if(HammingDataValid = '1')then
200  HammingData <= HammingData_in;
201  end if;
202  if(HammingData(17) = HammingData(16) and HammingData(17) = BC0_l and bcnt(3 downto 0) = HammingData(15 downto 12) and BC0_lock_i = '1')then
203  TTC_data_in <= BC0_l & HammingData(7 downto 0);
204  else
205  TTC_data_in <= BC0_l & x"00";
206  end if;
207  if(chk_HammingData = '1')then
208  TTC_data_we <= '1';
209  else
210  TTC_data_we <= '0';
211  end if;
212  end if;
213 end process;
214 i_HammingDataValid_dl3 : SRL16E
215  port map (
216  Q => HammingDataValid_dl3, -- SRL data output
217  A0 => '0', -- Select[0] input
218  A1 => '1', -- Select[1] input
219  A2 => '0', -- Select[2] input
220  A3 => '0', -- Select[3] input
221  CE => '1', -- Clock enable input
222  CLK => UsrClk, -- Clock input
223  D => HammingDataValid -- SRL data input
224  );
225 g_TTC_data : for i in 0 to 8 generate
226  i_TTC_data : SRL16E
227  port map (
228  Q => TTC_data(i), -- SRL data output
229  A0 => TTC_data_a(0), -- Select[0] input
230  A1 => TTC_data_a(1), -- Select[1] input
231  A2 => TTC_data_a(2), -- Select[2] input
232  A3 => '0', -- Select[3] input
233  CE => TTC_data_we, -- Clock enable input
234  CLK => UsrClk, -- Clock input
235  D => TTC_data_in(i) -- SRL data input
236  );
237 end generate;
238 g_TrigData : for i in 0 to 8 generate
239  i_TrigData : SRL16E
240  port map (
241  Q => TrigData_i(i), -- SRL data output
242  A0 => BC0_offset(0), -- Select[0] input
243  A1 => BC0_offset(1), -- Select[1] input
244  A2 => BC0_offset(2), -- Select[2] input
245  A3 => BC0_offset(3), -- Select[3] input
246  CE => '1', -- Clock enable input
247  CLK => TTCclk, -- Clock input
248  D => TrigData_d(i) -- SRL data input
249  );
250 end generate;
251 process(TTCclk, reset, TTC_lock_i)
252 begin
253  if(reset = '1' or TTC_lock_i = '0')then
254  ec_delta_BC0 <= '0';
255  delta_BC0 <= (others => '0');
256  BC0_offset <= (others => '0');
257  BC0_lock_i <= '0';
258  elsif(TTCclk'event and TTCclk = '1')then
259 -- if(BC0_link = '1')then
260  if(TrigData_d(8) = '1')then
261  ec_delta_BC0 <= '1';
262  elsif(BC0 = '1' or delta_BC0 = x"f")then
263  ec_delta_BC0 <= '0';
264  end if;
265  if(ec_delta_BC0 = '0')then
266  delta_BC0 <= (others => '0');
267  else
268  delta_BC0 <= delta_BC0 + 1;
269  end if;
270  if(BC0 = '1')then
271  if(ec_delta_BC0 = '1')then
272  BC0_offset <= delta_BC0;
273  BC0_lock_i <= '1';
274  else
275  BC0_offset <= (others => '0');
276  BC0_lock_i <= '0';
277  end if;
278  end if;
279  end if;
280 end process;
281 
282 end Behavioral;
283