1 ----------------------------------------------------------------------------------
5 -- Create Date: 09:
29:
47 08/28/2015
7 -- Module Name: TTC_trigger - Behavioral
16 -- Revision 0.
01 -
File Created
17 -- Additional Comments:
19 ----------------------------------------------------------------------------------
21 use IEEE.STD_LOGIC_1164.
ALL;
22 use IEEE.STD_LOGIC_ARITH.
ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.
ALL;
24 use IEEE.std_logic_misc.
all;
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with or values
28 --use IEEE.NUMERIC_STD.ALL;
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
33 use UNISIM.VComponents.
all;
36 generic(simulation : := false);
37 Port ( reset : in ;
-- async reset
40 HammingData_in : in (17 downto 0);
41 HammingDataValid : in ;
46 TrigData : out (7 downto 0));
50 signal TTC_lock_i : := '0';
51 signal BC0_lock_i : := '0';
52 signal Toggle : := '0';
53 signal ToggleSyncRegs : (3 downto 0) := (others => '0');
54 signal TTC_edge : (6 downto 0) := (others => '0');
55 signal HammingDataValid_dl3 : := '0';
56 signal chk_HammingData : := '0';
57 signal OutStrobe : := '0';
58 signal rd_enable : := '0';
59 signal rd_TTC_data : := '0';
60 signal BC0_l : := '0';
61 signal BcntMm_i : := '0';
62 signal BC0_matchCntr : (8 downto 0) := (others => '0');
63 signal HammingData : (17 downto 0) := (others => '0');
64 signal TTC_data_we : := '0';
65 signal TTC_data_in : (8 downto 0) := (others => '0');
66 signal TTC_data : (8 downto 0) := (others => '0');
67 signal TTC_data_a : (2 downto 0) := (others => '1');
68 signal bcnt : (11 downto 0) := (others => '0');
69 signal MmCntr : (3 downto 0) := (others => '0');
70 signal GoodBcnt : (3 downto 0) := (others => '0');
71 --signal BC0_link : := '0';
72 signal TrigData_d : (8 downto 0) := (others => '0');
73 signal TrigData_i : (8 downto 0) := (others => '0');
74 signal BC0_offset : (3 downto 0) := (others => '0');
75 signal ec_delta_BC0 : := '0';
76 signal delta_BC0 : (3 downto 0) := (others => '0');
77 signal sel_TTC_edge : (2 downto 0) := (others => '0');
78 type array6x9 is array(0 to 5) of (8 downto 0);
79 signal MatchCntr : array6x9 := (others => (others => '0'));
81 TrigData <= TrigData_i(7 downto 0);
82 TTC_lock <= TTC_lock_i;
83 BC0_lock <= BC0_lock_i;
87 if(TTCclk'event and TTCclk = '1')then
93 if(reset = '1' or TTC_lock_i = '0')then
94 TTC_data_a <= (others => '1');
97 elsif(UsrClk'event and UsrClk = '1')then
98 if(TTC_data_we = '1' and rd_TTC_data = '0')then
99 TTC_data_a <= TTC_data_a + 1;
100 elsif(TTC_data_we = '0' and rd_TTC_data = '1' and TTC_data_a /= "111")then
101 TTC_data_a <= TTC_data_a - 1;
103 if(TTC_data_a = "001")then
106 if(TTC_edge(3) = '1' and rd_enable = '1')then
113 OutStrobe <= TTC_edge(4);
115 variable reached256 : ;
116 variable MatchCntr_MSB : (5 downto 0);
119 reached256 := MatchCntr(5)(4) or MatchCntr(4)(4) or MatchCntr(3)(4) or MatchCntr(2)(4) or MatchCntr(1)(4) or MatchCntr(0)(4);
120 MatchCntr_MSB := MatchCntr(5)(4) & MatchCntr(4)(4) & MatchCntr(3)(4) & MatchCntr(2)(4) & MatchCntr(1)(4) & MatchCntr(0)(4);
122 reached256 := MatchCntr(5)(8) or MatchCntr(4)(8) or MatchCntr(3)(8) or MatchCntr(2)(8) or MatchCntr(1)(8) or MatchCntr(0)(8);
123 MatchCntr_MSB := MatchCntr(5)(8) & MatchCntr(4)(8) & MatchCntr(3)(8) & MatchCntr(2)(8) & MatchCntr(1)(8) & MatchCntr(0)(8);
125 if(UsrClk'event and UsrClk = '1')then
126 ToggleSyncRegs <= ToggleSyncRegs(2 downto 0) & Toggle;
127 TTC_edge <= TTC_edge(5 downto 0) & (ToggleSyncRegs(3) xor ToggleSyncRegs(2));
128 if(TTC_lock_i = '0')then
129 chk_HammingData <= HammingDataValid_dl3;
131 chk_HammingData <= TTC_edge(conv_integer(sel_TTC_edge));
133 if((chk_HammingData = '1' and BC0_l = '1') or TTC_lock_i = '1')then
134 MatchCntr <= (others => (others => '0'));
135 elsif(chk_HammingData = '1' and reached256 = '0')then
137 if(TTC_edge(i+1) = '1')then
138 MatchCntr(i) <= MatchCntr(i) + 1;
142 if(chk_HammingData = '1' and BC0_l = '1' and TTC_lock_i = '0')then
143 sel_TTC_edge(2) <= MatchCntr_MSB(4) or MatchCntr_MSB(5);
144 sel_TTC_edge(1) <= not MatchCntr_MSB(5) and (MatchCntr_MSB(2) or MatchCntr_MSB(3));
145 sel_TTC_edge(0) <= MatchCntr_MSB(5) or (not MatchCntr_MSB(4) and (MatchCntr_MSB(3) or (not MatchCntr_MSB(2) and MatchCntr_MSB(1))));
147 if(chk_HammingData = '1')then
148 if(TTC_lock_i = '0' and HammingData(17 downto 16) = "11")then
151 elsif(simulation and bcnt = x"10f")then
153 elsif(bcnt = x"deb")then
161 -- if(OutStrobe = '1')then
162 -- TrigData <= TTC_data(7 downto 0);
163 -- BC0_link <= TTC_data(8);
165 if(OutStrobe = '1')then
166 TrigData_d <= TTC_data;
168 if(chk_HammingData = '1' and bcnt(3 downto 0) /= HammingData(15 downto 12))then
173 if(TTC_lock_i = '1')then
174 BC0_matchCntr <= (others => '0');
175 elsif(chk_HammingData = '1' and HammingData(17 downto 16) = "11")then
177 BC0_matchCntr <= (others => '0');
179 BC0_matchCntr <= BC0_matchCntr + 1;
182 if(TTC_lock_i = '0')then
183 MmCntr <= (others => '0');
184 elsif(BcntMm_i = '1')then
185 MmCntr <= MmCntr + 1;
186 elsif(GoodBcnt(3) = '1')then
187 MmCntr <= MmCntr - 1;
189 if(or_reduce(MmCntr) = '0' or GoodBcnt(3) = '1' or BcntMm_i = '1')then
190 GoodBcnt <= (others => '0');
191 elsif(chk_HammingData = '1')then
192 GoodBcnt <= GoodBcnt + 1;
194 if(MmCntr(3) = '1')then
196 elsif(BC0_matchCntr(8) = '1' or (simulation and BC0_matchCntr(2) = '1'))then
199 if(HammingDataValid = '1')then
200 HammingData <= HammingData_in;
202 if(HammingData(17) = HammingData(16) and HammingData(17) = BC0_l and bcnt(3 downto 0) = HammingData(15 downto 12) and BC0_lock_i = '1')then
203 TTC_data_in <= BC0_l & HammingData(7 downto 0);
205 TTC_data_in <= BC0_l & x"00";
207 if(chk_HammingData = '1')then
214 i_HammingDataValid_dl3 : SRL16E
216 Q => HammingDataValid_dl3,
-- SRL data output
217 A0 => '0',
-- Select[0] input
218 A1 => '1',
-- Select[1] input
219 A2 => '0',
-- Select[2] input
220 A3 => '0',
-- Select[3] input
221 CE => '1',
-- Clock enable input
222 CLK => UsrClk,
-- Clock input
223 D => HammingDataValid
-- SRL data input
225 g_TTC_data : for i in 0 to 8 generate
228 Q => TTC_data
(i
),
-- SRL data output
229 A0 => TTC_data_a
(0),
-- Select[0] input
230 A1 => TTC_data_a
(1),
-- Select[1] input
231 A2 => TTC_data_a
(2),
-- Select[2] input
232 A3 => '0',
-- Select[3] input
233 CE => TTC_data_we,
-- Clock enable input
234 CLK => UsrClk,
-- Clock input
235 D => TTC_data_in
(i
) -- SRL data input
238 g_TrigData : for i in 0 to 8 generate
241 Q => TrigData_i
(i
),
-- SRL data output
242 A0 => BC0_offset
(0),
-- Select[0] input
243 A1 => BC0_offset
(1),
-- Select[1] input
244 A2 => BC0_offset
(2),
-- Select[2] input
245 A3 => BC0_offset
(3),
-- Select[3] input
246 CE => '1',
-- Clock enable input
247 CLK => TTCclk,
-- Clock input
248 D => TrigData_d
(i
) -- SRL data input
251 process(TTCclk, reset, TTC_lock_i)
253 if(reset = '1' or TTC_lock_i = '0')then
255 delta_BC0 <= (others => '0');
256 BC0_offset <= (others => '0');
258 elsif(TTCclk'event and TTCclk = '1')then
259 -- if(BC0_link = '1')then
260 if(TrigData_d(8) = '1')then
262 elsif(BC0 = '1' or delta_BC0 = x"f")then
265 if(ec_delta_BC0 = '0')then
266 delta_BC0 <= (others => '0');
268 delta_BC0 <= delta_BC0 + 1;
271 if(ec_delta_BC0 = '1')then
272 BC0_offset <= delta_BC0;
275 BC0_offset <= (others => '0');