AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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TCP_CC.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 09:47:17 10/04/2013
6 -- Design Name:
7 -- Module Name: TCP_CC - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use IEEE.numeric_std.all;
26 
27 -- Uncomment the following library declaration if using
28 -- arithmetic functions with Signed or Unsigned values
29 --use IEEE.NUMERIC_STD.ALL;
30 
31 -- Uncomment the following library declaration if instantiating
32 -- any Xilinx primitives in this code.
33 --library UNISIM;
34 --use UNISIM.VComponents.all;
35 
36 entity TCP_CC is
37  Port ( clk : in STD_LOGIC;
38  reset : in STD_LOGIC;
39  SYNRCVD : in STD_LOGIC;
40  RETX_TO : in STD_LOGIC;
41  Save_ReTx : in STD_LOGIC;
42  FastReTxStart : in STD_LOGIC;
43  FR : in STD_LOGIC;
44  PartialACK : in STD_LOGIC;
45  NewDataACK : in STD_LOGIC;
46  DupACK : in STD_LOGIC;
47  MSS : in STD_LOGIC_VECTOR (15 downto 0);
48 -- CWND_max : in STD_LOGIC_VECTOR (31 downto 0);
49  SEG_WND : in STD_LOGIC_VECTOR (31 downto 0);
50  SND_UNA : in STD_LOGIC_VECTOR (31 downto 0);
51  SND_NXT : in STD_LOGIC_VECTOR (31 downto 0);
52  CWND : out STD_LOGIC_VECTOR (31 downto 0);
53  SND_WND_UL : out STD_LOGIC_VECTOR (31 downto 0);
54  debug : out STD_LOGIC_VECTOR (271 downto 0)
55  );
56 end TCP_CC;
57 
58 architecture Behavioral of TCP_CC is
59 signal SND_UNA_OLD : std_logic_vector(31 downto 0) := (others => '0');
60 signal DataACKed : std_logic_vector(31 downto 0) := (others => '0');
61 signal DataACKedSUM : std_logic_vector(31 downto 0) := (others => '0');
62 signal MSS_old : std_logic_vector(15 downto 0) := (others => '0');
63 signal MSSx2 : std_logic_vector(27 downto 0) := (others => '0');
64 signal MSSx3 : std_logic_vector(27 downto 0) := (others => '0');
65 signal CWND_i : std_logic_vector(31 downto 0) := (others => '0');
66 signal CWND_INC : std_logic_vector(27 downto 0) := (others => '0');
67 signal CWND_FAST : std_logic_vector(27 downto 0) := (others => '0');
68 signal SSTHRESH : std_logic_vector(27 downto 0) := (others => '0');
69 signal CWND_sub_SSTHRESH : std_logic_vector(27 downto 0) := (others => '0');
70 signal FLIGHT_SIZE : std_logic_vector(31 downto 0) := (others => '0');
71 signal FLIGHT_SIZEplusMSS : std_logic_vector(27 downto 0) := (others => '0');
72 signal StartFlightSize : std_logic_vector(27 downto 0) := (others => '0');
73 signal SSTHRESH_RETX : std_logic_vector(27 downto 0) := (others => '0');
74 signal New_TO : std_logic := '0';
75 signal SS : std_logic := '0';
76 signal CA : std_logic := '0';
77 --signal FR : std_logic := '0';
78 signal PartACK : std_logic := '0';
79 signal FullACK : std_logic_vector(2 downto 0) := (others => '0');
80 signal NewDataACK_dl : std_logic_vector(1 downto 0) := (others => '0');
81 signal DataACKedSUM_GT_CWND : std_logic := '0';
82 
83 begin
84 debug(121 downto 94) <= FLIGHT_SIZE(27 downto 0);
85 debug(93 downto 66) <= SSTHRESH;
86 debug(65 downto 38) <= CWND_FAST;
87 debug(37 downto 10) <= CWND_i(27 downto 0);
88 debug(9) <= DupACK;
89 debug(8) <= PartialACK ;
90 debug(7) <= New_TO;
91 debug(6) <= RETX_TO;
92 debug(5) <= NewDataACK;
93 debug(4) <= FastReTxStart;
94 debug(3) <= PartACK;
95 debug(2) <= FR;
96 debug(1) <= CA;
97 debug(0) <= SS;
98 --debug(263 downto 232) <= FLIGHT_SIZE;
99 --debug(231 downto 200) <= x"0" & SSTHRESH;
100 --debug(199 downto 168) <= x"0" & CWND_FAST;
101 --debug(167 downto 136) <= x"0" & CWND_INC;
102 --debug(127 downto 96) <= x"0" & CWND_i;
103 --debug(95 downto 64) <= DataACKedSUM;
104 --debug(63) <= DupACK;
105 --debug(62) <= PartialACK ;
106 --debug(61) <= DataACKedSUM_GT_CWND;
107 --debug(59) <= New_TO;
108 --debug(58) <= RETX_TO;
109 --debug(57) <= NewDataACK;
110 --debug(56) <= FastReTxStart;
111 --debug(55) <= PartACK;
112 --debug(54) <= FR;
113 --debug(53) <= CA;
114 --debug(52) <= SS;
115 --debug(51 downto 32) <= DataACKed(19 downto 0);
116 --debug(31 downto 0) <= SND_UNA;
117 MSSx2(16 downto 1) <= MSS;
118 CWND <= CWND_i;
119 process(clk)
120 begin
121  if(clk'event and clk = '1')then
122 -- if(CWND_i > CWND_max)then
123 -- CWND <= CWND_max;
124 -- else
125 -- CWND <= CWND_i;
126 -- end if;
127  if(FR = '0')then
128  StartFlightSize <= FLIGHT_SIZE(27 downto 0);
129  end if;
130  if(Save_ReTx = '1')then
131  SND_WND_UL <= SND_NXT + ('0' & StartFlightSize(27 downto 1));
132  end if;
133  SND_UNA_OLD <= SND_UNA;
134  DataACKed <= SND_UNA - SND_UNA_OLD;
135  NewDataACK_dl <= NewDataACK_dl(0) & NewDataACK;
136  if(CA = '0' or DataACKedSUM_GT_CWND = '1')then
137  DataACKedSUM <= (others => '0');
138  elsif(NewDataACK_dl(0) = '1')then
139  DataACKedSUM <= DataACKedSUM + DataACKed;
140  end if;
141  if(CA = '1' and DataACKedSUM > CWND_i and NewDataACK_dl(1) = '1')then
142  DataACKedSUM_GT_CWND <= '1';
143  else
144  DataACKedSUM_GT_CWND <= '0';
145  end if;
146  if((or_reduce(DataACKed(31 downto 16)) = '1' or DataACKed(15 downto 0) >= MSS) and FR = '1' and NewDataACK_dl(0) = '1' and PartialACK = '1')then
147  PartACK <= '1';
148  else
149  PartACK <= '0';
150  end if;
151  if(SS = '1' and or_reduce(DataACKed(31 downto 16)) = '0' and DataACKed(15 downto 0) < MSS)then
152  CWND_INC(15 downto 0) <= DataACKed(15 downto 0);
153  else
154  CWND_INC(15 downto 0) <= MSS;
155  end if;
156  FullACK <= FullACK(1 downto 0) & (FR and NewDataACK and not PartialACK);
157  CWND_sub_SSTHRESH <= CWND_i(27 downto 0) - SSTHRESH;
158  MSS_old <= MSS;
159  if(reset = '1')then
160  CWND_i(27 downto 0) <= x"0000430";
161  elsif(MSS /= MSS_old)then
162  CWND_i(27 downto 0) <= MSSx2;
163  elsif(RETX_TO = '1')then
164  CWND_i <= x"0000" & MSS;
165  elsif(FastReTxStart = '1' or FullACK(2) = '1')then
166  CWND_i(27 downto 0) <= CWND_FAST;
167  elsif(FR = '1' and NewDataACK_dl(0) = '1' and PartialACK = '1')then
168  if(CWND_sub_SSTHRESH > DataACKed(27 downto 0) and DataACKed(31 downto 28) = x"0")then
169  CWND_i(27 downto 0) <= CWND_i(27 downto 0) - DataACKed(27 downto 0);
170  else
171  CWND_i(27 downto 0) <= SSTHRESH;
172  end if;
173  elsif(CWND_i(27) = '0' and ((SS = '1' and NewDataACK_dl(1) = '1') or DataACKedSUM_GT_CWND = '1' or (FR = '1' and DupACK = '1') or PartACK = '1'))then
174  CWND_i(27 downto 0) <= CWND_i(27 downto 0) + CWND_INC;
175  end if;
176  MSSx3 <= MSSx2 + (x"000" & MSS);
177  if(FR = '0')then
178  CWND_FAST <= ('0' & FLIGHT_SIZE(27 downto 1)) + MSSx3;
179  elsif(FLIGHT_SIZEplusMSS > SSTHRESH)then
180  CWND_FAST <= SSTHRESH;
181  else
182  CWND_FAST <= FLIGHT_SIZEplusMSS; -- this is MSS added by the flight size before the NewDataACK arrives
183  end if;
184  if(FR = '1')then
185  SS <= '0';
186  CA <= '0';
187  elsif(CWND_i(27 downto 0) < SSTHRESH)then
188  SS <= '1';
189  CA <= '0';
190  else
191  SS <= '0';
192  CA <= '1';
193  end if;
194  if(reset = '1' or NewDataACK = '1')then
195  New_TO <= '1';
196  elsif(RETX_TO = '1')then
197  New_TO <= '0';
198  end if;
199  if(SYNRCVD = '1')then
200  if(SEG_WND(31 downto 27) = "00000")then
201  SSTHRESH <= SEG_WND(27 downto 0);
202  else
203  SSTHRESH <= x"3ffffff";
204  end if;
205  elsif((RETX_TO = '1' and New_TO = '1') or FastReTxStart = '1')then
206  SSTHRESH <= SSTHRESH_RETX;
207  end if;
208  FLIGHT_SIZE <= SND_NXT - SND_UNA;
209  if(FLIGHT_SIZE > (x"000" & MSS))then
210  FLIGHT_SIZEplusMSS <= FLIGHT_SIZE(27 downto 0) + (x"000" & MSS);
211  else
212  FLIGHT_SIZEplusMSS <= MSSx2;
213  end if;
214  if(FLIGHT_SIZE(27 downto 1) > MSSx2(26 downto 0))then
215  SSTHRESH_RETX <= '0' & FLIGHT_SIZE(27 downto 1);
216  else
217  SSTHRESH_RETX <= MSSx2;
218  end if;
219  end if;
220 end process;
221 
222 end Behavioral;
223 
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