AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
DAQ_Link_7S.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:25:43 01/28/2012
6 -- Design Name:
7 -- Module Name: miniCTR - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity DAQ_Link_7S is
38  Generic (
39  simulation : boolean := false);
40  Port (
41  reset : in STD_LOGIC; -- asynchronous reset, assert reset until GTX REFCLK stable
42  USE_TRIGGER_PORT : boolean;
43 -- MGT signals
44  UsrClk : in STD_LOGIC; -- it must have a frequency of 250MHz
45  cplllock : in STD_LOGIC;
46  RxResetDone : in STD_LOGIC;
47  txfsmresetdone : in STD_LOGIC;
48  RXNOTINTABLE : in STD_LOGIC_VECTOR (1 downto 0);
49  RXCHARISCOMMA : in STD_LOGIC_VECTOR (1 downto 0);
50  RXCHARISK : in STD_LOGIC_VECTOR (1 downto 0);
51  RXDATA : in STD_LOGIC_VECTOR (15 downto 0);
52  TXCHARISK : out STD_LOGIC_VECTOR (1 downto 0);
53  TXDATA : out STD_LOGIC_VECTOR (15 downto 0);
54 -- TRIGGER port
55  TTCclk : in STD_LOGIC;
56  BcntRes : in STD_LOGIC;
57  trig : in STD_LOGIC_VECTOR (7 downto 0);
58 -- TTS port
59  TTSclk : in STD_LOGIC; -- clock source which clocks TTS signals
60  TTS : in STD_LOGIC_VECTOR (3 downto 0);
61 -- Data port
62  EventDataClk : in STD_LOGIC;
63  EventData_valid : in STD_LOGIC; -- used as data write enable
64  EventData_header : in STD_LOGIC; -- first data word
65  EventData_trailer : in STD_LOGIC; -- last data word
66  EventData : in STD_LOGIC_VECTOR (63 downto 0);
67  AlmostFull : out STD_LOGIC; -- buffer almost full
68  Ready : out STD_LOGIC;
69  sysclk : in STD_LOGIC;
70  L1A_DATA_we : out STD_LOGIC; -- last data word
71  L1A_DATA : out STD_LOGIC_VECTOR (15 downto 0)
72  );
73 end DAQ_Link_7S;
74 
75 architecture Behavioral of DAQ_Link_7S is
76 COMPONENT crc16D16
77  PORT(
78  clk : IN std_logic;
79  init_crc : IN std_logic;
80  we_crc : IN std_logic;
81  d : IN std_logic_vector(15 downto 0);
82  crc : OUT std_logic_vector(15 downto 0)
83  );
84 END COMPONENT;
85 COMPONENT EthernetCRCD32
86  PORT(
87  clk : IN std_logic;
88  init : IN std_logic;
89  ce : IN std_logic;
90  d : IN std_logic_vector(31 downto 0);
91  crc : OUT std_logic_vector(31 downto 0);
92  bad_crc : OUT std_logic
93  );
94 END COMPONENT;
95 COMPONENT TTS_TRIG_if
96  PORT(
97  reset : IN std_logic;
98  USE_TRIGGER_PORT : boolean;
99  UsrClk : IN std_logic;
100  TTCclk : IN std_logic;
101  BcntRes : IN std_logic;
102  trig : IN std_logic_vector(7 downto 0);
103  TTSclk : IN std_logic;
104  TTS : IN std_logic_vector(3 downto 0);
105  RXCHARISK : IN std_logic_vector(1 downto 0);
106  RXDATA : IN std_logic_vector(15 downto 0);
107  sel_TTS_TRIG : OUT std_logic;
108  TTS_TRIG_data : OUT std_logic_vector(17 downto 0)
109  );
110 END COMPONENT;
111 COMPONENT FIFO_RESET_7S
112  PORT(
113  reset : IN std_logic;
114  clk : IN std_logic;
115  fifo_rst : OUT std_logic;
116  fifo_en : OUT std_logic
117  );
118 END COMPONENT;
119 constant N : integer := 8;
120 constant Acknowledge : std_logic_vector(7 downto 0) := x"12";
121 constant version : std_logic_vector(7 downto 0) := x"0e";
122 constant data : std_logic_vector(7 downto 0) := x"34";
123 constant InitRqst : std_logic_vector(7 downto 0) := x"56";
124 constant Counter : std_logic_vector(7 downto 0) := x"78";
125 constant K_word : std_logic_vector(15 downto 0) := x"3cbc"; -- sequence K28.5 K28.1
126 constant R_word : std_logic_vector(15 downto 0) := x"dcfb"; -- sequence K27.7 K28.6
127 constant eof_word : std_logic_vector(15 downto 0) := x"5cf7"; -- sequence K23.7 K28.2
128 constant IDLE : std_logic_vector(3 downto 0) := x"0"; -- TxState
129 constant SendK : std_logic_vector(3 downto 0) := x"1"; -- TxState sending comma
130 constant SendType : std_logic_vector(3 downto 0) := x"2"; -- TxState sending event data words
131 constant SendSEQ : std_logic_vector(3 downto 0) := x"3"; -- TxState sending sequence number
132 constant SendWC : std_logic_vector(3 downto 0) := x"4"; -- TxState sending payload word count
133 constant WaitCRC : std_logic_vector(3 downto 0) := x"5"; -- TxState same as IDLE
134 constant WaitData : std_logic_vector(3 downto 0) := x"6"; -- TxState same as IDLE, used during sending packets
135 constant SendCRC : std_logic_vector(3 downto 0) := x"7"; -- TxState sending CRC
136 constant SendData : std_logic_vector(3 downto 0) := x"8"; -- TxState sending event data words
137 constant SendCntr : std_logic_vector(3 downto 0) := x"9"; -- TxState sending event data words
138 constant SendEOF : std_logic_vector(3 downto 0) := x"a"; -- TxState sending EOF
139 signal TxState: std_logic_vector(3 downto 0) := (others => '0');
140 signal sel_TTS_TRIG : std_logic := '0';
141 signal bcnt_err_cnt : std_logic_vector(3 downto 0) := (others => '0');
142 signal reset_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
143 signal RxResetDoneSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
144 signal DATA_VALID : std_logic := '0';
145 signal UsrClkDiv : std_logic_vector(1 downto 0) := (others => '0');
146 signal TTS_TRIG_data : std_logic_vector(17 downto 0) := (others => '0');
147 signal fifo_reset : std_logic := '0';
148 signal AlmostFull_i : std_logic := '0';
149 signal AlmostFull_sync : std_logic_vector(2 downto 0) := (others => '0');
150 signal Init_EventCRC : std_logic := '0';
151 signal ce_EventCRC : std_logic := '0';
152 signal EventCRC_d : std_logic_vector(31 downto 0) := (others => '0');
153 signal EventCRC : std_logic_vector(31 downto 0) := (others => '0');
154 signal BoE : std_logic := '0';
155 signal EoE : std_logic := '0';
156 signal FillDataBuf : std_logic := '0';
157 signal dataBuf_WrEn : std_logic := '0';
158 signal DataBuf_wa : std_logic_vector(14 downto 0) := (others => '0');
159 signal DataBuf_ra : std_logic_vector(14 downto 0) := (others => '0');
160 signal DataBuf_start : std_logic_vector(14 downto 0) := (others => '0');
161 signal DataBuf_Din : std_logic_vector(16 downto 0) := (others => '0');
162 signal DataBuf_Dout : std_logic_vector(16 downto 0) := (others => '0');
163 signal ec_DataBuf_ra : std_logic := '0';
164 signal ec_DataBuf_ra_q : std_logic := '0';
165 signal DataBuf_full : std_logic := '0';
166 signal DataBuf_used : std_logic_vector(14 downto 0) := (others => '0');
167 signal DataBuf_wc : std_logic_vector(14 downto 0) := (others => '0');
168 signal ReSendQueOut_q : std_logic_vector(14 downto 0) := (others => '0');
169 signal ReSendQue_a : std_logic_vector(1 downto 0) := (others => '1');
170 signal ReSendQue_empty : std_logic := '1';
171 signal we_DataPipe : std_logic := '0';
172 signal DataPipeDo : std_logic_vector(16 downto 0) := (others => '0');
173 signal DataPipe_a : std_logic_vector(3 downto 0) := (others => '1');
174 signal DataPipe_empty : std_logic := '1';
175 signal EventStatus_empty : std_logic := '1';
176 signal DataPipe_full : std_logic := '0';
177 signal InitLink : std_logic := '0';
178 signal InitACK : std_logic := '0';
179 signal ReSend : std_logic := '0';
180 signal Ready_i : std_logic := '1';
181 signal FoundEOF : std_logic := '0';
182 signal ACK : std_logic := '0';
183 signal CntrACK : std_logic := '0';
184 signal L1Aabort : std_logic := '0';
185 signal timer : std_logic_vector(N downto 0) := (others => '0');
186 signal we_ReSendQue : std_logic := '0';
187 signal we_TxCRC : std_logic := '0';
188 signal Init_TxCRC : std_logic := '0';
189 signal R_word_cnt : std_logic_vector(11 downto 0) := (others => '0');
190 signal TxCRC : std_logic_vector(15 downto 0) := (others => '0');
191 signal R_word_sent : std_logic := '0';
192 signal sel_cntr : std_logic := '0';
193 signal we_TxFIFO : std_logic := '0';
194 signal TxFIFO_empty : std_logic := '1';
195 signal TxFIFO_full : std_logic := '0';
196 signal TxFIFO_a : std_logic_vector(3 downto 0) := (others => '1');
197 signal TxFIFO_Dip : std_logic_vector(15 downto 0) := (others => '0');
198 signal TxFIFO_Di : std_logic_vector(16 downto 0) := (others => '0');
199 signal TxFIFO_Do : std_logic_vector(16 downto 0) := (others => '0');
200 signal packet_wc : std_logic_vector(15 downto 0) := (others => '0');
201 signal ACKNUM_IN : std_logic_vector(7 downto 0) := x"00";
202 signal RxSEQNUM : std_logic_vector(7 downto 0) := x"00";
203 signal SEQNUM : std_logic_vector(7 downto 0) := x"00";
204 signal NextSEQNUM : std_logic_vector(7 downto 0) := x"00";
205 signal ACKNUM : std_logic_vector(7 downto 0) := (others => '0');
206 signal bad_K : std_logic := '0';
207 signal SEQ_OK : std_logic := '0';
208 signal IllegalSeq : std_logic := '0';
209 signal CRC_OK : std_logic := '0';
210 signal frame_OK : std_logic := '0';
211 signal TypeInit : std_logic := '0';
212 signal TypeACK : std_logic := '0';
213 signal TypeData : std_logic := '0';
214 signal TypeCntr : std_logic := '0';
215 signal Receiving : std_logic := '0';
216 signal Header2 : std_logic := '0';
217 signal TxType : std_logic_vector(7 downto 0) := (others => '0');
218 signal AMC_ID : std_logic_vector(7 downto 0) := (others => '0');
219 signal RxType : std_logic_vector(15 downto 0) := (others => '0');
220 signal RxWC : std_logic_vector(2 downto 0) := (others => '0');
221 signal check_packet : std_logic := '0';
222 signal WC_OKp : std_logic := '0';
223 signal WC_OK : std_logic := '0';
224 signal L1Ainfo : std_logic := '0';
225 signal ACK_OK : std_logic := '0';
226 signal we_ACKNUM : std_logic := '0';
227 signal accept : std_logic := '0';
228 signal IsACK : std_logic := '0';
229 signal IsCntr : std_logic := '0';
230 signal IsData : std_logic := '0';
231 signal CntrSent : std_logic := '0';
232 signal ReSendQueIn : std_logic_vector(27 downto 0) := (others => '0');
233 signal ReSendQueOut : std_logic_vector(27 downto 0) := (others => '0');
234 signal ACKNUM_full : std_logic := '0';
235 signal ACKNUM_empty : std_logic := '1';
236 signal AMC_info : std_logic_vector(7 downto 0) := (others => '0');
237 signal ACKNUM_l : std_logic_vector(7 downto 0) := (others => '0');
238 signal ACKNUM_a : std_logic_vector(1 downto 0) := (others => '1');
239 signal we_RxCRC : std_logic := '0';
240 signal Init_RxCRC : std_logic := '0';
241 signal RxCRC : std_logic_vector(15 downto 0) := (others => '0');
242 signal AMCinfo_WrEn : std_logic := '0';
243 signal AMCinfo_wa : std_logic_vector(9 downto 0) := (others => '0');
244 signal AMCinfo_sel : std_logic_vector(2 downto 0) := (others => '0');
245 signal AMCinfo_Di : std_logic_vector(15 downto 0) := (others => '0');
246 signal AMCinfo_Do : std_logic_vector(15 downto 0) := (others => '0');
247 signal evnLSB : std_logic_vector(7 downto 0) := (others => '0');
248 signal bad_ID : std_logic := '0';
249 signal AMC_header : std_logic := '0';
250 signal L1Ainfo_WrEn : std_logic := '0';
251 signal OldL1Ainfo_wa : std_logic_vector(7 downto 0) := (others => '0');
252 signal L1Ainfo_wa : std_logic_vector(9 downto 0) := (others => '0');
253 signal info_ra : std_logic_vector(9 downto 0) := (others => '0');
254 signal L1Ainfo_Di : std_logic_vector(15 downto 0) := (others => '0');
255 signal L1Ainfo_Do : std_logic_vector(15 downto 0) := (others => '0');
256 signal L1Ainfo_empty : std_logic := '1';
257 signal RxL1Ainfo : std_logic := '0';
258 signal AMCinfo_empty : std_logic := '1';
259 signal ce_info_ra : std_logic := '0';
260 signal check_L1Ainfo : std_logic := '0';
261 signal check_L1Ainfo_q : std_logic := '0';
262 signal L1AinfoMM : std_logic := '0';
263 signal info_ra_q : std_logic_vector(1 downto 0) := (others => '0');
264 signal info_ra_q2 : std_logic_vector(1 downto 0) := (others => '0');
265 signal we_EventStatus : std_logic := '0';
266 signal EventData2Send : std_logic := '0';
267 signal UnknownEventLength : std_logic := '1';
268 signal bad_EventLength : std_logic := '1';
269 signal EventLength : std_logic_vector(19 downto 0) := (others => '0');
270 signal EventWC : std_logic_vector(19 downto 0) := (others => '0');
271 signal EventCnt : std_logic_vector(4 downto 0) := (others => '0');
272 signal WrEventCnt : std_logic_vector(4 downto 0) := (others => '0');
273 signal RdEventCnt : std_logic_vector(4 downto 0) := (others => '0');
274 signal EventStatus : std_logic_vector(7 downto 0) := (others => '0');
275 signal EventStatus_Di : std_logic_vector(7 downto 0) := (others => '0');
276 signal EventStatusCnt : std_logic_vector(4 downto 0) := (others => '1');
277 signal EventStatus_wa : std_logic_vector(4 downto 0) := (others => '1');
278 signal EventStatus_ra : std_logic_vector(4 downto 0) := (others => '1');
279 signal idle_cntr : std_logic_vector(3 downto 0) := (others => '0');
280 signal CntrTimeout : std_logic := '0';
281 signal cntr_timer : std_logic_vector(15 downto 0) := (others => '0');
282 signal cntrs : std_logic_vector(15 downto 0) := (others => '0');
283 signal cntr0 : std_logic_vector(15 downto 0) := (others => '0');
284 signal cntr1 : std_logic_vector(15 downto 0) := (others => '0');
285 signal cntr2 : std_logic_vector(15 downto 0) := (others => '0');
286 signal cntr3 : std_logic_vector(15 downto 0) := (others => '0');
287 signal cntr4 : std_logic_vector(15 downto 0) := (others => '0');
288 signal cntr5 : std_logic_vector(15 downto 0) := (others => '0');
289 signal cntr6 : std_logic_vector(15 downto 0) := (others => '0');
290 signal cntr7 : std_logic_vector(15 downto 0) := (others => '0');
291 signal cntr8 : std_logic_vector(15 downto 0) := (others => '0');
292 signal cntr9 : std_logic_vector(15 downto 0) := (others => '0');
293 signal cntra : std_logic_vector(15 downto 0) := (others => '0');
294 signal cntrb : std_logic_vector(15 downto 0) := (others => '0');
295 signal cntrc : std_logic_vector(15 downto 0) := (others => '0');
296 signal cntrd : std_logic_vector(15 downto 0) := (others => '0');
297 signal cntre : std_logic_vector(15 downto 0) := (others => '0');
298 signal cntrf : std_logic_vector(15 downto 0) := (others => '0');
299 signal cntr10 : std_logic_vector(15 downto 0) := (others => '0');
300 signal cntr11 : std_logic_vector(15 downto 0) := (others => '0');
301 signal cntr12 : std_logic_vector(15 downto 0) := (others => '0');
302 signal cntr13 : std_logic_vector(15 downto 0) := (others => '0');
303 signal cntr14 : std_logic_vector(15 downto 0) := (others => '0');
304 signal cntr15 : std_logic_vector(15 downto 0) := (others => '0');
305 signal cntr16 : std_logic_vector(15 downto 0) := (others => '0');
306 signal short_event_cntr : std_logic_vector(15 downto 0) := (others => '0');
307 signal input_word_cntr : std_logic_vector(15 downto 0) := (others => '0');
308 signal input_header_cntr : std_logic_vector(15 downto 0) := (others => '0');
309 signal input_trailer_cntr : std_logic_vector(15 downto 0) := (others => '0');
310 signal input_evnErr_cntr : std_logic_vector(15 downto 0) := (others => '0');
311 signal input_evn : std_logic_vector(23 downto 0) := (others => '0');
312 signal sample_sync : std_logic_vector(3 downto 0) := (others => '0');
313 signal sample : std_logic := '0';
314 signal FIFO_ovf : std_logic := '0';
315 signal RXCHARISK_q : std_logic_vector(1 downto 0) := (others => '1');
316 signal RXCHARISCOMMA_q : std_logic_vector(1 downto 0) := (others => '1');
317 signal RXDATA_q : std_logic_vector(15 downto 0) := (others => '1');
318 signal FIFO_rst : std_logic := '0';
319 signal FIFO_en : std_logic := '0';
320 signal DataFIFO_EMPTY : std_logic := '1';
321 signal DataFIFO_WRERR : std_logic := '0';
322 signal DataFIFO_RdEn : std_logic := '0';
323 signal DataFIFO_RdEnp : std_logic := '0';
324 signal DataFIFO_WrEn : std_logic := '0';
325 signal DataFIFO_di : std_logic_vector(65 downto 0) := (others => '0');
326 signal DataFIFO_do : std_logic_vector(65 downto 0) := (others => '0');
327 signal RDCOUNT : std_logic_vector(8 downto 0) := (others => '0');
328 signal WRCOUNT : std_logic_vector(8 downto 0) := (others => '0');
329 signal K_Cntr : std_logic_vector(7 downto 0) := (others => '0');
330 signal ChkEvtLen_in : std_logic_vector(1 downto 0) := (others => '1');
331 signal ChkEvtLen : std_logic_vector(1 downto 0) := (others => '1');
332 signal L1A_DATA_o : std_logic_vector(15 downto 0) := (others => '0');
333 signal L1A_DATA_ra : std_logic_vector(4 downto 0) := (others => '0');
334 signal L1A_DATA_wa : std_logic_vector(2 downto 0) := (others => '0');
335 signal OldL1Ainfo_wa0_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
336 signal ce_L1A_DATA_ra : std_logic := '0';
337 signal CriticalTTS : std_logic_vector(2 downto 0) := (others => '0');
338 begin
339 Ready <= fifo_en;
340 AlmostFull <= AlmostFull_i;
341 i_FIFO_RESET_7S: FIFO_RESET_7S PORT MAP(
342  reset => fifo_reset,
343  clk => EventDataClk,
344  fifo_rst => fifo_rst,
345  fifo_en => fifo_en
346  );
347 fifo_reset <= not Ready_i;
348 i_DataFIFO : FIFO_DUALCLOCK_MACRO
349  generic map (
350  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
351  ALMOST_FULL_OFFSET => X"000a", -- Sets almost full threshold
352  ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
353  DATA_WIDTH => 66, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
354  FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
355  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
356  port map (
357  ALMOSTEMPTY => open, -- 1-bit output almost empty
358  ALMOSTFULL => AlmostFull_i, -- 1-bit output almost full
359  DO => DataFIFO_do, -- Output data, width defined by DATA_WIDTH parameter
360  EMPTY => DataFIFO_EMPTY, -- 1-bit output empty
361  FULL => open, -- 1-bit output full
362  RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
363  RDERR => open, -- 1-bit output read error
364  WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
365  WRERR => DataFIFO_WRERR, -- 1-bit output write error
366  DI => DataFIFO_di, -- Input data, width defined by DATA_WIDTH parameter
367  RDCLK => UsrClk, -- 1-bit input read clock
368  RDEN => DataFIFO_RdEn, -- 1-bit input read enable
369  RST => FIFO_rst, -- 1-bit input reset
370  WRCLK => EventDataClk, -- 1-bit input write clock
371  WREN => DataFIFO_WrEn -- 1-bit input write enable
372  );
373 DataFIFO_WrEn <= FIFO_en and EventData_valid;
374 DataFIFO_di <= EventData_header & EventData_trailer & EventData;
375 process(UsrClk)
376 begin
377  if(UsrClk'event and UsrClk = '1')then
378  UsrClkDiv <= UsrClkDiv + 1;
379  if(UsrClkDiv(1) = '0')then
380  EventCRC_d <= DataFIFO_do(31 downto 0);
381  elsif(DataFIFO_do(65) = '1')then
382  EventCRC_d <= x"0" & AMC_ID(3 downto 0) & DataFIFO_do(55 downto 32);
383  else
384  EventCRC_d <= DataFIFO_do(63 downto 32);
385  end if;
386  if(DataFIFO_do(65) = '1' and DataFIFO_RdEnp = '1')then
387  EventLength <= DataFIFO_do(19 downto 0);
388  end if;
389  if(Ready_i = '0' or InitLink ='1')then
390  ChkEvtLen <= (others => '0');
391  elsif(DataFIFO_RdEnp = '1')then
392  if(DataFIFO_do(64) = '1' and ChkEvtLen(1) = '1')then
393  ChkEvtLen <= (others => '0');
394  else
395  ChkEvtLen(0) <= not ChkEvtLen(0);
396  ChkEvtLen(1) <= ChkEvtLen(1) or ChkEvtLen(0);
397  end if;
398  end if;
399  if(DataFIFO_RdEnp = '1')then
400  if(DataFIFO_do(65) = '1')then
401  EventWC <= x"00002";
402  else
403  EventWC <= EventWC + 1;
404  end if;
405  end if;
406  UnknownEventLength <= and_reduce(EventLength);
407  if(DataFIFO_RdEnp = '1' and DataFIFO_do(64) = '1' and (EventWC /= DataFIFO_do(19 downto 0) or (UnknownEventLength = '0' and EventLength /= EventWC)))then
408  bad_EventLength <= '1';
409  else
410  bad_EventLength <= '0';
411  end if;
412  Init_EventCRC <= not UsrClkDiv(1) and not UsrClkDiv(0) and DataFIFO_do(65) and not ChkEvtLen(1) and not ChkEvtLen(0) and not DataFIFO_EMPTY;
413  if(FIFO_en = '0' or Ready_i = '0' or InitLink = '1' or DataFIFO_EMPTY = '1')then
414  FillDataBuf <= '0';
415  elsif(UsrClkDiv = "00")then
416  if(DataBuf_full = '1' or EventCnt(4 downto 3) = "11")then
417  FillDataBuf <= '0';
418  else
419  FillDataBuf <= '1';
420  end if;
421  end if;
422  ce_EventCRC <= UsrClkDiv(0) and FillDataBuf;
423  DataFIFO_RdEn <= UsrClkDiv(1) and not UsrClkDiv(0) and FillDataBuf and (ChkEvtLen(1) or not DataFIFO_do(64));
424  DataFIFO_RdEnp <= UsrClkDiv(1) and not UsrClkDiv(0) and FillDataBuf and FIFO_en;
425  DataBuf_wrEn <= FillDataBuf;
426  BoE <= DataFIFO_do(65);
427  EoE <= DataFIFO_do(64) and ChkEvtLen(1);
428  if(BoE = '1' and ce_EventCRC = '1')then
429  evnLSB <= EventCRC_d(7 downto 0);
430  end if;
431  if(EventCRC_d(31 downto 24) = evnLSB)then
432  bad_ID <= '0';
433  else
434  bad_ID <= '1';
435  end if;
436  if(UsrClkDiv(0) = '1')then
437  if(EoE = '1' and UsrClkDiv(1) = '1')then
438  DataBuf_Din(15 downto 0) <= EventCRC(15 downto 0);
439  else
440  DataBuf_Din(15 downto 0) <= EventCRC_d(15 downto 0);
441  end if;
442  elsif(EoE = '1' and UsrClkDiv(1) = '0')then
443  DataBuf_Din(15 downto 0) <= EventCRC(31 downto 16);
444  else
445  DataBuf_Din(15 downto 0) <= EventCRC_d(31 downto 16);
446  end if;
447  DataBuf_Din(16) <= not UsrClkDiv(1) and not UsrClkDiv(0) and EoE;
448  end if;
449 end process;
450 i_EventCRC: EthernetCRCD32 PORT MAP(
451  clk => UsrClk ,
452  init => Init_EventCRC,
453  ce => ce_EventCRC,
454  d => EventCRC_d,
455  crc => EventCRC,
456  bad_crc => open
457  );
458 process(UsrClk,RxResetDone)
459 begin
460  if(RxResetDone = '0')then
461  RxResetDoneSyncRegs <= (others => '0');
462  elsif(UsrClk'event and UsrClk = '1')then
463  RxResetDoneSyncRegs <= RxResetDoneSyncRegs(1 downto 0) & '1';
464  end if;
465 end process;
466 process(UsrClk,reset,RxResetDone,txfsmresetdone,cplllock)
467 begin
468  if(reset = '1' or RXRESETDONE = '0' or txfsmresetdone = '0' or cplllock = '0')then
469  reset_SyncRegs <= (others => '1');
470  elsif(UsrClk'event and UsrClk = '1')then
471  reset_SyncRegs <= reset_SyncRegs(2 downto 0) & '0';
472  end if;
473 end process;
474 -- following is used to reset CDR when sync get lost
475 --w <= 8 when simulation = true else 16;
476 process(UsrClk)
477 begin
478  if(UsrClk'event and UsrClk = '1')then
479  if(RXCHARISK = "11" and RXDATA = x"3cbc")then
480  DATA_VALID <= '1';
481  elsif(RxResetDoneSyncRegs(2) = '0' or or_reduce(RXNOTINTABLE) = '1' or K_Cntr(7) = '1')then
482  DATA_VALID <= '0';
483  end if;
484  if((RXCHARISK = "11" and RXDATA = x"3cbc"))then
485  K_Cntr <= (others => '0');
486  else
487  K_Cntr <= K_Cntr + 1;
488  end if;
489  RXCHARISCOMMA_q <= RXCHARISCOMMA;
490  RXCHARISK_q <= RXCHARISK;
491  RXDATA_q <= RXDATA;
492  end if;
493 end process;
494 process(EventDataClk,reset,InitLink)
495 begin
496  if(reset = '1' or Ready_i = '0')then
497  ChkEvtLen_in <= (others => '0');
498  sample_sync <= (others => '0');
499  FIFO_ovf <= '0';
500  cntrc <= (others => '0');
501  cntrd <= (others => '0');
502  cntre <= (others => '0');
503  cntrf <= (others => '0');
504  cntr16 <= (others => '0');
505  short_event_cntr <= (others => '0');
506  input_word_cntr <= (others => '0');
507  input_header_cntr <= (others => '0');
508  input_trailer_cntr <= (others => '0');
509  input_evnErr_cntr <= (others => '0');
510  input_evn <= x"000001";
511  elsif(EventDataClk'event and EventDataClk = '1')then
512  sample_sync <= sample_sync(2 downto 0) & sample;
513  if(DataFIFO_WRERR = '1')then
514  FIFO_ovf <= '1';
515  end if;
516  if(dataFIFO_WrEn = '1')then
517  input_word_cntr <= input_word_cntr + 1;
518  if(DataFIFO_di(65) = '1')then
519  input_header_cntr <= input_header_cntr + 1;
520  input_evn <= DataFIFO_di(55 downto 32);
521  if(DataFIFO_di(55 downto 32) /= input_evn)then
522  input_evnErr_cntr <= input_evnErr_cntr + 1;
523  end if;
524  end if;
525  if(DataFIFO_di(64) = '1')then
526  input_trailer_cntr <= input_trailer_cntr + 1;
527  input_evn <= input_evn + 1;
528  end if;
529  if(DataFIFO_di(64) = '1')then
530  ChkEvtLen_in <= (others => '0');
531  else
532  ChkEvtLen_in(0) <= not ChkEvtLen_in(0);
533  ChkEvtLen_in(1) <= ChkEvtLen_in(1) or ChkEvtLen_in(0);
534  end if;
535  if(DataFIFO_di(64) = '1')then
536  input_trailer_cntr <= input_trailer_cntr + 1;
537  input_evn <= input_evn + 1;
538  if(ChkEvtLen_in(1) = '0')then
539  short_event_cntr <= short_event_cntr + 1;
540  end if;
541  end if;
542  end if;
543  if(sample_sync(3) /= sample_sync(2))then -- update after Counters sent
544  cntr16 <= short_event_cntr;
545  cntrc <= input_word_cntr;
546  cntrd <= input_header_cntr;
547  cntre <= input_trailer_cntr;
548  cntrf <= input_evnErr_cntr;
549  end if;
550  end if;
551 end process;
552 process(UsrClk)
553 begin
554  if(UsrClk'event and UsrClk = '1')then
555  if(Ready_i = '0' or InitLink = '1')then
556  DataBuf_wa <= (others => '0');
557  ReSendQueOut_q <= (others => '0');
558  DataBuf_used <= (others => '0');
559  DataBuf_wc <= (others => '0');
560  ec_DataBuf_ra_q <= '0';
561  ec_DataBuf_ra <= '0';
562  DataBuf_full <= '0';
563  we_DataPipe <= '0';
564  DataPipe_a <= (others => '1');
565  DataPipe_empty <= '1';
566  DataPipe_full <= '0';
567  RdEventCnt <= (others => '0');
568  WrEventCnt <= (others => '0');
569  EventData2Send <= '0';
570  EventCnt <= (others => '0');
571  ReSendQue_a <= (others => '1');
572  we_ReSendQue <= '0';
573  ReSendQue_empty <= '1';
574  timer <= (others => '0');
575  DataBuf_start <= (others => '0');
576  DataBuf_ra <= (others => '0');
577  else
578  if(DataBuf_wrEn = '1')then
579  DataBuf_wa <= DataBuf_wa + 1;
580  end if;
581  if(ReSendQue_a /= "11")then
582  ReSendQueOut_q <= ReSendQueOut(14 downto 0);
583  end if;
584  DataBuf_used <= DataBuf_wa - ReSendQueOut_q;
585  DataBuf_wc <= DataBuf_wa - DataBuf_ra;
586  if(or_reduce(DataBuf_wc(14 downto 2)) = '0' and (DataBuf_wc(1 downto 0) = "00" or ec_DataBuf_ra = '1' or ec_DataBuf_ra_q = '1'))then
587  ec_DataBuf_ra <= '0';
588  else
589  ec_DataBuf_ra <= not DataPipe_full and not Resend;
590  end if;
591  ec_DataBuf_ra_q <= ec_DataBuf_ra and not Resend;
592  DataBuf_full <= and_reduce(DataBuf_used(14 downto 3));
593  we_DataPipe <= ec_DataBuf_ra_q and not Resend;
594  if(Resend = '1')then
595  DataPipe_a <= (others => '1');
596  elsif(we_DataPipe = '1' and (TxFIFO_full = '1' or TxState /= SendData))then
597  DataPipe_a <= DataPipe_a + 1;
598  elsif(we_DataPipe = '0' and TxFIFO_full = '0' and TxState = SendData)then
599  DataPipe_a <= DataPipe_a - 1;
600  end if;
601  if(DataPipe_a = x"f" or Resend = '1' or (DataPipe_a = x"0" and TxFIFO_full = '0' and TxState = SendData))then
602  DataPipe_empty <= '1';
603  else
604  DataPipe_empty <= '0';
605  end if;
606  case DataPipe_a is
607  when x"e" | x"d" | x"c" | x"b" | x"a" | x"9" | x"8" => DataPipe_full <= '1';
608  when others => DataPipe_full <= '0';
609  end case;
610  if(DataBuf_Din(16) = '1' and DataBuf_wrEn = '1')then
611  WrEventCnt <= WrEventCnt + 1;
612  end if;
613  if(ReSend = '1')then
614  RdEventCnt <= ReSendQueOut(27 downto 23);
615  elsif(TxState = SendEOF and TxFIFO_full = '0')then
616  RdEventCnt <= RdEventCnt + 1;
617  end if;
618  if(WrEventCnt = RdEventCnt and DataBuf_wc(14 downto 12) = "000")then
619  EventData2Send <= '0';
620  else
621  EventData2Send <= '1';
622  end if;
623  EventCnt <= WrEventCnt - RdEventCnt;
624  if(ReSend = '1')then
625  ReSendQue_a <= (others => '1');
626  elsif(we_ReSendQue = '1' and ACK = '0')then
627  ReSendQue_a <= ReSendQue_a + 1;
628  elsif(we_ReSendQue = '0' and ACK = '1' and ReSendQue_a /= "11")then
629  ReSendQue_a <= ReSendQue_a - 1;
630  end if;
631  if(TxState = SendWC and TxFIFO_full = '0' and IsData = '1' and ReSend = '0')then
632  we_ReSendQue <= '1';
633  else
634  we_ReSendQue <= '0';
635  end if;
636  if(ReSend = '1')then
637  ReSendQue_empty <= '1';
638  elsif(we_ReSendQue = '1')then
639  ReSendQue_empty <= '0';
640  elsif(ACK = '1' and ReSendQue_a = "00")then
641  ReSendQue_empty <= '1';
642  end if;
643  if(timer(N) = '1' or ACK = '1' or ReSendQue_empty = '1')then
644  timer <= (others => '0');
645  else
646  timer <= timer + 1;
647  end if;
648  if(Resend = '1')then
649  DataBuf_start <= ReSendQueOut_q;
650  elsif(we_ReSendQue = '1')then
651  DataBuf_start <= DataBuf_start + packet_wc(14 downto 0);
652  end if;
653  if(ReSend = '1' and ReSendQue_empty = '0')then
654  DataBuf_ra <= ReSendQueOut_q;
655  elsif(ec_DataBuf_ra = '1')then
656  DataBuf_ra <= DataBuf_ra + 1;
657  end if;
658  end if;
659  end if;
660 end process;
661 -- ReSendQueue holds the starting address of the oldest unacknowledged packet
662 g_ReSendQueue : for i in 0 to 27 generate
663  i_ReSendQueue : SRL16E
664  port map (
665  Q => ReSendQueOut(i), -- SRL data output
666  A0 => ReSendQue_a(0), -- Select[0] input
667  A1 => ReSendQue_a(1), -- Select[1] input
668  A2 => '0', -- Select[2] input
669  A3 => '0', -- Select[3] input
670  CE => we_ReSendQue, -- Clock enable input
671  CLK => UsrClk, -- Clock input
672  D => ReSendQueIn(i) -- SRL data input
673  );
674 end generate;
675 ReSendQueIn <= RdEventCnt & SEQNUM & DataBuf_start;
676 ReSend <= timer(N);
677 g_DataBufPipe: for i in 0 to 16 generate
678  i_DataBuf : BRAM_SDP_MACRO
679  generic map (
680  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
681  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
682  WRITE_WIDTH => 1, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
683  READ_WIDTH => 1, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
684  DO_REG => 1) -- Optional output register (0 or 1)
685  port map (
686  DO => DataBuf_Dout(i downto i), -- Output read data port, width defined by READ_WIDTH parameter
687  DI => DataBuf_Din(i downto i), -- Input write data port, width defined by WRITE_WIDTH parameter
688  RDADDR => DataBuf_ra, -- Input read address, width defined by read port depth
689  RDCLK => UsrClk, -- 1-bit input read clock
690  RDEN => '1', -- 1-bit input read port enable
691  REGCE => '1', -- 1-bit input read output register enable
692  RST => '0', -- 1-bit input reset
693  WE => "1", -- Input write enable, width defined by write port depth
694  WRADDR => DataBuf_wa, -- Input write address, width defined by write port depth
695  WRCLK => UsrClk, -- 1-bit input write clock
696  WREN => DataBuf_WrEn -- 1-bit input write port enable
697  );
698  i_DataPipe : SRL16E
699  port map (
700  Q => DataPipeDo(i), -- SRL data output
701  A0 => DataPipe_a(0), -- Select[0] input
702  A1 => DataPipe_a(1), -- Select[1] input
703  A2 => DataPipe_a(2), -- Select[2] input
704  A3 => DataPipe_a(3), -- Select[3] input
705  CE => we_DataPipe, -- Clock enable input
706  CLK => UsrClk, -- Clock input
707  D => DataBuf_Dout(i) -- SRL data input
708  );
709 end generate;
710 g_TxFIFO : for i in 0 to 16 generate
711  i_TxFIFO : SRL16E
712  port map (
713  Q => TxFIFO_Do(i), -- SRL data output
714  A0 => TxFIFO_a(0), -- Select[0] input
715  A1 => TxFIFO_a(1), -- Select[1] input
716  A2 => TxFIFO_a(2), -- Select[2] input
717  A3 => TxFIFO_a(3), -- Select[3] input
718  CE => we_TxFIFO, -- Clock enable input
719  CLK => UsrClk, -- Clock input
720  D => TxFIFO_Di(i) -- SRL data input
721  );
722 end generate;
723 TxFIFO_Di(15 downto 0) <= cntrs when sel_cntr = '1' else TxFIFO_Dip;
724 process(UsrClk)
725 begin
726  if(UsrClk'event and UsrClk = '1')then
727  if(TxFIFO_a = x"f" or InitLink = '1' or (TxFIFO_a = x"0" and sel_TTS_TRIG = '0' and we_TxFIFO = '0'))then
728  TxFIFO_empty <= '1';
729  else
730  TxFIFO_empty <= '0';
731  end if;
732  if(TxFIFO_empty = '0' or idle_cntr(3) = '1')then
733  idle_cntr <= x"0";
734  else
735  idle_cntr <= idle_cntr + 1;
736  end if;
737  if(TxFIFO_a(3 downto 2) = "10")then
738  TxFIFO_full <= '1';
739  else
740  TxFIFO_full <= '0';
741  end if;
742  if(InitLink = '1')then
743  TxFIFO_a <= x"f";
744  elsif((sel_TTS_TRIG = '1' or TxFIFO_empty = '1' or R_word_cnt(11) = '1') and we_TxFIFO = '1')then
745  TxFIFO_a <= TxFIFO_a + 1;
746  elsif(sel_TTS_TRIG = '0' and we_TxFIFO = '0' and TxFIFO_empty = '0' and R_word_cnt(11) = '0')then
747  TxFIFO_a <= TxFIFO_a - 1;
748  end if;
749  if(sel_TTS_TRIG = '1')then
750  TXCHARISK <= TTS_TRIG_data(17 downto 16);
751  TXDATA <= TTS_TRIG_data(15 downto 0);
752  R_word_sent <= '0';
753  elsif(R_word_cnt(11) = '1' or TxFIFO_empty = '1')then
754  TXCHARISK <= "11";
755  TXDATA <= R_word;
756  R_word_sent <= '1';
757  else
758  TXCHARISK <= TxFIFO_Do(16) & TxFIFO_Do(16);
759  TXDATA <= TxFIFO_Do(15 downto 0);
760  R_word_sent <= '0';
761  end if;
762  if(reset_SyncRegs(3) = '1')then
763  InitLink <= '0';
764 -- whenever a good initialization packet is received, (re)initializa miniCTR
765  elsif(check_packet = '1' and CRC_OK = '1' and TypeInit = '1' and frame_OK = '1' and WC_OK = '1' and bad_K = '0')then
766  InitLink <= '1';
767  else
768  InitLink <= '0';
769  end if;
770  if(reset_SyncRegs(3) = '1' or InitLink = '1')then
771  Ready_i <= '0';
772  elsif(InitACK = '1' and TxState = SendCRC and TxType = InitRqst)then
773  Ready_i <= '1';
774  end if;
775  if(InitLink = '1')then
776  SEQNUM <= x"00";
777  elsif(ReSend = '1')then
778  SEQNUM <= ReSendQueOut(22 downto 15);
779  elsif(we_ReSendQue = '1')then
780  SEQNUM <= SEQNUM(6 downto 0) & not(SEQNUM(7) xor SEQNUM(5) xor SEQNUM(4) xor SEQNUM(3));
781  end if;
782  if(InitLink = '1')then
783  InitACK <= '1';
784  elsif(TxState = SendCRC and TxType = InitRqst)then
785  InitACK <= '0';
786  end if;
787  if(InitACK = '1')then
788  AMC_info <= version;
789  else
790  AMC_info <= EventStatus;
791  end if;
792  if(reset_SyncRegs(3) = '1' or InitLink = '1' or ReSend = '1')then
793  TxState <= SendK;
794  elsif(TxFIFO_full = '0')then
795  case TxState is
796  when IDLE => -- send R_word (idle)
797  if((ReSendQue_a(1) = ReSendQue_a(0) and EventStatus_empty = '0' and EventData2Send = '1' and DataPipe_empty = '0') or ACKNUM_empty = '0' or CntrTimeout = '1')then
798  TxState <= SendSEQ;
799  elsif(idle_cntr(3) = '1')then
800  TxState <= SendK;
801  end if;
802  if(InitACK = '1')then
803  TxType <= InitRqst;
804  IsData <= '0';
805  IsCntr <= '0';
806  IsACK <= '1';
807  elsif(ACKNUM_empty = '0')then
808  TxType <= Acknowledge;
809  IsData <= '0';
810  IsCntr <= '0';
811  IsACK <= '1';
812  elsif(CntrTimeout = '1')then
813  IsData <= '0';
814  IsCntr <= '1';
815  IsACK <= '0';
816  TxType <= Counter;
817  else
818  IsData <= '1';
819  IsCntr <= '0';
820  IsACK <= '0';
821  TxType <= data;
822  end if;
823  when SendK => -- send K_word
824  TxState <= IDLE;
825  when SendSEQ => -- send packet_seq
826  FoundEOF <= '0';
827  TxState <= SendType;
828  when SendType => -- send data type
829  if(IsData = '1')then
830  TxState <= SendData;
831  elsif(IsCntr = '1')then
832  TxState <= SendCntr;
833  else
834  TxState <= SendWC;
835  end if;
836  when SendWC => -- send packet_wc
837  TxState <= WaitCRC;
838  when WaitCRC => -- wait for CRC
839  TxState <= SendCRC;
840  when SendCntr => -- send counter data
841  if(packet_wc(4 downto 0) = "11111")then -- 32 counters sent, it has to be multiple of 4, i.e. packet_wc(1 downto 0) must always be "11"
842  TxState <= SendWC;
843  end if;
844  when SendData => -- send payload data
845  if(and_reduce(packet_wc(10 downto 0)) = '1' or DataPipeDo(16) = '1')then -- 4K bytes limit or eof reached
846  TxState <= SendWC;
847  FoundEOF <= DataPipeDo(16);
848  elsif(DataPipe_a = x"0")then
849  TxState <= WaitData;
850  end if;
851  when WaitData => -- wait for data
852  if(DataPipe_empty = '0')then
853  TxState <= SendData;
854  end if;
855  when SendCRC => -- send TxCRC
856  if(FoundEOF = '1')then
857  TxState <= SendEOF;
858  else
859  TxState <= SendK;
860  end if;
861  when SendEOF => -- send eof_word
862  TxState <= SendK;
863  when others => TxState <= x"0";
864  end case;
865  end if;
866  case TxState is
867  when SendK => TxFIFO_Dip <= K_word;
868  when SendData => TxFIFO_Dip <= DataPipeDo(15 downto 0);
869  when SendSEQ => TxFIFO_Dip <= SEQNUM & TxType;
870  when SendType => TxFIFO_Dip <= ACKNUM_l & AMC_info;
871  when SendWC => TxFIFO_Dip <= packet_wc;
872  when SendCRC => TxFIFO_Dip <= TxCRC;
873  when SendEOF => TxFIFO_Dip <= eof_word;
874  when others => TxFIFO_Dip <= (others => '0');
875  end case;
876  if(InitLink = '1')then
877  cntrs <= (others => '0');
878  elsif(packet_wc(4) = '0')then
879  case packet_wc(3 downto 0) is
880  when x"0" => cntrs <= cntr0;
881  when x"1" => cntrs <= cntr1;
882  when x"2" => cntrs <= cntr2;
883  when x"3" => cntrs <= cntr3;
884  when x"4" => cntrs <= cntr4;
885  when x"5" => cntrs <= cntr5;
886  when x"6" => cntrs <= cntr6;
887  when x"7" => cntrs <= cntr7;
888  when x"8" => cntrs <= cntr8;
889  when x"9" => cntrs <= cntr9;
890  when x"a" => cntrs <= cntra;
891  when x"b" => cntrs <= cntrb;
892  when x"c" => cntrs <= cntrc;
893  when x"d" => cntrs <= cntrd;
894  when x"e" => cntrs <= cntre;
895  when others => cntrs <= cntrf;
896  end case;
897  else
898  case packet_wc(3 downto 0) is
899  when x"0" => cntrs <= FIFO_ovf & "00" & EventStatus_ra & "000" & EventStatus_wa;
900  when x"1" => cntrs <= '0' & DataBuf_wa;
901  when x"2" => cntrs <= '0' & DataBuf_ra;
902  when x"3" => cntrs <= "000000" & L1Ainfo_wa;
903  when x"4" => cntrs <= "000000" & info_ra;
904  when x"5" => cntrs <= "000000" & AMCinfo_wa;
905  when x"6" => cntrs <= x"00" & version;
906  when x"7" => cntrs <= DataBuf_full & EventStatus_empty & EventData2Send & DataPipe_empty & CriticalTTS & EventCnt & ReSendQue_a & AlmostFull_i & dataFIFO_Empty;
907  when x"8" => cntrs <= cntr10;
908  when x"9" => cntrs <= cntr11;
909  when x"a" => cntrs <= cntr12;
910  when x"b" => cntrs <= cntr13;
911  when x"c" => cntrs <= cntr14;
912  when x"d" => cntrs <= cntr15;
913  when x"f" => cntrs <= cntr16; -- add more counter needs to update line if(packet_wc(4 downto 0) = "11110")then -- 16 counters and 13 status words sent
914  when others => cntrs <= (others => '0');
915  end case;
916  end if;
917  case TxState is
918  when SendK | SendEOF | IDLE | WaitData | WaitCRC => TxFIFO_Di(16) <= '1';
919  when others => TxFIFO_Di(16) <= '0';
920  end case;
921  if(InitLink = '1' or TxFIFO_full = '1')then
922  we_TxFIFO <= '0';
923  else
924  case TxState is
925  when IDLE | WaitData | WaitCRC => we_TxFIFO <= '0';
926  when others => we_TxFIFO <= '1';
927  end case;
928  end if;
929  if(TxState = SendCntr)then
930  sel_cntr <= '1';
931  else
932  sel_cntr <= '0';
933  end if;
934  if(TxState = SendK)then
935  packet_wc(11 downto 0) <= x"000";
936  elsif(TxFIFO_full = '0' and (TxState = SendData or TxState = SendCntr))then
937  packet_wc(11 downto 0) <= packet_wc(11 downto 0) + 1;
938  end if;
939  if(TxState = IDLE or TxState = SendK)then
940  Init_TxCRC <= '1';
941  else
942  Init_TxCRC <= '0';
943  end if;
944  if(R_word_sent = '1')then
945  R_word_cnt <= (others => '0');
946  else
947  R_word_cnt <= R_word_cnt + 1;
948  end if;
949  end if;
950 end process;
951 i_TxCRC: crc16D16 PORT MAP(
952  clk => UsrClk ,
953  init_crc => Init_TxCRC,
954  we_crc => we_TxCRC,
955  d => TxFIFO_Di(15 downto 0),
956  crc => TxCRC
957  );
958 we_TxCRC <= not TxFIFO_Di(16) and we_TxFIFO;
959 -- received data processing starts here
960 process(UsrClk)
961 begin
962  if(UsrClk'event and UsrClk = '1')then
963 -- Comma ends a packet and after that, any D-word marks the beginning of a packet
964  if(RXCHARISCOMMA_q = "11" or (L1Ainfo_wa(1 downto 0) = "11" and L1Ainfo_WrEn = '1'))then
965  L1Ainfo <= '0';
966  elsif(RXCHARISK_q = "00" and Header2 = '1' and Ready_i = '1' and TypeData = '1')then
967  L1Ainfo <= '1';
968  end if;
969  if(RXCHARISCOMMA_q = "11")then
970  Receiving <= '0';
971  elsif(RXCHARISK_q = "00")then
972  Receiving <= '1';
973  end if;
974 -- first word of a packet is the packet sequence number
975  if(RXCHARISK_q = "00")then
976  if(Receiving = '0')then
977  bad_K <= '0';
978  RxSEQNUM <= RXDATA_q(15 downto 8);
979  if(RXDATA_q(7 downto 0) = InitRqst)then
980  TypeInit <= '1';
981  else
982  TypeInit <= '0';
983  end if;
984  if(RXDATA_q(7 downto 0) = Acknowledge)then
985  TypeACK <= '1';
986  else
987  TypeACK <= '0';
988  end if;
989  if(RXDATA_q(7 downto 0) = data)then
990  TypeData <= '1';
991  else
992  TypeData <= '0';
993  end if;
994  if(RXDATA_q(7 downto 0) = Counter)then
995  TypeCntr <= '1';
996  else
997  TypeCntr <= '0';
998  end if;
999  Header2 <= '1';
1000  else
1001  Header2 <= '0';
1002  end if;
1003  if(Header2 = '1')then
1004  RxType <= RXDATA_q;
1005  RxWC <= "000";
1006  else
1007  RxWC <= RxWC + 1;
1008  end if;
1009  if(RxWC = RXDATA_q(2 downto 0))then
1010  WC_OKp <= '1';
1011  else
1012  WC_OKp <= '0';
1013  end if;
1014  WC_OK <= WC_OKp;
1015  elsif(RXDATA_q(7 downto 0) = x"5c" and RXCHARISK_q = "01")then
1016 -- acknowledge of TTS data, this will be processed by TTS_TRIG_if
1017  elsif((RXDATA_q /= R_word and RXCHARISCOMMA_q /= "11") or RXCHARISK_q(1) /= RXCHARISK_q(0))then
1018  bad_K <= '1';
1019  end if;
1020  if(Receiving = '0')then
1021  ACKNUM_IN <= RxSEQNUM;
1022  end if;
1023  if(TypeACK = '1' and RXType(15 downto 8) = ReSendQueOut(22 downto 15) and ReSendQue_empty = '0')then -- incoming acknowledge number is what waited for
1024  ACK_OK <= '1';
1025  else
1026  ACK_OK <= '0';
1027  end if;
1028  if(InitLink = '1')then
1029  AMC_ID <= RxType(7 downto 0);
1030  end if;
1031  if((RxSEQNUM = NextSEQNUM and TypeInit = '0') or (RxSEQNUM = x"00" and TypeInit = '1'))then -- incoming sequence number is what waited for
1032  SEQ_OK <= '1';
1033  else
1034  SEQ_OK <= '0';
1035  end if;
1036  if(WC_OK = '1' and (TypeInit = '1' or TypeCntr = '1' or TypeData = '1' or TypeACK = '1'))then
1037  frame_OK <= '1';
1038  else
1039  frame_OK <= '0';
1040  end if;
1041  if(or_reduce(RxCRC) = '0')then
1042  CRC_OK <= '1';
1043  else
1044  CRC_OK <= '0';
1045  end if;
1046  if(RXCHARISCOMMA_q = "11" and Receiving = '1')then
1047  check_packet <= '1';
1048  else
1049  check_packet <= '0';
1050  end if;
1051 -- accept <= (check_packet and SEQ_OK and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and TypeData) or InitLink;
1052  accept <= check_packet and SEQ_OK and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and (TypeInit or TypeData);
1053 -- acknowledge even received packet is not the expected one
1054  we_ACKNUM <= check_packet and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and (TypeInit or TypeData);
1055  ACK <= check_packet and SEQ_OK and ACK_OK and CRC_OK and frame_OK and not bad_K;
1056  CntrACK <= check_packet and TypeCntr and CRC_OK and frame_OK and not bad_K;
1057  L1Aabort <= check_packet and TypeData and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and not ACKNUM_full);
1058  if(reset_SyncRegs(3) = '1')then
1059  ACKNUM_a <= (others => '1');
1060  elsif(InitLink = '1')then
1061  ACKNUM_a <= (others => '0');
1062  elsif(we_ACKNUM = '1' and (TxFIFO_full = '1' or TxState /= SendCRC or IsACK = '0'))then
1063  ACKNUM_a <= ACKNUM_a + 1;
1064  elsif(we_ACKNUM = '0' and TxFIFO_full = '0' and TxState = SendCRC and IsACK = '1')then
1065  ACKNUM_a <= ACKNUM_a - 1;
1066  end if;
1067  if(InitLink = '1')then
1068  NextSEQNUM <= x"01";
1069  elsif(accept = '1')then
1070  NextSEQNUM <= NextSEQNUM(6 downto 0) & not(NextSEQNUM(7) xor NextSEQNUM(5) xor NextSEQNUM(4) xor NextSEQNUM(3));
1071  end if;
1072  if(ACKNUM_a = "11")then
1073  ACKNUM_empty <= '1';
1074  else
1075  ACKNUM_empty <= '0';
1076  end if;
1077  if(ACKNUM_a = "10")then
1078  ACKNUM_full <= '1';
1079  else
1080  ACKNUM_full <= '0';
1081  end if;
1082  if(ACKNUM_a /= "11")then
1083  ACKNUM_l <= ACKNUM;
1084  end if;
1085  if(InitLink = '1')then
1086  cntr0 <= (others => '0');
1087  elsif(accept = '1')then
1088  cntr0 <= cntr0 + 1;
1089  end if;
1090  if(InitLink = '1')then
1091  cntr1 <= (others => '0');
1092  elsif(ACK = '1')then
1093  cntr1 <= cntr1 + 1;
1094  end if;
1095  if(InitLink = '1')then
1096  cntr2 <= (others => '0');
1097  cntr10 <= (others => '0');
1098  cntr11 <= (others => '0');
1099  cntr12 <= (others => '0');
1100  cntr13 <= (others => '0');
1101  cntr14 <= (others => '0');
1102  elsif(L1Aabort = '1')then
1103  cntr2 <= cntr2 + 1;
1104  if(SEQ_OK = '0')then
1105  cntr10 <= cntr10 + 1;
1106  end if;
1107  if(CRC_OK = '0')then
1108  cntr11 <= cntr11 + 1;
1109  end if;
1110  if(frame_OK = '0')then
1111  cntr12 <= cntr12 + 1;
1112  end if;
1113  if(bad_K = '1')then
1114  cntr13 <= cntr13 + 1;
1115  end if;
1116  if(ACKNUM_full = '1')then
1117  cntr14 <= cntr14 + 1;
1118  end if;
1119  end if;
1120  if(InitLink = '1')then
1121  cntr15 <= (others => '0');
1122  elsif(DataFIFO_RdEnp = '1' and DataFIFO_do(64) = '1' and ChkEvtLen(1) = '0')then
1123  cntr15 <= cntr15 + 1;
1124  end if;
1125  if(InitLink = '1')then
1126  cntr3 <= (others => '0');
1127  cntr4 <= (others => '0');
1128  cntr5 <= (others => '0');
1129  cntr6 <= (others => '0');
1130  elsif(we_EventStatus = '1')then
1131  if(EventStatus_Di(0) = '0')then
1132  cntr3 <= cntr3 + 1;
1133  end if;
1134  if(EventStatus_Di(1) = '0')then
1135  cntr4 <= cntr4 + 1;
1136  end if;
1137  if(EventStatus_Di(2) = '0')then
1138  cntr5 <= cntr5 + 1;
1139  end if;
1140  cntr6 <= cntr6 + 1;
1141  end if;
1142  if(InitLink = '1')then
1143  cntr7 <= (others => '0');
1144  elsif(CntrACK = '1')then
1145  cntr7 <= cntr7 + 1;
1146  end if;
1147  if(InitLink = '1')then
1148  cntr8 <= (others => '0');
1149  elsif(ReSend = '1')then
1150  cntr8 <= cntr8 + 1;
1151  end if;
1152  if(InitLink = '1')then
1153  cntr9 <= (others => '0');
1154  elsif(bad_EventLength = '1')then
1155  cntr9 <= cntr9 + 1;
1156  end if;
1157  if(InitLink = '1')then
1158  cntra <= (others => '0');
1159  elsif(EoE = '1' and UsrClkDiv(1) = '1' and bad_ID = '1')then
1160  cntra <= cntra + 1;
1161  end if;
1162  AlmostFull_sync <= AlmostFull_sync(1 downto 0) & AlmostFull_i;
1163  if(InitLink = '1')then
1164  cntrb <= (others => '0');
1165  elsif(AlmostFull_sync(2) = '1')then
1166  cntrb <= cntrb + 1;
1167  end if;
1168  if(ready_i = '0' or CntrACK = '1')then
1169  CntrSent <= '0';
1170  elsif(TxState = SendCRC and IsCntr = '1')then
1171  CntrSent <= '1';
1172  end if;
1173  if(ready_i = '0' or CntrACK = '1' or (TxState = SendCRC and IsCntr = '1'))then
1174  cntr_timer <= (others => '0');
1175  elsif(CntrTimeout = '0')then
1176  cntr_timer <= cntr_timer + 1;
1177  end if;
1178  if(CntrSent = '1')then
1179  CntrTimeout <= cntr_timer(8);
1180  elsif(simulation)then
1181  CntrTimeout <= cntr_timer(8);
1182  else
1183  CntrTimeout <= cntr_timer(15);
1184  end if;
1185  if(TxState = SendCRC and IsCntr = '1')then
1186  sample <= not sample;
1187  end if;
1188  end if;
1189 end process;
1190 i_RxCRC: crc16D16 PORT MAP(
1191  clk => UsrClk ,
1192  init_crc => Init_RxCRC,
1193  we_crc => we_RxCRC,
1194  d => RXDATA_q,
1195  crc => RxCRC
1196  );
1197 we_RxCRC <= '1' when RXCHARISK_q = "00" else '0';
1198 Init_RxCRC <= '1' when RXCHARISCOMMA_q = "11" else '0';
1199 g_ACKNUM : for i in 0 to 7 generate
1200  i_ACKNUM : SRL16E
1201  port map (
1202  Q => ACKNUM(i), -- SRL data output
1203  A0 => ACKNUM_a(0), -- Select[0] input
1204  A1 => ACKNUM_a(1), -- Select[1] input
1205  A2 => '0', -- Select[2] input
1206  A3 => '0', -- Select[3] input
1207  CE => we_ACKNUM, -- Clock enable input
1208  CLK => UsrClk, -- Clock input
1209  D => ACKNUM_IN(i) -- SRL data input
1210  );
1211 end generate;
1212 process(UsrClk)
1213 begin
1214  if(UsrClk'event and UsrClk = '1')then
1215  if(Init_EventCRC = '1')then
1216  AMCinfo_sel <= "010";
1217  elsif(FillDataBuf = '1')then
1218  case AMCinfo_sel is
1219  when "010" => AMCinfo_sel <= "100";
1220  when "100" => AMCinfo_sel <= "101";
1221  when "101" => AMCinfo_sel <= "110";
1222  when "110" => AMCinfo_sel <= "011";
1223  when "011" => AMCinfo_sel <= "111";
1224  when others => AMCinfo_sel <= "000";
1225  end case;
1226  end if;
1227  AMCinfo_WrEn <= FillDataBuf and AMCinfo_sel(2);
1228  case AMCinfo_sel(1 downto 0) is
1229  when "00" => AMCinfo_Di <= DataBuf_Din(15 downto 4) & x"0";-- BX
1230  when "01" => AMCinfo_Di <= DataBuf_Din(15 downto 0);--evn(15 downto 0)
1231  when "10" => AMCinfo_Di <= x"00" & DataBuf_Din(7 downto 0);--evn(23 downto 16)
1232  when others => AMCinfo_Di <= DataBuf_Din(15 downto 0);--OrN(15 downto 0)
1233  end case;
1234  if(InitLink = '1')then
1235  AMCinfo_wa <= (others => '0');
1236  elsif(AMCinfo_WrEn = '1')then
1237  AMCinfo_wa <= AMCinfo_wa + 1;
1238  end if;
1239  end if;
1240 end process;
1241 i_AMCinfo : BRAM_SDP_MACRO
1242  generic map (
1243  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1244  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1245  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1246  READ_WIDTH => 16) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1247  port map (
1248  DO => AMCinfo_Do, -- Output read data port, width defined by READ_WIDTH parameter
1249  DI => AMCinfo_Di, -- Input write data port, width defined by WRITE_WIDTH parameter
1250  RDADDR => info_ra, -- Input read address, width defined by read port depth
1251  RDCLK => UsrClk, -- 1-bit input read clock
1252  RDEN => '1', -- 1-bit input read port enable
1253  REGCE => '1', -- 1-bit input read output register enable
1254  RST => '0', -- 1-bit input reset
1255  WE => "11", -- Input write enable, width defined by write port depth
1256  WRADDR => AMCinfo_wa, -- Input write address, width defined by write port depth
1257  WRCLK => UsrClk, -- 1-bit input write clock
1258  WREN => AMCinfo_WrEn -- 1-bit input write port enable
1259  );
1260 process(UsrClk)
1261 begin
1262  if(UsrClk'event and UsrClk = '1')then
1263  L1Ainfo_Di <= RXDATA_q;
1264  if(InitLink = '1')then
1265  OldL1Ainfo_wa <= (others => '0');
1266  elsif(accept = '1')then
1267  OldL1Ainfo_wa <= L1Ainfo_wa(9 downto 2);
1268  end if;
1269  if(InitLink = '1')then
1270  L1Ainfo_wa <= (others => '0');
1271  elsif(L1Aabort = '1')then
1272  L1Ainfo_wa(9 downto 2) <= OldL1Ainfo_wa;
1273  elsif(Receiving = '0')then
1274  L1Ainfo_wa(1 downto 0) <= "00";
1275  elsif(L1Ainfo_WrEn = '1')then
1276  L1Ainfo_wa <= L1Ainfo_wa + 1;
1277  end if;
1278  if(L1Ainfo = '1' and RXCHARISK_q = "00" and (L1Ainfo_wa(1 downto 0) /= "11" or L1Ainfo_WrEn = '0'))then
1279  L1Ainfo_WrEn <= '1';
1280  else
1281  L1Ainfo_WrEn <= '0';
1282  end if;
1283  end if;
1284 end process;
1285 i_L1Ainfo : BRAM_SDP_MACRO
1286  generic map (
1287  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1288  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1289  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1290  READ_WIDTH => 16) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1291  port map (
1292  DO => L1Ainfo_Do, -- Output read data port, width defined by READ_WIDTH parameter
1293  DI => L1Ainfo_Di, -- Input write data port, width defined by WRITE_WIDTH parameter
1294  RDADDR => info_ra, -- Input read address, width defined by read port depth
1295  RDCLK => UsrClk, -- 1-bit input read clock
1296  RDEN => '1', -- 1-bit input read port enable
1297  REGCE => '1', -- 1-bit input read output register enable
1298  RST => '0', -- 1-bit input reset
1299  WE => "11", -- Input write enable, width defined by write port depth
1300  WRADDR => L1Ainfo_wa, -- Input write address, width defined by write port depth
1301  WRCLK => UsrClk, -- 1-bit input write clock
1302  WREN => L1Ainfo_WrEn -- 1-bit input write port enable
1303  );
1304 process(TTSclk)
1305 begin
1306  if(TTSclk'event and TTSclk = '1')then
1307  if(InitLink = '1')then
1308  CriticalTTS <= "000";
1309  else
1310  if(TTS = x"0" or TTS = x"f")then
1311  CriticalTTS(2) <= '1';
1312  end if;
1313  if(TTS = x"c")then
1314  CriticalTTS(1) <= '1';
1315  end if;
1316  if(TTS = x"2")then
1317  CriticalTTS(0) <= '1';
1318  end if;
1319  end if;
1320  end if;
1321 end process;
1322 i_TTS_TRIG_if: TTS_TRIG_if
1323  PORT MAP(
1324  reset => reset,
1325  USE_TRIGGER_PORT => USE_TRIGGER_PORT,
1326  UsrClk => UsrClk,
1327  TTCclk => TTCclk,
1328  BcntRes => BcntRes,
1329  trig => trig,
1330  TTSclk => TTSclk,
1331  TTS => TTS,
1332  RXCHARISK => RXCHARISK,
1333  RXDATA => RXDATA,
1334  sel_TTS_TRIG => sel_TTS_TRIG,
1335  TTS_TRIG_data => TTS_TRIG_data
1336  );
1337 process(UsrClk)
1338 begin
1339  if(UsrClk'event and UsrClk = '1')then
1340  if(info_ra(9 downto 2) = OldL1Ainfo_wa or check_L1Ainfo = '1')then
1341  L1Ainfo_empty <= '1';
1342  elsif(RxL1Ainfo = '0')then
1343  L1Ainfo_empty <= '0';
1344  end if;
1345  if(Header2 = '1' and TypeData = '1')then
1346  RxL1Ainfo <= '1';
1347  elsif(accept = '1' or L1Aabort = '1')then
1348  RxL1Ainfo <= '0';
1349  end if;
1350  if(info_ra(9 downto 2) = AMCinfo_wa(9 downto 2) or check_L1Ainfo = '1')then
1351  AMCinfo_empty <= '1';
1352  else
1353  AMCinfo_empty <= '0';
1354  end if;
1355  if(info_ra(1 downto 0) = "11")then
1356  ce_info_ra <= '0';
1357  elsif(EventStatusCnt(4 downto 3) /= "11" and L1Ainfo_empty = '0' and AMCinfo_empty = '0')then
1358  ce_info_ra <= '1';
1359  end if;
1360  if(InitLink = '1')then
1361  info_ra <= (others => '0');
1362  elsif(ce_info_ra = '1')then
1363  info_ra <= info_ra + 1;
1364  end if;
1365  check_L1Ainfo <= ce_info_ra;
1366  check_L1Ainfo_q <= check_L1Ainfo;
1367  if(L1Ainfo_Do = AMCinfo_Do(15 downto 0))then
1368  L1AinfoMM <= '0';
1369  else
1370  L1AinfoMM <= '1';
1371  end if;
1372  we_EventStatus <= check_L1Ainfo_q and not check_L1Ainfo;
1373  info_ra_q <= info_ra(1 downto 0);
1374  info_ra_q2 <= info_ra_q;
1375  if(check_L1Ainfo_q = '0')then
1376  EventStatus_Di(2 downto 0) <= "111";
1377  elsif(L1AinfoMM = '1')then
1378  case info_ra_q2 is
1379  when "00" => EventStatus_Di(2) <= '0'; -- BcN mismatch
1380  when "11" => EventStatus_Di(1) <= '0'; -- OrN mismatch
1381  when others => EventStatus_Di(0) <= '0'; -- EvN mismatch
1382  end case;
1383  end if;
1384  EventStatusCnt <= EventStatus_wa - EventStatus_ra;
1385  if(EventStatus_wa = EventStatus_ra)then
1386  EventStatus_empty <= '1';
1387  else
1388  EventStatus_empty <= '0';
1389  end if;
1390  if(Ready_i = '0' or InitLink = '1')then
1391  EventStatus_wa <= (others => '0');
1392  elsif(we_EventStatus = '1')then
1393  EventStatus_wa <= EventStatus_wa + 1;
1394  end if;
1395  end if;
1396 end process;
1397 g_EventStatus : for i in 0 to 2 generate
1398  i_EventStatus : RAM32X1D
1399  port map (
1400  DPO => EventStatus(i), -- Read-only 1-bit data output
1401  SPO => open, -- R/W 1-bit data output
1402  A0 => EventStatus_wa (0), -- R/W address[0] input bit
1403  A1 => EventStatus_wa (1), -- R/W address[1] input bit
1404  A2 => EventStatus_wa (2), -- R/W address[2] input bit
1405  A3 => EventStatus_wa (3), -- R/W address[3] input bit
1406  A4 => EventStatus_wa (4), -- R/W address[4] input bit
1407  D => EventStatus_Di (i), -- Write 1-bit data input
1408  DPRA0 => EventStatus_ra (0), -- Read-only address[0] input bit
1409  DPRA1 => EventStatus_ra (1), -- Read-only address[1] input bit
1410  DPRA2 => EventStatus_ra (2), -- Read-only address[2] input bit
1411  DPRA3 => EventStatus_ra (3), -- Read-only address[3] input bit
1412  DPRA4 => EventStatus_ra (4), -- Read-only address[4] input bit
1413  WCLK => UsrClk, -- Write clock input
1414  WE => we_EventStatus -- Write enable input
1415  );
1416 end generate;
1417 EventStatus(6 downto 3) <= (others => '0');
1418 EventStatus_ra <= RdEventCnt;
1419 g_L1A_DATA: for i in 0 to 15 generate
1420  i_L1Adata : RAM32X1D
1421  port map (
1422  DPO => L1A_DATA_o(i), -- Read-only 1-bit data output
1423  SPO => open, -- R/W 1-bit data output
1424  A0 => L1Ainfo_wa(0), -- R/W address[0] input bit
1425  A1 => L1Ainfo_wa(1), -- R/W address[1] input bit
1426  A2 => L1Ainfo_wa(2), -- R/W address[2] input bit
1427  A3 => L1Ainfo_wa(3), -- R/W address[3] input bit
1428  A4 => L1Ainfo_wa(4), -- R/W address[4] input bit
1429  D => L1Ainfo_Di(i), -- Write 1-bit data input
1430  DPRA0 => L1A_DATA_ra(0), -- Read-only address[0] input bit
1431  DPRA1 => L1A_DATA_ra(1), -- Read-only address[1] input bit
1432  DPRA2 => L1A_DATA_ra(2), -- Read-only address[2] input bit
1433  DPRA3 => L1A_DATA_ra(3), -- Read-only address[3] input bit
1434  DPRA4 => L1A_DATA_ra(4), -- Read-only address[4] input bit
1435  WCLK => UsrClk, -- Write clock input
1436  WE => L1Ainfo_WrEn -- Write enable input
1437  );
1438 end generate;
1439 process(sysclk, InitLink)
1440 begin
1441  if(InitLink = '1')then
1442  L1A_DATA_ra <= (others => '0');
1443  L1A_DATA_wa <= (others => '0');
1444  OldL1Ainfo_wa0_SyncRegs <= (others => '0');
1445  L1A_DATA_we <= '0';
1446  L1A_DATA <= (others => '0');
1447  elsif(sysclk'event and sysclk = '1')then
1448  OldL1Ainfo_wa0_SyncRegs <= OldL1Ainfo_wa0_SyncRegs(2 downto 0) & OldL1Ainfo_wa(0);
1449  if(OldL1Ainfo_wa0_SyncRegs(3) /= OldL1Ainfo_wa0_SyncRegs(2))then
1450  L1A_DATA_wa <= L1A_DATA_wa + 1;
1451  end if;
1452  if(L1A_DATA_ra(1 downto 0) = "11")then
1453  ce_L1A_DATA_ra <= '0';
1454  elsif(L1A_DATA_wa /= L1A_DATA_ra(4 downto 2))then
1455  ce_L1A_DATA_ra <= '1';
1456  end if;
1457  if(ce_L1A_DATA_ra = '1')then
1458  L1A_DATA_ra <= L1A_DATA_ra + 1;
1459  end if;
1460  L1A_DATA_we <= ce_L1A_DATA_ra;
1461  L1A_DATA <= L1A_DATA_o;
1462  end if;
1463 end process;
1464 end Behavioral;
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