AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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src
CMS_DAQ_if
5Gb
slink
versioning.vhd
1
library
IEEE
;
2
library
WORK
;
3
use
IEEE.std_logic_1164.
all
;
4
use
IEEE.std_logic_arith.
all
;
5
6
package
mydefs
is
7
constant
version
:
std_logic_vector
(
31
downto
0
)
:=
x
"5E00000D"
;
8
--this
constant
is
defined
to
have
1
ms
with
a
125
Mhz
9
constant
freq_used
:
std_logic_vector
(
31
downto
0
)
:=
x
"0001E848"
;
10
end
package
mydefs
;
11
12
-- version .......
13
--
14
--
15
--*****************************************************************
16
-- version "
5E00000D
" 29/04/2016
17
-- error
on
retransmit
signal
increase tinout x1E0
to
x200
18
--*****************************************************************
19
-- version "
5E00000C
" 25/04/2016
20
-- Bug
on
Timeout
21
-- add debug
on
event_ongoing
and
DUP Header
and
Trailer
22
--*****************************************************************
23
-- version "
5E00000B
" 12/02/2016
24
-- reset the pckt_send counter by daq side
25
--*****************************************************************
26
-- version "
5E00000A
" 29/09/2015
27
-- Change the
signal
used
to
set the serdes_init
28
-- we used gtx_rxcdrlock (datasheet mention that this
signal
is
reserved since 12/2012)
29
-- we
use
now rxbyteisaligned
30
--*****************************************************************
31
-- version "
5E000009
" 24/09/2015
32
-- Did some resync reset
on
Event_generator
33
--*****************************************************************
34
-- version "
5E000008
" 30/03/2015
35
-- Resync
all
reset signals
36
-- large RESET pulse (
5
clocks)
37
-- disable
all
write
to
SLINKXpress incase
of
LInkDown
38
--*****************************************************************
39
-- version "
5E000007
" 21/01/2015
40
-- Add the frequency measure
41
-- large RESET pulse (
3
clocks) ;resync LINKDown
and
Test _mode
42
--*****************************************************************
43
-- version "
5E000006
" 18/12/2014
44
-- Change the CRC instance name :CRC_SLINKx & CRC_generator
45
--
46
--*****************************************************************
47
-- version "
5E000005
" 09/12/2014
48
-- registes data Uctrl
and
WEn
in
INPUT
of
the core
49
--
50
--*****************************************************************
51
-- version "5E000004"
52
-- fixe a bug
on
CRC compute
in
the SLINK sender part
53
--
54
--*****************************************************************
55
-- version "
5E000003
";
56
-- Add a retrasnmit counter
57
-- Counter data has move
to
64
bit
58
--*****************************************************************
59
-- version "
5E000002
";
60
-- Add the reset
of
the FIFO between FED
and
Core done by the resync command
61
-- which reset the sync_num
to
'1'and flush the internal
4
buffers
62
--*****************************************************************
63
-- version "
5E000001
";
64
-- Add some status readable from FED
and
DAQ side
65
--*****************************************************************
66
-- version "
00000000
";
67
-- Beta version used by HCAL
and
TCDS
68
--*****************************************************************
Generated on Wed Apr 18 2018 10:55:26 for AMC13 by
1.8.1
1.8.1
