AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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freq_measure.vhd
1 ------------------------------------------------------
2 -- Frequency Clock detection
3 --
4 -- Ver 1.00
5 --
6 -- Dominique Gigi Jan 2015
7 ------------------------------------------------------
8 -- Measure the clock frequency used by FED
9 --
10 --
11 --
12 ------------------------------------------------------
13 LIBRARY ieee;
14 library work;
15 
16 USE ieee.std_logic_1164.all;
17 use ieee.numeric_std.all;
18 use ieee.std_logic_unsigned.all;
19 use work.mydefs.all;
20 
21 
22 entity freq_measure is
23 port (
24  reset : in std_logic;
25 
26  sysclk : in std_logic;-- clock used by the FED to send data and to measure the backpressure
27  base_clk : in std_logic;-- clock base used to measure the sysclk
28 
29  frequency : out std_logic_vector(31 downto 0)-- measure of the frequency)
30 );
31 end freq_measure;
32 
33 architecture behavioral of freq_measure is
34 
35 signal counter_base : std_logic_vector(31 downto 0);
36 signal counter_measure : std_logic_vector(31 downto 0);
37 signal measure : std_logic_vector(31 downto 0);
38 signal latch_value : std_logic;
39 signal reset_cnt : std_logic;
40 --*********************************************************
41 --************ CODE START HERE ****************
42 --*********************************************************
43 begin
44 
45 -- counter base
46 process(base_clk)
47 begin
48  if rising_edge(base_clk) then
49  -- base on the base_clk of 125 MHz => 8ns => 125000 x to reach 1ms
50  latch_value <= '0';
51  if counter_base = freq_used then
52  counter_base <= (others => '0');
53  latch_value <= '1';
54  else
55  counter_base <= counter_base + '1';
56  end if;
57  end if;
58 end process;
59 
60 
61 -- counter measure
62 process(sysclk,reset_cnt)
63 begin
64  if reset_cnt = '1' then
65  counter_measure <= (others => '0');
66  elsif rising_edge(sysclk) then
67  counter_measure <= counter_measure + '1';
68  end if;
69 end process;
70 
71 -- latch the frequency
72 process(base_clk)
73 begin
74  if rising_edge(base_clk) then
75  reset_cnt <= '0'; -- reset the counter measure when the measure is latched
76  if latch_value = '1' then
77  measure <= counter_measure;
78  reset_cnt <= '1';
79  end if;
80  end if;
81 end process;
82 
83 frequency <= measure;
84 
85 end behavioral;
86 
87 
88