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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ `timescale 1ps/1ps // ===================================================================================================================== // This example design top module instantiates the example design wrapper; slices vectored ports for per-channel // assignment; and instantiates example resources such as buffers, pattern generators, and pattern checkers for core // demonstration purposes // ===================================================================================================================== module gtwizard_ultrascale_0_example_top ( // Differential reference clock inputs input wire mgtrefclk0_x0y3_p, input wire mgtrefclk0_x0y3_n, input wire mgtrefclk1_x0y2_p, input wire mgtrefclk1_x0y2_n, // Differential recovered clock outputs output wire rxrecclkout_chx0y11_p, output wire rxrecclkout_chx0y11_n, output wire rxusrclk, // Added by EBSM (this clock goes through the fabric) // Serial data ports for transceiver channel 0 input wire ch0_gthrxn_in, input wire ch0_gthrxp_in, output wire ch0_gthtxn_out, output wire ch0_gthtxp_out, // User-provided ports for reset helper block(s) input wire hb_gtwiz_reset_clk_freerun_in_p, input wire hb_gtwiz_reset_clk_freerun_in_n, input wire hb_gtwiz_reset_all_in, // PRBS-based link status ports input wire link_down_latched_reset_in, output wire link_status_out, output reg link_down_latched_out = 1'b1, // Link locking status output wire rx_locked_out, output wire tx_aligned_out ); // =================================================================================================================== // PER-CHANNEL SIGNAL ASSIGNMENTS // =================================================================================================================== // The core and example design wrapper vectorize ports across all enabled transceiver channel and common instances for // simplicity and compactness. This example design top module assigns slices of each vector to individual, per-channel // signal vectors for use if desired. Signals which connect to helper blocks are prefixed "hb#", signals which connect // to transceiver common primitives are prefixed "cm#", and signals which connect to transceiver channel primitives // are prefixed "ch#", where "#" is the sequential resource number. //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gthrxn_int; assign gthrxn_int[0:0] = ch0_gthrxn_in; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gthrxp_int; assign gthrxp_int[0:0] = ch0_gthrxp_in; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gthtxn_int; assign ch0_gthtxn_out = gthtxn_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gthtxp_int; assign ch0_gthtxp_out = gthtxp_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_tx_reset_int; wire [0:0] hb0_gtwiz_userclk_tx_reset_int; assign gtwiz_userclk_tx_reset_int[0:0] = hb0_gtwiz_userclk_tx_reset_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_tx_srcclk_int; wire [0:0] hb0_gtwiz_userclk_tx_srcclk_int; assign hb0_gtwiz_userclk_tx_srcclk_int = gtwiz_userclk_tx_srcclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_tx_usrclk_int; wire [0:0] hb0_gtwiz_userclk_tx_usrclk_int; assign hb0_gtwiz_userclk_tx_usrclk_int = gtwiz_userclk_tx_usrclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_tx_usrclk2_int; wire [0:0] hb0_gtwiz_userclk_tx_usrclk2_int; assign hb0_gtwiz_userclk_tx_usrclk2_int = gtwiz_userclk_tx_usrclk2_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_tx_active_int; wire [0:0] hb0_gtwiz_userclk_tx_active_int; assign hb0_gtwiz_userclk_tx_active_int = gtwiz_userclk_tx_active_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_rx_reset_int; wire [0:0] hb0_gtwiz_userclk_rx_reset_int; assign gtwiz_userclk_rx_reset_int[0:0] = hb0_gtwiz_userclk_rx_reset_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_rx_srcclk_int; wire [0:0] hb0_gtwiz_userclk_rx_srcclk_int; assign hb0_gtwiz_userclk_rx_srcclk_int = gtwiz_userclk_rx_srcclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_rx_usrclk_int; wire [0:0] hb0_gtwiz_userclk_rx_usrclk_int; assign hb0_gtwiz_userclk_rx_usrclk_int = gtwiz_userclk_rx_usrclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_rx_usrclk2_int; wire [0:0] hb0_gtwiz_userclk_rx_usrclk2_int; assign hb0_gtwiz_userclk_rx_usrclk2_int = gtwiz_userclk_rx_usrclk2_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_userclk_rx_active_int; wire [0:0] hb0_gtwiz_userclk_rx_active_int; assign hb0_gtwiz_userclk_rx_active_int = gtwiz_userclk_rx_active_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_buffbypass_rx_reset_int; wire [0:0] hb0_gtwiz_buffbypass_rx_reset_int; assign gtwiz_buffbypass_rx_reset_int[0:0] = hb0_gtwiz_buffbypass_rx_reset_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_buffbypass_rx_start_user_int; wire [0:0] hb0_gtwiz_buffbypass_rx_start_user_int = 1'b0; assign gtwiz_buffbypass_rx_start_user_int[0:0] = hb0_gtwiz_buffbypass_rx_start_user_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_buffbypass_rx_done_int; wire [0:0] hb0_gtwiz_buffbypass_rx_done_int; assign hb0_gtwiz_buffbypass_rx_done_int = gtwiz_buffbypass_rx_done_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_buffbypass_rx_error_int; wire [0:0] hb0_gtwiz_buffbypass_rx_error_int; assign hb0_gtwiz_buffbypass_rx_error_int = gtwiz_buffbypass_rx_error_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_clk_freerun_int; wire [0:0] hb0_gtwiz_reset_clk_freerun_int = 1'b0; assign gtwiz_reset_clk_freerun_int[0:0] = hb0_gtwiz_reset_clk_freerun_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_all_int; wire [0:0] hb0_gtwiz_reset_all_int = 1'b0; assign gtwiz_reset_all_int[0:0] = hb0_gtwiz_reset_all_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_tx_pll_and_datapath_int; wire [0:0] hb0_gtwiz_reset_tx_pll_and_datapath_int; //assign gtwiz_reset_tx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_tx_pll_and_datapath_int; //commented by EBSM, tx reset can also be issued by tx_phase_aligner //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_tx_datapath_int; wire [0:0] hb0_gtwiz_reset_tx_datapath_int; assign gtwiz_reset_tx_datapath_int[0:0] = hb0_gtwiz_reset_tx_datapath_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_rx_pll_and_datapath_int; wire [0:0] hb0_gtwiz_reset_rx_pll_and_datapath_int = 1'b0; assign gtwiz_reset_rx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_rx_pll_and_datapath_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_rx_datapath_int; wire [0:0] hb0_gtwiz_reset_rx_datapath_int = 1'b0; assign gtwiz_reset_rx_datapath_int[0:0] = hb0_gtwiz_reset_rx_datapath_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_rx_cdr_stable_int; wire [0:0] hb0_gtwiz_reset_rx_cdr_stable_int; assign hb0_gtwiz_reset_rx_cdr_stable_int = gtwiz_reset_rx_cdr_stable_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_tx_done_int; wire [0:0] hb0_gtwiz_reset_tx_done_int; assign hb0_gtwiz_reset_tx_done_int = gtwiz_reset_tx_done_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtwiz_reset_rx_done_int; wire [0:0] hb0_gtwiz_reset_rx_done_int; assign hb0_gtwiz_reset_rx_done_int = gtwiz_reset_rx_done_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [31:0] gtwiz_userdata_tx_int; wire [31:0] hb0_gtwiz_userdata_tx_int; wire tx_data_sel; assign gtwiz_userdata_tx_int[31:0] = (tx_data_sel) ? (32'b00000000000000011111111111111110) : hb0_gtwiz_userdata_tx_int; //modified by EBSM to include clock pattern //-------------------------------------------------------------------------------------------------------------------- wire [31:0] gtwiz_userdata_rx_int; wire [31:0] hb0_gtwiz_userdata_rx_int; assign hb0_gtwiz_userdata_rx_int = gtwiz_userdata_rx_int[31:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtrefclk00_int; wire [0:0] cm0_gtrefclk00_int; assign gtrefclk00_int[0:0] = cm0_gtrefclk00_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] gtrefclk01_int; wire [0:0] cm0_gtrefclk01_int; assign gtrefclk01_int[0:0] = cm0_gtrefclk01_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] qpll0outclk_int; wire [0:0] cm0_qpll0outclk_int; assign cm0_qpll0outclk_int = qpll0outclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] qpll0outrefclk_int; wire [0:0] cm0_qpll0outrefclk_int; assign cm0_qpll0outrefclk_int = qpll0outrefclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] qpll1outclk_int; wire [0:0] cm0_qpll1outclk_int; assign cm0_qpll1outclk_int = qpll1outclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] qpll1outrefclk_int; wire [0:0] cm0_qpll1outrefclk_int; assign cm0_qpll1outrefclk_int = qpll1outrefclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [8:0] drpaddr_int; //wire [8:0] ch0_drpaddr_int = 9'b000000000; //commented by EBSM - controlled by phase aligner //assign drpaddr_int[8:0] = ch0_drpaddr_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] drpclk_int; //wire [0:0] ch0_drpclk_int = 1'b0; //commented by EBSM - use clk_sys for drp for phase aligner //assign drpclk_int[0:0] = ch0_drpclk_int; //-------------------------------------------------------------------------------------------------------------------- wire [15:0] drpdi_int; //wire [15:0] ch0_drpdi_int = 16'b0000000000000000; //commented by EBSM - controlled by phase aligner //assign drpdi_int[15:0] = ch0_drpdi_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] drpen_int; //wire [0:0] ch0_drpen_int = 1'b0; //commented by EBSM - controlled by phase aligner //assign drpen_int[0:0] = ch0_drpen_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] drpwe_int; //wire [0:0] ch0_drpwe_int = 1'b0; //commented by EBSM - controlled by phase aligner //assign drpwe_int[0:0] = ch0_drpwe_int; //-------------------------------------------------------------------------------------------------------------------- wire [2:0] loopback_int; // This vector is not sliced because it is directly assigned in a debug core instance below //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxcdrreset_int; // This vector is not sliced because it is directly assigned in a debug core instance below //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxpolarity_int; wire [0:0] ch0_rxpolarity_int = 1'b0; assign rxpolarity_int[0:0] = ch0_rxpolarity_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxprbscntreset_int; // This vector is not sliced because it is directly assigned in a debug core instance below //-------------------------------------------------------------------------------------------------------------------- wire [3:0] rxprbssel_int; // This vector is not sliced because it is directly assigned in a debug core instance below //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxslide_int; //wire [0:0] ch0_rxslide_int = 1'b0; //commented by EBSM - controlled by word aligner //assign rxslide_int[0:0] = ch0_rxslide_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txpippmen_int; //wire [0:0] ch0_txpippmen_int = 1'b0; //commented by EBSM - controlled by phase aligner //assign txpippmen_int[0:0] = ch0_txpippmen_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txpippmovrden_int; //wire [0:0] ch0_txpippmovrden_int = 1'b0; //commented by EBSM - controlled by phase aligner //assign txpippmovrden_int[0:0] = ch0_txpippmovrden_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txpippmpd_int; //wire [0:0] ch0_txpippmpd_int = 1'b0; //commented by EBSM - controlled by phase aligner //assign txpippmpd_int[0:0] = ch0_txpippmpd_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txpippmsel_int; //wire [0:0] ch0_txpippmsel_int = 1'b0; //commented by EBSM - controlled by phase aligner //assign txpippmsel_int[0:0] = ch0_txpippmsel_int; //-------------------------------------------------------------------------------------------------------------------- wire [4:0] txpippmstepsize_int; //wire [4:0] ch0_txpippmstepsize_int = 5'b00000; //commented by EBSM - controlled by phase aligner //assign txpippmstepsize_int[4:0] = ch0_txpippmstepsize_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txpolarity_int; wire [0:0] ch0_txpolarity_int = 1'b0; assign txpolarity_int[0:0] = ch0_txpolarity_int; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txprbsforceerr_int; // This vector is not sliced because it is directly assigned in a debug core instance below //-------------------------------------------------------------------------------------------------------------------- wire [3:0] txprbssel_int; // This vector is not sliced because it is directly assigned in a debug core instance below //-------------------------------------------------------------------------------------------------------------------- wire [15:0] drpdo_int; wire [15:0] ch0_drpdo_int; assign ch0_drpdo_int = drpdo_int[15:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] drprdy_int; wire [0:0] ch0_drprdy_int; assign ch0_drprdy_int = drprdy_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxcdrlock_int; wire [0:0] ch0_rxcdrlock_int; assign ch0_rxcdrlock_int = rxcdrlock_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxoutclk_int; wire [0:0] ch0_rxoutclk_int; assign ch0_rxoutclk_int = rxoutclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxoutclkpcs_int; wire [0:0] ch0_rxoutclkpcs_int; assign ch0_rxoutclkpcs_int = rxoutclkpcs_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxpmaresetdone_int; wire [0:0] ch0_rxpmaresetdone_int; assign ch0_rxpmaresetdone_int = rxpmaresetdone_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxprbserr_int; wire [0:0] ch0_rxprbserr_int; assign ch0_rxprbserr_int = rxprbserr_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxprbslocked_int; wire [0:0] ch0_rxprbslocked_int; assign ch0_rxprbslocked_int = rxprbslocked_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] rxrecclkout_int; wire [0:0] ch0_rxrecclkout_int; assign ch0_rxrecclkout_int = rxrecclkout_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [1:0] txbufstatus_int; wire [1:0] ch0_txbufstatus_int; assign ch0_txbufstatus_int = txbufstatus_int[1:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txoutclk_int; wire [0:0] ch0_txoutclk_int; assign ch0_txoutclk_int = txoutclk_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txoutclkfabric_int; wire [0:0] ch0_txoutclkfabric_int; assign ch0_txoutclkfabric_int = txoutclkfabric_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txoutclkpcs_int; wire [0:0] ch0_txoutclkpcs_int; assign ch0_txoutclkpcs_int = txoutclkpcs_int[0:0]; //-------------------------------------------------------------------------------------------------------------------- wire [0:0] txpmaresetdone_int; wire [0:0] ch0_txpmaresetdone_int; assign ch0_txpmaresetdone_int = txpmaresetdone_int[0:0]; // =================================================================================================================== // BUFFERS // =================================================================================================================== // Buffer the hb_gtwiz_reset_all_in input and logically combine it with the internal signal from the example // initialization block as well as the VIO-sourced reset wire hb_gtwiz_reset_all_vio_int; wire hb_gtwiz_reset_all_buf_int; wire hb_gtwiz_reset_all_init_int; wire hb_gtwiz_reset_all_int; IBUF ibuf_hb_gtwiz_reset_all_inst ( .I (hb_gtwiz_reset_all_in), .O (hb_gtwiz_reset_all_buf_int) ); assign hb_gtwiz_reset_all_int = hb_gtwiz_reset_all_buf_int || hb_gtwiz_reset_all_init_int || hb_gtwiz_reset_all_vio_int; // Globally buffer the free-running input clock wire hb_gtwiz_reset_clk_freerun_buf_int; //Modified by EBSM - use differential buffer for free-running clock // IBUFDS: Differential Input Buffer // UltraScale // Xilinx HDL Libraries Guide, version 2014.1 IBUFDS #( .DQS_BIAS("FALSE") // (FALSE, TRUE) ) IBUFDS_inst ( .O(hb_gtwiz_reset_clk_freerun_buf_int), // 1-bit output: Buffer output .I(hb_gtwiz_reset_clk_freerun_in_p), // 1-bit input: Diff_p buffer input (connect directly to top-level port) .IB(hb_gtwiz_reset_clk_freerun_in_n) // 1-bit input: Diff_n buffer input (connect directly to top-level port) ); // End of IBUFDS_inst instantiation //BUFG bufg_clk_freerun_inst ( // .I (hb_gtwiz_reset_clk_freerun_in), // .O (hb_gtwiz_reset_clk_freerun_buf_int) //); // Instantiate a differential reference clock buffer for each reference clock differential pair in this configuration, // and assign the single-ended output of each differential reference clock buffer to the appropriate PLL input signal // Differential reference clock buffer for MGTREFCLK0_X0Y3 wire mgtrefclk0_x0y3_int; IBUFDS_GTE3 #( .REFCLK_EN_TX_PATH (1'b0), .REFCLK_HROW_CK_SEL (2'b00), .REFCLK_ICNTL_RX (2'b00) ) IBUFDS_GTE3_MGTREFCLK0_X0Y3_INST ( .I (mgtrefclk0_x0y3_p), .IB (mgtrefclk0_x0y3_n), .CEB (1'b0), .O (mgtrefclk0_x0y3_int), .ODIV2 () ); // Differential reference clock buffer for MGTREFCLK1_X0Y2 wire mgtrefclk1_x0y2_int; IBUFDS_GTE3 #( .REFCLK_EN_TX_PATH (1'b0), .REFCLK_HROW_CK_SEL (2'b00), .REFCLK_ICNTL_RX (2'b00) ) IBUFDS_GTE3_MGTREFCLK1_X0Y2_INST ( .I (mgtrefclk1_x0y2_p), .IB (mgtrefclk1_x0y2_n), .CEB (1'b0), .O (mgtrefclk1_x0y2_int), .ODIV2 () ); assign cm0_gtrefclk00_int = mgtrefclk1_x0y2_int; assign cm0_gtrefclk01_int = mgtrefclk0_x0y3_int; // Instantiate a differential recovered clock output buffer for each channel which drives out its recovered clock // Differential recovered clock buffer for channel X0Y11 OBUFDS_GTE3 #( .REFCLK_EN_TX_PATH (1'b1), .REFCLK_ICNTL_TX (5'b00111) ) OBUFDS_GTE3_CHX0Y11_INST ( .O (rxrecclkout_chx0y11_p), .OB (rxrecclkout_chx0y11_n), .CEB (1'b0), .I (ch0_rxrecclkout_int) ); // Added by EBSM - output the recovered clock which goes through the fabric wire rxusrclk_oddr; // ODDRE1: Dedicated Dual Data Rate (DDR) Output Register // Ultrascale // Xilinx HDL Libraries Guide, version 2014.1 ODDRE1 #( .IS_C_INVERTED(1'b0) // Optional inversion for C ,.IS_D1_INVERTED(1'b0) // Optional inversion for D1 ,.IS_D2_INVERTED(1'b0) // Optional inversion for D2 ,.SRVAL(1'b0) // Initializes the ODDRE1 Flip-Flops to the specified value ('0', '1') ) ODDRE1_rxusrclk_inst( .Q(rxusrclk_oddr) // 1-bit output: Data output to IOB ,.C(hb0_gtwiz_userclk_rx_usrclk2_int[0]) // 1-bit input: High-speed clock input ,.D1(1'b0) // 1-bit input: Parallel data input 1 ,.D2(1'b1) // 1-bit input: Parallel data input 2 ,.SR(1'b0) // 1-bit input: Active High Async Reset ); // End of ODDRE1_rxoutclk_inst instantiation assign rxusrclk = rxusrclk_oddr; //// OBUFDS: Differential Output Buffer //// UltraScale //// Xilinx HDL Libraries Guide, version 2014.1 //OBUFDS #( //) OBUFDS_rxoutclk_inst ( // .O(rxusrclk_p), // 1-bit output: Diff_p output (connect directly to top-level port) // .OB(rxusrclk_n), // 1-bit output: Diff_n output (connect directly to top-level port) // .I(rxusrclk_oddr) // 1-bit input: Buffer input // ); // End of OBUFDS_rxoutclk_inst instantiation // =================================================================================================================== // USER CLOCKING RESETS // =================================================================================================================== // The TX user clocking helper block should be held in reset until the clock source of that block is known to be // stable. The following assignment is an example of how that stability can be determined, based on the selected TX // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed. assign hb0_gtwiz_userclk_tx_reset_int = ~(&txpmaresetdone_int); // The RX user clocking helper block should be held in reset until the clock source of that block is known to be // stable. The following assignment is an example of how that stability can be determined, based on the selected RX // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed. assign hb0_gtwiz_userclk_rx_reset_int = ~(&rxpmaresetdone_int); // =================================================================================================================== // BUFFER BYPASS CONTROLLER RESETS // =================================================================================================================== // The RX buffer bypass controller helper block should be held in reset until the RX user clocking network helper // block which drives it is active (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_rx_reset_inst ( .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), .rst_in (~hb0_gtwiz_userclk_rx_active_int), .rst_out (hb0_gtwiz_buffbypass_rx_reset_int) ); // =================================================================================================================== // PRBS STIMULUS, CHECKING, AND LINK MANAGEMENT // =================================================================================================================== // PRBS stimulus // ------------------------------------------------------------------------------------------------------------------- //The block gtwizard_ultrascale_0_example_stimulus_raw was modified by EBSM - 30b prbs generation // PRBS-based data stimulus module for transceiver channel 0 (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_stimulus_raw example_stimulus_inst0 ( .gtwiz_reset_all_in (hb_gtwiz_reset_all_int), .gtwiz_userclk_tx_usrclk2_in (hb0_gtwiz_userclk_tx_usrclk2_int), .gtwiz_userclk_tx_active_in (tx_aligned), //hb0_gtwiz_userclk_tx_active_int), .txdata_out (hb0_gtwiz_userdata_tx_int[31:2]) ); assign hb0_gtwiz_userdata_tx_int[1:0] = 2'b10; // 2b header for word alignment // PRBS checking // ------------------------------------------------------------------------------------------------------------------- // Declare a signal vector of PRBS match indicators, with one indicator bit per transceiver channel wire [0:0] prbs_match_int; //The block gtwizard_ultrascale_0_example_checking_raw was modified by EBSM - 30b prbs checking // PRBS-based data checking module for transceiver channel 0 gtwizard_ultrascale_0_example_checking_raw example_checking_inst0 ( .gtwiz_reset_all_in (hb_gtwiz_reset_all_int || ~hb0_gtwiz_reset_rx_done_int || ~hb0_gtwiz_buffbypass_rx_done_int), .gtwiz_userclk_rx_usrclk2_in (hb0_gtwiz_userclk_rx_usrclk2_int), .gtwiz_userclk_rx_active_in (hb0_gtwiz_userclk_rx_active_int), .rxdata_in (hb0_gtwiz_userdata_rx_int[31:2]), .prbs_match_out (prbs_match_int[0]) ); // Added Rx word alignment by EBSM // Rx word alignment wire reset_word_aligner = ~(gtwiz_reset_rx_done_int && gtwiz_buffbypass_rx_done_int); wire header; assign header = hb0_gtwiz_userdata_rx_int[1] & (~hb0_gtwiz_userdata_rx_int[0]); wire rx_locked; wire rx_reset_from_word_aligner; rx_word_aligner rx_word_aligner_inst ( .clk_rxusr_i(hb0_gtwiz_userclk_rx_usrclk2_int) ,.reset_i(reset_word_aligner) ,.enable_i(1'b1) ,.header_i(header) ,.rx_locked_o(rx_locked) ,.rx_slide_o(rxslide_int[0]) ,.clk_sys_i(hb_gtwiz_reset_clk_freerun_buf_int) ,.rx_reset_o(rx_reset_from_word_aligner) ); assign rx_locked_out = rx_locked; // PRBS match and related link management // ------------------------------------------------------------------------------------------------------------------- // Perform a bitwise NAND of all PRBS match indicators, creating a combinatorial indication of any PRBS mismatch // across all transceiver channels wire prbs_error_any_async = ~(&prbs_match_int); wire prbs_error_any_sync; // Synchronize the PRBS mismatch indicator the free-running clock domain, using a reset synchronizer with asynchronous // reset and synchronous removal (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_reset_synchronizer reset_synchronizer_prbs_match_all_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .rst_in (prbs_error_any_async), .rst_out(prbs_error_any_sync) ); // Implement an example link status state machine using a simple leaky bucket mechanism. The link status indicates // the continual PRBS match status to both the top-level observer and the initialization state machine, while being // tolerant of occasional bit errors. This is an example and can be modified as necessary. localparam ST_LINK_DOWN = 1'b0; localparam ST_LINK_UP = 1'b1; reg sm_link = ST_LINK_DOWN; reg [6:0] link_ctr = 7'd0; always @(posedge hb_gtwiz_reset_clk_freerun_buf_int) begin case (sm_link) // The link is considered to be down when the link counter initially has a value less than 67. When the link is // down, the counter is incremented on each cycle where all PRBS bits match, but reset whenever any PRBS mismatch // occurs. When the link counter reaches 67, transition to the link up state. ST_LINK_DOWN: begin if (prbs_error_any_sync !== 1'b0 ) begin link_ctr <= 7'd0; end else begin if (link_ctr < 7'd67) link_ctr <= link_ctr + 7'd1; else sm_link <= ST_LINK_UP; end end // When the link is up, the link counter is decreased by 34 whenever any PRBS mismatch occurs, but is increased by // only 1 on each cycle where all PRBS bits match, up to its saturation point of 67. If the link counter reaches // 0 (including rollover protection), transition to the link down state. ST_LINK_UP: begin if (prbs_error_any_sync !== 1'b0) begin if (link_ctr > 7'd33) begin link_ctr <= link_ctr - 7'd34; if (link_ctr == 7'd34) sm_link <= ST_LINK_DOWN; end else begin link_ctr <= 7'd0; sm_link <= ST_LINK_DOWN; end end else begin if (link_ctr < 7'd67) link_ctr <= link_ctr + 7'd1; end end endcase end // Synchronize the latched link down reset input and the VIO-driven signal into the free-running clock domain wire link_down_latched_reset_vio_int; wire link_down_latched_reset_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_link_down_latched_reset_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (link_down_latched_reset_in || link_down_latched_reset_vio_int), .o_out (link_down_latched_reset_sync) ); // Reset the latched link down indicator when the synchronized latched link down reset signal is high. Otherwise, set // the latched link down indicator upon losing link. This indicator is available for user reference. always @(posedge hb_gtwiz_reset_clk_freerun_buf_int) begin if (link_down_latched_reset_sync) link_down_latched_out <= 1'b0; else if (!sm_link) link_down_latched_out <= 1'b1; end // Assign the link status indicator to the top-level two-state output for user reference assign link_status_out = sm_link; // =================================================================================================================== // TX_PHASE_ALIGNER signals - EBSM // =================================================================================================================== wire tx_aligned; // The Transmitter reset is only considered to be finished once the phase aligner has finished alignment wire reset_tx_phase_aligner; assign reset_tx_phase_aligner = ~gtwiz_reset_tx_done_vio_sync; wire [6:0] tx_pi_phase; wire [31:0] tx_fifo_fill_pd; wire tx_ui_align_calib; wire [6:0] tx_pi_phase_calib; wire [31:0] tx_fifo_fill_pd_max; wire tx_fine_realign; assign gtwiz_reset_tx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_tx_pll_and_datapath_int; assign tx_aligned_out = tx_aligned; // =================================================================================================================== // INITIALIZATION // =================================================================================================================== // Declare the receiver reset signals that interface to the reset controller helper block. For this configuration, // which uses different PLL types for transmitter and receiver, the "reset RX datapath" feature is not used. wire hb_gtwiz_reset_rx_pll_and_datapath_int; wire hb_gtwiz_reset_rx_datapath_int = 1'b0; // Declare signals which connect the VIO instance to the initialization module for debug purposes wire init_done_int; wire [3:0] init_retry_ctr_int; // Combine the receiver reset signals form the initialization module and the VIO to drive the appropriate reset // controller helper block reset input wire hb_gtwiz_reset_rx_pll_and_datapath_vio_int; wire hb_gtwiz_reset_rx_datapath_vio_int; wire hb_gtwiz_reset_rx_pll_and_datapath_init_int; assign hb_gtwiz_reset_rx_pll_and_datapath_int = hb_gtwiz_reset_rx_pll_and_datapath_init_int || hb_gtwiz_reset_rx_pll_and_datapath_vio_int || rx_reset_from_word_aligner; //Included also reset from word aligner (EBSM) // The block gtwizard_ultrascale_0_example_init and its connections were modified by EBSM // The example initialization module interacts with the reset controller helper block and other example design logic // to retry failed reset attempts in order to mitigate bring-up issues such as initially-unavilable reference clocks // or data connections. It also resets the receiver in the event of link loss in an attempt to regain link, so please // note the possibility that this behavior can have the effect of overriding or disturbing user-provided inputs that // destabilize the data stream. It is a demonstration only and can be modified to suit your system needs. gtwizard_ultrascale_0_example_init example_init_inst ( .clk_freerun_in (hb_gtwiz_reset_clk_freerun_buf_int), .reset_all_in (hb_gtwiz_reset_all_int), .tx_init_done_in (tx_aligned),//(gtwiz_reset_tx_done_int), The Transmitter reset is only considered to be finished once the phase aligner has finished alignment .rx_init_done_in (rx_locked), //(gtwiz_reset_rx_done_int && gtwiz_buffbypass_rx_done_int), The receiver is only considered locked when the word aligner has finished .rx_data_good_in (1'b1), //(sm_link), do not reset if seeing prbs errors .reset_all_out (hb_gtwiz_reset_all_init_int), .reset_rx_out (hb_gtwiz_reset_rx_pll_and_datapath_init_int), .init_done_out (init_done_int), .retry_ctr_out (init_retry_ctr_int) ); // =================================================================================================================== // VIO FOR HARDWARE BRING-UP AND DEBUG // =================================================================================================================== // Synchronize txpmaresetdone into the free-running clock domain for VIO usage wire [0:0] txpmaresetdone_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txpmaresetdone_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (txpmaresetdone_int[0]), .o_out (txpmaresetdone_vio_sync[0]) ); // Synchronize rxpmaresetdone into the free-running clock domain for VIO usage wire [0:0] rxpmaresetdone_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxpmaresetdone_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (rxpmaresetdone_int[0]), .o_out (rxpmaresetdone_vio_sync[0]) ); // Synchronize gtwiz_reset_tx_done into the free-running clock domain for VIO usage wire [0:0] gtwiz_reset_tx_done_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_reset_tx_done_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (gtwiz_reset_tx_done_int[0]), .o_out (gtwiz_reset_tx_done_vio_sync[0]) ); // Synchronize gtwiz_reset_rx_done into the free-running clock domain for VIO usage wire [0:0] gtwiz_reset_rx_done_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_reset_rx_done_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (gtwiz_reset_rx_done_int[0]), .o_out (gtwiz_reset_rx_done_vio_sync[0]) ); // Synchronize gtwiz_buffbypass_rx_done into the free-running clock domain for VIO usage wire [0:0] gtwiz_buffbypass_rx_done_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_done_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (gtwiz_buffbypass_rx_done_int[0]), .o_out (gtwiz_buffbypass_rx_done_vio_sync[0]) ); // Synchronize gtwiz_buffbypass_rx_error into the free-running clock domain for VIO usage wire [0:0] gtwiz_buffbypass_rx_error_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_error_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (gtwiz_buffbypass_rx_error_int[0]), .o_out (gtwiz_buffbypass_rx_error_vio_sync[0]) ); // Synchronize rxprbserr into the free-running clock domain for VIO usage wire [0:0] rxprbserr_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbserr_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (rxprbserr_int[0]), .o_out (rxprbserr_vio_sync[0]) ); // Synchronize rxprbslocked into the free-running clock domain for VIO usage wire [0:0] rxprbslocked_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbslocked_0_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (rxprbslocked_int[0]), .o_out (rxprbslocked_vio_sync[0]) ); // Synchronize rx_locked into the free-running clock domain for VIO usage (EBSM) wire [0:0] rx_locked_vio_sync; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rx_locked_inst ( .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), .i_in (rx_locked), .o_out (rx_locked_vio_sync[0]) ); // Synchronize txprbssel into the TXUSRCLK2 clock domain from VIO usage wire [3:0] txprbssel_vio_async; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_0_inst ( .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), .i_in (txprbssel_vio_async[0]), .o_out (txprbssel_int[0]) ); (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_1_inst ( .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), .i_in (txprbssel_vio_async[1]), .o_out (txprbssel_int[1]) ); (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_2_inst ( .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), .i_in (txprbssel_vio_async[2]), .o_out (txprbssel_int[2]) ); (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_3_inst ( .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), .i_in (txprbssel_vio_async[3]), .o_out (txprbssel_int[3]) ); // Synchronize rxprbssel into the RXUSRCLK2 clock domain from VIO usage wire [3:0] rxprbssel_vio_async; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_0_inst ( .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), .i_in (rxprbssel_vio_async[0]), .o_out (rxprbssel_int[0]) ); (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_1_inst ( .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), .i_in (rxprbssel_vio_async[1]), .o_out (rxprbssel_int[1]) ); (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_2_inst ( .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), .i_in (rxprbssel_vio_async[2]), .o_out (rxprbssel_int[2]) ); (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_3_inst ( .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), .i_in (rxprbssel_vio_async[3]), .o_out (rxprbssel_int[3]) ); // Synchronize txprbsforceerr into the TXUSRCLK2 clock domain from VIO usage wire [0:0] txprbsforceerr_vio_async; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbsforceerr_0_inst ( .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), .i_in (txprbsforceerr_vio_async[0]), .o_out (txprbsforceerr_int[0]) ); // Synchronize rxprbscntreset into the RXUSRCLK2 clock domain from VIO usage wire [0:0] rxprbscntreset_vio_async; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbscntreset_0_inst ( .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), .i_in (rxprbscntreset_vio_async[0]), .o_out (rxprbscntreset_int[0]) ); // Synchronize tx_data_sel into the TXUSRCLK2 clock domain from VIO usage (EBSM) wire tx_data_sel_vio_async; (* DONT_TOUCH = "TRUE" *) gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_tx_data_sel_0_inst ( .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), .i_in (tx_data_sel_vio_async), .o_out (tx_data_sel) ); // Instantiate the VIO IP core for hardware bring-up and debug purposes, connecting relevant debug and analysis // signals which have been enabled during Wizard IP customization. This initial set of connected signals is // provided as a convenience and example, but more or fewer ports can be used as needed; simply re-customize and // re-generate the VIO instance, then connect any exposed signals that are needed. Signals which are synchronous to // clocks other than the free-running clock will require synchronization. For usage, refer to Vivado Design Suite // User Guide: Programming and Debugging (UG908) gtwizard_ultrascale_0_vio_0 gtwizard_ultrascale_0_vio_0_inst ( .clk (hb_gtwiz_reset_clk_freerun_buf_int) ,.probe_in0 (link_status_out) ,.probe_in1 (link_down_latched_out) ,.probe_in2 (init_done_int) ,.probe_in3 (init_retry_ctr_int) ,.probe_in4 (txpmaresetdone_vio_sync) ,.probe_in5 (rxpmaresetdone_vio_sync) ,.probe_in6 (gtwiz_reset_tx_done_vio_sync) ,.probe_in7 (gtwiz_reset_rx_done_vio_sync) ,.probe_in8 (gtwiz_buffbypass_rx_done_vio_sync) ,.probe_in9 (gtwiz_buffbypass_rx_error_vio_sync) ,.probe_in10 (rxprbserr_vio_sync) ,.probe_in11 (rxprbslocked_vio_sync) ,.probe_in12 (tx_aligned) //Added for the phase aligner exdsg (EBSM) ,.probe_in13 (tx_pi_phase) //Added for the phase aligner exdsg (EBSM) ,.probe_in14 (tx_fifo_fill_pd) //Added for the phase aligner exdsg (EBSM) ,.probe_in15 (rx_locked_vio_sync) //Added to check receiver is properly word locked (EBSM) ,.probe_out0 (hb_gtwiz_reset_all_vio_int) ,.probe_out1 (hb0_gtwiz_reset_tx_pll_and_datapath_int) ,.probe_out2 (hb0_gtwiz_reset_tx_datapath_int) ,.probe_out3 (hb_gtwiz_reset_rx_pll_and_datapath_vio_int) ,.probe_out4 (hb_gtwiz_reset_rx_datapath_vio_int) ,.probe_out5 (link_down_latched_reset_vio_int) ,.probe_out6 (rxcdrreset_int) ,.probe_out7 (loopback_int) ,.probe_out8 (txprbssel_vio_async) ,.probe_out9 (rxprbssel_vio_async) ,.probe_out10 (txprbsforceerr_vio_async) ,.probe_out11 (rxprbscntreset_vio_async) ,.probe_out12 (tx_ui_align_calib) //Added for the phase aligner exdsg (EBSM) ,.probe_out13 (tx_fine_realign) //Added for the phase aligner exdsg (EBSM) ,.probe_out14 (tx_pi_phase_calib) //Added for the phase aligner exdsg (EBSM) ,.probe_out15 (tx_fifo_fill_pd_max) //Added for the phase aligner exdsg (EBSM) ,.probe_out16 (tx_data_sel_vio_async) //Added for the phase aligner exdsg (EBSM) ); // =================================================================================================================== // EXAMPLE WRAPPER INSTANCE // =================================================================================================================== // Instantiate the example design wrapper, mapping its enabled ports to per-channel internal signals and example // resources as appropriate gtwizard_ultrascale_0_example_wrapper example_wrapper_inst ( .gthrxn_in (gthrxn_int) ,.gthrxp_in (gthrxp_int) ,.gthtxn_out (gthtxn_int) ,.gthtxp_out (gthtxp_int) ,.gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_int) ,.gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_int) ,.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_int) ,.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_int) ,.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int) ,.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_int) ,.gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_int) ,.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_int) ,.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_int) ,.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_int) ,.gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_int) ,.gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_int) ,.gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_int) ,.gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_int) ,.gtwiz_reset_clk_freerun_in ({1{hb_gtwiz_reset_clk_freerun_buf_int}}) ,.gtwiz_reset_all_in ({1{hb_gtwiz_reset_all_int}}) ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_int) ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_int) ,.gtwiz_reset_rx_pll_and_datapath_in ({1{hb_gtwiz_reset_rx_pll_and_datapath_int}}) ,.gtwiz_reset_rx_datapath_in ({1{hb_gtwiz_reset_rx_datapath_int}}) ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_int) ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_int) ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_int) ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_int) ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_int) ,.gtrefclk00_in (gtrefclk00_int) ,.gtrefclk01_in (gtrefclk01_int) ,.qpll0outclk_out (qpll0outclk_int) ,.qpll0outrefclk_out (qpll0outrefclk_int) ,.qpll1outclk_out (qpll1outclk_int) ,.qpll1outrefclk_out (qpll1outrefclk_int) ,.drpaddr_in (drpaddr_int) ,.drpclk_in (hb_gtwiz_reset_clk_freerun_buf_int)//(drpclk_int) (EBSM) ,.drpdi_in (drpdi_int) ,.drpen_in (drpen_int) ,.drpwe_in (drpwe_int) ,.loopback_in (loopback_int) ,.rxcdrreset_in (rxcdrreset_int) ,.rxpolarity_in (rxpolarity_int) ,.rxprbscntreset_in (rxprbscntreset_int) ,.rxprbssel_in (rxprbssel_int) ,.rxslide_in (rxslide_int) ,.txpippmen_in (txpippmen_int) ,.txpippmovrden_in (txpippmovrden_int) ,.txpippmpd_in (txpippmpd_int) ,.txpippmsel_in (txpippmsel_int) ,.txpippmstepsize_in (txpippmstepsize_int) ,.txpolarity_in (txpolarity_int) ,.txprbsforceerr_in (txprbsforceerr_int) ,.txprbssel_in (txprbssel_int) ,.drpdo_out (drpdo_int) ,.drprdy_out (drprdy_int) ,.rxcdrlock_out (rxcdrlock_int) ,.rxoutclk_out (rxoutclk_int) ,.rxoutclkpcs_out (rxoutclkpcs_int) ,.rxpmaresetdone_out (rxpmaresetdone_int) ,.rxprbserr_out (rxprbserr_int) ,.rxprbslocked_out (rxprbslocked_int) ,.rxrecclkout_out (rxrecclkout_int) ,.txbufstatus_out (txbufstatus_int) ,.txoutclk_out (txoutclk_int) ,.txoutclkfabric_out (txoutclkfabric_int) ,.txoutclkpcs_out (txoutclkpcs_int) ,.txpmaresetdone_out (txpmaresetdone_int) ); wire tx_ps_done; //============================================================================== // Phase aligner instantiation //============================================================================== tx_phase_aligner tx_phase_aligner_inst( //============================================================================== // User control/monitor ports //============================================================================== // Clock / reset .clk_sys_i(hb_gtwiz_reset_clk_freerun_buf_int) // system clock input ,.reset_i(reset_tx_phase_aligner) // active high sync. reset // Top level interface ,.tx_aligned_o(tx_aligned) // Use it as a reset for the user transmitter logic // Config (for different flavours) ,.tx_pi_phase_calib_i(tx_pi_phase_calib) // previous calibrated tx pi phase (tx_pi_phase_o after first reset calibration) ,.tx_ui_align_calib_i(tx_ui_align_calib) // align with previous calibrated tx pi phase ,.tx_fifo_fill_pd_max_i(tx_fifo_fill_pd_max) // phase detector accumulated max output, sets precision of phase detector // this is supposedly a static signal, this block shall be reset whenever this signal changes // the time for each phase detection after a clear is given by tx_fifo_fill_pd_max_i * PERIOD_clk_txusr_i ,.tx_fine_realign_i(tx_fine_realign) // It is only valid to re-shift clock once aligned (tx_aligned_o = '1') ,.ps_strobe_i(1'b0) ,.ps_inc_ndec_i(1'b0) ,.ps_phase_step_i(4'h0) ,.ps_done_o(tx_ps_done) // Tx PI phase value ,.tx_pi_phase_o(tx_pi_phase) // phase shift accumulated // Tx fifo fill level phase detector ,.tx_fifo_fill_pd_o(tx_fifo_fill_pd) // phase detector output, when aligned this value should be close to (0x2_0000) //============================================================================== // MGT ports //============================================================================== ,.clk_txusr_i(hb0_gtwiz_userclk_tx_usrclk2_int) // txusr2clk // Tx fifo fill level - see Xilinx transceiver User Guide for more information ,.tx_fifo_fill_level_i(txbufstatus_int[0]) // connect to txbufstatus[0] // Transmitter PI ports - see Xilinx transceiver User Guide for more information // obs1: all txpi ports shall be connected to the transceiver even when using this block in DRP-mode ,.txpippmen_o(txpippmen_int) // enable tx phase interpolator controller ,.txpippmovrden_o(txpippmovrden_int) // enable DRP control of tx phase interpolator ,.txpippmsel_o(txpippmsel_int) // set to 1 when using tx pi ppm controler ,.txpippmpd_o(txpippmpd_int) // power down transmitter phase interpolator ,.txpippmstepsize_o(txpippmstepsize_int) // sets step size and direction of phase shift with port control PI code stepping mode // DRP interface - see Xilinx transceiver User Guide for more information // obs2: connect clk_sys_i to drpclk // obs3: if using this block in port-mode, DRP output can be left floating and input connected to '0' ,.drpaddr_o(drpaddr_int) // For devices with a 10-bit DRP address interface, connect MSB to '0' ,.drpen_o(drpen_int) // DRP enable transaction ,.drpdi_o(drpdi_int) // DRP data write ,.drprdy_i(drprdy_int) // DRP finished transaction ,.drpdo_i(drpdo_int) // DRP data read; not used nowadays, write only interface ,.drpwe_o(drpwe_int) // DRP write enable ); endmodule