add wave -position insertpoint  \
sim:/tb_lpgbt10g/g_DATARATE \
sim:/tb_lpgbt10g/g_FEC \
sim:/tb_lpgbt10g/g_PAYLOAD_LENGTH \
sim:/tb_lpgbt10g/TEST_BENCH_STATUS_O \
sim:/tb_lpgbt10g/FECMONITOR_O \
sim:/tb_lpgbt10g/PRBSMONITOR_O \
sim:/tb_lpgbt10g/common_clk_sys \
sim:/tb_lpgbt10g/common_clk_mgt \
sim:/tb_lpgbt10g/prbsgen_strobe_cntr \
sim:/tb_lpgbt10g/prbsgen_strobe \
sim:/tb_lpgbt10g/prbsgen_reset \
sim:/tb_lpgbt10g/prbsgen_seed \
sim:/tb_lpgbt10g/prbsgen_load \
sim:/tb_lpgbt10g/prbsgen_frame \
sim:/tb_lpgbt10g/Tx_reset \
sim:/tb_lpgbt10g/Tx_tx_strobe \
sim:/tb_lpgbt10g/Tx_tx_data \
sim:/tb_lpgbt10g/Tx_tx_ec \
sim:/tb_lpgbt10g/Tx_tx_ic \
sim:/tb_lpgbt10g/Tx_tx_word \
sim:/tb_lpgbt10g/Tx_scrambler_bypass \
sim:/tb_lpgbt10g/Tx_interleaver_bypass \
sim:/tb_lpgbt10g/Tx_tx_error \
sim:/tb_lpgbt10g/channel_reset \
sim:/tb_lpgbt10g/channel_ready \
sim:/tb_lpgbt10g/channel_rx_data \
sim:/tb_lpgbt10g/channel_data \
sim:/tb_lpgbt10g/channel_bitslide_r \
sim:/tb_lpgbt10g/channel_bitslip_position \
sim:/tb_lpgbt10g/channel_rx_frame_reset_phy \
sim:/tb_lpgbt10g/Rx_uplinkClkOutEn \
sim:/tb_lpgbt10g/Rx_uplinkRst_n \
sim:/tb_lpgbt10g/Rx_mgt_word \
sim:/tb_lpgbt10g/Rx_USErData \
sim:/tb_lpgbt10g/Rx_EcData \
sim:/tb_lpgbt10g/Rx_IcData \
sim:/tb_lpgbt10g/Rx_bypassInterleaver \
sim:/tb_lpgbt10g/Rx_bypassFECEncoder \
sim:/tb_lpgbt10g/Rx_bypassScrambler \
sim:/tb_lpgbt10g/Rx_mgt_bitslipCtrl \
sim:/tb_lpgbt10g/Rx_rst_mgtctrler \
sim:/tb_lpgbt10g/Rx_rst_rstoneven \
sim:/tb_lpgbt10g/Rx_dataCorrected \
sim:/tb_lpgbt10g/Rx_IcCorrected \
sim:/tb_lpgbt10g/Rx_EcCorrected \
sim:/tb_lpgbt10g/Rx_rdy \
sim:/tb_lpgbt10g/prbschk_reset \
sim:/tb_lpgbt10g/prbschk_frame \
sim:/tb_lpgbt10g/prbschk_strobe \
sim:/tb_lpgbt10g/prbschk_gen \
sim:/tb_lpgbt10g/prbschk_error \
sim:/tb_lpgbt10g/prbschk_locked