-- ngFEC core logic -- Original designer: M. Ozgur Sahin (OS): -- email: ozgur.sahin@desy.de, ozgur.sahin@cern.ch -- Developers: F.Costanza (FC), francesco.costanza@desy.de, francesco.costanza@cern.ch -- OS -- functionality: -- next generation Front End Control module: Distriubtes the LHC clock, fast control commands (from TCDS) and -- slow control commands (from CCM Server) to the Front-end readout electonics of HCAL and collects diagnostic -- information in return. -- Important modules: -- gbtDsgn: modified CERN FPGA GBT implementation. Two instances, each can control 3 GBT links (SFP+ -- connections to FE) $ code is taken from CERN-GBT Groups reference design and modified -- DTC: Recovers the TTC signal from AMC13 $ code is modified from the uHTR rep. -- ngFEC module: buffers and executes the commands that are received from the CCM server via IPBUS. -- Then it stores and sends back the responses. -- TTC Counter: Counts BC0, QIE reset, even and odd TTC stream errors. It also includes a histogram for -- the BC0 signal which holds the timing information of the signal (early, late, ontime) -- ngCCM_GBT module: It is a modified version of Stephen Goadhouse's ngCCM_GBT module. Unlike the former version, -- it can control all I2C links simultanously: It also has a PRBS error rate counter implementation from Tugba Karakaya. -- Current version: 3.1.0 29.03.2017 -- Version logs: -- #1.1.0 17.11.2015 QIE reset signal is now driven directly from BC0 -- #1.2.0 10.01.2016 Unnecessary I2C busses are cleaned from the code -- #1.2.a 19.01.2016 Fast control signals are looped back, unnecessary I2C busses are cleaned from the code -- #1.3.0 27.01.2016 GBT TX and RX latency_optimized, new debug pin module, Stephen Goadhouse's fix (FC) -- #1.4.0 14.03.2016 JTAG programming for QIE cards, I2C reduced delay, 100KHz I2C freq (FC) -- #1.7.0 01.06.2016 JTAG programming using buffers for reducing ipbus transactions (FC) -- #1.8.0 15.06.2016 Changes for FC7-R2 (FC) -- #2.0.0 19.11.2016 The major GBT (4.1) fix for the RS dec is implemented -- JTAG module has been improved with a longer JTAG signal, JTAG signal hysteresis and filter has been implemented. -- The JTAG logic condition locking the state to timeout has been modified. -- Minor bug fixes. -- RS FEC Raw error counter is implemented. -- #2.1.0 04.12.2016 Major changes in the i2c_master_bit_ctrl as recommended by Stephen Goadhouse. -- Added glitch_filter for i2c -- sfp i2c inferface -- redundant path implementation -- #2.1.2 15.12.2016 QIE_RESET delay ctrl_reg(14+sfp)(11 downto 0), ctrl_reg(14+sfp)(27 downto 16) -- SFP TX switch using ctrl_reg(21)(sfp) -- fec_bkp_pwr_flip_cnt reset using ctrl_reg(5)(sfp) -- jtag reset using ctrl_reg(8+sfp)(jtag_partition)(FC) -- new JTAG filtering -- WTE def updated according to -- http://cmsdoc.cern.ch/cms/HCAL/document/CountingHouse/TTC/TTCcommands.html -- #2.1.3 20.12.2016 fixed a bug on SEL_ADDR -- #2.1.4 24.01.2017 added local_reset to partition -- #2.1.5 24.01.2017 bkp commands on a special partition -- #2.1.6 27.01.2017 redundant partitions are removed -- #2.1.7 additional partition check when writing to bram -- #2.1.8 18.02.2017 fixed shorter tick TCK in JTAG_master -- #3.0.0 23.03.2017 Migration to Vivado 2016.3, 5.0.2 system fw, 5.0.0 GBT-FPGA core -- #3.1.0 29.03.2017 Phase monitoring activated library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; --! system packages use work.ipbus.all; use work.system_package.all; --! user packages use work.user_package.all; use work.user_version_package.all; use work.ngFEC_pack.all; -- Custom libraries and packages: use work.gbt_bank_package.all; use work.vendor_specific_gbt_bank_package.all; library unisim; use unisim.vcomponents.all; Library xpm; use xpm.vcomponents.all; entity ngFEC_logic is port ( --# led usrled1_r : out std_logic; -- fmc_l12_spare[8] usrled1_g : out std_logic; -- fmc_l12_spare[9] usrled1_b : out std_logic; -- fmc_l12_spare[10] usrled2_r : out std_logic; -- fmc_l12_spare[11] usrled2_g : out std_logic; -- fmc_l12_spare[12] usrled2_b : out std_logic; -- fmc_l12_spare[13] header : inout std_logic_vector(10 downto 9); -- header P4 pins 9 & 10 (schematics page 6 "K7_GEN_IO") --## cdce mgt clk ttc_mgt_xpoint_a_p : in std_logic; ttc_mgt_xpoint_a_n : in std_logic; ttc_mgt_xpoint_b_p : in std_logic; ttc_mgt_xpoint_b_n : in std_logic; ttc_mgt_xpoint_c_p : in std_logic; ttc_mgt_xpoint_c_n : in std_logic; fmc_l12_pg_m2c : in std_logic; fmc_l12_prsnt_l : in std_logic; fmc_l8_pg_m2c : in std_logic; fmc_l8_prsnt_l : in std_logic; --# fmc mgt -- fmc_l8_dp_c2m_p : out std_logic_vector( 3 downto 0); -- fmc_l8_dp_c2m_n : out std_logic_vector( 3 downto 0); -- fmc_l8_dp_m2c_p : in std_logic_vector( 3 downto 0); -- fmc_l8_dp_m2c_n : in std_logic_vector( 3 downto 0); -- fmc_l12_dp_c2m_p : out std_logic_vector( 11 downto 0); -- fmc_l12_dp_c2m_n : out std_logic_vector( 11 downto 0); -- fmc_l12_dp_m2c_p : in std_logic_vector( 11 downto 0); -- fmc_l12_dp_m2c_n : in std_logic_vector( 11 downto 0); fmc_sfp_tx_p : out std_logic_vector( 1 to 12); fmc_sfp_tx_n : out std_logic_vector( 1 to 12); fmc_sfp_rx_p : in std_logic_vector( 1 to 12); fmc_sfp_rx_n : in std_logic_vector( 1 to 12); --# fmc fabric clk fmc_l8_clk0 : in std_logic; fmc_l8_clk1 : in std_logic; fmc_l12_clk0 : in std_logic; fmc_l12_clk1 : in std_logic; --# fmc gpio fmc_l8_la_p : inout std_logic_vector(33 downto 0); fmc_l8_la_n : inout std_logic_vector(33 downto 0); fmc_l12_la_p : inout std_logic_vector(33 downto 0); fmc_l12_la_n : inout std_logic_vector(33 downto 0); --# amc fabric k7_fabric_amc_rx_p03 : in std_logic; k7_fabric_amc_rx_n03 : in std_logic; k7_fabric_amc_tx_p03 : out std_logic; --not used k7_fabric_amc_tx_n03 : out std_logic; --not used --==========================-- -- system_core interface --==========================-- --# cdce cdce_pll_lock_i : in std_logic; -- new port [PV 2015.08.19] cdce_pri_clk_bufg_o : out std_logic; -- new port [PV 2015.08.19] cdce_ref_sel_o : out std_logic; -- new port [PV 2015.08.19] cdce_pwrdown_o : out std_logic; -- new port [PV 2015.08.19] cdce_sync_o : out std_logic; -- new port [PV 2015.08.19] cdce_sync_clk_o : out std_logic; -- new port [PV 2015.08.19] --# system clk fabric_clk_p : in std_logic; fabric_clk_n : in std_logic; osc125_a_bufg_i : in std_logic; osc125_a_mgtrefclk_i : in std_logic; osc125_b_bufg_i : in std_logic; osc125_b_mgtrefclk_i : in std_logic; clk_31_250_bufg_i : in std_logic; -- new port [PV 2015.08.19] --# ipbus comm ipb_clk_o : out std_logic; ipb_rst_i : in std_logic; ipb_miso_o : out ipb_rbus_array(0 to nbr_usr_slaves-1); ipb_mosi_i : in ipb_wbus_array(0 to nbr_usr_slaves-1); --# ipbus conf ip_addr_o : out std_logic_vector(31 downto 0); mac_addr_o : out std_logic_vector(47 downto 0); rarp_en_o : out std_logic; use_i2c_eeprom_o : out std_logic ); end ngFEC_logic; architecture ngFEC of ngFEC_logic is --===========================================-- -- clocks --===========================================-- signal fabric_clk_nobuf, fabric_clk : STD_LOGIC; signal ttcMgtXpoint_from_ibufdsAGtxe2 : STD_LOGIC; signal ttcMgtXpoint_from_ibufdsAGtxe2_buf : STD_LOGIC; signal ttc_clk_nobuf, ttc_clk : STD_LOGIC; signal ttcMgtXpoint_from_ibufdsCGtxe2 : STD_LOGIC; signal ttcMgtXpoint_from_ibufdsCGtxe2_buf : STD_LOGIC; --===========================================-- --===========================================-- --TTC/TTT signal handling --===========================================-- signal COUNTERS : TTC_COUNTER_REGS; signal reset : STD_LOGIC; signal l1accept : STD_LOGIC; signal BCntRes : STD_LOGIC; signal EvCntRes : STD_LOGIC; signal SinErrStr : STD_LOGIC; signal DbErrStr : STD_LOGIC; signal Brcst : STD_LOGIC_VECTOR(7 downto 2); signal BrcstStr : STD_LOGIC; signal QIE_RESET : STD_LOGIC_VECTOR(1 to 12); signal WTE : STD_LOGIC; component DTC_top is Port ( TTC_data_p : in STD_LOGIC; TTC_data_n : in STD_LOGIC; TTC_CLK : in STD_LOGIC; TTC_rst : in STD_LOGIC; Clock200ref : in STD_LOGIC; TTCready : out STD_LOGIC; L1Accept : out STD_LOGIC; BCntRes : out STD_LOGIC; EvCntRes : out STD_LOGIC; SinErrStr : out STD_LOGIC; DbErrStr : out STD_LOGIC; BrcstStr : out STD_LOGIC; Brcst : out STD_LOGIC_VECTOR (7 downto 2)); end component DTC_top; component ttc_counter is Port( ttc_clk_i : in STD_LOGIC; counters : out ttc_counter_regs; BC0_missing : out STD_LOGIC; L1Accept : in STD_LOGIC; BCntRes : in STD_LOGIC; EvCntRes : in STD_LOGIC; SinErrStr : in STD_LOGIC; DbErrStr : in STD_LOGIC; BrcstStr : in STD_LOGIC; Brcst : in STD_LOGIC_VECTOR(7 downto 2); reset_i : in STD_LOGIC); end component ttc_counter; --===========================================-- --===========================================-- -- clock monitors --===========================================-- COMPONENT clkRateTool32 IS GENERIC (CLKREF_RATE_IN_MHZ : INTEGER); PORT ( clkref : IN STD_LOGIC; clktest : IN STD_LOGIC; clktest_en : IN STD_LOGIC; clkvalue: IN STD_LOGIC; value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT clkRateTool32; --===========================================-- COMPONENT delay_counter GENERIC( orbit : INTEGER range 0 to 4095 ); PORT( din : IN std_logic; shift_i : IN std_logic_vector(11 downto 0); clk_i : IN std_logic; reset_i : IN std_logic; dout : OUT std_logic); END COMPONENT; COMPONENT clk_divide3 Port ( clk_i : in STD_LOGIC; reset_i : in STD_LOGIC; refclk_i : in STD_LOGIC; clk_o : out STD_LOGIC); end COMPONENT; component xlx_k7v7_gbt_ngFEC_design generic ( NUM_LINKS : integer := 1; TX_OPTIMIZATION : integer range 0 to 1 := LATENCY_OPTIMIZED; RX_OPTIMIZATION : integer range 0 to 1 := LATENCY_OPTIMIZED; TX_ENCODING : integer range 0 to 1 := GBT_FRAME; RX_ENCODING : integer range 0 to 1 := GBT_FRAME ); port ( --==============-- -- Clocks -- --==============-- TX_FRAMECLK_I : in std_logic; XCVRCLK : in std_logic; TX_CLKEN_I : in std_logic; RX_CLKEN_O : out std_logic_vector(1 to NUM_LINKS); RX_WORDCLK_O : out std_logic_vector(1 to NUM_LINKS); TX_CLKEN_O : out std_logic_vector(1 to NUM_LINKS); TX_WORDCLK_O : out std_logic_vector(1 to NUM_LINKS); RX_WORDCLK_RDY_O : out std_logic_vector(1 to NUM_LINKS); RX_FRAMECLK_RDY_O : out std_logic_vector(1 to NUM_LINKS); --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I : in std_logic; GBTBANK_MANUAL_RESET_TX_I : in std_logic; GBTBANK_MANUAL_RESET_RX_I : in std_logic; GBT_CHANNEL_RESET_TX_I : in std_logic_vector(1 to NUM_LINKS); GBT_CHANNEL_RESET_RX_I : in std_logic_vector(1 to NUM_LINKS); GBT_DATA_VALID : in std_logic_vector(1 to NUM_LINKS); GBT_PD : in std_logic_vector(1 to NUM_LINKS); --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P : in std_logic_vector(1 to NUM_LINKS); GBTBANK_MGT_RX_N : in std_logic_vector(1 to NUM_LINKS); GBTBANK_MGT_TX_P : out std_logic_vector(1 to NUM_LINKS); GBTBANK_MGT_TX_N : out std_logic_vector(1 to NUM_LINKS); --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I : in gbt_reg84_A(1 to NUM_LINKS); GBTBANK_WB_DATA_I : in gbt_reg116_A(1 to NUM_LINKS); TX_DATA_O : out gbt_reg84_A(1 to NUM_LINKS); WB_DATA_O : out gbt_reg116_A(1 to NUM_LINKS); GBTBANK_GBT_DATA_O : out gbt_reg84_A(1 to NUM_LINKS); GBTBANK_WB_DATA_O : out gbt_reg116_A(1 to NUM_LINKS); --==============-- -- Reconf. -- --==============-- GBTBANK_MGT_DRP_RST : in std_logic; GBTBANK_MGT_DRP_CLK : in std_logic; --==============-- -- TX ctrl -- --==============-- TX_ENCODING_SEL_i : in std_logic_vector(1 to NUM_LINKS); --! Select the Tx encoding in dynamic mode ('1': GBT / '0': WideBus) GBTBANK_TX_ISDATA_SEL_I : in std_logic_vector(1 to NUM_LINKS); --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i : in std_logic_vector(1 to NUM_LINKS); --! Select the Rx encoding in dynamic mode ('1': GBT / '0': WideBus) GBTBANK_RXBITSLIP_RSTONEVEN_I : in std_logic_vector(1 to NUM_LINKS); --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O : out std_logic_vector(1 to NUM_LINKS); GBTBANK_LINK_READY_O : out std_logic_vector(1 to NUM_LINKS); GBTBANK_TX_ALIGNED_O : out std_logic_vector(1 to NUM_LINKS); GBTBANK_TX_ALIGNCOMPUTED_O : out std_logic_vector(1 to NUM_LINKS); --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O : out std_logic_vector(1 to NUM_LINKS); GBTBANK_RX_ISDATA_SEL_O : out std_logic_vector(1 to NUM_LINKS); GBTBANK_RX_ERRORDETECTED_O : out std_logic_vector(1 to NUM_LINKS); GBTBANK_RX_BITMODIFIED_FLAG_O : out gbt_reg84_A(1 to NUM_LINKS); GBTBANK_RXBITSLIP_RST_CNT_O : out gbt_reg8_A(1 to NUM_LINKS); --==============-- -- XCVR ctrl -- --==============-- GBTBANK_LOOPBACK_I : in std_logic_vector(2 downto 0); GBTBANK_TX_POL : in std_logic_vector(1 to NUM_LINKS); GBTBANK_RX_POL : in std_logic_vector(1 to NUM_LINKS) ); end component; COMPONENT debug_mux IS port( global_signal_sel : in std_logic_vector(6 downto 0); sfp_signal_sel : in std_logic_vector(5 downto 0); sfp_sel : in std_logic_vector(2 downto 0); ttc_clk : in std_logic; qie_reset : in std_logic; tx_wordclk : in std_logic; tx_frameclk : in std_logic_vector(0 to 7); rx_frameclk : in std_logic_vector(0 to 7); rx_wordclk : in std_logic_vector(0 to 7); rx_frameclk_locked : in std_logic_vector(0 to 7); rx_wordclk_locked : in std_logic_vector(0 to 7); sfp_sda : in std_logic_vector(0 to 7); sfp_scl : in std_logic_vector(0 to 7); debug_out : out std_logic ); END COMPONENT debug_mux; component pm is Port ( reset : in STD_LOGIC; fabric_clk : in STD_LOGIC; ipb_clk : in STD_LOGIC; tx_wordclk : in STD_LOGIC; sample_PS : in STD_LOGIC; update_status : in STD_LOGIC; fabric_clk_PS : in STD_LOGIC; fabric_clk_PS_toggle : in STD_LOGIC; pscnt : in STD_LOGIC_VECTOR (9 downto 0); status : out STD_LOGIC_VECTOR (31 downto 0)); end component; function SFP2GBT(a : in integer) return integer is variable v: integer; begin if (a = 1) then v := 4; elsif (a < 5) then v := a - 1; elsif (a < 9) then v := a + 4; else v := a - 4; end if; return v; end function; signal ipb_clk : std_logic; -- signal ctrl_reg : array_32x32bit; signal stat_reg : array_256x32bit; --------------------------------------- signal cdce_pri_clk_bufg : std_logic; signal cdce_sync_from_ipb_n : std_logic; signal cdce_sel_from_ipb : std_logic; signal cdce_pwrdown_from_ipb_n : std_logic; signal cdce_ctrl_from_ipb_n : std_logic; ---------------------- -- gbt/gtx signals ---------------------- -- clocks signal GBT_TxFrame_ce : std_logic_vector(1 to 12); signal GBT_tx_wordclk : std_logic_vector(1 to 12); signal GBT_RxFrame_ce : std_logic_vector(1 to 12); signal GBT_rx_wordclk : std_logic_vector(1 to 12); signal TxFrame_ce : std_logic_vector(1 to 12); signal tx_wordclk : std_logic_vector(1 to 12); signal RxFrame_ce : std_logic_vector(1 to 12); signal rx_wordclk : std_logic_vector(1 to 12); signal rx_wordclk_locked : std_logic_vector(1 TO 12); signal RxFrame_locked : std_logic_vector(1 TO 12); signal GBT_rx_wordclk_locked : std_logic_vector(1 TO 12); signal GBT_RxFrame_locked : std_logic_vector(1 TO 12); signal rst_dmdt, rst_dmdt_n, phmon_clk, dmdt_phase_meas_clk : std_logic; -- reset signal reset_gbtbank : std_logic_vector(4 downto 1); -- Serial lanes signal GBT_tx_p : std_logic_vector(1 to 12); signal GBT_tx_n : std_logic_vector(1 to 12); signal GBT_rx_p : std_logic_vector(1 to 12); signal GBT_rx_n : std_logic_vector(1 to 12); -- data signal ngccm_tx : gbt_reg84_A(1 to 12); signal GBT_tx_data : gbt_reg84_A(1 to 12); signal GBT_rx_data : gbt_reg84_A(1 to 12); signal rx_data : gbt_reg84_A(1 to 12); -- RX ctrl signal rx_reset : std_logic := '0'; -- TX Status signal GBT_mgt_ready : std_logic_vector(1 to 12); signal GBT_tx_ready : std_logic_vector(1 to 12); -- RX Status signal gbt_rx_ready : std_logic_vector(1 to 12); signal sfp_rx_ready : std_logic_vector(1 to 12); signal GBT_rx_data_valid : std_logic_vector(1 to 12); signal GBT_rx_rs_err : std_logic_vector(1 to 12); signal rx_rs_err : std_logic_vector(1 to 12); signal rx_data_valid : std_logic_vector(1 to 12); signal rx_data_valid_r : std_logic_vector(1 to 12); signal sfp_rx_locked_and_ready : std_logic_vector(1 TO 12); -- ngccm declarations signal ngccm_mosi : ipb_sfp_in; signal ngccm_miso : ipb_sfp_out; signal TimeoutError : std_logic_vector(1 to 12); signal sfp_abs : std_logic_vector(1 to 12); signal sfp_tx_fault : std_logic_vector(1 to 12); signal sfp_rx_lost : std_logic_vector(1 to 12); --gbt counter signals--------------------------------------- type gbtRX_sfp_register is array (natural range <>) of std_logic_vector(31 downto 0); signal sfp_register : gbtRX_sfp_register(1 to 12); signal rx_los_counter : gbtRX_sfp_register(1 to 12); -- signal rs_raw_error_counter : gbtRX_sfp_register(1 to 12); signal ngccm_rx_down_counter : gbtRX_sfp_register(1 to 12); -- --------------------------------------- -- --------------------------------------- signal reg_sfp_I2C_prescale : gbtRX_sfp_register(1 to 12); signal PRBS_rx_pattern_error_cnt : gbtRX_sfp_register(1 to 12); signal PRBS_rx_pattern_bitwise_error_cnt : gbtRX_sfp_register(1 to 12); signal GBT_data_valid : std_logic_vector(1 to 12); signal GBT_abs : std_logic_vector(1 to 12); --sfp i2c signal sfp_sda_i : std_logic_vector(1 to 12); signal sfp_sda_o : std_logic_vector(1 to 12); signal sfp_scl_i : std_logic_vector(1 to 12); signal sfp_scl_o : std_logic_vector(1 to 12); signal sfp_sda_sec_i : std_logic_vector(1 to 12); signal sfp_sda_sec_o : std_logic_vector(1 to 12); signal sfp_scl_sec_i : std_logic_vector(1 to 12); signal sfp_scl_sec_o : std_logic_vector(1 to 12); signal fabric_clk_OUT0 : std_logic; signal fabric_clk_OUT1 : std_logic; signal fabric_clk_sel : std_logic := '0'; signal fabric_clk_FBOUT : std_logic; signal fabric_clk_LOCKED : std_logic; signal fabric_clk_RST : std_logic := '0'; signal g_resetl12 : std_logic := '0'; signal g_resetl8 : std_logic := '0'; signal fabric_clk_div2 : std_logic; --signal pm_reset : std_logic_vector(3 downto 0) := (others => '0'); signal pm_reset : std_logic := '0'; signal PSCNT : std_logic_vector(9 downto 0) := (others => '0'); signal PS_TIMEOUT_CNT : std_logic_vector(7 downto 0) := (others => '0'); signal fabric_clk_PSOUT : std_logic := '0'; signal fabric_clk_PS_toggle : std_logic := '0'; signal fabric_clk_PS : std_logic := '0'; signal PSDONE : std_logic := '0'; signal PSDONE_dl16 : std_logic := '0'; signal PSDONE_dl32 : std_logic := '0'; signal PSEN : std_logic := '0'; signal PSEN_q : std_logic := '0'; signal sample_PS: std_logic := '0'; signal update_toggle : std_logic := '0'; signal update_status : std_logic := '0'; signal update_toggle_Sync_Regs : std_logic_vector(3 downto 0) := (others => '0'); signal fabric_clk_LOCK_lost : std_logic_vector(1 downto 0); signal cdce_pll_lock_lost : std_logic_vector(1 downto 0); signal rx_frameclk_locked_sync : std_logic_vector(11 downto 0); signal tx_ready_sync : std_logic_vector(11 downto 0); signal bkp_pwr_enable : std_logic_vector(12 downto 1); signal bkp_pwr_enable_r : std_logic_vector(12 downto 1); signal channel_mgt_txreset : std_logic_vector(1 to 12); signal channel_mgt_rxreset : std_logic_vector(1 to 12); signal ngCCM_status_counter : array12X8X32; --signal PMclk_LOCKED : std_logic := '0'; --signal FRAMECLK_20MHZ_toggle_dl : std_logic_vector(0 to 1); --signal ipb_clk_cntr : std_logic_vector(9 downto 0); --signal ipb_clk_sync1 : std_logic_vector(3 downto 0); --signal ipb_clk_sync2 : std_logic_vector(3 downto 0); --signal ipb_clk_sync3 : std_logic_vector(3 downto 0); --signal ipb_clk_sync4 : std_logic_vector(3 downto 0); --signal ipb_clk_sync5 : std_logic_vector(3 downto 0); --signal ipb_clk_sync6 : std_logic_vector(3 downto 0); --signal ipb_clk_sync7 : std_logic_vector(3 downto 0); --signal ipb_clk_sync8 : std_logic_vector(3 downto 0); --attribute mark_debug : string; --attribute mark_debug of rx_frameclk_locked : signal is "true"; --attribute mark_debug of rx_wordclk_locked : signal is "true"; --attribute mark_debug of sfp_abs : signal is "true"; --attribute mark_debug of sfp_rx_lost : signal is "true"; --attribute mark_debug of FRAMECLK_20MHZ_q : signal is "true"; attribute pullup : string; attribute pullup of sfp_abs, sfp_rx_lost : signal is "true"; begin -- --===========================================-- -- clocks --===========================================-- fclk_ibuf: ibufgds port map (i => fabric_clk_p, ib => fabric_clk_n, o => fabric_clk_nobuf); fabric_clk_MMCME2 : MMCME2_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) CLKFBOUT_MULT_F => 18.0, -- Multiply value for all CLKOUT (2.000-64.000). -- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). CLKOUT0_DIVIDE_F => 18.0, -- Divide amount for CLKOUT0 (1.000-128.000). CLKIN1_PERIOD => 24.999, COMPENSATION => "EXTERNAL", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL CLKOUT0_PHASE => 0.0, -- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE) CLKOUT0_USE_FINE_PS => TRUE ) port map ( -- Clock Outputs: 1-bit (each) output: User configurable clock outputs CLKOUT0 => fabric_clk_PSOUT, -- 1-bit output: CLKOUT0 -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs PSDONE => PSDONE, -- 1-bit output: Phase shift done -- Feedback Clocks: 1-bit (each) output: Clock feedback ports CLKFBOUT => fabric_clk_FBOUT, -- 1-bit output: Feedback clock -- Status Ports: 1-bit (each) output: MMCM status ports LOCKED => fabric_clk_LOCKED, -- 1-bit output: LOCK -- Clock Inputs: 1-bit (each) input: Clock inputs CLKIN1 => fabric_clk_nobuf, -- 1-bit input: Primary clock CLKIN2 => '0', -- 1-bit input: Secondary clock -- Control Ports: 1-bit (each) input: MMCM control ports CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2 PWRDWN => '0', -- 1-bit input: Power-down RST => fabric_clk_RST, -- 1-bit input: Reset -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports DADDR => (others => '0'), -- 7-bit input: DRP address DCLK => '0', -- 1-bit input: DRP clock DEN => '0', -- 1-bit input: DRP enable DI => (others => '0'), -- 16-bit input: DRP data DWE => '0', -- 1-bit input: DRP write enable -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs PSCLK => fabric_clk, -- 1-bit input: Phase shift clock PSEN => PSEN, -- 1-bit input: Phase shift enable PSINCDEC => '1', -- 1-bit input: Phase shift increment/decrement -- Feedback Clocks: 1-bit (each) input: Clock feedback ports CLKFBIN => fabric_clk -- 1-bit input: Feedback clock ); fclk_bufg: bufg port map (i => fabric_clk_FBOUT, o => fabric_clk); fabric_clk_PS_bufg: bufg port map (i => fabric_clk_PSOUT, o => fabric_clk_PS); process(fabric_clk,fabric_clk_LOCKED) begin if(fabric_clk_LOCKED = '0')then PSEN <= '0'; PSCNT <= (others => '0'); PS_TIMEOUT_CNT <= (others => '0'); elsif(fabric_clk'event and fabric_clk = '1')then if(PS_TIMEOUT_CNT = x"ff" or PSDONE_dl32 = '1')then PSEN <= '1'; else PSEN <= '0'; end if; if(PSEN = '1')then PS_TIMEOUT_CNT <= (others => '0'); else PS_TIMEOUT_CNT <= PS_TIMEOUT_CNT + 1; end if; if(PSDONE = '1')then if(PSCNT = "0101001111")then PSCNT <= (others => '0'); else PSCNT <= PSCNT + 1; end if; end if; end if; end process; i_PSDONE_dl32 : SRLC32E port map (Q31 => PSDONE_dl32, Q => PSDONE_dl16, A => "01111", CE => fabric_clk_LOCKED, CLK => fabric_clk, D => PSDONE); process(fabric_clk) begin if(fabric_clk'event and fabric_clk = '1')then fabric_clk_div2 <= not fabric_clk_div2; end if; end process; cdceOut1IbufdsAGtxe2: ibufds_gte2 port map ( O => ttcMgtXpoint_from_ibufdsAGtxe2, --cdce out U0 LHC CLK freq*3 (120) ODIV2 => open, CEB => '0', I => ttc_mgt_xpoint_a_p, IB => ttc_mgt_xpoint_a_n); cdceOut0IbufdsCGtxe2: ibufds_gte2 port map ( O => ttcMgtXpoint_from_ibufdsCGtxe2, --cdce out U0 LHC CLK freq*3 (120) ODIV2 => open, CEB => '0', I => ttc_mgt_xpoint_c_p, IB => ttc_mgt_xpoint_c_n); --#############################-- --#############################-- --## dmdt phase measurement ###-- --#############################-- --#############################-- i_ttcMgtXpoint_from_ibufdsCGtxe2_buf: bufh port map(i => ttcMgtXpoint_from_ibufdsCGtxe2, o => ttcMgtXpoint_from_ibufdsCGtxe2_buf); i_ttcMgtXpoint_from_ibufdsAGtxe2_buf: bufh port map(i => ttcMgtXpoint_from_ibufdsAGtxe2, o => ttcMgtXpoint_from_ibufdsAGtxe2_buf); rst_dmdt <= ipb_rst_i or (not cdce_pll_lock_i and not ctrl_reg(1)(8)) or ctrl_reg(1)(9); rst_dmdt_n <= not rst_dmdt; --=============================-- phmon: entity work.clk_divide3 --=============================-- PORT MAP ( clk_i => ttcMgtXpoint_from_ibufdsCGtxe2_buf, reset_i => rst_dmdt, refclk_i => fabric_clk, clk_o => phmon_clk); --=============================-- dmdt_clk: entity work.dmdt_clock_gen --=============================-- PORT MAP ( rst_mmcm1_i => rst_dmdt, rst_mmcm2_i => rst_dmdt, refclk_i => fabric_clk, dmdt_clk_o => dmdt_phase_meas_clk, mmcm1_locked_o => open, mmcm2_locked_o => open); --=============================-- dmdt_meas: entity work.dmtd_phase_meas -- ohwr --=============================-- generic map (g_deglitcher_threshold => 2000) port map( clk_sys_i => ipb_clk, clk_a_i => fabric_clk, clk_b_i => phmon_clk, clk_dmtd_i => dmdt_phase_meas_clk, -- rst_n_i => rst_dmdt_n, en_i => '1',--dmdt_phase_meas_en(i), navg_i => x"3ff", phase_meas_o => stat_reg(74), clk_s_ticks_o => stat_reg(75), clk_a_ticks_o => stat_reg(76), dv_o => open); --===========================================-- -- ipbus management --===========================================-- ipb_clk <= clk_31_250_bufg_i; -- select the frequency of the ipbus clock ipb_clk_o <= ipb_clk; -- always forward the selected ipb_clk to system core -- ip_addr_o <= x"c0_a8_00_50"; mac_addr_o <= x"aa_bb_cc_dd_ee_50"; -- x"aa_bb_cc_dd_ee" & dipsw; -- switch J7 (pins pulled-up inside the FPGA) rarp_en_o <= '1'; use_i2c_eeprom_o <= '1'; --===========================================-- --===================================-- cdce_synch: entity work.cdce_synchronizer --===================================-- generic map ( pwrdown_delay => 1000, sync_delay => 1000000 ) port map ( reset_i => ipb_rst_i, ------------------ ipbus_ctrl_i => cdce_ctrl_from_ipb_n, -- default: 1 (ipb controlled) ipbus_sel_i => cdce_sel_from_ipb, -- default: 0 (select secondary clock) ipbus_pwrdown_i => cdce_pwrdown_from_ipb_n, -- default: 1 (powered up) ipbus_sync_i => cdce_sync_from_ipb_n, -- default: 1 (disable sync mode), rising edge needed to resync ------------------ user_sel_i => '0', -- cdce_sel_from_fabric -- effective only when ipbus_ctrl_i = '0' -- default 1 user_pwrdown_i => '1', -- cdce_pwrdown_from_fabric -- effective only when ipbus_ctrl_i = '0' user_sync_i => '1', -- cdce_sync_from_fabric -- effective only when ipbus_ctrl_i = '0' ------------------ pri_clk_i => cdce_pri_clk_bufg, sec_clk_i => fabric_clk, -- copy of what is actually send to the secondary clock input pwrdown_o => cdce_pwrdown_o, sync_o => cdce_sync_o, ref_sel_o => cdce_ref_sel_o, sync_clk_o => cdce_sync_clk_o ); cdce_pri_clk_bufg_o <= cdce_pri_clk_bufg; cdce_pri_clk_bufg <= '0'; -- [note: in this design, the cdce_pri_clk_bufg is not used] --===================================-- --===========================================-- stat_regs_inst: entity work.ipb_user_status_regs --===========================================-- port map ( clk => ipb_clk, reset => ipb_rst_i, ipb_mosi_i => ipb_mosi_i(user_ipb_stat_regs), ipb_miso_o => ipb_miso_o(user_ipb_stat_regs), regs_i => stat_reg ); --===========================================-- --===========================================-- ctrl_regs_inst: entity work.ipb_user_control_regs --===========================================-- port map ( clk => ipb_clk, reset => ipb_rst_i, ipb_mosi_i => ipb_mosi_i(user_ipb_ctrl_regs), ipb_miso_o => ipb_miso_o(user_ipb_ctrl_regs), regs_o => ctrl_reg ); --===========================================-- --===========================================-- --TTC/TTT signal handling --===========================================-- reset <= ipb_rst_i or (not cdce_pll_lock_i and not ctrl_reg(1)(8)); DTC: DTC_top Port map( TTC_data_p => k7_fabric_amc_rx_p03, TTC_data_n => k7_fabric_amc_rx_n03, TTC_CLK => fabric_clk, ttc_rst => reset, TTCready => OPEN, clock200ref => '0', L1Accept => L1Accept, BCntRes => BCntRes, EvCntRes => EvCntRes, SinErrStr => SinErrStr, DbErrStr => DbErrStr, BrcstStr => BrcstStr, Brcst => Brcst); --TTC counters for debugging DTC_Counter: TTC_COUNTER Port map( ttc_clk_i => fabric_clk, counters => counters, BC0_missing => stat_reg(4)(5), L1Accept => L1ACCEPT, BCntRes => BCntRes, EvCntRes => EvCntRes, SinErrStr => SinErrStr, DbErrStr => DbErrStr, BrcstStr => BrcstStr, Brcst => Brcst, reset_i => ipb_rst_i); WTE <= '1' when (brcst(7 downto 4)=x"8" or brcst(7 downto 4)=x"6" or brcst(7 downto 4)=x"4") and brcstStr='1' and (SinErrStr='0' and DbErrStr='0') else '0'; --===========================================-- --===========================================-- -- clock monitors --===========================================-- clkRate0 : clkRateTool32 GENERIC MAP (CLKREF_RATE_IN_MHZ => 125) -- clock rate of clkref in MHz PORT MAP ( -- clkref => osc125_a_mgtrefclk_i, clkref => osc125_a_bufg_i, clktest => fabric_clk, clktest_en => '1', clkvalue => ipb_clk, value => stat_reg(7)); clkRate1 : clkRateTool32 GENERIC MAP (CLKREF_RATE_IN_MHZ => 125) -- clock rate of clkref in MHz PORT MAP ( -- clkref => osc125_a_mgtrefclk_i, clkref => osc125_a_bufg_i, clktest => tx_wordclk(first_sfp), clktest_en => '1', clkvalue => ipb_clk, value => stat_reg(8)); clkRate2 : clkRateTool32 GENERIC MAP (CLKREF_RATE_IN_MHZ => 125) -- clock rate of clkref in MHz PORT MAP ( -- clkref => osc125_a_mgtrefclk_i, clkref => osc125_a_bufg_i, clktest => TxFrame_ce(first_sfp), clktest_en => '1', clkvalue => ipb_clk, value => stat_reg(9)); clk_rate_gen: FOR SFP IN first_sfp TO last_sfp GENERATE clkRate3 : clkRateTool32 GENERIC MAP (CLKREF_RATE_IN_MHZ => 125) -- clock rate of clkref in MHz PORT MAP ( clkref => osc125_a_bufg_i, clktest => rx_wordclk(SFP), clktest_en => RxFrame_ce(SFP), clkvalue => ipb_clk, value => stat_reg(9+SFP)); END GENERATE; --===========================================-- g_resetl12 <= ipb_rst_i or (not cdce_pll_lock_i and not ctrl_reg(1)(8)) or (not fmc_l12_pg_m2c) or (not fabric_clk_LOCKED); g_resetl8 <= ipb_rst_i or (not cdce_pll_lock_i and not ctrl_reg(1)(8)) or (not fmc_l8_pg_m2c) or (not fabric_clk_LOCKED); GBT_data_valid(1 to 3) <= not (sfp_abs(2 to 4) or sfp_rx_lost(2 to 4) or GBT_rx_rs_err(1 to 3)); GBT_data_valid(4) <= not (sfp_abs(1) or sfp_rx_lost(1) or GBT_rx_rs_err(4)); GBT_data_valid(5 to 8) <= not (sfp_abs(9 to 12) or sfp_rx_lost(9 to 12) or GBT_rx_rs_err(5 to 8)); GBT_data_valid(9 to 12) <= not (sfp_abs(5 to 8) or sfp_rx_lost(5 to 8) or GBT_rx_rs_err(9 to 12)); GBT_abs <= sfp_abs(2 to 4) & sfp_abs(1) & sfp_abs(9 to 12) & sfp_abs(5 to 8); channel_mgt_rxreset(1) <= ctrl_reg(31)(1); channel_mgt_rxreset(2) <= ctrl_reg(31)(2); channel_mgt_rxreset(3) <= ctrl_reg(31)(3); channel_mgt_rxreset(4) <= ctrl_reg(31)(0); channel_mgt_rxreset(5) <= ctrl_reg(31)(8); channel_mgt_rxreset(6) <= ctrl_reg(31)(9); channel_mgt_rxreset(7) <= ctrl_reg(31)(10); channel_mgt_rxreset(8) <= ctrl_reg(31)(11); channel_mgt_rxreset(9) <= ctrl_reg(31)(4); channel_mgt_rxreset(10) <= ctrl_reg(31)(5); channel_mgt_rxreset(11) <= ctrl_reg(31)(6); channel_mgt_rxreset(12) <= ctrl_reg(31)(7); channel_mgt_txreset(1) <= ctrl_reg(31)(17); channel_mgt_txreset(2) <= ctrl_reg(31)(18); channel_mgt_txreset(3) <= ctrl_reg(31)(19); channel_mgt_txreset(4) <= ctrl_reg(31)(16); channel_mgt_txreset(5) <= ctrl_reg(31)(24); channel_mgt_txreset(6) <= ctrl_reg(31)(25); channel_mgt_txreset(7) <= ctrl_reg(31)(26); channel_mgt_txreset(8) <= ctrl_reg(31)(27); channel_mgt_txreset(9) <= ctrl_reg(31)(20); channel_mgt_txreset(10) <= ctrl_reg(31)(21); channel_mgt_txreset(11) <= ctrl_reg(31)(22); channel_mgt_txreset(12) <= ctrl_reg(31)(23); --===========================================-- -- GBT banks --===========================================-- gbtbank1_l12_118: xlx_k7v7_gbt_ngFEC_design generic map( NUM_LINKS => 3) port map ( --==============-- -- Clocks -- --==============-- TX_FRAMECLK_I => fabric_clk, XCVRCLK => ttcMgtXpoint_from_ibufdsCGtxe2, TX_CLKEN_I => fabric_clk_div2, TX_CLKEN_O => GBT_TxFrame_ce(1 to 3), TX_WORDCLK_O => GBT_tx_wordclk(1 to 3), RX_CLKEN_O => GBT_RxFrame_ce(1 to 3), RX_WORDCLK_O => GBT_rx_wordclk(1 to 3), RX_WORDCLK_RDY_O => GBT_rx_wordclk_locked(1 to 3), RX_FRAMECLK_RDY_O => GBT_RxFrame_locked(1 to 3), --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I => g_resetl12, GBTBANK_MANUAL_RESET_TX_I => reset_gbtbank(1), GBTBANK_MANUAL_RESET_RX_I => reset_gbtbank(1), GBT_CHANNEL_RESET_TX_I => channel_mgt_txreset( 1 to 3), GBT_CHANNEL_RESET_RX_I => channel_mgt_rxreset( 1 to 3), GBT_DATA_VALID => GBT_data_valid(1 to 3), GBT_PD => GBT_abs(1 to 3), --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P => GBT_rx_p(1 to 3), GBTBANK_MGT_RX_N => GBT_rx_n(1 to 3), GBTBANK_MGT_TX_P => GBT_tx_p(1 to 3), GBTBANK_MGT_TX_N => GBT_tx_n(1 to 3), --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I => GBT_tx_data(1 to 3), GBTBANK_WB_DATA_I => (others => (others => '0')), TX_DATA_O => open, WB_DATA_O => open, GBTBANK_GBT_DATA_O => GBT_rx_data(1 to 3), GBTBANK_WB_DATA_O => open, --==============-- -- Reconf. -- --==============-- GBTBANK_MGT_DRP_RST => '0', GBTBANK_MGT_DRP_CLK => fabric_clk, --==============-- -- TX ctrl -- --==============-- GBTBANK_TX_ISDATA_SEL_I => (others=> '1'), TX_ENCODING_SEL_i => (others=> '1'), --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i => (others=> '1'), GBTBANK_RXBITSLIP_RSTONEVEN_I => (others=> '0'), --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O => GBT_tx_ready(1 to 3), GBTBANK_LINK_READY_O => GBT_mgt_ready(1 to 3), GBTBANK_TX_ALIGNED_O => open, GBTBANK_TX_ALIGNCOMPUTED_O => open, --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O => gbt_rx_ready(1 to 3), GBTBANK_RX_ISDATA_SEL_O => GBT_rx_data_valid(1 to 3), GBTBANK_RX_ERRORDETECTED_O => GBT_rx_rs_err(1 to 3), --==============-- -- XCVR ctrl -- --==============-- GBTBANK_LOOPBACK_I => (others => '0'), GBTBANK_TX_POL => (others => '0'), GBTBANK_RX_POL => (others => '0') ); gbtbank2_l12_117: xlx_k7v7_gbt_ngFEC_design generic map( NUM_LINKS => 2) port map ( --==============-- -- Clocks -- --==============-- TX_FRAMECLK_I => fabric_clk, XCVRCLK => ttcMgtXpoint_from_ibufdsCGtxe2, TX_CLKEN_I => fabric_clk_div2, TX_CLKEN_O => GBT_TxFrame_ce(4 to 5), TX_WORDCLK_O => GBT_tx_wordclk(4 to 5), RX_CLKEN_O => GBT_RxFrame_ce(4 to 5), RX_WORDCLK_O => GBT_rx_wordclk(4 to 5), RX_WORDCLK_RDY_O => GBT_rx_wordclk_locked(4 to 5), RX_FRAMECLK_RDY_O => GBT_RxFrame_locked(4 to 5), --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I => g_resetl12, GBTBANK_MANUAL_RESET_TX_I => reset_gbtbank(2), GBTBANK_MANUAL_RESET_RX_I => reset_gbtbank(2), GBT_CHANNEL_RESET_TX_I => channel_mgt_txreset(4 to 5), GBT_CHANNEL_RESET_RX_I => channel_mgt_rxreset( 4 to 5), GBT_DATA_VALID => GBT_data_valid(4 to 5), GBT_PD => GBT_abs(4 to 5), --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P => GBT_rx_p(4 to 5), GBTBANK_MGT_RX_N => GBT_rx_n(4 to 5), GBTBANK_MGT_TX_P => GBT_tx_p(4 to 5), GBTBANK_MGT_TX_N => GBT_tx_n(4 to 5), --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I => GBT_tx_data(4 to 5), GBTBANK_WB_DATA_I => (others => (others => '0')), TX_DATA_O => open, WB_DATA_O => open, GBTBANK_GBT_DATA_O => GBT_rx_data(4 to 5), GBTBANK_WB_DATA_O => open, --==============-- -- Reconf. -- --==============-- GBTBANK_MGT_DRP_RST => '0', GBTBANK_MGT_DRP_CLK => fabric_clk, --==============-- -- TX ctrl -- --==============-- GBTBANK_TX_ISDATA_SEL_I => (others=> '1'), TX_ENCODING_SEL_i => (others=> '1'), --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i => (others=> '1'), GBTBANK_RXBITSLIP_RSTONEVEN_I => (others=> '0'), --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O => GBT_tx_ready(4 to 5), GBTBANK_LINK_READY_O => GBT_mgt_ready(4 to 5), GBTBANK_TX_ALIGNED_O => open, GBTBANK_TX_ALIGNCOMPUTED_O => open, --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O => gbt_rx_ready(4 to 5), GBTBANK_RX_ISDATA_SEL_O => GBT_rx_data_valid(4 to 5), GBTBANK_RX_ERRORDETECTED_O => GBT_rx_rs_err(4 to 5), --==============-- -- XCVR ctrl -- --==============-- GBTBANK_LOOPBACK_I => (others => '0'), GBTBANK_TX_POL => (others => '0'), GBTBANK_RX_POL => (others => '0') ); gbtbank3_l12_116: xlx_k7v7_gbt_ngFEC_design generic map( NUM_LINKS => 3) port map ( --==============-- -- Clocks -- --==============-- TX_FRAMECLK_I => fabric_clk, XCVRCLK => ttcMgtXpoint_from_ibufdsCGtxe2, TX_CLKEN_I => fabric_clk_div2, TX_CLKEN_O => GBT_TxFrame_ce(6 to 8), TX_WORDCLK_O => GBT_tx_wordclk(6 to 8), RX_CLKEN_O => GBT_RxFrame_ce(6 to 8), RX_WORDCLK_O => GBT_rx_wordclk(6 to 8), RX_WORDCLK_RDY_O => GBT_rx_wordclk_locked(6 to 8), RX_FRAMECLK_RDY_O => GBT_RxFrame_locked(6 to 8), --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I => g_resetl12, GBTBANK_MANUAL_RESET_TX_I => reset_gbtbank(3), GBTBANK_MANUAL_RESET_RX_I => reset_gbtbank(3), GBT_CHANNEL_RESET_TX_I => channel_mgt_txreset( 6 to 8), GBT_CHANNEL_RESET_RX_I => channel_mgt_rxreset( 6 to 8), GBT_DATA_VALID => GBT_data_valid(6 to 8), GBT_PD => GBT_abs(6 to 8), --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P => GBT_rx_p(6 to 8), GBTBANK_MGT_RX_N => GBT_rx_n(6 to 8), GBTBANK_MGT_TX_P => GBT_tx_p(6 to 8), GBTBANK_MGT_TX_N => GBT_tx_n(6 to 8), --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I => GBT_tx_data(6 to 8), GBTBANK_WB_DATA_I => (others => (others => '0')), TX_DATA_O => open, WB_DATA_O => open, GBTBANK_GBT_DATA_O => GBT_rx_data(6 to 8), GBTBANK_WB_DATA_O => open, --==============-- -- Reconf. -- --==============-- GBTBANK_MGT_DRP_RST => '0', GBTBANK_MGT_DRP_CLK => fabric_clk, --==============-- -- TX ctrl -- --==============-- GBTBANK_TX_ISDATA_SEL_I => (others=> '1'), TX_ENCODING_SEL_i => (others=> '1'), --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i => (others=> '1'), GBTBANK_RXBITSLIP_RSTONEVEN_I => (others=> '0'), --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O => GBT_tx_ready(6 to 8), GBTBANK_LINK_READY_O => GBT_mgt_ready(6 to 8), GBTBANK_TX_ALIGNED_O => open, GBTBANK_TX_ALIGNCOMPUTED_O => open, --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O => gbt_rx_ready(6 to 8), GBTBANK_RX_ISDATA_SEL_O => GBT_rx_data_valid(6 to 8), GBTBANK_RX_ERRORDETECTED_O => GBT_rx_rs_err(6 to 8), --==============-- -- XCVR ctrl -- --==============-- GBTBANK_LOOPBACK_I => (others => '0'), GBTBANK_TX_POL => (others => '0'), GBTBANK_RX_POL => (others => '0') ); gbtbank4_l8_112: xlx_k7v7_gbt_ngFEC_design generic map( NUM_LINKS => 4) port map ( --==============-- -- Clocks -- --==============-- TX_FRAMECLK_I => fabric_clk, XCVRCLK => ttcMgtXpoint_from_ibufdsAGtxe2, TX_CLKEN_I => fabric_clk_div2, TX_CLKEN_O => GBT_TxFrame_ce(9 to 12), TX_WORDCLK_O => GBT_tx_wordclk(9 to 12), RX_CLKEN_O => GBT_RxFrame_ce(9 to 12), RX_WORDCLK_O => GBT_rx_wordclk(9 to 12), RX_WORDCLK_RDY_O => GBT_rx_wordclk_locked(9 to 12), RX_FRAMECLK_RDY_O => GBT_RxFrame_locked(9 to 12), --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I => g_resetl8, GBTBANK_MANUAL_RESET_TX_I => reset_gbtbank(4), GBTBANK_MANUAL_RESET_RX_I => reset_gbtbank(4), GBT_CHANNEL_RESET_TX_I => channel_mgt_txreset(9 to 12), GBT_CHANNEL_RESET_RX_I => channel_mgt_rxreset(9 to 12), GBT_DATA_VALID => GBT_data_valid(9 to 12), GBT_PD => GBT_abs(9 to 12), --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P => GBT_rx_p(9 to 12), GBTBANK_MGT_RX_N => GBT_rx_n(9 to 12), GBTBANK_MGT_TX_P => GBT_tx_p(9 to 12), GBTBANK_MGT_TX_N => GBT_tx_n(9 to 12), --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I => GBT_tx_data(9 to 12), GBTBANK_WB_DATA_I => (others => (others => '0')), TX_DATA_O => open, WB_DATA_O => open, GBTBANK_GBT_DATA_O => GBT_rx_data(9 to 12), GBTBANK_WB_DATA_O => open, --==============-- -- Reconf. -- --==============-- GBTBANK_MGT_DRP_RST => '0', GBTBANK_MGT_DRP_CLK => fabric_clk, --==============-- -- TX ctrl -- --==============-- GBTBANK_TX_ISDATA_SEL_I => (others=> '1'), TX_ENCODING_SEL_i => (others=> '1'), --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i => (others=> '1'), GBTBANK_RXBITSLIP_RSTONEVEN_I => (others=> '0'), --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O => GBT_tx_ready(9 to 12), GBTBANK_LINK_READY_O => GBT_mgt_ready(9 to 12), GBTBANK_TX_ALIGNED_O => open, GBTBANK_TX_ALIGNCOMPUTED_O => open, --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O => gbt_rx_ready(9 to 12), GBTBANK_RX_ISDATA_SEL_O => GBT_rx_data_valid(9 to 12), GBTBANK_RX_ERRORDETECTED_O => GBT_rx_rs_err(9 to 12), --==============-- -- XCVR ctrl -- --==============-- GBTBANK_LOOPBACK_I => (others => '0'), GBTBANK_TX_POL => (others => '1'), GBTBANK_RX_POL => (others => '1') ); fmc_sfp_tx_p <= GBT_tx_p(4) & GBT_tx_p(1 to 3) & GBT_tx_p(9 to 12) & GBT_tx_p(5 to 8); fmc_sfp_tx_n <= GBT_tx_n(4) & GBT_tx_n(1 to 3) & GBT_tx_n(9 to 12) & GBT_tx_n(5 to 8); GBT_rx_p <= fmc_sfp_rx_p(2 to 4) & fmc_sfp_rx_p(1) & fmc_sfp_rx_p(9 to 12) & fmc_sfp_rx_p(5 to 8); GBT_rx_n <= fmc_sfp_rx_n(2 to 4) & fmc_sfp_rx_n(1) & fmc_sfp_rx_n(9 to 12) & fmc_sfp_rx_n(5 to 8); GBT_tx_data <= ngccm_tx(2 to 4) & ngccm_tx(1) & ngccm_tx(9 to 12) & ngccm_tx(5 to 8); G_conv: for i in 1 to 12 generate TxFrame_ce(i) <= GBT_TxFrame_ce(SFP2GBT(i)); tx_wordclk(i) <= GBT_tx_wordclk(SFP2GBT(i)); RxFrame_ce(i) <= GBT_RxFrame_ce(SFP2GBT(i)); rx_wordclk(i) <= GBT_rx_wordclk(SFP2GBT(i)); rx_data_valid(i) <= GBT_rx_data_valid(SFP2GBT(i)); end generate; -- Comment in for the debugging. debug_mux_gen : FOR pin IN 0 TO 1 GENERATE debug_mux_inst: debug_mux port map( global_signal_sel => ctrl_reg(4)(15+16*pin downto 9+16*pin), sfp_signal_sel => ctrl_reg(4)(8+16*pin downto 3+16*pin), sfp_sel => ctrl_reg(4)(2+16*pin downto 16*pin), ttc_clk => fabric_clk, qie_reset => BCntRes, tx_wordclk => ttcMgtXpoint_from_ibufdsCGtxe2_buf, tx_frameclk => TxFrame_ce(1 to 8), rx_frameclk => RxFrame_ce(1 to 8), rx_wordclk => rx_wordclk(1 to 8), rx_wordclk_locked => rx_wordclk_locked(1 to 8), rx_frameclk_locked => RxFrame_locked(1 to 8), sfp_sda => sfp_sda_o(1 to 8), sfp_scl => sfp_scl_o(1 to 8), debug_out => header(pin+9) ); end generate debug_mux_gen; ---------------------------- -- HPC connection primary -- ---------------------------- -- GBT -- MOD_ABS sfp_abs(1) <= fmc_l12_la_n(15); sfp_abs(2) <= fmc_l12_la_p(12); sfp_abs(3) <= fmc_l12_la_n(8); sfp_abs(4) <= fmc_l12_la_p(5); sfp_abs(5) <= fmc_l8_la_n(15); sfp_abs(6) <= fmc_l8_la_p(12); sfp_abs(7) <= fmc_l8_la_n(8); sfp_abs(8) <= fmc_l8_la_p(5); sfp_abs(9) <= fmc_l12_la_n(31); sfp_abs(10) <= fmc_l12_la_p(28); sfp_abs(11) <= fmc_l12_la_n(24); sfp_abs(12) <= fmc_l12_la_p(21); -- TX_FAULT, RX_LOS sfp_tx_fault(1) <= fmc_l12_la_n(17); sfp_rx_lost(1) <= fmc_l12_la_n(14); sfp_tx_fault(2) <= fmc_l12_la_p(14); sfp_rx_lost(2) <= fmc_l12_la_p(11); sfp_tx_fault(3) <= fmc_l12_la_n(10); sfp_rx_lost(3) <= fmc_l12_la_n(7); sfp_tx_fault(4) <= fmc_l12_la_p(7); sfp_rx_lost(4) <= fmc_l12_la_p(4); sfp_tx_fault(5) <= fmc_l8_la_n(17); sfp_rx_lost(5) <= fmc_l8_la_n(14); sfp_tx_fault(6) <= fmc_l8_la_p(14); sfp_rx_lost(6) <= fmc_l8_la_p(11); sfp_tx_fault(7) <= fmc_l8_la_n(10); sfp_rx_lost(7) <= fmc_l8_la_n(7); sfp_tx_fault(8) <= fmc_l8_la_p(7); sfp_rx_lost(8) <= fmc_l8_la_p(4); sfp_tx_fault(9) <= fmc_l12_la_n(33); sfp_rx_lost(9) <= fmc_l12_la_n(30); sfp_tx_fault(10) <= fmc_l12_la_p(30); sfp_rx_lost(10) <= fmc_l12_la_p(27); sfp_tx_fault(11) <= fmc_l12_la_n(26); sfp_rx_lost(11) <= fmc_l12_la_n(23); sfp_tx_fault(12) <= fmc_l12_la_p(23); sfp_rx_lost(12) <= fmc_l12_la_p(20); -- TX_DISABLE, RATE_SEL fmc_l12_la_p(17) <= ctrl_reg(30)(0); fmc_l12_la_p(15) <= '0'; fmc_l12_la_n(13) <= ctrl_reg(30)(1); fmc_l12_la_n(11) <= '0'; fmc_l12_la_p(10) <= ctrl_reg(30)(2); fmc_l12_la_p(8) <= '0'; fmc_l12_la_n(6) <= ctrl_reg(30)(3); fmc_l12_la_n(4) <= '0'; fmc_l8_la_p(17) <= ctrl_reg(30)(4); fmc_l8_la_p(15) <= '0'; fmc_l8_la_n(13) <= ctrl_reg(30)(5); fmc_l8_la_n(11) <= '0'; fmc_l8_la_p(10) <= ctrl_reg(30)(6); fmc_l8_la_p(8) <= '0'; fmc_l8_la_n(6) <= ctrl_reg(30)(7); fmc_l8_la_n(4) <= '0'; fmc_l12_la_p(33) <= ctrl_reg(30)(8); fmc_l12_la_p(31) <= '0'; fmc_l12_la_n(29) <= ctrl_reg(30)(9); fmc_l12_la_n(27) <= '0'; fmc_l12_la_p(26) <= ctrl_reg(30)(10); fmc_l12_la_p(24) <= '0'; fmc_l12_la_n(22) <= ctrl_reg(30)(11); fmc_l12_la_n(20) <= '0'; -- SFP i2c i_sfp_sda_1 : IOBUF port map (O => sfp_sda_i(1), IO => fmc_l12_la_n(16), I => '0', T => sfp_sda_o(1)); i_sfp_sda_2 : IOBUF port map (O => sfp_sda_i(2), IO => fmc_l12_la_p(13), I => '0', T => sfp_sda_o(2)); i_sfp_sda_3 : IOBUF port map (O => sfp_sda_i(3), IO => fmc_l12_la_n(9), I => '0', T => sfp_sda_o(3)); i_sfp_sda_4 : IOBUF port map (O => sfp_sda_i(4), IO => fmc_l12_la_p(6), I => '0', T => sfp_sda_o(4)); i_sfp_sda_5 : IOBUF port map (O => sfp_sda_i(5), IO => fmc_l8_la_n(16), I => '0', T => sfp_sda_o(5)); i_sfp_sda_6 : IOBUF port map (O => sfp_sda_i(6), IO => fmc_l8_la_p(13), I => '0', T => sfp_sda_o(6)); i_sfp_sda_7 : IOBUF port map (O => sfp_sda_i(7), IO => fmc_l8_la_n(9), I => '0', T => sfp_sda_o(7)); i_sfp_sda_8 : IOBUF port map (O => sfp_sda_i(8), IO => fmc_l8_la_p(6), I => '0', T => sfp_sda_o(8)); i_sfp_sda_9 : IOBUF port map (O => sfp_sda_i(9), IO => fmc_l12_la_n(32), I => '0', T => sfp_sda_o(9)); i_sfp_sda_10 : IOBUF port map (O => sfp_sda_i(10), IO => fmc_l12_la_p(29), I => '0', T => sfp_sda_o(10)); i_sfp_sda_11 : IOBUF port map (O => sfp_sda_i(11), IO => fmc_l12_la_n(25), I => '0', T => sfp_sda_o(11)); i_sfp_sda_12 : IOBUF port map (O => sfp_sda_i(12), IO => fmc_l12_la_p(22), I => '0', T => sfp_sda_o(12)); i_sfp_scl_1 : IOBUF port map (O => sfp_scl_i(1), IO => fmc_l12_la_p(16), I => '0', T => sfp_scl_o(1)); i_sfp_scl_2 : IOBUF port map (O => sfp_scl_i(2), IO => fmc_l12_la_n(12), I => '0', T => sfp_scl_o(2)); i_sfp_scl_3 : IOBUF port map (O => sfp_scl_i(3), IO => fmc_l12_la_p(9), I => '0', T => sfp_scl_o(3)); i_sfp_scl_4 : IOBUF port map (O => sfp_scl_i(4), IO => fmc_l12_la_n(5), I => '0', T => sfp_scl_o(4)); i_sfp_scl_5 : IOBUF port map (O => sfp_scl_i(5), IO => fmc_l8_la_p(16), I => '0', T => sfp_scl_o(5)); i_sfp_scl_6 : IOBUF port map (O => sfp_scl_i(6), IO => fmc_l8_la_n(12), I => '0', T => sfp_scl_o(6)); i_sfp_scl_7 : IOBUF port map (O => sfp_scl_i(7), IO => fmc_l8_la_p(9), I => '0', T => sfp_scl_o(7)); i_sfp_scl_8 : IOBUF port map (O => sfp_scl_i(8), IO => fmc_l8_la_n(5), I => '0', T => sfp_scl_o(8)); i_sfp_scl_9 : IOBUF port map (O => sfp_scl_i(9), IO => fmc_l12_la_p(32), I => '0', T => sfp_scl_o(9)); i_sfp_scl_10 : IOBUF port map (O => sfp_scl_i(10), IO => fmc_l12_la_n(28), I => '0', T => sfp_scl_o(10)); i_sfp_scl_11 : IOBUF port map (O => sfp_scl_i(11), IO => fmc_l12_la_p(25), I => '0', T => sfp_scl_o(11)); i_sfp_scl_12 : IOBUF port map (O => sfp_scl_i(12), IO => fmc_l12_la_n(21), I => '0', T => sfp_scl_o(12)); sfp_sda_sec_i <= (others => '0'); sfp_scl_sec_i <= (others => '0'); -- LEDs fmc_l12_la_p(18) <= not sfp_rx_lost(1); fmc_l12_la_n(18) <= not sfp_rx_lost(2); fmc_l12_la_p(19) <= not sfp_rx_lost(3); fmc_l12_la_n(19) <= not sfp_rx_lost(4); fmc_l8_la_p(18) <= not sfp_rx_lost(5); fmc_l8_la_n(18) <= not sfp_rx_lost(6); fmc_l8_la_p(19) <= not sfp_rx_lost(7); fmc_l8_la_n(19) <= not sfp_rx_lost(8); -- pins not connected on fc7 -- fmc_l12_ha_n(0) <= not sfp_rx_lost(9); -- fmc_l12_ha_p(0) <= not sfp_rx_lost(10); -- fmc_l12_ha_n(1) <= not sfp_rx_lost(11); -- fmc_l12_ha_p(1) <= not sfp_rx_lost(12); --===========================================-- -- status register mapping --===========================================-- stat_reg(0) <= firmware_ver; --x"fec1_0429"; stat_reg(1) <= creation_date; --x"0510_2018"; stat_reg(2) <= reg_sfp_I2C_prescale(first_sfp); g_stat_reg: for i in 0 to 11 generate stat_reg(3)(i) <= sfp_tx_fault(i+1); stat_reg(3)(i+16) <= sfp_rx_lost(i+1); stat_reg(4)(i+8) <= sfp_abs(i+1); stat_reg(4)(i+20) <= rx_data_valid(i+1); stat_reg(5)(i) <= RxFrame_locked(i+1); stat_reg(5)(i+16) <= rx_wordclk_locked(i+1); stat_reg(6)(i) <= sfp_rx_ready(i+1); stat_reg(6)(i+16) <= GBT_mgt_ready(SFP2GBT(i+1)); stat_reg(31+i) <= PRBS_rx_pattern_error_cnt(i+1); stat_reg(43+i) <= ngccm_rx_down_counter(i+1); stat_reg(251)(i) <= GBT_tx_ready(SFP2GBT(i+1)); -- stat_reg(81+i) <= rs_raw_error_counter(SFP2GBT(i+1)); end generate; stat_reg(4)(0) <= fmc_l12_pg_m2c; stat_reg(4)(1) <= not fmc_l12_prsnt_l; --original signal is active low stat_reg(4)(2) <= fmc_l8_pg_m2c; stat_reg(4)(3) <= not fmc_l8_prsnt_l; -- original signal is active low stat_reg(4)(4) <= cdce_pll_lock_i; stat_reg(4)(6) <= fabric_clk_LOCKED; stat_reg(4)(7) <= ipb_rst_i; --DTC counters----------------- stat_reg (22) <= counters(0); --QIE_reset_counter; stat_reg (23) <= counters(1); --DbErr_counter stat_reg (24) <= counters(2); --SinErr_counter stat_reg (25) <= counters(3); --BCnt stat_reg (26) <= counters(4); --EvCnt stat_reg (27) <= counters(5); --BC0 late stat_reg (28) <= counters(6); --BC0 ontime stat_reg (29) <= counters(7); --BC0 early stat_reg (30) <= counters(8); -- reset_gbtbank <= ctrl_reg(1)(4 downto 1); fabric_clk_RST <= ctrl_reg(1)(10); cdce_ctrl_from_ipb_n <= not ctrl_reg(3)(0); cdce_sel_from_ipb <= ctrl_reg(3)(1); cdce_pwrdown_from_ipb_n <= not ctrl_reg(3)(2); cdce_sync_from_ipb_n <= not ctrl_reg(3)(3); SFP_GEN : FOR sfp IN first_sfp TO last_sfp GENERATE reg_sfp_I2C_prescale(sfp) <= ctrl_reg(2); -- the same I2C clk prescale RxFrame_locked(sfp) <= GBT_RxFrame_locked(SFP2GBT(sfp)); rx_wordclk_locked(sfp) <= GBT_rx_wordclk_locked(SFP2GBT(sfp)); sfp_rx_ready(sfp) <= gbt_rx_ready(SFP2GBT(sfp)); sfp_rx_locked_and_ready(sfp) <= GBT_rx_wordclk_locked(SFP2GBT(sfp)) and GBT_RxFrame_locked(SFP2GBT(sfp)) and gbt_rx_ready(SFP2GBT(sfp)); RX_Word_inst : PROCESS (rx_wordclk(sfp), rx_reset) IS BEGIN IF (rx_reset = '1') THEN rx_data_valid_r(sfp) <= '0'; rx_data(sfp) <= (OTHERS => '0'); ngccm_rx_down_counter(sfp) <= (OTHERS => '0'); ELSIF rising_edge(rx_wordclk(sfp)) THEN -- rising clock edge IF(RxFrame_ce(sfp) = '1') THEN -- rising clock edge rx_data_valid_r(sfp) <= rx_data_valid(sfp); IF (rx_data_valid(sfp) = '1' and sfp_rx_locked_and_ready(sfp) = '1' ) THEN rx_data(sfp) <= GBT_rx_data(SFP2GBT(sfp)); END IF; if rx_data_valid(sfp) = '0' and rx_data_valid_r(sfp) = '1' then ngccm_rx_down_counter(sfp) <= ngccm_rx_down_counter(sfp) + '1'; end if; END IF; END IF; END PROCESS RX_Word_inst; ------------------------------------------------------------------------------ ngFEC_module: ENTITY work.ngFEC_module ------------------------------------------------------------------------------ PORT MAP ( ipb_clk_i => ipb_clk, ipb_reset_i => reset, local_reset_i => ctrl_reg(5+sfp)(no_partition-1 downto 0), ipb_miso => ipb_miso_o(sfp), ipb_mosi => ipb_mosi_i(sfp), ngccm_miso => ngCCM_miso(sfp), ngccm_mosi => ngCCM_mosi(sfp) ); ------------------------------------------------------------------------------ QIE_RESET_DELAY: delay_counter ------------------------------------------------------------------------------ GENERIC MAP ( ORBIT => 3564 ) PORT MAP ( din => BCntRes, shift_i => ctrl_reg(17+sfp)(11 downto 0), clk_i => fabric_clk, reset_i => ipb_rst_i, dout => QIE_RESET(sfp) ); ------------------------------------------------------------------------------ ngCCM_gbt : ENTITY work.ngCCM ------------------------------------------------------------------------------ PORT MAP ( reset_IN => reset, reset_OUT => OPEN, reset_partition => ctrl_reg(5+sfp)(no_partition-1 downto 0), error_counter_reset_i => ctrl_reg(5)(sfp), ngccm_bkp_regs => stat_reg(54+sfp), TX_Clock_20MHz => fabric_clk_div2, RX_Clock_20MHz => RxFrame_ce(sfp), RX_wordCLK => rx_wordclk(sfp), fabric_clk => fabric_clk, TX_Word_o => ngccm_tx(sfp), RX_Word_i => rx_data(sfp), RX_Word_DV_i => rx_data_valid_r(sfp), clk_6x_o => OPEN, sfp_rx_lost => sfp_rx_lost(sfp), sfp_tx_fault => sfp_tx_fault(sfp), QIE_RESET => QIE_RESET(sfp), WTE => WTE, ipb_clk_i => ipb_clk, ipb_miso => ngccm_miso(sfp), ipb_mosi => ngccm_mosi(sfp), prescale => reg_sfp_I2C_prescale(sfp), TimeoutErrorCounter_o => stat_reg(67+((sfp-1)/2))(((sfp-1) mod 2)*16+15 downto ((sfp-1) mod 2)*16), TCK_counter => stat_reg(130+sfp), PRBS_rx_pattern_error_cnt_o => PRBS_rx_pattern_error_cnt(sfp), PRBS_rx_pattern_bitwise_error_cnt_o => PRBS_rx_pattern_bitwise_error_cnt(sfp), ngCCM_status_reset => ctrl_reg(1)(5), ngCCM_status_counter_o => ngCCM_status_counter(sfp-1), sfp_sda_i(0) => sfp_sda_i(sfp), sfp_sda_i(1) => sfp_sda_sec_i(sfp), sfp_sda_o(0) => sfp_sda_o(sfp), sfp_sda_o(1) => sfp_sda_sec_o(sfp), sfp_scl_i(0) => sfp_scl_i(sfp), sfp_scl_i(1) => sfp_scl_sec_i(sfp), sfp_scl_o(0) => sfp_scl_o(sfp), sfp_scl_o(1) => sfp_scl_sec_o(sfp) ); g_ngCCM_status_counter : for i in 0 to 7 generate stat_reg(147+8*sfp+i) <= ngCCM_status_counter(sfp-1)(i); end generate g_ngCCM_status_counter; -------------------------------------------------------------------------- END GENERATE SFP_GEN; process(fabric_clk) begin if(fabric_clk'event and fabric_clk = '1')then if(PSDONE_dl32 = '1')then update_toggle <= not update_toggle; end if; if(PSDONE = '1')then sample_PS <= '1'; elsif(PSDONE_dl16 = '1')then sample_PS <= '0'; end if; end if; end process; process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then update_toggle_Sync_Regs <= update_toggle_Sync_Regs(2 downto 0) & update_toggle; update_status <= update_toggle_Sync_Regs(3) xor update_toggle_Sync_Regs(2); end if; end process; process(fabric_clk_PS) begin if(fabric_clk_PS'event and fabric_clk_PS = '1')then fabric_clk_PS_toggle <= not fabric_clk_PS_toggle; end if; end process; pm_reset <= ipb_rst_i or (not fabric_clk_LOCKED) or ctrl_reg(1)(0); g_pm : for i in 1 to 12 generate phase_mon : pm PORT MAP ( reset => pm_reset, tx_wordclk => tx_wordclk(i), fabric_clk => fabric_clk, ipb_clk => ipb_clk, fabric_clk_PS => fabric_clk_PS, fabric_clk_PS_toggle => fabric_clk_PS_toggle, sample_PS => sample_PS, update_status => update_status, pscnt => PSCNT, status => stat_reg(142+i) ); end generate g_pm; --phase_monquad117: pm PORT MAP ( -- reset => pm_reset, -- tx_wordclk => tx_wordclk(4), -- fabric_clk => fabric_clk, -- ipb_clk => ipb_clk, -- fabric_clk_PS => fabric_clk_PS, -- fabric_clk_PS_toggle => fabric_clk_PS_toggle, -- sample_PS => PSDONE_dl16, -- update_status => update_status, -- pscnt => PSCNT, -- status => stat_reg(78), -- status => open -- ); --phase_monquad116: pm PORT MAP ( -- reset => pm_reset, -- tx_wordclk => tx_wordclk(10), -- fabric_clk => fabric_clk, -- ipb_clk => ipb_clk, -- fabric_clk_PS => fabric_clk_PS, -- fabric_clk_PS_toggle => fabric_clk_PS_toggle, -- sample_PS => PSDONE_dl16, -- update_status => update_status, -- pscnt => PSCNT, -- status => stat_reg(79) -- ); --phase_monquad112: pm PORT MAP ( -- reset => pm_reset, -- tx_wordclk => tx_wordclk(5), -- fabric_clk => fabric_clk, -- ipb_clk => ipb_clk, -- fabric_clk_PS => fabric_clk_PS, -- fabric_clk_PS_toggle => fabric_clk_PS_toggle, -- sample_PS => PSDONE_dl16, -- update_status => update_status, -- pscnt => PSCNT, -- status => stat_reg(80) -- ); process(ipb_clk,fabric_clk_LOCKED) begin if(fabric_clk_LOCKED = '0')then fabric_clk_LOCK_lost <= "11"; elsif(ipb_clk'event and ipb_clk = '1')then fabric_clk_LOCK_lost <= fabric_clk_LOCK_lost(0) & '0'; end if; end process; process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(fabric_clk_LOCK_lost = "10")then stat_reg(81)(15 downto 0) <= stat_reg(81)(15 downto 0) + 1; end if; end if; end process; process(ipb_clk,cdce_pll_lock_i) begin if(cdce_pll_lock_i = '0')then cdce_pll_LOCK_lost <= "11"; elsif(ipb_clk'event and ipb_clk = '1')then cdce_pll_LOCK_lost <= cdce_pll_LOCK_lost(0) & '0'; end if; end process; process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(cdce_pll_lock_lost = "10")then stat_reg(82)(15 downto 0) <= stat_reg(82)(15 downto 0) + 1; end if; end if; end process; process(fabric_clk) begin if(fabric_clk'event and fabric_clk = '1')then if(cdce_pll_lock_i = '0')then stat_reg(82)(31 downto 16) <= stat_reg(82)(31 downto 16) + 1; end if; end if; end process; g_rx_frameclk_lock_cnt: for i in 0 to 11 generate rx_frameclk_lock_Sync_inst: xpm_cdc_single generic map ( DEST_SYNC_FF => 4, -- integer; range: 2-10 INIT_SYNC_FF => 0, -- integer; 0=disable simulation init values, 1=enable simulation init values SIM_ASSERT_CHK => 0, -- integer; 0=disable simulation messages, 1=enable simulation messages SRC_INPUT_REG => 0 -- integer; 0=do not register input, 1=register input ) port map ( src_clk => '0', -- optional; required when SRC_INPUT_REG = 1 src_in => RxFrame_locked(i+1), dest_clk => ipb_clk, dest_out => rx_frameclk_locked_Sync(i) ); process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(rx_frameclk_locked_Sync(i) = '0')then stat_reg(83+i)(15 downto 0) <= stat_reg(83+i)(15 downto 0) + 1; end if; end if; end process; end generate; g_tx_ready_cnt: for i in 0 to 11 generate tx_ready_Sync_inst: xpm_cdc_single generic map ( DEST_SYNC_FF => 4, -- integer; range: 2-10 INIT_SYNC_FF => 0, -- integer; 0=disable simulation init values, 1=enable simulation init values SIM_ASSERT_CHK => 0, -- integer; 0=disable simulation messages, 1=enable simulation messages SRC_INPUT_REG => 0 -- integer; 0=do not register input, 1=register input ) port map ( src_clk => '0', -- optional; required when SRC_INPUT_REG = 1 src_in => GBT_tx_ready(SFP2GBT(i+1)), dest_clk => ipb_clk, dest_out => tx_ready_Sync(i) ); process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(tx_ready_Sync(i) = '0')then stat_reg(95+i)(15 downto 0) <= stat_reg(95+i)(15 downto 0) + 1; end if; end if; end process; end generate; g_bkp_pwr_flip: for i in 1 to 12 generate bkp_pwr_enable(i) <= stat_reg(54+i)(3); process(fabric_clk,ipb_rst_i) begin if(ipb_rst_i = '1')then bkp_pwr_enable_r(i) <= '0'; stat_reg(106+i) <= (others => '0'); elsif(fabric_clk'event and fabric_clk = '1')then bkp_pwr_enable_r(i) <= bkp_pwr_enable(i); if(bkp_pwr_enable_r(i) /= bkp_pwr_enable(i))then stat_reg(106+i)(15 downto 0) <= stat_reg(106+i)(15 downto 0) + 1; end if; end if; end process; end generate; g_rx_rs_err_cnt: for i in 1 to 12 generate process(rx_wordclk(i),ipb_rst_i) begin if(ipb_rst_i = '1')then rx_rs_err(i) <= '0'; stat_reg(118+i) <= (others => '0'); elsif(rx_wordclk(i)'event and rx_wordclk(i) = '1')then if(RxFrame_ce(i) = '1')then rx_rs_err(i) <= GBT_rx_rs_err(SFP2GBT(i)); if(rx_rs_err(i) = '1')then stat_reg(118+i)(15 downto 0) <= stat_reg(118+i)(15 downto 0) + 1; end if; end if; end if; end process; end generate; end ngFEC;