################################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 3.6
##  \   \         Application : 7 Series FPGAs Transceivers Wizard
##  /   /         Filename : ngFEC_mgt.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
## Generated by Xilinx 7 Series FPGAs Transceivers Wizard
##
## Device:  xc7k420t
## Package: ffg1156
##
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################################## Clock Constraints ##########################



# User Clock Constraints
create_clock -period 8.333 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt0_ngFEC_mgt_i*gtxe2_i*}]]
create_clock -period 8.333 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLKFABRIC} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt0_ngFEC_mgt_i*gtxe2_i*}]]
create_clock -period 8.333 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLKFABRIC} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt0_ngFEC_mgt_i*gtxe2_i*}]]
create_clock -period 8.333 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt0_ngFEC_mgt_i*gtxe2_i*}]]
#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_ngFEC_mgt_i*gtxe2_i*TXOUTCLK}]]
#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_ngFEC_mgt_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]

#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_ngFEC_mgt_i*gtxe2_i*RXOUTCLK}]]
#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_ngFEC_mgt_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]



set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]




####################### GT reference clock constraints #########################


#create_clock -name GT0_GTREFCLK0_IN -period 8.333 [get_pins -hier -filter {name=~*gt0_ngFEC_mgt_i*gtxe2_i*GTREFCLK0}]

################################# RefClk Location constraints (Can be uncommented) ##################### 
## set_property LOC AJ7 [get_ports  Q0_CLK1_GTREFCLK_PAD_N_IN ] 
## set_property LOC AJ8 [get_ports  Q0_CLK1_GTREFCLK_PAD_P_IN ]