2018.3: * Version 3.6 (Rev. 10) * General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries. 2018.2: * Version 3.6 (Rev. 9) * No changes 2018.1: * Version 3.6 (Rev. 9) * General: Added support for xa7a12tcpg238, xa7a12tcsg325, xa7a25tcpg238 and xa7a25csg325 Artix-7 devices. 2017.4: * Version 3.6 (Rev. 8) * Bug Fix: Fixed logic related to XAZU devices support * Bug Fix: Fixed GUI to follow Zync datasheet condition to not support 2 byte internal data width for line rates above 5.0 Gbps * Bug Fix: Updated the DRC used for checking valid Reference Clock selection 2017.3: * Version 3.6 (Rev. 7) * No changes 2017.2: * Version 3.6 (Rev. 7) * Bug Fix: txpmareset port is added as optional port 2017.1: * Version 3.6 (Rev. 6) * Bug Fix: When chipscope is enabled, userrdy is made an input, the userrdy to GT channel primitive is now asserted only if both the input and signal from resetfsm are asserted: AR68829 * Feature Enhancement: Maximum Line rate increased to 10.3125 gbps for XC7K70TFBG484 and XC7K70TFBV484 devices * Feature Enhancement: Maximum Line rate increased to 10.3125 gbps for XC7K160TFBG484 and XC7K160TFBV484 devices * Feature Enhancement: Maximum Line rate increased to 10.3125 gbps for XC7K160TIFBG484 and XC7K160TIFBV484 devices * Other: Dont touch attribute added for GTZ based design devices: AR67714 2016.4: * Version 3.6 (Rev. 5) * General: Added support for XC7A12TCPG236 and XC7A25TCPG236 devices 2016.3: * Version 3.6 (Rev. 4) * Feature Enhancement: JESD204 template preset for align_comma_word updated * Feature Enhancement: resetdones updated for JESD template based configurations * Other: Added support for XC7A12TCSG325, XC7A25TCSG325 and XC7Z012SCLG485 devices 2016.2: * Version 3.6 (Rev. 3) * COMMON_CFG[6] attribute value updated for configurations with QPLL on GTH transceiver based devices 2016.1: * Version 3.6 (Rev. 2) * RX_CM_TRIM attribute for Display Port Preset updated for GTH and GTP transceiver based devices * ACCLK_TERM_EN_0 and ACCLK_TERM_EN_1 updated for GTZ transceiver based devices as per latest UG478 2015.4.2: * Version 3.6 (Rev. 1) * No changes 2015.4.1: * Version 3.6 (Rev. 1) * No changes 2015.4: * Version 3.6 (Rev. 1) * Added support for new speedgrades of XQ7K325T and XQ7K410T devices * Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices * Added support for new speedgrade of XQ7A050T, XQ7A100T and XQ7A200T devices 2015.3: * Version 3.6 * Added support for XC7Z030SBV485 devices * Added GUI option to extend CPLL or QPLL reset by 3 ms * Added HDMI template support for GTX and GTP based devices * Renamed vby1 template to vby1_no_SSC * Added PRBS patterns for raw encoding for GTZ 2015.2.1: * Version 3.5 (Rev. 1) * No changes 2015.2: * Version 3.5 (Rev. 1) * Added support for XQ7Z045RFG676, XQ7Z100RF1156 and XQ7VX690TRF1158 devices * Updated the GTZ design to release the resets of individual lanes one after another starting from master lane . 2015.1: * Version 3.5 * Updated the GTZ CTLE tuning code to enable tuning of individual lanes. * Added separate resets for TX and RX startup FSMs except for GTZ. 2014.4.1: * Version 3.4 (Rev. 1) * No changes 2014.4: * Version 3.4 (Rev. 1) * Added SATA gen1 and SATA gen2 templates for GTX and GTP * Added support for XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices * Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices * Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices 2014.3: * Version 3.4 * Production updates to GTZ * Added SATA template for GTX and GTP * Removed logic to keep QPLL in powerdown till reference clock is available * Removed PCIE template 2014.2: * Version 3.3 * Added support for rf900 package for defense-grade(XQ) Zynq 7045 * Added logic to keep CPLL/QPLL in powerdown till reference clock is available * Fixed multiple reset issue for GTH/GTP. * Modified constraint files for false paths(Design Advisory 60356) 2014.1: * Version 3.2 * Added support for Aartix35T, Aartix50T, Aartix75T * Fixed simulation issue for GTX Bufferbypass AUTO mode * Added support for XC7VH870T and XC7VH580T FLG package devices 2013.4: * Version 3.1 * Reset FSM updates- removed the posedge detection logic for plllock * GTZ updates- added new line rate support and updated xdc file for the constraints * Increased the number of optional transceiver control and status ports * Added support for Artix35t and Artix50t devices 2013.3: * Version 3.0 * Updated GTH Attributes and QPLL range - Refer to AR 56332 and DS183 * Updated GTZ Attributes and Clocking * Updated timing constraints (XDC) to resolve Critical Warnings and added support for out-of-context synthesis * Updated timing constraints for recovered clocks in IP level.For details, refer to Migrating section of Product Guide - pg168-gtwizard.pdf * Updated TX and RX FSM to fix MMCM lock synchronization and simulation issues (for all GTs) * GTX TX buffer bypass is enabled in both Manual & Auto modes for single lane as per UG476. * Added check in the GUI to disallow mixed encode/decode for TX and RX * Added GUI option to include or exclude Vivado Lab tools support for debug * Removed LPM and DFE Manual mode option from the GUI * Added checks to limit DRP frequency selection * Protocol templates updated for -- Display port, sRIO gen2, CEI6, Aurora 8B10b * Reduced warnings in synthesis and simulation * Enhanced Support for IP Integrator * Added support for Cadence IES and Synopsys VCS simulators * Updated clock synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from met stability * Added GUI option to include or exclude shareable logic resources. For details, refer to Upgrading in Vivado Design Suite section of Product Guide - pg168-gtwizard.pdf * Added optional ports to enable transceiver core debug - Refer to pg168-gtwizard.pdf * Updated line rate ranges for A7 Wire bond package from 5.4G to 6.25G * Added support for XC7Z015 and XC7A75T * Moved clock constraints for the recovered clocks to core level xdc file from example design level * Added optional vivado (ILA and VIO) lab tools support for core debug in example design 2013.2: * Version 2.6 * New Protocol Templates added for GTH - Interlaken * Updated Port and Attribute Settings to support GTX, GTH and GTP Production Silicon * Increased line rate support for GTZ Transceivers * Support for Asymmetrical data widths on TX and RX (core generation and implementation only, not supported in simulation) 2013.1: * Version 2.5 * Native Vivado release * Support for Production Silicon for GTH and GTP. * New Protocol Templates added for GTH - SRIO multi lane, JESD204 * New Protocol Templates added for GTP - JESD204 (c) Copyright 2010 - 2018 Xilinx, Inc. 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