--------------------------------------------------------------------------------
-- Title      : Reset watch dog timer
-- File       : gig_ethernet_pcs_pma_16_1_reset_wtd_timer.vhd
-- Author     : Xilinx
--------------------------------------------------------------------------------
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--  Description:  This logic describes a watch dog counter for 3 seconds.
--                If data valid is not received withing 3 seconds a reset is
--                asserted.
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


------------------------------------------------------------------------------
--Entity declaration.
-----------------------------------------------------------------------------

entity gig_ethernet_pcs_pma_16_1_reset_wtd_timer is
  generic (
    WAIT_TIME  : std_logic_vector(23 downto 0) := x"8F0D18"
  );
  port (
    clk        : in  std_logic;    -- Input clock
    data_valid : in  std_logic;    -- Indication that data is received
    reset      : out std_logic     -- Reset on timer timeout
  );
end gig_ethernet_pcs_pma_16_1_reset_wtd_timer;

architecture rtl of gig_ethernet_pcs_pma_16_1_reset_wtd_timer is
   signal   counter_stg1        : std_logic_vector (5  downto 0) := (others => '0');
   signal   counter_stg2        : std_logic_vector (11 downto 0) := (others => '0');
   signal   counter_stg3        : std_logic_vector (11 downto 0) := (others => '0');
   signal   counter_stg1_roll   : std_logic;
   signal   counter_stg2_roll   : std_logic;
   signal   timer_reset         : std_logic;
   signal   three_sec_timeout   : std_logic;

 begin
   process (clk)
   begin
       if rising_edge(clk) then	   
           if ((data_valid = '1') OR (timer_reset = '1')) then
               counter_stg1 <= "000000";
          else
              if (data_valid = '0') then
                 counter_stg1 <= counter_stg1 + 1;
              end if;
          end if;
       end if;
   end process;
   
   counter_stg1_roll <= '1' when (counter_stg1 = "111111") else '0';

   process (clk)
   begin
       if rising_edge(clk) then	   
           if ((data_valid = '1') OR (timer_reset = '1')) then
               counter_stg2 <= "000000000000";
           else
               if ((data_valid = '0') AND (counter_stg1_roll = '1')) then
                   counter_stg2 <= counter_stg2 + 1;
               end if;
           end if;
       end if;
   end process;

   counter_stg2_roll <= '1' when (counter_stg2 = "111111111111") else '0';

   process (clk)
   begin
       if rising_edge(clk) then	   
           if ((data_valid = '1') OR (timer_reset = '1')) then
               counter_stg3 <= "000000000000";
           else
	       if ((data_valid = '0') AND (counter_stg2_roll = '1') AND (counter_stg1_roll = '1')) then
                   counter_stg3 <= counter_stg3 + 1;
               end if;
           end if;
       end if;
   end process;


   three_sec_timeout <= '1' when ((counter_stg3 = WAIT_TIME(23 downto 12)) AND (counter_stg2 = WAIT_TIME(11 downto 0))) else '0';
   timer_reset       <= '1' when ((counter_stg3 = WAIT_TIME(23 downto 12)) AND (counter_stg2 = WAIT_TIME(11 downto 0)) AND (counter_stg1 = x"3F")) else '0';

   process (clk)
   begin
       if rising_edge(clk) then	   
           if ((three_sec_timeout = '1') AND (counter_stg1(5) = '1')) then
               reset <= '1';
           else
               reset <= '0';
           end if;
       end if;
   end process;

end rtl;