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// IP VLNV: xilinx.com:ip:gig_ethernet_pcs_pma:16.1
// IP Revision: 5

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
gig_ethernet_pcs_pma_16_1 your_instance_name (
  .gtrefclk_bufg(gtrefclk_bufg),                    // input wire gtrefclk_bufg
  .gtrefclk(gtrefclk),                              // input wire gtrefclk
  .txn(txn),                                        // output wire txn
  .txp(txp),                                        // output wire txp
  .rxn(rxn),                                        // input wire rxn
  .rxp(rxp),                                        // input wire rxp
  .independent_clock_bufg(independent_clock_bufg),  // input wire independent_clock_bufg
  .txoutclk(txoutclk),                              // output wire txoutclk
  .rxoutclk(rxoutclk),                              // output wire rxoutclk
  .resetdone(resetdone),                            // output wire resetdone
  .cplllock(cplllock),                              // output wire cplllock
  .mmcm_reset(mmcm_reset),                          // output wire mmcm_reset
  .userclk(userclk),                                // input wire userclk
  .userclk2(userclk2),                              // input wire userclk2
  .pma_reset(pma_reset),                            // input wire pma_reset
  .mmcm_locked(mmcm_locked),                        // input wire mmcm_locked
  .rxuserclk(rxuserclk),                            // input wire rxuserclk
  .rxuserclk2(rxuserclk2),                          // input wire rxuserclk2
  .gmii_txd(gmii_txd),                              // input wire [7 : 0] gmii_txd
  .gmii_tx_en(gmii_tx_en),                          // input wire gmii_tx_en
  .gmii_tx_er(gmii_tx_er),                          // input wire gmii_tx_er
  .gmii_rxd(gmii_rxd),                              // output wire [7 : 0] gmii_rxd
  .gmii_rx_dv(gmii_rx_dv),                          // output wire gmii_rx_dv
  .gmii_rx_er(gmii_rx_er),                          // output wire gmii_rx_er
  .gmii_isolate(gmii_isolate),                      // output wire gmii_isolate
  .configuration_vector(configuration_vector),      // input wire [4 : 0] configuration_vector
  .status_vector(status_vector),                    // output wire [15 : 0] status_vector
  .reset(reset),                                    // input wire reset
  .signal_detect(signal_detect),                    // input wire signal_detect
  .gt0_qplloutclk_in(gt0_qplloutclk_in),            // input wire gt0_qplloutclk_in
  .gt0_qplloutrefclk_in(gt0_qplloutrefclk_in)      // input wire gt0_qplloutrefclk_in
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file gig_ethernet_pcs_pma_16_1.v when simulating
// the core, gig_ethernet_pcs_pma_16_1. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.