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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:38:40 12/12/2017 
-- Design Name: 
-- Module Name:    pm - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
Library xpm;
use xpm.vcomponents.all;

entity pm is
    Port ( reset : in  STD_LOGIC;
           fabric_clk : in  STD_LOGIC;
           ipb_clk : in  STD_LOGIC;
           fabric_clk_PS : in  STD_LOGIC;
           fabric_clk_PS_toggle : in  STD_LOGIC;
           tx_wordclk : in  STD_LOGIC;
           sample_PS : in  STD_LOGIC;
           update_status : in  STD_LOGIC;
           pscnt : in  STD_LOGIC_VECTOR (9 downto 0);
           status : out  STD_LOGIC_VECTOR (31 downto 0));
end pm;

architecture Behavioral of pm is
signal inh_cntr : std_logic_vector(4 downto 0) := (others => '0');	
signal PS_min : std_logic_vector(9 downto 0) := (others => '0');	
signal PS_max : std_logic_vector(9 downto 0) := (others => '0');	
signal en_chk : std_logic_vector(2 downto 0) := (others => '0');
signal old_fabric_clk_PS_toggle : std_logic := '0';
signal fabric_clk_PS_toggle_Sync : std_logic;
signal sample_PS_Sync : std_logic := '0';
signal sample_PS_Sync_q : std_logic := '0';
begin
fabric_clk_PS_toggle_Sync_inst: xpm_cdc_single
  generic map (
     DEST_SYNC_FF   => 4, -- integer; range: 2-10
     INIT_SYNC_FF   => 0, -- integer; 0=disable simulation init values, 1=enable simulation init values
     SIM_ASSERT_CHK => 0, -- integer; 0=disable simulation messages, 1=enable simulation messages
     SRC_INPUT_REG  => 1  -- integer; 0=do not register input, 1=register input
  )
  port map (
     src_clk  => fabric_clk_PS,  -- optional; required when SRC_INPUT_REG = 1
     src_in   => fabric_clk_PS_toggle,
     dest_clk => tx_wordclk,
     dest_out => fabric_clk_PS_toggle_Sync
  );
sample_PS_Sync_inst: xpm_cdc_single
  generic map (
     DEST_SYNC_FF   => 4, -- integer; range: 2-10
     INIT_SYNC_FF   => 0, -- integer; 0=disable simulation init values, 1=enable simulation init values
     SIM_ASSERT_CHK => 0, -- integer; 0=disable simulation messages, 1=enable simulation messages
     SRC_INPUT_REG  => 1  -- integer; 0=do not register input, 1=register input
  )
  port map (
     src_clk  => fabric_clk,  -- optional; required when SRC_INPUT_REG = 1
     src_in   => sample_PS,
     dest_clk => tx_wordclk,
     dest_out => sample_PS_Sync
  );
process(tx_wordclk,reset)
begin
	if(reset = '1')then
		en_chk <= "000";
		sample_PS_Sync_q <= '0';
		inh_cntr <= (others => '1');
		old_fabric_clk_PS_toggle <= '0';
		PS_max <= (others => '0');
		PS_min <= (others => '1');
	elsif(tx_wordclk'event and tx_wordclk = '1')then
		if(en_chk = "101")then
			en_chk <= "000";
		else
			en_chk <= en_chk + 1;
		end if;
		if(en_chk = "101")then
			sample_PS_Sync_q <= sample_PS_Sync;
			if(sample_PS_Sync = '0' and sample_PS_Sync_q = '1')then
				old_fabric_clk_PS_toggle <= fabric_clk_PS_toggle_Sync;
				if(fabric_clk_PS_toggle_Sync /= old_fabric_clk_PS_toggle)then
					inh_cntr <= (others => '1');
				elsif(inh_cntr(4) = '1')then
					inh_cntr <= inh_cntr - 1;
				end if;
				if(inh_cntr(4) = '0' and fabric_clk_PS_toggle_Sync /= old_fabric_clk_PS_toggle)then
					if(PSCNT < PS_min)then
						PS_min <= PSCNT;
					end if;
					if(PSCNT > PS_max)then
						PS_max <= PSCNT;
					end if;
				end if;
			end if;
		end if;
	end if;
end process;
status(31 downto 25) <= (others => '0');
status(15 downto 9) <= (others => '0');
process(ipb_clk)
begin
	if(ipb_clk'event and ipb_clk = '1')then
		if(update_status =  '1')then
			status(24 downto 16) <= PS_max(8 downto 0);
			status(8 downto 0) <= PS_min(8 downto 0);
		end if;
	end if;
end process;
end Behavioral;