----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Ozgur Sahin
-- 
-- Create Date:    15:51:51 06/17/2013 
-- Design Name: 
-- Module Name:    DTC_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Wrapper for the DTC logic from Eric Hazen
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity DTC_top is
    Port ( 
--				TTC_CLK_p : in  STD_LOGIC;
--				TTC_CLK_n : in  STD_LOGIC;
				TTC_data_p : in  STD_LOGIC;
				TTC_data_n : in  STD_LOGIC;
				TTC_rst : IN std_logic;
				TTC_CLK : IN  STD_LOGIC;
				Clock200ref : IN std_logic;								
				TTCready : out  STD_LOGIC;
				L1Accept : out  STD_LOGIC;
				BCntRes : out  STD_LOGIC;
				EvCntRes : out  STD_LOGIC;
				SinErrStr : out  STD_LOGIC;
				DbErrStr : out  STD_LOGIC;
				BrcstStr : out  STD_LOGIC;
				Brcst : out  STD_LOGIC_VECTOR (7 downto 2));
end DTC_top;

architecture Behavioral of DTC_top is
	COMPONENT TTC_decoder
	PORT(
--				TTC_CLK_p : IN std_logic;
--				TTC_CLK_n : IN std_logic;
				TTC_data_p : IN std_logic;
				TTC_data_n : IN std_logic; 
				clock40 : IN std_logic;
				clock200 : IN std_logic;								
				L1Accept : OUT std_logic;
				BCntRes : OUT std_logic;
				EvCntRes : OUT std_logic;
				SinErrStr : OUT std_logic;
				DbErrStr : OUT std_logic;
				BrcstStr : OUT std_logic;
				Brcst : OUT std_logic_vector(7 downto 2)
		);
	END COMPONENT;
signal Clock40 : std_logic;
	begin
				Inst_TTC_decoder: TTC_decoder PORT MAP(
--				TTC_CLK_p => TTC_CLK_p,
--				TTC_CLK_n => TTC_CLK_n,
				clock40     => TTC_CLK,
				clock200     => Clock200ref,
				TTC_data_p => TTC_data_p,
				TTC_data_n => TTC_data_n,
				L1Accept => L1Accept,
				BCntRes => BCntRes,
				EvCntRes => EvCntRes,
				SinErrStr => SinErrStr,
				DbErrStr => DbErrStr,
				BrcstStr => BrcstStr,
				Brcst => Brcst
		);


end Behavioral;