---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/18/2020 11:15:44 AM -- Design Name: -- Module Name: fc7_pm_tb - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. library UNISIM; use UNISIM.VComponents.all; entity fc7_pm_tb is -- Port ( ); end fc7_pm_tb; architecture Behavioral of fc7_pm_tb is component pm is Port ( reset : in STD_LOGIC; DRPclk : in STD_LOGIC; ipb_clk : in STD_LOGIC; tx_wordclk : in STD_LOGIC; sample_PS : in STD_LOGIC; update_status : in STD_LOGIC; fabric_clk_PS : in STD_LOGIC; fabric_clk_PS_toggle : in STD_LOGIC; pscnt : in unsigned (9 downto 0); status : out STD_LOGIC_VECTOR (31 downto 0)); end component; signal fabric_clk_in : std_logic := '0'; signal fabric_clk : std_logic := '0'; signal fabric_clk_div2 : std_logic := '0'; signal fabric_clk_div2_sync : std_logic := '0'; signal fabric_clk_div2_q : std_logic := '0'; signal fabric_clk_FBOUT : std_logic := '0'; signal fabric_clk_LOCKED : std_logic := '0'; signal fabric_clk_RST : std_logic := '0'; signal PSCNT : unsigned(9 downto 0) := (others => '0'); signal PS_TIMEOUT_CNT : unsigned(7 downto 0) := (others => '0'); signal fabric_clk_PSOUT : std_logic := '0'; signal fabric_clk_PS_toggle : std_logic := '0'; signal fabric_clk_PS : std_logic := '0'; signal PSDONE : std_logic := '0'; signal PSDONE_dl16 : std_logic := '0'; signal PSDONE_dl32 : std_logic := '0'; signal sample_PS: std_logic := '0'; signal PSEN : std_logic := '0'; signal PSEN_q : std_logic := '0'; signal reset : std_logic := '1'; signal update_toggle : std_logic := '0'; signal update_toggle_Sync_Regs : std_logic_vector(3 downto 0) := (others => '0'); signal update_status : std_logic := '0'; signal tx_wordclk : std_logic := '1'; signal ipb_clk : std_logic := '0'; signal pm_stat0 : std_logic_vector(31 downto 0) := (others => '0'); signal fabric_clk_div2_sync_q : std_logic_vector(2 downto 0) := (others => '0'); signal TX_CLKEN : std_logic := '0'; signal tx_wordclk_reset : std_logic := '0'; signal tx_reset_sync : std_logic := '0'; signal tx_word : std_logic := '0'; begin fabric_clk_MMCME2 : MMCME2_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) CLKFBOUT_MULT_F => 18.0, -- Multiply value for all CLKOUT (2.000-64.000). -- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). CLKOUT0_DIVIDE_F => 18.0, -- Divide amount for CLKOUT0 (1.000-128.000). CLKIN1_PERIOD => 24.999, COMPENSATION => "EXTERNAL", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL CLKOUT0_PHASE => 0.0, -- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE) CLKOUT0_USE_FINE_PS => TRUE ) port map ( -- Clock Outputs: 1-bit (each) output: User configurable clock outputs CLKOUT0 => fabric_clk_PSOUT, -- 1-bit output: CLKOUT0 -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs PSDONE => PSDONE, -- 1-bit output: Phase shift done -- Feedback Clocks: 1-bit (each) output: Clock feedback ports CLKFBOUT => fabric_clk_FBOUT, -- 1-bit output: Feedback clock -- Status Ports: 1-bit (each) output: MMCM status ports LOCKED => fabric_clk_LOCKED, -- 1-bit output: LOCK -- Clock Inputs: 1-bit (each) input: Clock inputs CLKIN1 => fabric_clk_in, -- 1-bit input: Primary clock CLKIN2 => '0', -- 1-bit input: Secondary clock -- Control Ports: 1-bit (each) input: MMCM control ports CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2 PWRDWN => '0', -- 1-bit input: Power-down RST => fabric_clk_RST, -- 1-bit input: Reset -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports DADDR => (others => '0'), -- 7-bit input: DRP address DCLK => '0', -- 1-bit input: DRP clock DEN => '0', -- 1-bit input: DRP enable DI => (others => '0'), -- 16-bit input: DRP data DWE => '0', -- 1-bit input: DRP write enable -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs PSCLK => fabric_clk, -- 1-bit input: Phase shift clock PSEN => PSEN, -- 1-bit input: Phase shift enable PSINCDEC => '1', -- 1-bit input: Phase shift increment/decrement -- Feedback Clocks: 1-bit (each) input: Clock feedback ports CLKFBIN => fabric_clk -- 1-bit input: Feedback clock ); fclk_bufg: bufg port map (i => fabric_clk_FBOUT, o => fabric_clk); fabric_clk_PS_bufg: bufg port map (i => fabric_clk_PSOUT, o => fabric_clk_PS); process(fabric_clk,fabric_clk_LOCKED) begin if(fabric_clk_LOCKED = '0')then PSEN <= '0'; PSCNT <= (others => '0'); PS_TIMEOUT_CNT <= (others => '0'); elsif(fabric_clk'event and fabric_clk = '1')then if(PS_TIMEOUT_CNT = x"ff" or PSDONE_dl32 = '1')then PSEN <= '1'; else PSEN <= '0'; end if; if(PSEN = '1')then PS_TIMEOUT_CNT <= (others => '0'); else PS_TIMEOUT_CNT <= PS_TIMEOUT_CNT + 1; end if; if(PSDONE = '1')then if(PSCNT = "0101001111")then PSCNT <= (others => '0'); else PSCNT <= PSCNT + 1; end if; end if; end if; end process; i_PSDONE_dl32 : SRLC32E port map (Q31 => PSDONE_dl32, Q => PSDONE_dl16, A => "01111", CE => fabric_clk_LOCKED, CLK => fabric_clk, D => PSDONE); --i_PSDONE_dl16 : SRLC32E port map (Q => PSDONE_dl16, A => "01111", CE => fabric_clk_LOCKED, CLK => fabric_clk, D => PSDONE); phase_mon_a : pm PORT MAP ( reset => reset, tx_wordclk => tx_wordclk, DRPclk => fabric_clk, ipb_clk => ipb_clk, fabric_clk_PS => fabric_clk_PS, fabric_clk_PS_toggle => fabric_clk_PS_toggle, sample_PS => sample_PS, update_status => update_status, pscnt => PSCNT, status => pm_stat0 ); process(fabric_clk) begin if(fabric_clk'event and fabric_clk = '1')then fabric_clk_div2 <= not fabric_clk_div2; tx_word <= tx_word xor fabric_clk_div2; end if; end process; process(fabric_clk) begin if(fabric_clk'event and fabric_clk = '1')then if(PSDONE_dl32 = '1')then update_toggle <= not update_toggle; end if; if(PSDONE = '1')then sample_PS <= '1'; elsif(PSDONE_dl16 = '1')then sample_PS <= '0'; end if; end if; end process; process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then update_toggle_Sync_Regs <= update_toggle_Sync_Regs(2 downto 0) & update_toggle; update_status <= update_toggle_Sync_Regs(3) xor update_toggle_Sync_Regs(2); end if; end process; process(fabric_clk_PS) begin if(fabric_clk_PS'event and fabric_clk_PS = '1')then fabric_clk_PS_toggle <= not fabric_clk_PS_toggle; end if; end process; ipb_clk <= not ipb_clk after 16ns; fabric_clk_in <= not fabric_clk_in after 12.498ns; tx_wordclk <= not tx_wordclk after 4.166 ns; stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; reset <= '0'; wait; end process; end Behavioral;