v Command: %s 53* vivadotcl2E 1synth_design -top fc7_top -part xc7k420tffg1156-22default:defaultZ4-113hpx : Starting synth_design 149* vivadotclZ4-321hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2 Synthesis2default:default2 xc7k420t2default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2 Synthesis2default:default2 xc7k420t2default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2020.012default:defaultZ17-1540hpx  Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2! CrossClock_RX2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 422default:default8@Z8-2507hpx  Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 112default:default8@Z8-2507hpx  Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 312default:default8@Z8-2507hpx  %s *synth2 xStarting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 486.211 ; gain = 112.293 2default:defaulthp x   $overwriting existing primary unit %s2488*oasys2 ipbus2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/ipbus_package.vhd2default:default2 302default:default8@Z8-2488hpx  Sactual for formal port %s is neither a static name nor a globally static expression1565*oasys2 slaveaddress2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_core.vhd2default:default2 1722default:default8@Z8-1565hpx  Sactual for formal port %s is neither a static name nor a globally static expression1565*oasys2 divider_i2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd2default:default2 472default:default8@Z8-1565hpx  Sactual for formal port %s is neither a static name nor a globally static expression1565*oasys2% tx_common_frame_i2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd2default:default2 962default:default8@Z8-1565hpx  Sactual for formal port %s is neither a static name nor a globally static expression1565*oasys2 reset2default:default2 zD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd2default:default2 732default:default8@Z8-1565hpx  synthesizing module '%s'638*oasys2 fc7_top2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd2default:default2 1672default:default8@Z8-638hpx l %s *synth2T @ Parameter DDR_CLK_EDGE bound to: OPPOSITE_EDGE - type: string 2default:defaulthp x  L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_C_INVERTED bound to: 1'b0 2default:defaulthp x  V %s *synth2> * Parameter IS_D1_INVERTED bound to: 1'b0 2default:defaulthp x  V %s *synth2> * Parameter IS_D2_INVERTED bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter SRTYPE bound to: SYNC - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 clk_oddr2default:default2 ODDR2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd2default:default2 2202default:default8@Z8-113hpx g %s *synth2O ; Parameter CAPACITANCE bound to: DONT_CARE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 clk_obuf2default:default2 OBUFDS2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd2default:default2 2232default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_C_INVERTED bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_D_INVERTED bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_R_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2% cdce_sync_r1_fdre2default:default2 FDRE2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd2default:default2 2362default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_C_INVERTED bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_D_INVERTED bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_R_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2% cdce_sync_r0_fdre2default:default2 FDRE2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd2default:default2 2482default:default8@Z8-113hpx  synthesizing module '%s'638*oasys2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1012default:default8@Z8-638hpx [ %s *synth2C / Parameter CLKCM_CFG bound to: 1 - type: bool 2default:defaulthp x  ] %s *synth2E 1 Parameter CLKRCV_TRST bound to: 1 - type: bool 2default:defaulthp x  U %s *synth2= ) Parameter CLKSWING_CFG bound to: 2'b11 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" osc125a_gtebuf2default:default2 IBUFDS_GTE22default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 2132default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2" osc125a_clkbuf2default:default2 BUFG2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 2142default:default8@Z8-113hpx [ %s *synth2C / Parameter CLKCM_CFG bound to: 1 - type: bool 2default:defaulthp x  ] %s *synth2E 1 Parameter CLKRCV_TRST bound to: 1 - type: bool 2default:defaulthp x  U %s *synth2= ) Parameter CLKSWING_CFG bound to: 2'b11 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" osc125b_gtebuf2default:default2 IBUFDS_GTE22default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 2152default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2" osc125b_clkbuf2default:default2 BUFG2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 2162default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_gen2default:default2 SRL162default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 2242default:default8@Z8-113hpx  synthesizing module '%s'638*oasys2$ clocks_7s_serdes2default:default2 yD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd2default:default2 382default:default8@Z8-638hpx h %s *synth2P < Parameter powerup_delay bound to: 3125000 - type: integer 2default:defaulthp x  e %s *synth2M 9 Parameter BANDWIDTH bound to: OPTIMIZED - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter CLKFBOUT_MULT bound to: 12 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKIN1_PERIOD bound to: 8.000000 - type: float 2default:defaulthp x  d %s *synth2L 8 Parameter CLKOUT0_DIVIDE bound to: 48 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  d %s *synth2L 8 Parameter CLKOUT1_DIVIDE bound to: 24 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  b %s *synth2J 6 Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  e %s *synth2M 9 Parameter REF_JITTER1 bound to: 0.010000 - type: float 2default:defaulthp x  d %s *synth2L 8 Parameter STARTUP_WAIT bound to: FALSE - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2# PLLE2_BASE_inst2default:default2 PLLE2_BASE2default:default2 yD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd2default:default2 712default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2 clk_ipb_buf2default:default2 BUFG2default:default2 yD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd2default:default2 932default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2 clk62_5_buf2default:default2 BUFG2default:default2 yD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd2default:default2 942default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2 clk125_buf2default:default2 BUFG2default:default2 yD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd2default:default2 952default:default8@Z8-113hpx  synthesizing module '%s'638*oasys2# ipbus_clock_div2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd2default:default2 502default:default8@Z8-638hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_gen2default:default2 SRL162default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd2default:default2 572default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2# ipbus_clock_div2default:default2 12default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd2default:default2 502default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ clocks_7s_serdes2default:default2 22default:default2 12default:default2 yD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd2default:default2 382default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2$ eth_7s_1000basex2default:default2 uD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd2default:default2 492default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2) tri_mode_eth_mac_v5_52default:default2 zD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd2default:default2 32default:default2 mac2default:default2) tri_mode_eth_mac_v5_52default:default2 uD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd2default:default2 1452default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2) tri_mode_eth_mac_v5_52default:default2 zD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd2default:default2 402default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 soft_emac2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 402default:default2 i_mac2default:default2 soft_emac2default:default2 zD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd2default:default2 722default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 soft_emac2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 622default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 EthernetCRC2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd2default:default2 552default:default2 i_tx_CRC32D82default:default2 EthernetCRC2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2082default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 EthernetCRC2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd2default:default2 652default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 EthernetCRC2default:default2 32default:default2 12default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd2default:default2 652default:default8@Z8-256hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 rx_crc_d2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2172default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 phyemacrxd2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2172default:default8@Z8-614hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 EthernetCRC2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd2default:default2 552default:default2 i_rx_CRC32D82default:default2 EthernetCRC2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2672default:default8@Z8-3491hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 SRL16E_inst2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2772default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" i_ce_rx_crc_dl2default:default2 SRL16E2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 2892default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 soft_emac2default:default2 42default:default2 12default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd2default:default2 622default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2) tri_mode_eth_mac_v5_52default:default2 52default:default2 12default:default2 zD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd2default:default2 402default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2- gig_ethernet_pcs_pma_16_12default:default2 {D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/gig_ethernet_pcs_pma_16_1_stub.vhdl2default:default2 52default:default2 phy2default:default2- gig_ethernet_pcs_pma_16_12default:default2 uD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd2default:default2 1932default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2- gig_ethernet_pcs_pma_16_12default:default2 {D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/gig_ethernet_pcs_pma_16_1_stub.vhdl2default:default2 422default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ eth_7s_1000basex2default:default2 62default:default2 12default:default2 uD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd2default:default2 492default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 ipbus_ctrl2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd2default:default2 902default:default8@Z8-638hpx O %s *synth27 # Parameter MAC_CFG bound to: 1'b0 2default:defaulthp x  N %s *synth26 " Parameter IP_CFG bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter INTERNALWIDTH bound to: 1 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter ADDRWIDTH bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter IPBUSPORT bound to: 16'b1100001101010001 2default:defaulthp x  U %s *synth2= ) Parameter SECONDARYPORT bound to: 1'b0 2default:defaulthp x  Z %s *synth2B . Parameter N_OOB bound to: 1 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 UDP_if2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_if_flat.vhd2default:default2 902default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter INTERNALWIDTH bound to: 1 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter ADDRWIDTH bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter IPBUSPORT bound to: 16'b1100001101010001 2default:defaulthp x  U %s *synth2= ) Parameter SECONDARYPORT bound to: 1'b0 2default:defaulthp x   synthesizing module '%s'638*oasys2$ udp_ipaddr_block2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd2default:default2 542default:default8@Z8-638hpx  merging register '%s' into '%s'3619*oasys2( IP_addr_rx_reg[31:0]2default:default2, IP_addr_rx_int_reg[31:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd2default:default2 1002default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2" IP_addr_rx_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd2default:default2 1002default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ udp_ipaddr_block2default:default2 72default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd2default:default2 542default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" udp_rarp_block2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 502default:default8@Z8-638hpx  +Unused sequential element %s was removed. 4326*oasys2" end_addr_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 682default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 send_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 692default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 addr_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 1402default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 tick_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 1592default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 t_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 1902default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ rarp_req_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 2152default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" udp_rarp_block2default:default2 82default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2 502default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2! udp_build_arp2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 542default:default8@Z8-638hpx  +Unused sequential element %s was removed. 4326*oasys2 send_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 712default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2" end_addr_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 732default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ set_addr_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 1072default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' addr_to_set_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 1082default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ data_to_send_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 2512default:default8@Z8-6014hpx  merging register '%s' into '%s'3619*oasys2" arp_we_sig_reg2default:default2 arp_we_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 632default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 load_buf_reg2default:default2$ load_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 2022default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) buf_to_load_reg[47:0]2default:default2- buf_to_load_int_reg[47:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 2072default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 send_buf_reg2default:default2$ send_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 2122default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ address_reg[5:0]2default:default2% addr_int_reg[5:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 642default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2" arp_we_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 632default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 load_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 2022default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2# buf_to_load_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 2072default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 send_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 2122default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 address_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 642default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2! udp_build_arp2default:default2 92default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2 542default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2% udp_build_payload2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 592default:default8@Z8-638hpx  +Unused sequential element %s was removed. 4326*oasys2 state_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 842default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 send_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 872default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ set_addr_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1392default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' addr_to_set_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1402default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ next_low_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4332default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ data_to_send_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 5102default:default8@Z8-6014hpx  merging register '%s' into '%s'3619*oasys2$ send_pending_reg2default:default2& send_pending_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1102default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2& payload_we_sig_reg2default:default2$ payload_we_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 692default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 load_buf_reg2default:default2$ load_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 2922default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) buf_to_load_reg[15:0]2default:default2- buf_to_load_int_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 2972default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 send_buf_reg2default:default2$ send_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3022default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2& do_sum_payload_reg2default:default2" do_sum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3862default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' clr_sum_payload_reg2default:default2# clr_sum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3912default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2- int_data_payload_reg[7:0]2default:default2) int_data_int_reg[7:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3962default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) int_valid_payload_reg2default:default2% int_valid_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4012default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 cksum_reg2default:default2! cksum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4062default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' next_addr_reg[12:0]2default:default2+ next_addr_int_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4322default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% address_reg[12:0]2default:default2& addr_int_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1502default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 low_addr_reg2default:default2" low_addr_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1472default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 byteswap_reg2default:default2$ byteswap_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4972default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2* ipbus_in_hdr_reg[31:0]2default:default2+ ipbus_hdr_int_reg[31:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 5392default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2$ send_pending_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1102default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2& payload_we_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 692default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 load_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 2922default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2# buf_to_load_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 2972default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 send_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3022default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2& do_sum_payload_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3862default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' clr_sum_payload_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3912default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2( int_data_payload_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 3962default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) int_valid_payload_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4012default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 cksum_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4062default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2! next_addr_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4322default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 address_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1502default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 low_addr_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 1472default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 byteswap_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 4972default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ ipbus_in_hdr_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 5392default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2% udp_build_payload2default:default2 102default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2 592default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" udp_build_ping2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 572default:default8@Z8-638hpx  +Unused sequential element %s was removed. 4326*oasys2 state_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 782default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ set_addr_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1382default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' addr_to_set_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1392default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2! ping_we_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2032default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2# clr_sum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2752default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2% int_valid_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2762default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ int_data_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2772default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ data_to_send_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 3752default:default8@Z8-6014hpx  merging register '%s' into '%s'3619*oasys2+ ping_end_addr_reg[12:0]2default:default2( end_addr_i_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1012default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2! ping_send_reg2default:default2 send_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1062default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ send_pending_reg2default:default2& send_pending_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1112default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 load_buf_reg2default:default2$ load_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2502default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) buf_to_load_reg[15:0]2default:default2- buf_to_load_int_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2552default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 send_buf_reg2default:default2$ send_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2602default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2# do_sum_ping_reg2default:default2" do_sum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 3092default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% address_reg[12:0]2default:default2& addr_int_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 672default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 low_addr_reg2default:default2" low_addr_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1452default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2% ping_end_addr_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1012default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2! ping_send_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1062default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ send_pending_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1112default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 load_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2502default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2# buf_to_load_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2552default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 send_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 2602default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2# do_sum_ping_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 3092default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 address_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 672default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 low_addr_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 1452default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" udp_build_ping2default:default2 112default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2 572default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2$ udp_build_resend2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd2default:default2 492default:default8@Z8-638hpx  merging register '%s' into '%s'3619*oasys2+ resend_pkt_id_reg[15:0]2default:default2/ resend_pkt_id_int_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd2default:default2 912default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2% resend_pkt_id_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd2default:default2 912default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ udp_build_resend2default:default2 122default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd2default:default2 492default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2$ udp_build_status2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 542default:default8@Z8-638hpx  +Unused sequential element %s was removed. 4326*oasys2" end_addr_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 692default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ set_addr_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 1232default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' addr_to_set_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 1242default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2# request_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 2092default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ data_to_send_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 2732default:default8@Z8-6014hpx  merging register '%s' into '%s'3619*oasys2$ address_reg[6:0]2default:default2% addr_int_reg[6:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 622default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 load_buf_reg2default:default2$ load_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 2452default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 send_buf_reg2default:default2$ send_buf_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 2502default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2 address_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 622default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 load_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 2452default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 send_buf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 2502default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ udp_build_status2default:default2 132default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2 542default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2% udp_status_buffer2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 752default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter ADDRWIDTH bound to: 11 - type: integer 2default:defaulthp x   +Unused sequential element %s was removed. 4326*oasys2 bufsize_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1142default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 nbuf_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1152default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2! new_event_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1622default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2# async_ready_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1632default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2+ rarp_arp_ping_ipbus_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1692default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2- payload_status_resend_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1712default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2! got_event_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 2522default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 event_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 2532default:default8@Z8-6014hpx  merging register '%s' into '%s'3619*oasys2) next_pkt_id_reg[15:0]2default:default2- next_pkt_id_int_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1362default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2# next_pkt_id_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 1362default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2% udp_status_buffer2default:default2 142default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2 752default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 udp_byte_sum2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2 512default:default8@Z8-638hpx  merging register '%s' into '%s'3619*oasys2! carry_bit_reg2default:default2% carry_bit_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2 1142default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ hi_byte_reg[8:0]2default:default2( hi_byte_int_reg[8:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2 582default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2! carry_bit_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2 1142default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 hi_byte_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2 582default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 udp_byte_sum2default:default2 152default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2 512default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2# udp_do_rx_reset2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd2default:default2 452default:default8@Z8-638hpx  merging register '%s' into '%s'3619*oasys2$ rx_reset_sig_reg2default:default2# reset_latch_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd2default:default2 512default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2$ rx_reset_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd2default:default2 512default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2# udp_do_rx_reset2default:default2 162default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd2default:default2 452default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2% udp_packet_parser2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 612default:default8@Z8-638hpx a %s *synth2I 5 Parameter IPBUSPORT bound to: 16'b1100001101010001 2default:defaulthp x  U %s *synth2= ) Parameter SECONDARYPORT bound to: 1'b0 2default:defaulthp x   merging register '%s' into '%s'3619*oasys2( pkt_drop_arp_sig_reg2default:default2 pkt_drop_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 712default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) pkt_drop_rarp_sig_reg2default:default2 pkt_drop_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 722default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' pkt_drop_ip_sig_reg2default:default2 pkt_drop_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 1982default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) pkt_drop_ping_sig_reg2default:default2 pkt_drop_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 732default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2* pkt_drop_ipbus_sig_reg2default:default2 pkt_drop_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 742default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) ipbus_status_mask_reg2default:default2! last_mask_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 3122default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2- pkt_drop_reliable_sig_reg2default:default2+ pkt_drop_reliable_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 762default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2- pkt_reliable_drop_sig_reg2default:default2+ pkt_drop_reliable_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 762default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' pkt_drop_status_reg2default:default2 pkt_drop_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 4312default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' pkt_drop_resend_reg2default:default2 pkt_drop_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 4642default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% pkt_broadcast_reg2default:default2% broadcast_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 4862default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2( pkt_drop_arp_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 712default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) pkt_drop_rarp_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 722default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' pkt_drop_ip_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 1982default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) pkt_drop_ping_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 732default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2* pkt_drop_ipbus_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 742default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) ipbus_status_mask_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 3122default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2- pkt_drop_reliable_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 762default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2- pkt_reliable_drop_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 762default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' pkt_drop_status_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 4312default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2' pkt_drop_resend_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 4642default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2% pkt_broadcast_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 4862default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2% udp_packet_parser2default:default2 172default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2 612default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2! udp_rxram_mux2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 802default:default8@Z8-638hpx  +Unused sequential element %s was removed. 4326*oasys2) rxram_dropped_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 982default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2* rxram_end_addr_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 1212default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2& rxram_send_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 1222default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 dia_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 1572default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2! addra_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 1582default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 wea_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 1592default:default8@Z8-6014hpx  merging register '%s' into '%s'3619*oasys2! ram_ready_reg2default:default2% ram_ready_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 862default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2! ram_ready_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 862default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2! udp_rxram_mux2default:default2 182default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2 802default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2# udp_DualPortRAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram.vhd2default:default2 482default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 1 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter ADDRWIDTH bound to: 11 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2# udp_DualPortRAM2default:default2 192default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram.vhd2default:default2 482default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2' udp_buffer_selector2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 582default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 1 - type: integer 2default:defaulthp x   +Unused sequential element %s was removed. 4326*oasys2" req_send_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 1672default:default8@Z8-6014hpx  merging register '%s' into '%s'3619*oasys2! free_reg[1:0]2default:default2# free_i_reg[1:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 882default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2" clean_reg[1:0]2default:default2$ clean_i_reg[1:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 692default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) send_pending_reg[1:0]2default:default2+ send_pending_i_reg[1:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 1342default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 busy_sig_reg2default:default2 busy_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 682default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 sending_reg2default:default2! sending_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 1712default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2& write_sig_reg[0:0]2default:default2$ write_i_reg[0:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 662default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% send_sig_reg[0:0]2default:default2# send_i_reg[0:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 672default:default8@Z8-4471hpx  +Unused sequential element %s was removed. 4326*oasys2 free_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 882default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 clean_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 692default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2$ send_pending_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 1342default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 busy_sig_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 682default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2 sending_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 1712default:default8@Z8-6014hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-60142default:default2 1002default:defaultZ17-14hpx  %done synthesizing module '%s' (%s#%s)256*oasys2' udp_buffer_selector2default:default2 202default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 582default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" udp_rxram_shim2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd2default:default2 562default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 1 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2" udp_rxram_shim2default:default2 212default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd2default:default2 562default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2& udp_DualPortRAM_rx2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2 482default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter ADDRWIDTH bound to: 11 - type: integer 2default:defaulthp x   default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2 622default:default8@Z8-226hpx  %done synthesizing module '%s' (%s#%s)256*oasys2& udp_DualPortRAM_rx2default:default2 222default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2 482default:default8@Z8-256hpx  synthesizing module '%s'638*oasys27 #udp_buffer_selector__parameterized02default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 582default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x   merging register '%s' into '%s'3619*oasys2" free_reg[15:0]2default:default2$ free_i_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 882default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2# clean_reg[15:0]2default:default2% clean_i_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 692default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2* send_pending_reg[15:0]2default:default2, send_pending_i_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 1342default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 busy_sig_reg2default:default2 busy_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 682default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 sending_reg2default:default2! sending_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 1712default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2& write_sig_reg[3:0]2default:default2$ write_i_reg[3:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 662default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% send_sig_reg[3:0]2default:default2# send_i_reg[3:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 672default:default8@Z8-4471hpx  %done synthesizing module '%s' (%s#%s)256*oasys27 #udp_buffer_selector__parameterized02default:default2 222default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2 582default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2& udp_DualPortRAM_tx2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd2default:default2 482default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter ADDRWIDTH bound to: 11 - type: integer 2default:defaulthp x   default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd2default:default2 832default:default8@Z8-226hpx  %done synthesizing module '%s' (%s#%s)256*oasys2& udp_DualPortRAM_tx2default:default2 232default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd2default:default2 482default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2' udp_rxtransactor_if2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd2default:default2 492default:default8@Z8-638hpx  merging register '%s' into '%s'3619*oasys2 ram_ok_reg2default:default2 ram_ok_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd2default:default2 552default:default8@Z8-4471hpx  %done synthesizing module '%s' (%s#%s)256*oasys2' udp_rxtransactor_if2default:default2 242default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd2default:default2 492default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 udp_tx_mux2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 712default:default8@Z8-638hpx  merging register '%s' into '%s'3619*oasys2& rxram_busy_sig_reg2default:default2& rxram_busy_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 902default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys20 rxram_end_addr_sig_reg[12:0]2default:default20 rxram_end_addr_int_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 1242default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' udpram_busy_sig_reg2default:default2' udpram_busy_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 912default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% udp_short_sig_reg2default:default2! short_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 972default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ send_special_reg2default:default2( send_special_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 2332default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ special_reg[7:0]2default:default2( special_int_reg[7:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 2382default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2* last_udpram_active_reg2default:default2* last_udpram_active_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 2612default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ udp_counting_reg2default:default2 counting_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 2662default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2( udp_counter_reg[4:0]2default:default2$ counter_reg[4:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 2712default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 cksum_reg2default:default2! cksum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 3402default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 clr_sum_reg2default:default2# clr_sum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 3452default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 do_sum_reg2default:default2" do_sum_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 3502default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2! int_valid_reg2default:default2% int_valid_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 3552default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys21 udpram_end_addr_sig_reg[12:0]2default:default21 udpram_end_addr_int_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 4292default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% int_data_reg[7:0]2default:default2) int_data_int_reg[7:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 4342default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ ip_len_reg[15:0]2default:default2( ip_len_int_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 1932default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2& ip_cksum_reg[15:0]2default:default2* ip_cksum_int_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 1982default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% udp_len_reg[15:0]2default:default2) udp_len_int_reg[15:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 2232default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2& addr_sig_reg[12:0]2default:default2& addr_int_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 1612default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ byteswapping_reg2default:default2( byteswapping_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 4862default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2, mac_tx_data_sig_reg[7:0]2default:default2, mac_tx_data_int_reg[7:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 932default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2+ ipbus_out_hdr_reg[31:0]2default:default2+ ipbus_hdr_int_reg[31:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 5722default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ byteswap_sig_reg2default:default2$ byteswap_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 4762default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' next_state_reg[2:0]2default:default2" state_reg[2:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 6062default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2$ rxram_active_reg2default:default2( rxram_active_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 1142default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2% udpram_active_reg2default:default2) udpram_active_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 1402default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 counting_reg2default:default2$ counting_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 4652default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 prefetch_reg2default:default2$ prefetch_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 5192default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2' mac_tx_last_sig_reg2default:default2' mac_tx_last_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 942default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2( mac_tx_valid_sig_reg2default:default2( mac_tx_valid_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 952default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2 set_addr_reg2default:default2$ set_addr_int_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 4622default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2) addr_to_set_reg[12:0]2default:default2- addr_to_set_int_reg[12:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 4632default:default8@Z8-4471hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 udp_tx_mux2default:default2 252default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2 712default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2' udp_txtransactor_if2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd2default:default2 612default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2' udp_txtransactor_if2default:default2 262default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd2default:default2 612default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2) udp_clock_crossing_if2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 692default:default8@Z8-638hpx ] %s *synth2E 1 Parameter BUFWIDTH bound to: 4 - type: integer 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 722default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 722default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 722default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 722default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 732default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 732default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 732default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 732default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 742default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 752default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 752default:default8@Z8-5534hpx  %done synthesizing module '%s' (%s#%s)256*oasys2) udp_clock_crossing_if2default:default2 272default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 692default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 UDP_if2default:default2 282default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_if_flat.vhd2default:default2 902default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 trans_arb2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/trans_arb.vhd2default:default2 552default:default8@Z8-638hpx Y %s *synth2A - Parameter NSRC bound to: 2 - type: integer 2default:defaulthp x   RAM %s from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers 4277*oasys2 buf_out_reg2default:defaultZ8-5858hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 trans_arb2default:default2 292default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/trans_arb.vhd2default:default2 552default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 transactor2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor.vhd2default:default2 602default:default8@Z8-638hpx  synthesizing module '%s'638*oasys2! transactor_if2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 572default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2! transactor_if2default:default2 302default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 572default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2! transactor_sm2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 652default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2! transactor_sm2default:default2 312default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 652default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" transactor_cfg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_cfg.vhd2default:default2 532default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" transactor_cfg2default:default2 322default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_cfg.vhd2default:default2 532default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 transactor2default:default2 332default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor.vhd2default:default2 602default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 ipbus_ctrl2default:default2 342default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd2default:default2 902default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 uc_if2default:default2u _D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_if.vhd2default:default2 402default:default8@Z8-638hpx  synthesizing module '%s'638*oasys2 trans_buffer2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd2default:default2 622default:default8@Z8-638hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd2default:default2 882default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 TRUE2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd2default:default2 892default:default8@Z8-5534hpx  5synthesizing blackbox instance '%s' of component '%s'637*oasys2 ram_in2default:default2% sdpram_16x10_32x92default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd2default:default2 1532default:default8@Z8-637hpx  5synthesizing blackbox instance '%s' of component '%s'637*oasys2 ram_out2default:default2% sdpram_32x9_16x102default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd2default:default2 1662default:default8@Z8-637hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 trans_buffer2default:default2 352default:default2 12default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd2default:default2 622default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2! spi_interface2default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd2default:default2 532default:default8@Z8-638hpx [ %s *synth2C / Parameter width bound to: 16 - type: integer 2default:defaulthp x   default block is never used226*oasys2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd2default:default2 1222default:default8@Z8-226hpx  default block is never used226*oasys2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd2default:default2 1942default:default8@Z8-226hpx  default block is never used226*oasys2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd2default:default2 2872default:default8@Z8-226hpx  %done synthesizing module '%s' (%s#%s)256*oasys2! spi_interface2default:default2 362default:default2 12default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd2default:default2 532default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2% uc_pipe_interface2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd2default:default2 432default:default8@Z8-638hpx  5synthesizing blackbox instance '%s' of component '%s'637*oasys2% ram_pipe_to_ipbus2default:default2% sdpram_16x10_32x92default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd2default:default2 2092default:default8@Z8-637hpx  5synthesizing blackbox instance '%s' of component '%s'637*oasys2% ram_ipbus_to_pipe2default:default2% sdpram_32x9_16x102default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd2default:default2 2222default:default8@Z8-637hpx  %done synthesizing module '%s' (%s#%s)256*oasys2% uc_pipe_interface2default:default2 372default:default2 12default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd2default:default2 432default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 uc_if2default:default2 382default:default2 12default:default2u _D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_if.vhd2default:default2 402default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2! ip_mac_select2default:default2} gD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd2default:default2 422default:default8@Z8-638hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2# user_mac_addr_i2default:default2} gD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd2default:default2 732default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2" user_ip_addr_i2default:default2} gD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd2default:default2 732default:default8@Z8-614hpx  %done synthesizing module '%s' (%s#%s)256*oasys2! ip_mac_select2default:default2 392default:default2 12default:default2} gD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd2default:default2 422default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2$ ipbus_sys_fabric2default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ipbus_sys_fabric.vhd2default:default2 282default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter n_sys_slv bound to: 3 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter n_usr_slv bound to: 15 - type: integer 2default:defaulthp x  u %s *synth2] I Parameter usr_base_addr bound to: 32'b01000000000000000000000000000000 2default:defaulthp x  \ %s *synth2D 0 Parameter strobe_gap bound to: 0 - type: bool 2default:defaulthp x   RAM %s from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers 4277*oasys2% ipb_to_slaves_reg2default:defaultZ8-5858hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ ipbus_sys_fabric2default:default2 402default:default2 12default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ipbus_sys_fabric.vhd2default:default2 282default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 system_regs2default:default2x bD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/regs/system_regs.vhd2default:default2 262default:default8@Z8-638hpx _ %s *synth2G 3 Parameter addr_width bound to: 6 - type: integer 2default:defaulthp x   Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2 regs_reg[13]2default:default2 system_regs2default:default2x bD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/regs/system_regs.vhd2default:default2 422default:default8@Z8-6426hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 system_regs2default:default2 412default:default2 12default:default2x bD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/regs/system_regs.vhd2default:default2 262default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2* icap_interface_wrapper2default:default2 mD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_wrapper.vhd2default:default2 472default:default8@Z8-638hpx  synthesizing module '%s'638*oasys2' flashIcap_ioControl2default:default2 oD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_ioControl.vhd2default:default2 552default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2' flashIcap_ioControl2default:default2 422default:default2 12default:default2 oD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_ioControl.vhd2default:default2 552default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" icap_interface2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd2default:default2 262default:default8@Z8-638hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd2default:default2 292default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd2default:default2 352default:default8@Z8-5534hpx q %s *synth2Y E Parameter DEVICE_ID bound to: 32'b00000100001001001010000010010011 2default:defaulthp x  ` %s *synth2H 4 Parameter ICAP_WIDTH bound to: x32 - type: string 2default:defaulthp x  h %s *synth2P < Parameter SIM_CFG_FILE_NAME bound to: none - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 icap2default:default2 ICAPE22default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd2default:default2 1732default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" icap_interface2default:default2 432default:default2 12default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd2default:default2 262default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2& icap_interface_fsm2default:default2 iD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_fsm.vhd2default:default2 482default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2& icap_interface_fsm2default:default2 442default:default2 12default:default2 iD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_fsm.vhd2default:default2 482default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2* icap_interface_wrapper2default:default2 452default:default2 12default:default2 mD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_wrapper.vhd2default:default2 472default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" i2c_master_top2default:default2z dD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd2default:default2 312default:default8@Z8-638hpx b %s *synth2J 6 Parameter nbr_of_busses bound to: 1 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2# i2c_master_core2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_core.vhd2default:default2 332default:default8@Z8-638hpx b %s *synth2J 6 Parameter nbr_of_busses bound to: 1 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 i2c_bitwise2default:default2w aD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_bitwise.vhd2default:default2 442default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 i2c_bitwise2default:default2 462default:default2 12default:default2w aD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_bitwise.vhd2default:default2 442default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 i2c_ctrl2default:default2t ^D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_ctrl.vhd2default:default2 532default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 i2c_ctrl2default:default2 472default:default2 12default:default2t ^D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_ctrl.vhd2default:default2 532default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2# i2c_master_core2default:default2 482default:default2 12default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_core.vhd2default:default2 332default:default8@Z8-256hpx Z %s *synth2B . Parameter DRIVE bound to: 4 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: slow - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 scl_buf2default:default2 IOBUF2default:default2z dD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd2default:default2 702default:default8@Z8-113hpx Z %s *synth2B . Parameter DRIVE bound to: 4 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: slow - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 sda_buf2default:default2 IOBUF2default:default2z dD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd2default:default2 742default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" i2c_master_top2default:default2 492default:default2 12default:default2z dD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd2default:default2 312default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2$ i2c_eep_autoread2default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_eep_autoread.vhd2default:default2 302default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ i2c_eep_autoread2default:default2 502default:default2 12default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_eep_autoread.vhd2default:default2 302default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 spi_master2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 432default:default8@Z8-638hpx \ %s *synth2D 0 Parameter dwidth bound to: 32 - type: integer 2default:defaulthp x   default block is never used226*oasys2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 722default:default8@Z8-226hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 cpol_i2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 582default:default8@Z8-614hpx  default block is never used226*oasys2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1352default:default8@Z8-226hpx  default block is never used226*oasys2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1722default:default8@Z8-226hpx  default block is never used226*oasys2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2592default:default8@Z8-226hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 spi_master2default:default2 512default:default2 12default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 432default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ regs_to_ipbus[0]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ regs_to_ipbus[1]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ regs_to_ipbus[2]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ regs_to_ipbus[3]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ regs_to_ipbus[4]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ regs_to_ipbus[5]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2 reg_status_22default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1662default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ regs_to_ipbus[8]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2# reg_status_sram2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1682default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[10]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[11]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[14]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[16]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[17]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[18]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[19]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[20]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[21]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[22]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[23]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[24]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[25]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[26]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2% regs_to_ipbus[27]2default:default2 system_core2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1602default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 system_core2default:default2 522default:default2 12default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 1012default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 ngFEC_logic2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 1682default:default8@Z8-638hpx g %s *synth2O ; Parameter CAPACITANCE bound to: DONT_CARE - type: string 2default:defaulthp x  [ %s *synth2C / Parameter DIFF_TERM bound to: 0 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 fclk_ibuf2default:default2 IBUFGDS2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 5612default:default8@Z8-113hpx e %s *synth2M 9 Parameter BANDWIDTH bound to: OPTIMIZED - type: string 2default:defaulthp x  j %s *synth2R > Parameter CLKFBOUT_MULT_F bound to: 18.000000 - type: float 2default:defaulthp x  h %s *synth2P < Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  f %s *synth2N : Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  h %s *synth2P < Parameter CLKIN1_PERIOD bound to: 24.999000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 2default:defaulthp x  k %s *synth2S ? Parameter CLKOUT0_DIVIDE_F bound to: 18.000000 - type: float 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT0_USE_FINE_PS bound to: 1 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  a %s *synth2I 5 Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  g %s *synth2O ; Parameter COMPENSATION bound to: EXTERNAL - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 2default:defaulthp x  X %s *synth2@ , Parameter IS_PSEN_INVERTED bound to: 1'b0 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 2default:defaulthp x  Z %s *synth2B . Parameter IS_PWRDWN_INVERTED bound to: 1'b0 2default:defaulthp x  W %s *synth2? + Parameter IS_RST_INVERTED bound to: 1'b0 2default:defaulthp x  e %s *synth2M 9 Parameter REF_JITTER1 bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter REF_JITTER2 bound to: 0.000000 - type: float 2default:defaulthp x  ] %s *synth2E 1 Parameter SS_EN bound to: FALSE - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter SS_MODE bound to: CENTER_HIGH - type: string 2default:defaulthp x  f %s *synth2N : Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter STARTUP_WAIT bound to: 0 - type: bool 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2% fabric_clk_MMCME22default:default2 MMCME2_ADV2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 5622default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2 fclk_bufg2default:default2 BUFG2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 6042default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2& fabric_clk_PS_bufg2default:default2 BUFG2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 6052default:default8@Z8-113hpx l %s *synth2T @ Parameter INIT bound to: 32'b00000000000000000000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2! i_PSDONE_dl322default:default2 SRLC32E2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 6322default:default8@Z8-113hpx [ %s *synth2C / Parameter CLKCM_CFG bound to: 1 - type: bool 2default:defaulthp x  ] %s *synth2E 1 Parameter CLKRCV_TRST bound to: 1 - type: bool 2default:defaulthp x  U %s *synth2= ) Parameter CLKSWING_CFG bound to: 2'b11 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2( cdceOut1IbufdsAGtxe22default:default2 IBUFDS_GTE22default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 6392default:default8@Z8-113hpx [ %s *synth2C / Parameter CLKCM_CFG bound to: 1 - type: bool 2default:defaulthp x  ] %s *synth2E 1 Parameter CLKRCV_TRST bound to: 1 - type: bool 2default:defaulthp x  U %s *synth2= ) Parameter CLKSWING_CFG bound to: 2'b11 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2( cdceOut0IbufdsCGtxe22default:default2 IBUFDS_GTE22default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 6472default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys28 $i_ttcMgtXpoint_from_ibufdsCGtxe2_buf2default:default2 BUFH2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 6612default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys28 $i_ttcMgtXpoint_from_ibufdsAGtxe2_buf2default:default2 BUFH2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 6622default:default8@Z8-113hpx  synthesizing module '%s'638*oasys2 clk_divide32default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clk_divide3.vhd2default:default2 422default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 clk_divide32default:default2 532default:default2 12default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clk_divide3.vhd2default:default2 422default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" dmdt_clock_gen2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/dmdt_clock_gen.vhd2default:default2 182default:default8@Z8-638hpx  synthesizing module '%s'638*oasys2$ phase_mon_mmcm_12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1.vhd2default:default2 862default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2, phase_mon_mmcm_1_clk_wiz2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd2default:default2 742default:default2 U02default:default2, phase_mon_mmcm_1_clk_wiz2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1.vhd2default:default2 1042default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2, phase_mon_mmcm_1_clk_wiz2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd2default:default2 862default:default8@Z8-638hpx g %s *synth2O ; Parameter CAPACITANCE bound to: DONT_CARE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  f %s *synth2N : Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 clkin1_ibufg2default:default2 IBUF2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd2default:default2 1202default:default8@Z8-113hpx e %s *synth2M 9 Parameter BANDWIDTH bound to: OPTIMIZED - type: string 2default:defaulthp x  j %s *synth2R > Parameter CLKFBOUT_MULT_F bound to: 62.625000 - type: float 2default:defaulthp x  h %s *synth2P < Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  f %s *synth2N : Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  h %s *synth2P < Parameter CLKIN1_PERIOD bound to: 25.000000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 2default:defaulthp x  k %s *synth2S ? Parameter CLKOUT0_DIVIDE_F bound to: 31.250000 - type: float 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  a %s *synth2I 5 Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter COMPENSATION bound to: ZHOLD - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter DIVCLK_DIVIDE bound to: 2 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 2default:defaulthp x  X %s *synth2@ , Parameter IS_PSEN_INVERTED bound to: 1'b0 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 2default:defaulthp x  Z %s *synth2B . Parameter IS_PWRDWN_INVERTED bound to: 1'b0 2default:defaulthp x  W %s *synth2? + Parameter IS_RST_INVERTED bound to: 1'b0 2default:defaulthp x  e %s *synth2M 9 Parameter REF_JITTER1 bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter REF_JITTER2 bound to: 0.000000 - type: float 2default:defaulthp x  ] %s *synth2E 1 Parameter SS_EN bound to: FALSE - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter SS_MODE bound to: CENTER_HIGH - type: string 2default:defaulthp x  f %s *synth2N : Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter STARTUP_WAIT bound to: 0 - type: bool 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2! mmcm_adv_inst2default:default2 MMCME2_ADV2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd2default:default2 1322default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2 clkout1_buf2default:default2 BUFG2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd2default:default2 2032default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2, phase_mon_mmcm_1_clk_wiz2default:default2 542default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd2default:default2 862default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ phase_mon_mmcm_12default:default2 552default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1.vhd2default:default2 862default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2$ phase_mon_mmcm_22default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2.vhd2default:default2 862default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2, phase_mon_mmcm_2_clk_wiz2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd2default:default2 742default:default2 U02default:default2, phase_mon_mmcm_2_clk_wiz2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2.vhd2default:default2 1042default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2, phase_mon_mmcm_2_clk_wiz2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd2default:default2 862default:default8@Z8-638hpx g %s *synth2O ; Parameter CAPACITANCE bound to: DONT_CARE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  f %s *synth2N : Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 clkin1_ibufg2default:default2 IBUF2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd2default:default2 1202default:default8@Z8-113hpx e %s *synth2M 9 Parameter BANDWIDTH bound to: OPTIMIZED - type: string 2default:defaulthp x  j %s *synth2R > Parameter CLKFBOUT_MULT_F bound to: 60.250000 - type: float 2default:defaulthp x  h %s *synth2P < Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  f %s *synth2N : Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  h %s *synth2P < Parameter CLKIN1_PERIOD bound to: 24.950000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 2default:defaulthp x  k %s *synth2S ? Parameter CLKOUT0_DIVIDE_F bound to: 20.125000 - type: float 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  a %s *synth2I 5 Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 2default:defaulthp x  g %s *synth2O ; Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter COMPENSATION bound to: ZHOLD - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter DIVCLK_DIVIDE bound to: 3 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 2default:defaulthp x  X %s *synth2@ , Parameter IS_PSEN_INVERTED bound to: 1'b0 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 2default:defaulthp x  Z %s *synth2B . Parameter IS_PWRDWN_INVERTED bound to: 1'b0 2default:defaulthp x  W %s *synth2? + Parameter IS_RST_INVERTED bound to: 1'b0 2default:defaulthp x  e %s *synth2M 9 Parameter REF_JITTER1 bound to: 0.000000 - type: float 2default:defaulthp x  e %s *synth2M 9 Parameter REF_JITTER2 bound to: 0.000000 - type: float 2default:defaulthp x  ] %s *synth2E 1 Parameter SS_EN bound to: FALSE - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter SS_MODE bound to: CENTER_HIGH - type: string 2default:defaulthp x  f %s *synth2N : Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter STARTUP_WAIT bound to: 0 - type: bool 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2! mmcm_adv_inst2default:default2 MMCME2_ADV2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd2default:default2 1322default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2 clkf_buf2default:default2 BUFG2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd2default:default2 1952default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2 clkout1_buf2default:default2 BUFG2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd2default:default2 2022default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2, phase_mon_mmcm_2_clk_wiz2default:default2 562default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd2default:default2 862default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ phase_mon_mmcm_22default:default2 572default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2.vhd2default:default2 862default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" dmdt_clock_gen2default:default2 582default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/dmdt_clock_gen.vhd2default:default2 182default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2# dmtd_phase_meas2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd2default:default2 732default:default8@Z8-638hpx n %s *synth2V B Parameter g_deglitcher_threshold bound to: 2000 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter g_counter_bits bound to: 14 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 gc_sync_ffs2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd2default:default2 592default:default8@Z8-638hpx f %s *synth2N : Parameter g_sync_edge bound to: positive - type: string 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd2default:default2 602default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2! shreg_extract2default:default2 no2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd2default:default2 602default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd2default:default2 602default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2! shreg_extract2default:default2 no2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd2default:default2 602default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2! shreg_extract2default:default2 no2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd2default:default2 602default:default8@Z8-5534hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 gc_sync_ffs2default:default2 592default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd2default:default2 592default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2( dmtd_with_deglitcher2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd2default:default2 1262default:default8@Z8-638hpx d %s *synth2L 8 Parameter g_counter_bits bound to: 14 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter g_chipscope bound to: 0 - type: bool 2default:defaulthp x  e %s *synth2M 9 Parameter g_divide_input_by_2 bound to: 0 - type: bool 2default:defaulthp x  [ %s *synth2C / Parameter g_reverse bound to: 0 - type: bool 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd2default:default2 1382default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd2default:default2 1392default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd2default:default2 1392default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd2default:default2 1392default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd2default:default2 1392default:default8@Z8-5534hpx  synthesizing module '%s'638*oasys2) gc_pulse_synchronizer2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_pulse_synchronizer.vhd2default:default2 652default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2) gc_pulse_synchronizer2default:default2 602default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_pulse_synchronizer.vhd2default:default2 652default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2# gc_extend_pulse2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_extend_pulse.vhd2default:default2 652default:default8@Z8-638hpx _ %s *synth2G 3 Parameter g_width bound to: 3000 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2# gc_extend_pulse2default:default2 612default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_extend_pulse.vhd2default:default2 652default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2( dmtd_with_deglitcher2default:default2 622default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd2default:default2 1262default:default8@Z8-256hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd2default:default2 1972default:default8@Z8-226hpx  merging register '%s' into '%s'3619*oasys2 done_reg2default:default2$ phase_meas_p_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd2default:default2 2682default:default8@Z8-4471hpx  %done synthesizing module '%s' (%s#%s)256*oasys2# dmtd_phase_meas2default:default2 632default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd2default:default2 732default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2% cdce_synchronizer2default:default2~ hD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd2default:default2 662default:default8@Z8-638hpx e %s *synth2M 9 Parameter pwrdown_delay bound to: 1000 - type: integer 2default:defaulthp x  e %s *synth2M 9 Parameter sync_delay bound to: 1000000 - type: integer 2default:defaulthp x   default block is never used226*oasys2~ hD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd2default:default2 1502default:default8@Z8-226hpx c %s *synth2K 7 Parameter CLK_SEL_TYPE bound to: SYNC - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 bufg_mux2default:default2 BUFGMUX2default:default2~ hD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd2default:default2 1992default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2% cdce_synchronizer2default:default2 642default:default2 12default:default2~ hD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd2default:default2 662default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2( ipb_user_status_regs2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_status_regsX12.vhd2default:default2 212default:default8@Z8-638hpx _ %s *synth2G 3 Parameter addr_width bound to: 8 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2( ipb_user_status_regs2default:default2 652default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_status_regsX12.vhd2default:default2 212default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2) ipb_user_control_regs2default:default2 ~D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_control_regs.vhd2default:default2 212default:default8@Z8-638hpx _ %s *synth2G 3 Parameter addr_width bound to: 6 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2) ipb_user_control_regs2default:default2 662default:default2 12default:default2 ~D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_control_regs.vhd2default:default2 212default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 DTC_top2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd2default:default2 322default:default2 DTC2default:default2 DTC_top2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 7782default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 DTC_top2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd2default:default2 512default:default8@Z8-638hpx  -Port '%s' is missing in component declaration4102*oasys2 ttcready2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd2default:default2 522default:default8@Z8-5640hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 TTC_decoder2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 472default:default2$ Inst_TTC_decoder2default:default2 TTC_decoder2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd2default:default2 712default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 TTC_decoder2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 642default:default8@Z8-638hpx g %s *synth2O ; Parameter CAPACITANCE bound to: DONT_CARE - type: string 2default:defaulthp x  [ %s *synth2C / Parameter DIFF_TERM bound to: 1 - type: bool 2default:defaulthp x  ` %s *synth2H 4 Parameter DQS_BIAS bound to: FALSE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  f %s *synth2N : Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: LVDS_25 - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2! i_TTC_data_in2default:default2 IBUFDS2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 1202default:default8@Z8-113hpx r %s *synth2Z F Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string 2default:defaulthp x  O %s *synth27 # Parameter INIT_Q1 bound to: 1'b0 2default:defaulthp x  O %s *synth27 # Parameter INIT_Q2 bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_C_INVERTED bound to: 1'b0 2default:defaulthp x  U %s *synth2= ) Parameter IS_D_INVERTED bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter SRTYPE bound to: SYNC - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_TTC_data2default:default2 IDDR2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 1602default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_L1Accept2default:default2 SRL16E2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 4482default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_brcst_str12default:default2 SRL16E2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 4592default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_brcst_str32default:default2 SRL16E2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 4702default:default8@Z8-113hpx \ %s *synth2D 0 Parameter INIT bound to: 16'b0000000000000000 2default:defaulthp x  W %s *synth2? + Parameter IS_CLK_INVERTED bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_indiv_str12default:default2 SRL16E2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 4812default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 TTC_decoder2default:default2 672default:default2 12default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl2default:default2 642default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys2 TTCready2default:default2 DTC_top2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd2default:default2 412default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 DTC_top2default:default2 682default:default2 12default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ttc_counter2default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ttc_counter.vhd2default:default2 292default:default2 DTC_Counter2default:default2 ttc_counter2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 7942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 ttc_counter2default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ttc_counter.vhd2default:default2 432default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 ttc_counter2default:default2 692default:default2 12default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ttc_counter.vhd2default:default2 432default:default8@Z8-256hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate02default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8152default:default8@Z8-3491hpx  synthesizing module '%s'%s4497*oasys2! clkRateTool322default:default2 2default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default8@Z8-6157hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter REFCTR_SIZE bound to: 23 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter REFCTR_TERMINAL bound to: 1249999 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys2! clkRateTool322default:default2 2default:default2 702default:default2 12default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default8@Z8-6155hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate12default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8242default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate22default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8332default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx i %s *synth2Q = Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! clkRateTool322default:default2 vD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v2default:default2 12default:default2 clkRate32default:default2! clkRateTool322default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8432default:default8@Z8-3491hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 3 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2- xlx_k7v7_gbt_ngFEC_design2default:default2o [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 702default:default2$ gbtbank1_l12_1182default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 8872default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1722default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 3 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  synthesizing module '%s'638*oasys2" gbt_bank_reset2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd2default:default2 1142default:default8@Z8-638hpx i %s *synth2Q = Parameter INITIAL_DELAY bound to: 40000000 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2" gbt_bank_reset2default:default2 712default:default2 12default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd2default:default2 1142default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 gbt_bank2default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 1072default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 3 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 gbt_tx2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd2default:default2 412default:default8@Z8-638hpx ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2$ gbt_tx_scrambler2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd2default:default2 782default:default8@Z8-638hpx ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2* gbt_tx_scrambler_21bit2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd2default:default2 582default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2* gbt_tx_scrambler_21bit2default:default2 722default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd2default:default2 582default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ gbt_tx_scrambler2default:default2 732default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd2default:default2 782default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" gbt_tx_encoder2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd2default:default2 692default:default8@Z8-638hpx ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys24 gbt_tx_encoder_gbtframe_rsencode2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd2default:default2 312default:default8@Z8-638hpx  synthesizing module '%s'638*oasys23 gbt_tx_encoder_gbtframe_polydiv2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd2default:default2 332default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys23 gbt_tx_encoder_gbtframe_polydiv2default:default2 742default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd2default:default2 332default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys24 gbt_tx_encoder_gbtframe_rsencode2default:default2 752default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd2default:default2 312default:default8@Z8-256hpx  synthesizing module '%s'638*oasys23 gbt_tx_encoder_gbtframe_intlver2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd2default:default2 282default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys23 gbt_tx_encoder_gbtframe_intlver2default:default2 762default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd2default:default2 282default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" gbt_tx_encoder2default:default2 772default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd2default:default2 692default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 gbt_tx2default:default2 782default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd2default:default2 412default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" gbt_tx_gearbox2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd2default:default2 652default:default8@Z8-638hpx d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 1 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" xpm_cdc_single2default:default2N :D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 1532default:default2' xpm_cdc_single_inst2default:default2" xpm_cdc_single2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd2default:default2 1082default:default8@Z8-3491hpx  synthesizing module '%s'%s4497*oasys2" xpm_cdc_single2default:default2 2default:default2P :D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 1532default:default8@Z8-6157hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 1 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 ASYNC_REG2default:default2 TRUE2default:default2P :D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2052default:default8@Z8-5534hpx  'done synthesizing module '%s'%s (%s#%s)4495*oasys2" xpm_cdc_single2default:default2 2default:default2 792default:default2 12default:default2P :D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 1532default:default8@Z8-6155hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" gbt_tx_gearbox2default:default2 802default:default2 12default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd2default:default2 652default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 832default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 3 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2012default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2172default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2182default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2202default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2212default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2332default:default8@Z8-5534hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 752default:default8@Z8-638hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  synthesizing module '%s'638*oasys2# mgt_bitslipctrl2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd2default:default2 582default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2# mgt_bitslipctrl2default:default2 812default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd2default:default2 582default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2/ mgt_framealigner_pattsearch2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd2default:default2 592default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2/ mgt_framealigner_pattsearch2default:default2 822default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd2default:default2 592default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys25 !gtxLatOpt_gen[3].rxBitSlipControl2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 4592default:default8@Z8-6071hpx  fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys25 !gtxLatOpt_gen[2].rxBitSlipControl2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 4592default:default8@Z8-6071hpx  fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys25 !gtxLatOpt_gen[1].rxBitSlipControl2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 4592default:default8@Z8-6071hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[1].resetGtxRx_from_rxBitSlipControl_reg2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[1].resetGtxTx_from_rxBitSlipControl_reg2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[2].resetGtxRx_from_rxBitSlipControl_reg2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[2].resetGtxTx_from_rxBitSlipControl_reg2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[3].resetGtxRx_from_rxBitSlipControl_reg2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[3].resetGtxTx_from_rxBitSlipControl_reg2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  0Net %s in module/entity %s does not have driver.3422*oasys2, MGT_DEVSPEC_o[rxCdrLock]2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 MGT_DEVSPEC_o[rx_phMonitor][4]2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys26 "MGT_DEVSPEC_o[rx_phSlipMonitor][4]2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2, MGT_DEVSPEC_o[drp_do][4]2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2- MGT_DEVSPEC_o[prbs_rxErr]2default:default2 mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 mgt2default:default2 832default:default2 12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 832default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" gbt_rx_gearbox2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd2default:default2 512default:default8@Z8-638hpx d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd2default:default2 542default:default8@Z8-5534hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" gbt_rx_gearbox2default:default2 842default:default2 12default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd2default:default2 512default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 gbt_rx2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd2default:default2 542default:default8@Z8-638hpx ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2" gbt_rx_decoder2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd2default:default2 572default:default8@Z8-638hpx ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys25 !gbt_rx_decoder_gbtframe_deintlver2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd2default:default2 352default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys25 !gbt_rx_decoder_gbtframe_deintlver2default:default2 852default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd2default:default2 352default:default8@Z8-256hpx  synthesizing module '%s'638*oasys21 gbt_rx_decoder_gbtframe_rsdec2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd2default:default2 462default:default8@Z8-638hpx  synthesizing module '%s'638*oasys23 gbt_rx_decoder_gbtframe_syndrom2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd2default:default2 422default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys23 gbt_rx_decoder_gbtframe_syndrom2default:default2 862default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd2default:default2 422default:default8@Z8-256hpx  synthesizing module '%s'638*oasys23 gbt_rx_decoder_gbtframe_lmbddet2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd2default:default2 422default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys23 gbt_rx_decoder_gbtframe_lmbddet2default:default2 872default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd2default:default2 422default:default8@Z8-256hpx  synthesizing module '%s'638*oasys25 !gbt_rx_decoder_gbtframe_errlcpoly2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd2default:default2 442default:default8@Z8-638hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  %done synthesizing module '%s' (%s#%s)256*oasys25 !gbt_rx_decoder_gbtframe_errlcpoly2default:default2 882default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd2default:default2 442default:default8@Z8-256hpx  synthesizing module '%s'638*oasys23 gbt_rx_decoder_gbtframe_chnsrch2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd2default:default2 442default:default8@Z8-638hpx  synthesizing module '%s'638*oasys23 gbt_rx_decoder_gbtframe_elpeval2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd2default:default2 412default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys23 gbt_rx_decoder_gbtframe_elpeval2default:default2 892default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd2default:default2 412default:default8@Z8-256hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  %done synthesizing module '%s' (%s#%s)256*oasys23 gbt_rx_decoder_gbtframe_chnsrch2default:default2 902default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd2default:default2 442default:default8@Z8-256hpx  synthesizing module '%s'638*oasys25 !gbt_rx_decoder_gbtframe_rs2errcor2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd2default:default2 452default:default8@Z8-638hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1282default:default8@Z8-226hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1532default:default8@Z8-226hpx  default block is never used226*oasys2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd2default:default2 1532default:default8@Z8-226hpx  %done synthesizing module '%s' (%s#%s)256*oasys25 !gbt_rx_decoder_gbtframe_rs2errcor2default:default2 912default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd2default:default2 452default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys21 gbt_rx_decoder_gbtframe_rsdec2default:default2 922default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd2default:default2 462default:default8@Z8-256hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 RX_RESET_I2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd2default:default2 1242default:default8@Z8-614hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" gbt_rx_decoder2default:default2 932default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd2default:default2 572default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2& gbt_rx_descrambler2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd2default:default2 572default:default8@Z8-638hpx ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2, gbt_rx_descrambler_21bit2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd2default:default2 562default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2, gbt_rx_descrambler_21bit2default:default2 942default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd2default:default2 562default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2& gbt_rx_descrambler2default:default2 952default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd2default:default2 572default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 gbt_rx2default:default2 962default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd2default:default2 542default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys2' GBT_ERRORDETECTED_o2default:default2 gbt_bank2default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 722default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 gbt_bank2default:default2 972default:default2 12default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 1072default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys25 !mgt_devspecific_to_s[loopBack][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 mgt_devspecific_to_s[tx_reset]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 mgt_devspecific_to_s[rx_reset]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2: &mgt_devspecific_to_s[conf_diffCtrl][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2< (mgt_devspecific_to_s[conf_postCursor][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2; 'mgt_devspecific_to_s[conf_preCursor][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys25 !mgt_devspecific_to_s[drp_addr][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys23 mgt_devspecific_to_s[drp_di][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys27 #mgt_devspecific_to_s[prbs_txSel][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys27 #mgt_devspecific_to_s[prbs_rxSel][4]2default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2- xlx_k7v7_gbt_ngFEC_design2default:default2 982default:default2 12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1722default:default8@Z8-256hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 2 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2- xlx_k7v7_gbt_ngFEC_design2default:default2o [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 702default:default2$ gbtbank2_l12_1172default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 9772default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1722default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 2 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  synthesizing module '%s'638*oasys2, gbt_bank__parameterized02default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 1072default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 2 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 832default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 2 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[1].resetGtxRx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[1].resetGtxTx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[2].resetGtxRx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[2].resetGtxTx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  0Net %s in module/entity %s does not have driver.3422*oasys2, MGT_DEVSPEC_o[rxCdrLock]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 MGT_DEVSPEC_o[rx_phMonitor][3]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 MGT_DEVSPEC_o[rx_phMonitor][4]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys26 "MGT_DEVSPEC_o[rx_phSlipMonitor][3]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys26 "MGT_DEVSPEC_o[rx_phSlipMonitor][4]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2, MGT_DEVSPEC_o[drp_do][3]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2, MGT_DEVSPEC_o[drp_do][4]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2- MGT_DEVSPEC_o[prbs_rxErr]2default:default2' mgt__parameterized02default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2' mgt__parameterized02default:default2 982default:default2 12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 832default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys2' GBT_ERRORDETECTED_o2default:default2, gbt_bank__parameterized02default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 722default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2, gbt_bank__parameterized02default:default2 982default:default2 12default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 1072default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys25 !mgt_devspecific_to_s[loopBack][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys25 !mgt_devspecific_to_s[loopBack][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 mgt_devspecific_to_s[tx_reset]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 mgt_devspecific_to_s[rx_reset]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2: &mgt_devspecific_to_s[conf_diffCtrl][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2: &mgt_devspecific_to_s[conf_diffCtrl][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2< (mgt_devspecific_to_s[conf_postCursor][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2< (mgt_devspecific_to_s[conf_postCursor][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2; 'mgt_devspecific_to_s[conf_preCursor][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2; 'mgt_devspecific_to_s[conf_preCursor][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys25 !mgt_devspecific_to_s[drp_addr][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys25 !mgt_devspecific_to_s[drp_addr][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys23 mgt_devspecific_to_s[drp_di][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys23 mgt_devspecific_to_s[drp_di][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys27 #mgt_devspecific_to_s[prbs_txSel][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys27 #mgt_devspecific_to_s[prbs_txSel][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys27 #mgt_devspecific_to_s[prbs_rxSel][3]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys27 #mgt_devspecific_to_s[prbs_rxSel][4]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2= )xlx_k7v7_gbt_ngFEC_design__parameterized12default:default2 982default:default2 12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1722default:default8@Z8-256hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 3 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2- xlx_k7v7_gbt_ngFEC_design2default:default2o [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 702default:default2$ gbtbank3_l12_1162default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 10672default:default8@Z8-3491hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 4 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2- xlx_k7v7_gbt_ngFEC_design2default:default2o [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 702default:default2# gbtbank4_l8_1122default:default2- xlx_k7v7_gbt_ngFEC_design2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 11572default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2= )xlx_k7v7_gbt_ngFEC_design__parameterized42default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1722default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 4 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! mgt_txready_s2default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 2372default:default8@Z8-614hpx  synthesizing module '%s'638*oasys2, gbt_bank__parameterized12default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 1072default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 4 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 832default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter NUM_LINKS bound to: 4 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter TX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter RX_OPTIMIZATION bound to: 1 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter TX_ENCODING bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_ENCODING bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 ngFEC_mgt2default:default2 kD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl2default:default2 52default:default2, xlx_k7v7_mgt_latopt_inst2default:default2 ngFEC_mgt2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2642default:default8@Z8-3491hpx  ,binding component instance '%s' to cell '%s'113*oasys2! rxWordClkBufg2default:default2 BUFH2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3652default:default8@Z8-113hpx  ,binding component instance '%s' to cell '%s'113*oasys2! txWordClkBufg2default:default2 BUFG2default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 3702default:default8@Z8-113hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[1].resetGtxRx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[1].resetGtxTx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[2].resetGtxRx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[2].resetGtxTx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[3].resetGtxRx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[3].resetGtxTx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[4].resetGtxRx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2602default:default8@Z8-6426hpx  Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2I 5gtxLatOpt_gen[4].resetGtxTx_from_rxBitSlipControl_reg2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 2612default:default8@Z8-6426hpx  0Net %s in module/entity %s does not have driver.3422*oasys2, MGT_DEVSPEC_o[rxCdrLock]2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2- MGT_DEVSPEC_o[prbs_rxErr]2default:default2' mgt__parameterized12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 742default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2' mgt__parameterized12default:default2 982default:default2 12default:default2 nD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd2default:default2 832default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys2' GBT_ERRORDETECTED_o2default:default2, gbt_bank__parameterized12default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 722default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2, gbt_bank__parameterized12default:default2 982default:default2 12default:default2 jD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd2default:default2 1072default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 mgt_devspecific_to_s[tx_reset]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized42default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys22 mgt_devspecific_to_s[rx_reset]2default:default2= )xlx_k7v7_gbt_ngFEC_design__parameterized42default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1972default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2= )xlx_k7v7_gbt_ngFEC_design__parameterized42default:default2 982default:default2 12default:default2q [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd2default:default2 1722default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 debug_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 932default:default2" debug_mux_inst2default:default2 debug_mux2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 12592default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 debug_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1172default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 462default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" sfp_signal_mux2default:default2 992default:default2 12default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 462default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 292default:default2( debug_sfp_signal_mux2default:default2" sfp_signal_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1552default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 global_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 662default:default2$ debug_global_mux2default:default2 global_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1752default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 global_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 772default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 global_mux2default:default2 1002default:default2 12default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 772default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 debug_mux2default:default2 1012default:default2 12default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 1172default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 debug_mux2default:default2 tD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd2default:default2 932default:default2" debug_mux_inst2default:default2 debug_mux2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 12592default:default8@Z8-3491hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_12default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13272default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_22default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13282default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_32default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13292default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_42default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13302default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_52default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13312default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_62default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13322default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_72default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13332default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_82default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13342default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_92default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13352default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_102default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13362default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_112default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13372default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_sda_122default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13382default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_12default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13392default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_22default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13402default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_32default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13412default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_42default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13422default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_52default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13432default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_62default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13442default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_72default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13452default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_82default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13462default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_92default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13472default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_102default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13482default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_112default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13492default:default8@Z8-113hpx [ %s *synth2C / Parameter DRIVE bound to: 12 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter IBUF_LOW_PWR bound to: 1 - type: bool 2default:defaulthp x  d %s *synth2L 8 Parameter IOSTANDARD bound to: DEFAULT - type: string 2default:defaulthp x  [ %s *synth2C / Parameter SLEW bound to: SLOW - type: string 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 i_sfp_scl_122default:default2 IOBUF2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 13502default:default8@Z8-113hpx  synthesizing module '%s'638*oasys2 ngFEC_module2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 602default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 492default:default8@Z8-638hpx ` %s *synth2H 4 Parameter BRAM_SIZE bound to: 36Kb - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter DEVICE bound to: 7SERIES - type: string 2default:defaulthp x  \ %s *synth2D 0 Parameter DOA_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOB_REG bound to: 0 - type: integer 2default:defaulthp x   %s *synth2  Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter INIT_FILE bound to: NONE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_A bound to: 16 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_B bound to: 16 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter SIM_COLLISION_CHECK bound to: ALL - type: string 2default:defaulthp x  _ %s *synth2G 3 Parameter SIM_MODE bound to: SAFE - type: string 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_A bound to: 16 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_B bound to: 16 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" BRAM_TDP_MACRO2default:default2U AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 362default:default2 BRAM_l2default:default2" BRAM_TDP_MACRO2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 1082default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2+ unimacro_BRAM_TDP_MACRO2default:default2W AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 2242default:default8@Z8-638hpx ` %s *synth2H 4 Parameter BRAM_SIZE bound to: 36Kb - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter DEVICE bound to: 7SERIES - type: string 2default:defaulthp x  \ %s *synth2D 0 Parameter DOA_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOB_REG bound to: 0 - type: integer 2default:defaulthp x   %s *synth2  Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter INIT_FILE bound to: NONE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_A bound to: 16 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_B bound to: 16 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter SIM_COLLISION_CHECK bound to: ALL - type: string 2default:defaulthp x  _ %s *synth2G 3 Parameter SIM_MODE bound to: SAFE - type: string 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_A bound to: 16 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_B bound to: 16 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOA_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOB_REG bound to: 0 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter EN_ECC_READ bound to: 0 - type: bool 2default:defaulthp x  ^ %s *synth2F 2 Parameter EN_ECC_WRITE bound to: 0 - type: bool 2default:defaulthp x   %s *synth2  Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter INIT_FILE bound to: NONE - type: string 2default:defaulthp x  ] %s *synth2E 1 Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_ENARDEN_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_ENBWREN_INVERTED bound to: 1'b0 2default:defaulthp x  a %s *synth2I 5 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 2default:defaulthp x  a %s *synth2I 5 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_RSTREGB_INVERTED bound to: 1'b0 2default:defaulthp x  f %s *synth2N : Parameter RAM_EXTENSION_A bound to: NONE - type: string 2default:defaulthp x  f %s *synth2N : Parameter RAM_EXTENSION_B bound to: NONE - type: string 2default:defaulthp x  ^ %s *synth2F 2 Parameter RAM_MODE bound to: TDP - type: string 2default:defaulthp x  y %s *synth2a M Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_A bound to: 18 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_B bound to: 18 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string 2default:defaulthp x  j %s *synth2R > Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string 2default:defaulthp x  i %s *synth2Q = Parameter SIM_COLLISION_CHECK bound to: ALL - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter SIM_DEVICE bound to: 7SERIES - type: string 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_A bound to: 18 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_B bound to: 18 - type: integer 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 ram36_bl2default:default2 RAMB36E12default:default2W AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 22602default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2+ unimacro_BRAM_TDP_MACRO2default:default2 1022default:default2 12default:default2W AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 2242default:default8@Z8-256hpx ` %s *synth2H 4 Parameter BRAM_SIZE bound to: 36Kb - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter DEVICE bound to: 7SERIES - type: string 2default:defaulthp x  \ %s *synth2D 0 Parameter DOA_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOB_REG bound to: 0 - type: integer 2default:defaulthp x   %s *synth2  Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter INIT_FILE bound to: NONE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_A bound to: 16 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_B bound to: 16 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter SIM_COLLISION_CHECK bound to: ALL - type: string 2default:defaulthp x  _ %s *synth2G 3 Parameter SIM_MODE bound to: SAFE - type: string 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_A bound to: 16 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_B bound to: 16 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" BRAM_TDP_MACRO2default:default2U AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 362default:default2 BRAM_l2default:default2" BRAM_TDP_MACRO2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 1082default:default8@Z8-3491hpx ` %s *synth2H 4 Parameter BRAM_SIZE bound to: 36Kb - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter DEVICE bound to: 7SERIES - type: string 2default:defaulthp x  \ %s *synth2D 0 Parameter DOA_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOB_REG bound to: 0 - type: integer 2default:defaulthp x   %s *synth2  Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter INIT_FILE bound to: NONE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_A bound to: 32 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_B bound to: 32 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter SIM_COLLISION_CHECK bound to: ALL - type: string 2default:defaulthp x  _ %s *synth2G 3 Parameter SIM_MODE bound to: SAFE - type: string 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_A bound to: 32 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_B bound to: 32 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2" BRAM_TDP_MACRO2default:default2U AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 362default:default2 BRAM_h2default:default2" BRAM_TDP_MACRO2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 1352default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2; 'unimacro_BRAM_TDP_MACRO__parameterized02default:default2W AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 2242default:default8@Z8-638hpx ` %s *synth2H 4 Parameter BRAM_SIZE bound to: 36Kb - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter DEVICE bound to: 7SERIES - type: string 2default:defaulthp x  \ %s *synth2D 0 Parameter DOA_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOB_REG bound to: 0 - type: integer 2default:defaulthp x   %s *synth2  Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter INIT_FILE bound to: NONE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_A bound to: 32 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_B bound to: 32 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter SIM_COLLISION_CHECK bound to: ALL - type: string 2default:defaulthp x  _ %s *synth2G 3 Parameter SIM_MODE bound to: SAFE - type: string 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_A bound to: 32 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_B bound to: 32 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOA_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter DOB_REG bound to: 0 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter EN_ECC_READ bound to: 0 - type: bool 2default:defaulthp x  ^ %s *synth2F 2 Parameter EN_ECC_WRITE bound to: 0 - type: bool 2default:defaulthp x   %s *synth2  Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2  Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  r %s *synth2Z F Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter INIT_FILE bound to: NONE - type: string 2default:defaulthp x  ] %s *synth2E 1 Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_ENARDEN_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_ENBWREN_INVERTED bound to: 1'b0 2default:defaulthp x  a %s *synth2I 5 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 2default:defaulthp x  a %s *synth2I 5 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter IS_RSTREGB_INVERTED bound to: 1'b0 2default:defaulthp x  f %s *synth2N : Parameter RAM_EXTENSION_A bound to: NONE - type: string 2default:defaulthp x  f %s *synth2N : Parameter RAM_EXTENSION_B bound to: NONE - type: string 2default:defaulthp x  ^ %s *synth2F 2 Parameter RAM_MODE bound to: TDP - type: string 2default:defaulthp x  y %s *synth2a M Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_A bound to: 36 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter READ_WIDTH_B bound to: 36 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string 2default:defaulthp x  j %s *synth2R > Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string 2default:defaulthp x  i %s *synth2Q = Parameter SIM_COLLISION_CHECK bound to: ALL - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter SIM_DEVICE bound to: 7SERIES - type: string 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  s %s *synth2[ G Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string 2default:defaulthp x  j %s *synth2R > Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_A bound to: 36 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter WRITE_WIDTH_B bound to: 36 - type: integer 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 ram36_bl2default:default2 RAMB36E12default:default2W AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 22602default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys2; 'unimacro_BRAM_TDP_MACRO__parameterized02default:default2 1022default:default2 12default:default2W AD:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd2default:default2 2242default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 Module_RAM2default:default2 1032default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 492default:default8@Z8-256hpx U %s *synth2= ) Parameter partition bound to: 5'b00000 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00000 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2% buffer_server_com2default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b00001 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys25 !buffer_server_com__parameterized12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00001 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys25 !buffer_server_com__parameterized12default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b00010 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys25 !buffer_server_com__parameterized32default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00010 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys25 !buffer_server_com__parameterized32default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b00011 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys25 !buffer_server_com__parameterized52default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00011 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys25 !buffer_server_com__parameterized52default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b00100 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys25 !buffer_server_com__parameterized72default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00100 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys25 !buffer_server_com__parameterized72default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b00101 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys25 !buffer_server_com__parameterized92default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00101 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys25 !buffer_server_com__parameterized92default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b00110 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized112default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00110 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized112default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b00111 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized132default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b00111 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized132default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b01000 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized152default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b01000 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized152default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b01001 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized172default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b01001 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized172default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b01010 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized192default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b01010 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized192default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b01011 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized212default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b01011 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized212default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b11101 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized232default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b11101 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized232default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b01111 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized252default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b01111 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized252default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2 282default:default2 RAM2default:default2 Module_RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1542default:default8@Z8-3491hpx U %s *synth2= ) Parameter partition bound to: 5'b11111 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 312default:default2! buffer_server2default:default2% buffer_server_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 1942default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "buffer_server_com__parameterized272default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-638hpx U %s *synth2= ) Parameter partition bound to: 5'b11111 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys26 "buffer_server_com__parameterized272default:default2 1042default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd2default:default2 512default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 502default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2$ buffer_ngccm_com2default:default2 1052default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 502default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2 buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2172default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2) buffer_ngccm_jtag_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_jtag_com.vhd2default:default2 312default:default2% buffer_ngccm_jtag2default:default2) buffer_ngccm_jtag_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2372default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2) buffer_ngccm_jtag_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_jtag_com.vhd2default:default2 502default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2) buffer_ngccm_jtag_com2default:default2 1062default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_jtag_com.vhd2default:default2 502default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 302default:default2$ bkp_buffer_ngccm2default:default2$ buffer_ngccm_com2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 2542default:default8@Z8-3491hpx  RAM %s from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers 4277*oasys2 ram_mosi_reg2default:defaultZ8-5858hpx  0Net %s in module/entity %s does not have driver.3422*oasys2, ngccm_mosi[13][ipb_addr]2default:default2 ngFEC_module2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 572default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2- ngccm_mosi[13][ipb_wdata]2default:default2 ngFEC_module2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 572default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2. ngccm_mosi[13][ipb_strobe]2default:default2 ngFEC_module2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 572default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2- ngccm_mosi[13][ipb_write]2default:default2 ngFEC_module2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 572default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 ngFEC_module2default:default2 1072default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2 602default:default8@Z8-256hpx ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2! delay_counter2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/qie_reset_shifter/delay_counter.vhd2default:default2 322default:default2# QIE_RESET_DELAY2default:default2! delay_counter2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 14542default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2! delay_counter2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/qie_reset_shifter/delay_counter.vhd2default:default2 412default:default8@Z8-638hpx ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2! delay_counter2default:default2 1082default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/qie_reset_shifter/delay_counter.vhd2default:default2 412default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 952default:default8@Z8-638hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2 Sync2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Sync.vhd2default:default2 252default:default2! Sync_TX_Reset2default:default2 Sync2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 3982default:default8@Z8-3491hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-34912default:default2 1002default:defaultZ17-14hpx  synthesizing module '%s'638*oasys2 Sync2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Sync.vhd2default:default2 342default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 Sync2default:default2 1092default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Sync.vhd2default:default2 342default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2 prbs2default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/prbs.vhd2default:default2 432default:default8@Z8-638hpx ` %s *synth2H 4 Parameter seed bound to: 20'b00101010001000000001 2default:defaulthp x  Z %s *synth2B . Parameter inverter bound to: 0 - type: bool 2default:defaulthp x  X %s *synth2@ , Parameter hbhehf bound to: 0 - type: bool 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2 prbs2default:default2 1102default:default2 12default:default2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/prbs.vhd2default:default2 432default:default8@Z8-256hpx  synthesizing module '%s'638*oasys2" gbt_rx_checker2default:default2 }D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/gbt_rx_checker.vhd2default:default2 442default:default8@Z8-638hpx a %s *synth2I 5 Parameter seed_length bound to: 20 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter nobReg bound to: 32 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2" gbt_rx_checker2default:default2 1112default:default2 12default:default2 }D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/gbt_rx_checker.vhd2default:default2 442default:default8@Z8-256hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2' error_counter_reset2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 7312default:default8@Z8-614hpx c %s *synth2K 7 Parameter gCOUNTER_SIZE bound to: 26 - type: integer 2default:defaulthp x  o %s *synth2W C Parameter gCOUNTER_TERM bound to: 26'b11111111111111111111111111 2default:defaulthp x   synthesizing module '%s'638*oasys2$ Agnostic_Counter2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Agnostic_counter.vhd2default:default2 372default:default8@Z8-638hpx c %s *synth2K 7 Parameter gCOUNTER_SIZE bound to: 26 - type: integer 2default:defaulthp x  o %s *synth2W C Parameter gCOUNTER_TERM bound to: 26'b11111111111111111111111111 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2$ Agnostic_Counter2default:default2 1122default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Agnostic_counter.vhd2default:default2 372default:default8@Z8-256hpx ` %s *synth2H 4 Parameter DataBtoA_SZ bound to: 1 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DataAtoB_SZ bound to: 84 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter WAIT_STATES_A bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'%s4497*oasys2! CrossClock_RX2default:default2 2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 202default:default8@Z8-6157hpx ` %s *synth2H 4 Parameter DataBtoA_SZ bound to: 1 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DataAtoB_SZ bound to: 84 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter WAIT_STATES_A bound to: 0 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter SHIFTA_MSB bound to: 3 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys2! CrossClock_RX2default:default2 2default:default2 1132default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 202default:default8@Z8-6155hpx ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 IPbus_local2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 582default:default8@Z8-638hpx ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 442default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 452default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 502default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 512default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 612default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 mark_debug2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 622default:default8@Z8-5534hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x   synthesizing module '%s'%s4497*oasys22 xpm_cdc_single__parameterized12default:default2 2default:default2P :D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 1532default:default8@Z8-6157hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys22 xpm_cdc_single__parameterized12default:default2 2default:default2 1132default:default2 12default:default2P :D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 1532default:default8@Z8-6155hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 IPbus_local2default:default2 1142default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd2default:default2 582default:default8@Z8-256hpx ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter ADDR_MSB bound to: 11 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WAIT_STATES bound to: 10 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 2default:defaulthp x   -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  synthesizing module '%s'638*oasys2" LocalI2CBridge2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalI2CBridge.vhd2default:default2 782default:default8@Z8-638hpx P %s *synth28 $ Parameter ARST_LVL bound to: 1'b0 2default:defaulthp x   synthesizing module '%s'638*oasys2" i2c_master_usr2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_top.vhd2default:default2 1122default:default8@Z8-638hpx P %s *synth28 $ Parameter ARST_LVL bound to: 1'b0 2default:defaulthp x   synthesizing module '%s'638*oasys2( i2c_master_byte_ctrl2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd2default:default2 1132default:default8@Z8-638hpx  synthesizing module '%s'638*oasys2' i2c_master_bit_ctrl2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd2default:default2 1782default:default8@Z8-638hpx Y %s *synth2A - Parameter SIZE bound to: 8 - type: integer 2default:defaulthp x  P %s *synth28 $ Parameter DOUT_RST bound to: 1'b1 2default:defaulthp x   synthesizing module '%s'%s4497*oasys2! glitch_filter2default:default2 2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/glitch_filter.v2default:default2 572default:default8@Z8-6157hpx Y %s *synth2A - Parameter SIZE bound to: 8 - type: integer 2default:defaulthp x  P %s *synth28 $ Parameter DOUT_RST bound to: 1'b1 2default:defaulthp x  \ %s *synth2D 0 Parameter BUFSIZE bound to: 7 - type: integer 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 KEEP2default:default2 TRUE2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/glitch_filter.v2default:default2 852default:default8@Z8-5534hpx  'done synthesizing module '%s'%s (%s#%s)4495*oasys2! glitch_filter2default:default2 2default:default2 1152default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/glitch_filter.v2default:default2 572default:default8@Z8-6155hpx Y %s *synth2A - Parameter SIZE bound to: 8 - type: integer 2default:defaulthp x  P %s *synth28 $ Parameter DOUT_RST bound to: 1'b1 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2' i2c_master_bit_ctrl2default:default2 1162default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd2default:default2 1782default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2( i2c_master_byte_ctrl2default:default2 1172default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd2default:default2 1132default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" i2c_master_usr2default:default2 1182default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_top.vhd2default:default2 1122default:default8@Z8-256hpx  0Net %s in module/entity %s does not have driver.3422*oasys2 I2C_ack_o2default:default2" LocalI2CBridge2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalI2CBridge.vhd2default:default2 642default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2" LocalI2CBridge2default:default2 1192default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalI2CBridge.vhd2default:default2 782default:default8@Z8-256hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 i2c_ack_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 1702default:default8@Z8-5640hpx  synthesizing module '%s'638*oasys2# LocalJTAGBridge2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalJTAGBridge.vhd2default:default2 942default:default8@Z8-638hpx ` %s *synth2H 4 Parameter gADDR_BITS bound to: 10 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter gDATA_BITS bound to: 32 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 JTAGMaster2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd2default:default2 922default:default8@Z8-638hpx ` %s *synth2H 4 Parameter gADDR_BITS bound to: 10 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter gDATA_BITS bound to: 32 - type: integer 2default:defaulthp x   "Detected attribute (* %s = "%s" *)3982*oasys2 fsm_encoding2default:default2 one-hot2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd2default:default2 2242default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 fsm_encoding2default:default2 one-hot2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd2default:default2 2312default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 fsm_encoding2default:default2 one-hot2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd2default:default2 2362default:default8@Z8-5534hpx  "Detected attribute (* %s = "%s" *)3982*oasys2 keep2default:default2 true2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd2default:default2 2852default:default8@Z8-5534hpx ` %s *synth2H 4 Parameter gADDR_BITS bound to: 10 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter gDATA_BITS bound to: 32 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 RAM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagBram.vhd2default:default2 662default:default8@Z8-638hpx ` %s *synth2H 4 Parameter gADDR_BITS bound to: 10 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter gDATA_BITS bound to: 32 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2 RAM2default:default2 1202default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagBram.vhd2default:default2 662default:default8@Z8-256hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x   Mix of Sync and Async assignments to register '%s' in module '%s' in the same process may cause logic issues. Please split the sync and async parts into different processes 4518*oasys2! TCKi_sync_reg2default:default2 JTAGMaster2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd2default:default2 6302default:default8@Z8-6426hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 JTAGMaster2default:default2 1212default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd2default:default2 922default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2# LocalJTAGBridge2default:default2 1222default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalJTAGBridge.vhd2default:default2 942default:default8@Z8-256hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 sel_sec_jtag2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2% jtag_bridge_tck_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2% jtag_bridge_tdi_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2% jtag_bridge_tms_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2& jtag_bridge_trst_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2" sec_jtag_tck_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2" sec_jtag_tdi_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2" sec_jtag_tms_o2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2! ngccmPinsInRx2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 10212default:default8@Z8-614hpx  0Net %s in module/entity %s does not have driver.3422*oasys2) ipb_miso[15][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2) ipb_miso[14][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2+ ipb_miso[13][ipb_rdata]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2) ipb_miso[13][ipb_ack]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2) ipb_miso[13][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2) ipb_miso[12][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2) ipb_miso[11][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2) ipb_miso[10][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[9][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[8][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[7][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[6][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[5][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[4][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[3][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[2][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[1][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2( ipb_miso[0][ipb_err]2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 772default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2' reg_ngccmio_sec_i2c2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 2602default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2$ heartBeat_Enable2default:default2 ngCCM2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 2752default:default8@Z8-3848hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 ngCCM2default:default2 1232default:default2 12default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 952default:default8@Z8-256hpx ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter orbit bound to: 3564 - type: integer 2default:defaulthp x   synthesizing module '%s'638*oasys2 pm2default:default2} gD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/pm.vhd2default:default2 482default:default8@Z8-638hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 1 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 1 - type: integer 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2 pm2default:default2 1242default:default2 12default:default2} gD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/pm.vhd2default:default2 482default:default8@Z8-256hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 4 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SRC_INPUT_REG bound to: 0 - type: integer 2default:defaulthp x   0Net %s in module/entity %s does not have driver.3422*oasys2 usrled1_r2default:default2 ngFEC_logic2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 812default:default8@Z8-3848hpx  0Net %s in module/entity %s does not have driver.3422*oasys2 usrled1_g2default:default2 ngFEC_logic2default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 822default:default8@Z8-3848hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-38482default:default2 1002default:defaultZ17-14hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 ngFEC_logic2default:default2 1252default:default2 12default:default2f PD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd2default:default2 1682default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2 fc7_top2default:default2 1262default:default2 12default:default2| fD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd2default:default2 1672default:default8@Z8-256hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[2]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[3]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[4]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[5]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2' k7_pcie_clk_ctrl[2]2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2' k7_pcie_clk_ctrl[3]2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2" fmc_l12_pwr_en2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2! fmc_l8_pwr_en2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2 fmc_pg_c2m2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_spare[6]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_spare[7]2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_spare[8]2default:default2 02default:defaultZ8-3917hpx  !design %s has unconnected port %s3331*oasys22 xpm_cdc_single__parameterized12default:default2 src_clk2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 IPbus_local2default:default2 reset_local2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[31]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[30]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[29]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[28]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[27]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[26]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[25]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[24]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[23]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[22]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[21]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[20]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[19]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[18]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[17]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" i2c_master_usr2default:default2 wb_dat_i[16]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" LocalI2CBridge2default:default2 I2C_ack_o2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2" LocalI2CBridge2default:default2! addr_local[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2# LocalJTAGBridge2default:default2" jtag_reg_i[11]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2# LocalJTAGBridge2default:default2" jtag_reg_i[10]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2# LocalJTAGBridge2default:default2 tms_i2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2# LocalJTAGBridge2default:default2 trst_i2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2) ipb_miso[15][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2) ipb_miso[14][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][31]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][30]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][29]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][28]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][27]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][26]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][25]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][24]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][23]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][22]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][21]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][20]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][19]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][18]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][17]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][16]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][15]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][14]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][13]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][12]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][11]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2/ ipb_miso[13][ipb_rdata][10]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][6]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][5]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_miso[13][ipb_rdata][0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2) ipb_miso[13][ipb_ack]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2) ipb_miso[13][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2) ipb_miso[12][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2) ipb_miso[11][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2) ipb_miso[10][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[9][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[8][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[7][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[6][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[5][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[4][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[3][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[2][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[1][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2( ipb_miso[0][ipb_err]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2 sfp_sda_i[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2 sfp_scl_i[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2 sfp_sda_o[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2 sfp_scl_o[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2' reset_partition[15]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2' reset_partition[13]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][31]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][30]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][29]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][28]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][27]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][26]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][25]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][24]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][23]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][22]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][21]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][20]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][19]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][18]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][17]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][16]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][15]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][14]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][13]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[15][ipb_addr][12]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 ngCCM2default:default2. ipb_mosi[14][ipb_addr][31]2default:defaultZ8-3331hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-33312default:default2 1002default:defaultZ17-14hpx  %s *synth2 xFinished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 780.688 ; gain = 406.770 2default:defaulthp x  D %s *synth2,  Report Check Netlist: 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I| |Item |Errors |Warnings |Status |Description | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x   'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][31]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][30]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][29]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][28]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][27]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][26]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][25]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][24]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][23]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][22]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][21]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][20]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][19]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][18]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][17]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][16]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][15]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][14]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][13]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][12]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][11]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[7][10]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][9]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][8]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][7]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][6]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][5]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][4]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][3]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][2]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][1]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[7][0]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][31]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][30]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][29]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][28]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][27]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][26]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][25]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][24]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][23]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][22]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][21]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][20]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][19]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][18]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][17]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][16]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][15]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][14]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][13]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][12]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][11]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[9][10]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][9]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][8]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][7]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][6]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][5]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][4]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][3]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][2]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][1]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2 regs_i[9][0]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][31]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][30]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][29]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][28]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][27]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][26]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][25]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][24]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][23]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][22]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][21]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][20]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][19]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][18]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][17]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][16]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][15]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][14]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][13]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][12]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][11]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[17][10]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][9]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][8]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][7]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][6]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][5]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][4]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][3]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][2]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][1]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2! regs_i[17][0]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[19][31]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[19][30]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[19][29]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  'tying undriven pin %s:%s to constant 0 3295*oasys2 ipb_sys_regs2default:default2" regs_i[19][28]2default:default2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd2default:default2 4472default:default8@Z8-3295hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-32952default:default2 1002default:defaultZ17-14hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  M %s *synth25 !Start Handling Custom Attributes 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 780.688 ; gain = 406.770 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 780.688 ; gain = 406.770 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  g -Analyzing %s Unisim elements for replacement 17*netlist2 5782default:defaultZ29-17hpx j 2Unisim Transformation completed in %s CPU seconds 28*netlist2 02default:defaultZ29-28hpx X Loading part %s157*device2% xc7k420tffg1156-22default:defaultZ21-403hpx K )Preparing netlist for logic optimization 349*projectZ1-570hpx >  Processing XDC Constraints 244*projectZ1-262hpx = Initializing timing engine 348*projectZ1-569hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2h RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 id:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc2default:default2g QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_in_context.xdc2default:default2! sys/eth/phy 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_in_context.xdc2default:default2! sys/eth/phy 2default:default8Z20-847hpx  Parsing XDC File [%s] 179* designutils2 lD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc2default:default8Z20-179hpx  Finished Parsing XDC File [%s] 178* designutils2 lD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc2default:default8Z20-178hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2 lD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc2default:default2- .Xil/fc7_top_propImpl.xdc2default:defaultZ1-236hpx  Parsing XDC File [%s] 179* designutils2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc2default:default8Z20-179hpx  Finished Parsing XDC File [%s] 178* designutils2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc2default:default8Z20-178hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2 pD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc2default:default2- .Xil/fc7_top_propImpl.xdc2default:defaultZ1-236hpx  Parsing XDC File [%s] 179* designutils2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc2default:default8Z20-179hpx  Deriving generated clocks 2*timing2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc2default:default2 672default:default8@Z38-2hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 get_clocks: 2default:default2 00:00:252default:default2 00:00:152default:default2 2450.3912default:default2 57.4142default:defaultZ17-268hp x   Finished Parsing XDC File [%s] 178* designutils2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc2default:default8Z20-178hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc2default:default2- .Xil/fc7_top_propImpl.xdc2default:defaultZ1-236hpx  Parsing XDC File [%s] 179* designutils2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc2default:default8Z20-179hpx  Finished Parsing XDC File [%s] 178* designutils2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc2default:default8Z20-178hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2 sD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc2default:default2- .Xil/fc7_top_propImpl.xdc2default:defaultZ1-236hpx  Parsing XDC File [%s] 179* designutils2 wD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc2default:default8Z20-179hpx  Finished Parsing XDC File [%s] 178* designutils2 wD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc2default:default8Z20-178hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2 wD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc2default:default2- .Xil/fc7_top_propImpl.xdc2default:defaultZ1-236hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1672default:default2 2450.3912default:default2 0.0002default:defaultZ17-268hp x   %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2M 7ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2M 7ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2B ,ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2B ,ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2M 7ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2M 7ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2B ,ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2B ,ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2M 7ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2M 7ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2B ,ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2B ,ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2L 6ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2{ engFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2z dngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2g QngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2g QngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2g QngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2g QngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2t ^ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2g QngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2g QngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2s ]ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2r \ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2f PngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2Q ;ngFEC/g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2Q ;ngFEC/g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2Q ;ngFEC/g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2Q ;ngFEC/g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2P :ngFEC/g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[0].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[0].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_tx_ready_cnt[10].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_tx_ready_cnt[10].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_tx_ready_cnt[11].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2A +ngFEC/g_tx_ready_cnt[11].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[1].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[1].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[2].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[2].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[3].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[3].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[4].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[4].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[5].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[5].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[6].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[6].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[7].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[7].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[8].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[8].tx_ready_Sync_inst 2default:default8Z20-1687hpx  %Sourcing Tcl File [%s] for cell '%s' 1448* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[9].tx_ready_Sync_inst 2default:default8Z20-1689hpx  .Finished Sourcing Tcl File [%s] for cell '%s' 1446* designutils2X BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2@ *ngFEC/g_tx_ready_cnt[9].tx_ready_Sync_inst 2default:default8Z20-1687hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2V BD:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2- .Xil/fc7_top_propImpl.xdc2default:defaultZ1-236hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.2012default:default2 2450.3912default:default2 0.0002default:defaultZ17-268hp x  H &Completed Processing XDC Constraints 245*projectZ1-263hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1452default:default2 2450.3912default:default2 0.0002default:defaultZ17-268hp x   !Unisim Transformation Summary: %s111*project2  A total of 32 instances were transformed. BUFGMUX => BUFGCTRL (inverted pins: CE0): 1 instances IBUFGDS => IBUFDS: 1 instances IOBUF => IOBUF (IBUF, OBUFT): 26 instances OBUFDS => OBUFDS: 1 instances PLLE2_BASE => PLLE2_ADV: 1 instances SRL16 => SRL16E: 2 instances 2default:defaultZ1-111hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1452default:default2 2450.3912default:default2 0.0002default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common24 Constraint Validation Runtime : 2default:default2 00:00:012default:default2 00:00:00.8302default:default2 2450.3912default:default2 0.0002default:defaultZ17-268hp x   Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2f RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2e QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2e QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2e QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 25.0002default:default2e QngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst2default:default2 SYSCLK_IN2default:default2 24.9512default:defaultZ38-316hpx  Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results. 203*timing2 16.0002default:default2 sys/eth/phy2default:default2 rxuserclk22default:default2 8.0002default:defaultZ38-316hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Constraint Validation : Time (s): cpu = 00:02:29 ; elapsed = 00:02:10 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   HMultithreading enabled for synth_design using a maximum of %s processes.4031*oasys2 22default:defaultZ8-5580hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  V %s *synth2> *Start Loading Part and Timing Information 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Loading part: xc7k420tffg1156-2 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Loading Part and Timing Information : Time (s): cpu = 00:02:29 ; elapsed = 00:02:10 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Z %s *synth2B .Start Applying 'set_property' XDC Constraints 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:02:32 ; elapsed = 00:02:13 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 rst2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 timer2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 bad_crc2default:default2 322default:default2 252default:defaultZ8-5545hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 invert2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 byte_cnt2default:default2 22default:default2 52default:defaultZ8-5544hpx x 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 tick_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 set_addr_int2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# addr_to_set_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 send_buf_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 load_buf_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2# buf_to_load_int2default:defaultZ8-5587hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 set_addr_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2# addr_to_set_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 send_buf_int2default:defaultZ8-5587hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 load_buf_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 load_buf_int2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 payload_len2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# buf_to_load_int2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# buf_to_load_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 do_sum_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 clr_sum_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2! int_valid_int2default:defaultZ8-5587hpx y 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 cksum_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 int_data_int2default:defaultZ8-5587hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 payload_len2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 set_addr_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2# addr_to_set_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 send_buf_int2default:defaultZ8-5587hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 load_buf_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 load_buf_int2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 payload_len2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# buf_to_load_int2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# buf_to_load_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 do_sum_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 clr_sum_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2! int_valid_int2default:defaultZ8-5587hpx y 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 cksum_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2 int_data_int2default:defaultZ8-5587hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 payload_len2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2" send_pending_i2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2# addr_to_set_int2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2# addr_to_set_int2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 shift_buf2default:default2 12default:default2 52default:defaultZ8-5544hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 set_addr_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2# addr_to_set_int2default:defaultZ8-5587hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 send_buf_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 load_buf_int2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# buf_to_load_int2default:defaultZ8-5546hpx } 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2! cksum_pending2default:defaultZ8-5546hpx z 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 do_sum_int2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 clr_sum_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 int_data_int2default:defaultZ8-5546hpx } 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2! int_valid_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 set_addr_int2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# addr_to_set_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 send_buf_int2default:defaultZ8-5546hpx y 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 next_load2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 request_int2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 event_data2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 event_data2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 header2default:default2 12default:default2 52default:defaultZ8-5544hpx y 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 short_int2default:defaultZ8-5546hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2$ send_special_int2default:defaultZ8-5587hpx z 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 flip_cksum2default:defaultZ8-5546hpx x 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 counting2default:defaultZ8-5546hpx y 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 cksum_int2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 clr_sum_int2default:defaultZ8-5546hpx z 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 do_sum_int2default:defaultZ8-5546hpx } 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2! int_valid_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 low_addr_int2default:defaultZ8-5546hpx } 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2! ipbus_hdr_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 byteswap_int2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 byteswap_int2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2' ipbus_out_valid_int2default:defaultZ8-5546hpx z 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 next_state2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% rxram_active_int02default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[15]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[14]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[13]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[12]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[11]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[10]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[9]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[8]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[7]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[6]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[5]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[4]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[3]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[2]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[1]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[0]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[15]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[14]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[13]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[12]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[11]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2& pkt_id_buf_reg[10]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[9]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[8]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[7]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[6]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[5]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[4]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[3]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[2]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[1]2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% pkt_id_buf_reg[0]2default:default2 42default:default2 52default:defaultZ8-5544hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2# pkt_rdy_buf_reg2default:default2 32default:default2 22default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2 1542default:default8@Z8-3936hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2! transactor_if2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 wctr2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2' trans_out[pkt_done]2default:default2 32default:default2 52default:defaultZ8-5544hpx u 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 state2default:defaultZ8-5546hpx u 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 state2default:defaultZ8-5546hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2! transactor_sm2default:defaultZ8-802hpx w 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 last_wd2default:defaultZ8-5546hpx u 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 state2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 tx_hdr2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 rmw_write2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 err_d2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 state2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 buf_req2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 buf_we2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2! SerialInValid2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2" SerialOutValid2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 we_pipe2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 r_addr_pipe2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2( ipbus_out[ipb_rdata]2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2' reset_ipbus_to_pipe2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 sel2default:default2 12default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 w_state_reg2default:default2" icap_interface2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 r_state_reg2default:default2" icap_interface2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 r_state2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 read_delay2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 r_state2default:default2 22default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2& icap_interface_fsm2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 FMS_SELECT_O2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 state2default:default2 42default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 datafsm_reg2default:default2 i2c_bitwise2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 datafsm2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 completed2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 datafsm2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 completed2default:default2 32default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# chopexecfsm_reg2default:default2 i2c_ctrl2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 ctrlfsm_reg2default:default2 i2c_ctrl2default:defaultZ8-802hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 error_rdack12default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsmprev2default:default2 32default:default2 52default:defaultZ8-5544hpx v 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 p_2_in2default:defaultZ8-5546hpx v 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 p_0_in2default:defaultZ8-5546hpx v 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 p_7_in2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 error_rdack12default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsmprev2default:default2 32default:default2 52default:defaultZ8-5544hpx v 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 p_2_in2default:defaultZ8-5546hpx v 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 p_0_in2default:defaultZ8-5546hpx v 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 p_7_in2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ctrlfsm2default:default2 12default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 fsm_reg2default:default2$ i2c_eep_autoread2default:defaultZ8-802hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2( player_rxdata_reg[1]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2( player_rxdata_reg[3]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2( player_rxdata_reg[5]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2( player_rxdata_reg[7]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2( player_rxdata_reg[9]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[11]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[13]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[15]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[17]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[19]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[21]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[23]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[25]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[27]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[29]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[31]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[33]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[35]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[37]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[39]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[41]2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2) player_rxdata_reg[43]2default:defaultZ8-5546hpx w 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 addrcnt2default:defaultZ8-5546hpx s 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 fsm2default:defaultZ8-5546hpx  merging register '%s' into '%s'3619*oasys2$ data_o_reg[31:0]2default:default2$ rxdata_reg[31:0]2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2402default:default8@Z8-4471hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2 spi_master2default:defaultZ8-802hpx t 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 busy2default:defaultZ8-5546hpx u 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 state2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 pos_cnt2default:default2 22default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2( dmtd_with_deglitcher2default:defaultZ8-802hpx z 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 resync_p_o2default:defaultZ8-5546hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 pd_state_reg2default:default2# dmtd_phase_meas2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 phase_raw_b2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 start2default:default2 22default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2% cdce_synchronizer2default:defaultZ8-802hpx u 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 state2default:defaultZ8-5546hpx u 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 timer2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 fsm_pwrdown2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 sync_busy_o2default:default2 22default:default2 52default:defaultZ8-5544hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[0]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[1]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[2]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[3]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[4]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[5]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[6]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[7]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[8]2default:defaultZ8-5546hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[9]2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 regs_reg[10]2default:defaultZ8-5546hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-55462default:default2 1002default:defaultZ17-14hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2# mgt_bitslipctrl2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2/ mgt_framealigner_pattsearch2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 headerFlag_s2default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 state2default:default2 12default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2" mgt__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2" mgt__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[3].rstBitSlip_FSM_reg[3]2default:default2" mgt__xdcDup__12default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 reg12default:default2 32default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2! DET_IS_ZERO_O2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 ZERO_O2default:default2 42default:default2 52default:defaultZ8-5544hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-55442default:default2 1002default:defaultZ17-14hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2' mgt__parameterized02default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2' mgt__parameterized02default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2 mgt2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2 mgt2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[3].rstBitSlip_FSM_reg[3]2default:default2 mgt2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2' mgt__parameterized12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2' mgt__parameterized12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[3].rstBitSlip_FSM_reg[3]2default:default2' mgt__parameterized12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2: >xLatOpt_gen[4].rstBitSlip_FSM_reg[4]2default:default2' mgt__parameterized12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2! fe_status_reg2default:default2) buffer_ngccm_jtag_com2default:defaultZ8-802hpx  merging register '%s' into '%s'3619*oasys2) output_size_reg[31:0]2default:default2- response_length_reg[31:0]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd2default:default2 932default:default8@Z8-4471hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-44712default:default2 1002default:defaultZ17-14hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default2% buffer_server_com2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default25 !buffer_server_com__parameterized12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default25 !buffer_server_com__parameterized32default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default25 !buffer_server_com__parameterized52default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default25 !buffer_server_com__parameterized72default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default25 !buffer_server_com__parameterized92default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized112default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized132default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized152default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized172default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized192default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized212default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized232default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized252default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2" server_ack_reg2default:default26 "buffer_server_com__parameterized272default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__12default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 c_state_reg2default:default2' i2c_master_bit_ctrl2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2, statemachine.c_state_reg2default:default2( i2c_master_byte_ctrl2default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__22default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__22default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__22default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__32default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__32default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__32default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__42default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__42default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__42default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__52default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__52default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__52default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__62default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__62default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__62default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__72default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__72default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__72default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__82default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__82default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__82default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2) JTAGMaster__xdcDup__92default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2) JTAGMaster__xdcDup__92default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2) JTAGMaster__xdcDup__92default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2* JTAGMaster__xdcDup__102default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2* JTAGMaster__xdcDup__102default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2* JTAGMaster__xdcDup__102default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2* JTAGMaster__xdcDup__112default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2* JTAGMaster__xdcDup__112default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2* JTAGMaster__xdcDup__112default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2% StateJTAGCtrl_reg2default:default2 JTAGMaster2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2# StateJTAGIO_reg2default:default2 JTAGMaster2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2$ StateJTAGTDO_reg2default:default2 JTAGMaster2default:defaultZ8-802hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 DoSleep2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ st_idle | 0000010 | 000 2default:defaulthp x   %s *synth2s _ st_first | 1000000 | 001 2default:defaulthp x   %s *synth2s _ st_hdr | 0100000 | 010 2default:defaulthp x   %s *synth2s _ st_prebody | 0010000 | 011 2default:defaulthp x   %s *synth2s _ st_body | 0001000 | 100 2default:defaulthp x   %s *synth2s _ st_done | 0000100 | 101 2default:defaulthp x   %s *synth2s _ st_gap | 0000001 | 110 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2! transactor_if2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ st_idle | 100000 | 000 2default:defaulthp x   %s *synth2s _ st_hdr | 001000 | 001 2default:defaulthp x   %s *synth2s _ st_addr | 010000 | 010 2default:defaulthp x   %s *synth2s _ st_bus_cycle | 000010 | 011 2default:defaulthp x   %s *synth2s _ st_rmw_1 | 000100 | 100 2default:defaulthp x   %s *synth2s _ st_rmw_2 | 000001 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2! transactor_sm2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ w_s0 | 000 | 000 2default:defaulthp x   %s *synth2s _ w_s1 | 001 | 001 2default:defaulthp x   %s *synth2s _ w_s2 | 010 | 010 2default:defaulthp x   %s *synth2s _ w_s3 | 011 | 011 2default:defaulthp x   %s *synth2s _ w_s4 | 100 | 100 2default:defaulthp x   %s *synth2s _ w_s5 | 101 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 w_state_reg2default:default2 sequential2default:default2" icap_interface2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ r_s0 | 00 | 00 2default:defaulthp x   %s *synth2s _ r_s1 | 01 | 01 2default:defaulthp x   %s *synth2s _ r_s2 | 10 | 10 2default:defaulthp x   %s *synth2s _ r_s3 | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 r_state_reg2default:default2 sequential2default:default2" icap_interface2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ s0 | 00001 | 000 2default:defaulthp x   %s *synth2s _ s1 | 00010 | 001 2default:defaulthp x   %s *synth2s _ s2 | 00100 | 010 2default:defaulthp x   %s *synth2s _ s3 | 01000 | 011 2default:defaulthp x   %s *synth2s _ s4 | 10000 | 100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2& icap_interface_fsm2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ start | 001 | 001 2default:defaulthp x   %s *synth2s _ stop | 010 | 010 2default:defaulthp x   %s *synth2s _ writebyte | 011 | 011 2default:defaulthp x   %s *synth2s _ readbyte | 100 | 101 2default:defaulthp x   %s *synth2s _ getack | 101 | 100 2default:defaulthp x   %s *synth2s _ sendack | 110 | 110 2default:defaulthp x   %s *synth2s _ sendnak | 111 | 111 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 datafsm_reg2default:default2 sequential2default:default2 i2c_bitwise2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ a | 01 | 01 2default:defaulthp x   %s *synth2s _ b | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# chopexecfsm_reg2default:default2 sequential2default:default2 i2c_ctrl2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00000 | 00000 2default:defaulthp x   %s *synth2s _ req_startclk | 00001 | 00001 2default:defaulthp x   %s *synth2s _ req_start_1 | 00010 | 00010 2default:defaulthp x   %s *synth2s _ req_chipaddr_1 | 00011 | 00011 2default:defaulthp x   %s *synth2s _ req_getack_1 | 00100 | 00100 2default:defaulthp x   %s *synth2s _ req_regaddr | 00101 | 00101 2default:defaulthp x   %s *synth2s _ req_getack_2 | 00110 | 00110 2default:defaulthp x   %s *synth2s _ req_start_2 | 00111 | 01010 2default:defaulthp x   %s *synth2s _ req_chipaddr_2 | 01000 | 01011 2default:defaulthp x   %s *synth2s _ req_getack_4 | 01001 | 01100 2default:defaulthp x   %s *synth2s _ req_wrdata | 01010 | 00111 2default:defaulthp x   %s *synth2s _ req_getack_3 | 01011 | 01000 2default:defaulthp x   %s *synth2s _ req_rddata | 01100 | 01101 2default:defaulthp x   %s *synth2s _ req_sendack | 01101 | 01110 2default:defaulthp x   %s *synth2s _ req_rddata_2 | 01110 | 01111 2default:defaulthp x   %s *synth2s _ req_sendnak | 01111 | 10000 2default:defaulthp x   %s *synth2s _ req_stop_2 | 10000 | 10001 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 ctrlfsm_reg2default:default2 sequential2default:default2 i2c_ctrl2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE2 | 00001 | 000 2default:defaulthp x   %s *synth2s _ iSTATE | 00010 | 001 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00100 | 010 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01000 | 011 2default:defaulthp x   %s *synth2s _ iSTATE3 | 10000 | 100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 fsm_reg2default:default2 one-hot2default:default2$ i2c_eep_autoread2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE1 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE0 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE2 | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 sequential2default:default2 spi_master2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ wait_stable_0 | 001 | 00 2default:defaulthp x   %s *synth2s _ wait_edge | 010 | 01 2default:defaulthp x   %s *synth2s _ got_edge | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2( dmtd_with_deglitcher2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ pd_wait_tag | 00 | 00 2default:defaulthp x   %s *synth2s _ pd_wait_b | 01 | 10 2default:defaulthp x   %s *synth2s _ pd_wait_a | 10 | 01 2default:defaulthp x   %s *synth2s _ pd_get_phase | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 pd_state_reg2default:default2 sequential2default:default2# dmtd_phase_meas2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE | 0001 | 00 2default:defaulthp x   %s *synth2s _ iSTATE0 | 0010 | 01 2default:defaulthp x   %s *synth2s _ iSTATE1 | 0100 | 10 2default:defaulthp x   %s *synth2s _ iSTATE2 | 1000 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2% cdce_synchronizer2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ e0_idle | 001 | 00 2default:defaulthp x   %s *synth2s _ e4_dobitslip | 010 | 01 2default:defaulthp x   %s *synth2s _ e5_waitncycles | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2# mgt_bitslipctrl2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ unlocked | 00 | 00 2default:defaulthp x   %s *synth2s _ going_lock | 01 | 01 2default:defaulthp x   %s *synth2s _ locked | 10 | 10 2default:defaulthp x   %s *synth2s _ going_unlock | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 sequential2default:default2/ mgt_framealigner_pattsearch2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2 one-hot2default:default2" mgt__xdcDup__12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2 one-hot2default:default2" mgt__xdcDup__12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[3].rstBitSlip_FSM_reg[3]2default:default2 one-hot2default:default2" mgt__xdcDup__12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2 one-hot2default:default2' mgt__parameterized02default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2 one-hot2default:default2' mgt__parameterized02default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2 one-hot2default:default2 mgt2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2 one-hot2default:default2 mgt2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[3].rstBitSlip_FSM_reg[3]2default:default2 one-hot2default:default2 mgt2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[1].rstBitSlip_FSM_reg[1]2default:default2 one-hot2default:default2' mgt__parameterized12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[2].rstBitSlip_FSM_reg[2]2default:default2 one-hot2default:default2' mgt__parameterized12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[3].rstBitSlip_FSM_reg[3]2default:default2 one-hot2default:default2' mgt__parameterized12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 001 | 00 2default:defaulthp x   %s *synth2s _ reset_tx | 010 | 01 2default:defaulthp x   %s *synth2s _ reset_rx | 100 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2: >xLatOpt_gen[4].rstBitSlip_FSM_reg[4]2default:default2 one-hot2default:default2' mgt__parameterized12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle_s | 000 | 000 2default:defaulthp x   %s *synth2s _ write_s | 001 | 011 2default:defaulthp x   %s *synth2s _ wait_s | 010 | 100 2default:defaulthp x   %s *synth2s _ precmd_s | 011 | 101 2default:defaulthp x   %s *synth2s _ cmd_s | 100 | 110 2default:defaulthp x   %s *synth2s _ busy_s | 101 | 001 2default:defaulthp x   %s *synth2s _ response_s | 110 | 010 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2! fe_status_reg2default:default2 sequential2default:default2) buffer_ngccm_jtag_com2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default2% buffer_server_com2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default25 !buffer_server_com__parameterized12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default25 !buffer_server_com__parameterized32default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default25 !buffer_server_com__parameterized52default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default25 !buffer_server_com__parameterized72default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default25 !buffer_server_com__parameterized92default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized112default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized132default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized152default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized172default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized192default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized212default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized232default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized252default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE0 | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE1 | 01 | 01 2default:defaulthp x   %s *synth2s _ iSTATE2 | 10 | 10 2default:defaulthp x   %s *synth2s _ iSTATE | 11 | 11 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2" server_ack_reg2default:default2 sequential2default:default26 "buffer_server_com__parameterized272default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle_b | 00000 | 00001 2default:defaulthp x   %s *synth2s _ idle_c | 00001 | 00010 2default:defaulthp x   %s *synth2s _ idle_d | 00010 | 00011 2default:defaulthp x   %s *synth2s _ idle_e | 00011 | 00100 2default:defaulthp x   %s *synth2s _ idle_f | 00100 | 00101 2default:defaulthp x   %s *synth2s _ start_a | 00101 | 00110 2default:defaulthp x   %s *synth2s _ start_b | 00110 | 00111 2default:defaulthp x   %s *synth2s _ start_c | 00111 | 01000 2default:defaulthp x   %s *synth2s _ start_d | 01000 | 01001 2default:defaulthp x   %s *synth2s _ start_e | 01001 | 01010 2default:defaulthp x   %s *synth2s _ stop_a | 01010 | 01011 2default:defaulthp x   %s *synth2s _ stop_b | 01011 | 01100 2default:defaulthp x   %s *synth2s _ stop_c | 01100 | 01101 2default:defaulthp x   %s *synth2s _ stop_d | 01101 | 01110 2default:defaulthp x   %s *synth2s _ stop_e | 01110 | 01111 2default:defaulthp x   %s *synth2s _ wr_a | 01111 | 10101 2default:defaulthp x   %s *synth2s _ wr_b | 10000 | 10110 2default:defaulthp x   %s *synth2s _ wr_c | 10001 | 10111 2default:defaulthp x   %s *synth2s _ wr_d | 10010 | 11000 2default:defaulthp x   %s *synth2s _ wr_e | 10011 | 11001 2default:defaulthp x   %s *synth2s _ rd_a | 10100 | 10000 2default:defaulthp x   %s *synth2s _ rd_b | 10101 | 10001 2default:defaulthp x   %s *synth2s _ rd_c | 10110 | 10010 2default:defaulthp x   %s *synth2s _ rd_d | 10111 | 10011 2default:defaulthp x   %s *synth2s _ rd_e | 11000 | 10100 2default:defaulthp x   %s *synth2s _ idle_a | 11001 | 00000 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 c_state_reg2default:default2 sequential2default:default2' i2c_master_bit_ctrl2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ st_idle | 000 | 000 2default:defaulthp x   %s *synth2s _ st_start | 001 | 001 2default:defaulthp x   %s *synth2s _ st_read | 010 | 010 2default:defaulthp x   %s *synth2s _ st_write | 011 | 011 2default:defaulthp x   %s *synth2s _ st_ack | 100 | 100 2default:defaulthp x   %s *synth2s _ st_stop | 101 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2, statemachine.c_state_reg2default:default2 sequential2default:default2( i2c_master_byte_ctrl2default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__22default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__22default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__22default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__32default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__32default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__32default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__42default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__42default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__42default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__52default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__52default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__52default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__62default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__62default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__62default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__72default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__72default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__72default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__82default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__82default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__82default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__92default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__92default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2) JTAGMaster__xdcDup__92default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2* JTAGMaster__xdcDup__102default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2* JTAGMaster__xdcDup__102default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2* JTAGMaster__xdcDup__102default:defaultZ8-3354hpx  !inferring latch for variable '%s'327*oasys2" jtag_tck_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5532default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5542default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2" jtag_tms_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5552default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys22 ngccmPinsOutReg_reg[sec_reset]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys25 !ngccmPinsOutReg_reg[sec_sel_addr]2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 4682default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tdo_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9702default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tck_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9712default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2) jtag_bridge_tms_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9732default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2* jtag_bridge_trst_i_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 9742default:default8@Z8-327hpx  !inferring latch for variable '%s'327*oasys2& sec_jtag_tdi_o_reg2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd2default:default2 5592default:default8@Z8-327hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-3272default:default2 1002default:defaultZ17-14hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2* JTAGMaster__xdcDup__112default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2* JTAGMaster__xdcDup__112default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2* JTAGMaster__xdcDup__112default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 00 | 00 2default:defaulthp x   %s *synth2s _ capture | 01 | 01 2default:defaulthp x   %s *synth2s _ next_bit | 10 | 10 2default:defaulthp x   %s *synth2s _ wait_tck | 11 | 11 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$ StateJTAGTDO_reg2default:default2 sequential2default:default2 JTAGMaster2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ jtag_idle | 00 | 00 2default:defaulthp x   %s *synth2s _ jtag_go | 01 | 01 2default:defaulthp x   %s *synth2s _ jtag_wait | 10 | 10 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2% StateJTAGCtrl_reg2default:default2 sequential2default:default2 JTAGMaster2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ idle | 000 | 000 2default:defaulthp x   %s *synth2s _ next_word_ld | 001 | 110 2default:defaulthp x   %s *synth2s _ fall | 010 | 001 2default:defaulthp x   %s *synth2s _ prerise | 011 | 010 2default:defaulthp x   %s *synth2s _ rise | 100 | 011 2default:defaulthp x   %s *synth2s _ prefall | 101 | 100 2default:defaulthp x   %s *synth2s _ next_word_rd | 110 | 101 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2# StateJTAGIO_reg2default:default2 sequential2default:default2 JTAGMaster2default:defaultZ8-3354hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:03:13 ; elapsed = 00:02:56 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q| |RTL Partition |Replication |Instances | 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q|1 |i2c_master_core | 1| 1974| 2default:defaulthp x  } %s *synth2e Q|2 |system_core__GC0 | 1| 32499| 2default:defaulthp x  } %s *synth2e Q|3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| 2default:defaulthp x  } %s *synth2e Q|4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q|5 |TTC_decoder__GC0 | 1| 366| 2default:defaulthp x  } %s *synth2e Q|6 |gbt_rx | 12| 10684| 2default:defaulthp x  } %s *synth2e Q|7 |gbt_bank__xdcDup__1__GC0 | 1| 22419| 2default:defaulthp x  } %s *synth2e Q|8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 516| 2default:defaulthp x  } %s *synth2e Q|9 |gbt_bank__parameterized0__GC0 | 1| 14932| 2default:defaulthp x  } %s *synth2e Q|10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 344| 2default:defaulthp x  } %s *synth2e Q|11 |gbt_bank__GC0 | 1| 22419| 2default:defaulthp x  } %s *synth2e Q|12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 516| 2default:defaulthp x  } %s *synth2e Q|13 |gbt_bank__parameterized1__GC0 | 1| 29920| 2default:defaulthp x  } %s *synth2e Q|14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 688| 2default:defaulthp x  } %s *synth2e Q|15 |ngFEC_module__GBM0 | 1| 34676| 2default:defaulthp x  } %s *synth2e Q|16 |ngFEC_module__GBM1 | 1| 12685| 2default:defaulthp x  } %s *synth2e Q|17 |ngFEC_module__GBM2 | 1| 16886| 2default:defaulthp x  } %s *synth2e Q|18 |ngFEC_logic__GCB0 | 1| 27110| 2default:defaulthp x  } %s *synth2e Q|19 |ngFEC_logic__GCB1 | 1| 22694| 2default:defaulthp x  } %s *synth2e Q|20 |ngFEC_logic__GCB2 | 1| 22692| 2default:defaulthp x  } %s *synth2e Q|21 |ngFEC_logic__GCB3 | 1| 22692| 2default:defaulthp x  } %s *synth2e Q|22 |ngFEC_logic__GCB4 | 1| 25447| 2default:defaulthp x  } %s *synth2e Q|23 |ngFEC_logic__GCB5 | 1| 22692| 2default:defaulthp x  } %s *synth2e Q|24 |ngFEC_logic__GCB6 | 1| 22692| 2default:defaulthp x  } %s *synth2e Q|25 |ngFEC_logic__GCB7 | 1| 22692| 2default:defaulthp x  } %s *synth2e Q|26 |ngFEC_logic__GCB8 | 1| 22692| 2default:defaulthp x  } %s *synth2e Q|27 |ngCCM | 1| 22608| 2default:defaulthp x  } %s *synth2e Q|28 |ngCCM__xdcDup__11 | 1| 22608| 2default:defaulthp x  } %s *synth2e Q|29 |ngCCM__xdcDup__10 | 1| 22608| 2default:defaulthp x  } %s *synth2e Q|30 |ngFEC_logic__GCB12 | 1| 22692| 2default:defaulthp x  } %s *synth2e Q|31 |ngFEC_logic__GCB13 | 1| 170| 2default:defaulthp x  } %s *synth2e Q|32 |fc7_top__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Start RTL Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 723 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 24 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 13 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 24 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 24 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 186 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 24 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 14 2default:defaulthp x  Z %s *synth2B . 3 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 218 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 26 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 18 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 28 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 25 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 30 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 50 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 224 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 233 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 17 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 44 Bit XORs := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 40 Bit XORs := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 26841 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 5676 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 394 2default:defaulthp x  Z %s *synth2B . 10 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 4740 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 2779 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 1068 2default:defaulthp x  Z %s *synth2B . 12 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 9 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 19 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 17 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 11 Input 1 Bit XORs := 2 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 39 Bit Wide XORs := 1 2default:defaulthp x  Z %s *synth2B . 13 Bit Wide XORs := 1 2default:defaulthp x  Z %s *synth2B . 7 Bit Wide XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 336 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 12 2default:defaulthp x  Z %s *synth2B . 112 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 12 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 72 2default:defaulthp x  Z %s *synth2B . 48 Bit Registers := 5 2default:defaulthp x  Z %s *synth2B . 45 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 42 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 39 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 38 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 36 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 34 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 3076 2default:defaulthp x  Z %s *synth2B . 31 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 30 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 12 2default:defaulthp x  Z %s *synth2B . 24 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 144 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 49 2default:defaulthp x  Z %s *synth2B . 18 Bit Registers := 12 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 95 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 12 2default:defaulthp x  Z %s *synth2B . 14 Bit Registers := 7 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 24 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1108 2default:defaulthp x  Z %s *synth2B . 11 Bit Registers := 14 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 36 2default:defaulthp x  Z %s *synth2B . 9 Bit Registers := 11 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1077 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 330 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 40 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 66 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 726 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 597 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 204 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 9948 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 256K Bit RAMs := 1 2default:defaulthp x  Z %s *synth2B . 64K Bit RAMs := 4 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 13 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 336 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 128 Bit Muxes := 9 2default:defaulthp x  Z %s *synth2B . 4 Input 128 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 112 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 2 Input 60 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 2 Input 48 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 4 Input 48 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 44 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 2 Input 42 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 4540 2default:defaulthp x  Z %s *synth2B . 3 Input 32 Bit Muxes := 38 2default:defaulthp x  Z %s *synth2B . 6 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 193 2default:defaulthp x  Z %s *synth2B . 19 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 11 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 829 2default:defaulthp x  Z %s *synth2B . 44 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 252 2default:defaulthp x  Z %s *synth2B . 2 Input 31 Bit Muxes := 14 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 24 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 24 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 19 Input 24 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 96 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 4 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 15 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 3 Input 18 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 14 Input 18 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 343 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 14 2default:defaulthp x  Z %s *synth2B . 14 Input 16 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 11 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 16 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 18 Input 16 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 16 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 14 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 48 2default:defaulthp x  Z %s *synth2B . 4 Input 13 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 8 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 666 2default:defaulthp x  Z %s *synth2B . 7 Input 12 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 7 Input 11 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 44 2default:defaulthp x  Z %s *synth2B . 4 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 41 2default:defaulthp x  Z %s *synth2B . 8 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 3675 2default:defaulthp x  Z %s *synth2B . 17 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 14 2default:defaulthp x  Z %s *synth2B . 4 Input 8 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 13 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 170 2default:defaulthp x  Z %s *synth2B . 9 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 27 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 7 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 7 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 58 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 6 Input 6 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 6 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 17 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 36 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 42 2default:defaulthp x  Z %s *synth2B . 5 Input 5 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 156 2default:defaulthp x  Z %s *synth2B . 8 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 161 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 776 2default:defaulthp x  Z %s *synth2B . 5 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 4 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 16 Input 4 Bit Muxes := 48 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 156 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 157 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 5106 2default:defaulthp x  Z %s *synth2B . 17 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 3 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 182 2default:defaulthp x  Z %s *synth2B . 6 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 360 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 168 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 357 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 647 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 208 2default:defaulthp x  Z %s *synth2B . 17 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 6 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 348 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 10926 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 309 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit Muxes := 22 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 2286 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1224 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 869 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 961 2default:defaulthp x  Z %s *synth2B . 17 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 9 Input 1 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 11 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 12 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 13 Input 1 Bit Muxes := 9 2default:defaulthp x  Z %s *synth2B . 16 Input 1 Bit Muxes := 9 2default:defaulthp x  Z %s *synth2B . 19 Input 1 Bit Muxes := 16 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 1092 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Finished RTL Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Y %s *synth2A -Start RTL Hierarchical Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Hierarchical RTL Component report 2default:defaulthp x  @ %s *synth2( Module i2c_bitwise 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 9 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 9 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 8 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 8 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit Muxes := 13 2default:defaulthp x  = %s *synth2% Module i2c_ctrl 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 9 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 39 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 17 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 17 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 36 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 17 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 24 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 17 Input 1 Bit Muxes := 25 2default:defaulthp x  D %s *synth2, Module i2c_master_core 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  E %s *synth2- Module clocks_7s_serdes 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 1 2default:defaulthp x  C %s *synth2+ Module EthernetCRC__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 22 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 10 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 9 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 12 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 9 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 3 2default:defaulthp x  @ %s *synth2( Module EthernetCRC 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 22 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 10 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 9 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 12 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 9 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 3 2default:defaulthp x  > %s *synth2& Module soft_emac 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 11 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 6 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 19 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 3 2default:defaulthp x  E %s *synth2- Module eth_7s_1000basex 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  E %s *synth2- Module udp_ipaddr_block 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 42 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  C %s *synth2+ Module udp_rarp_block 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 24 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 2 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 336 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 42 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 24 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 336 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 42 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 24 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module udp_build_arp 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 48 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 48 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 6 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 5 2default:defaulthp x  F %s *synth2. Module udp_build_payload 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 6 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 20 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 14 Input 16 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 11 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 13 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 23 2default:defaulthp x  Z %s *synth2B . 9 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 11 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 12 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 13 Input 1 Bit Muxes := 9 2default:defaulthp x  C %s *synth2+ Module udp_build_ping 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 8 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 4 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 7 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 3 2default:defaulthp x  E %s *synth2- Module udp_build_resend 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 45 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module udp_build_status 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 9 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 128 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 9 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 3 2default:defaulthp x  F %s *synth2. Module udp_status_buffer 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 128 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 4 Input 128 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 2 2default:defaulthp x  D %s *synth2, Module udp_byte_sum__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 9 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 9 2default:defaulthp x  D %s *synth2, Module udp_do_rx_reset 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module udp_packet_parser 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 112 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 48 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 45 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 42 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 38 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 36 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 34 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 24 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 17 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 128 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 112 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 48 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 48 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 3 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 24 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 24 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 8 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 32 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  B %s *synth2* Module udp_rxram_mux 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 6 2default:defaulthp x  D %s *synth2, Module udp_DualPortRAM 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  H %s *synth20 Module udp_buffer_selector 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  C %s *synth2+ Module udp_rxram_shim 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module udp_DualPortRAM_rx 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 4 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 64K Bit RAMs := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  [ %s *synth2C /Module udp_buffer_selector__parameterized0__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module udp_DualPortRAM_tx 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 256K Bit RAMs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 8 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module udp_buffer_selector__parameterized0 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  A %s *synth2) Module udp_byte_sum 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 9 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 9 2default:defaulthp x  H %s *synth20 Module udp_rxtransactor_if 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  ? %s *synth2' Module udp_tx_mux 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 6 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 24 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 6 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 18 Input 16 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 10 2default:defaulthp x  Z %s *synth2B . 8 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 9 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 17 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 17 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 27 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 9 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 16 Input 1 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 17 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module udp_txtransactor_if 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 16 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 16 2default:defaulthp x  Z %s *synth2B . 16 Input 1 Bit Muxes := 1 2default:defaulthp x  J %s *synth22 Module udp_clock_crossing_if 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 10 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 5 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 7 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 5 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 8 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  ; %s *synth2# Module UDP_if 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  B %s *synth2* Module transactor_if 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 7 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 1 2default:defaulthp x  B %s *synth2* Module transactor_sm 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 3 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 5 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 6 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 1 2default:defaulthp x  C %s *synth2+ Module transactor_cfg 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 128 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  > %s *synth2& Module trans_arb 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 8 2default:defaulthp x  A %s *synth2) Module trans_buffer 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 9 2default:defaulthp x  B %s *synth2* Module spi_interface 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 30 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 10 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module uc_pipe_interface 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 9 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  B %s *synth2* Module ip_mac_select 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 48 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 48 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  E %s *synth2- Module ipbus_sys_fabric 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 19 2default:defaulthp x  Z %s *synth2B . 15 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 18 2default:defaulthp x  @ %s *synth2( Module system_regs 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 19 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 19 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 24 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 19 Input 24 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 19 Input 1 Bit Muxes := 16 2default:defaulthp x  H %s *synth20 Module flashIcap_ioControl 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  C %s *synth2+ Module icap_interface 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 9 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 6 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 11 2default:defaulthp x  G %s *synth2/ Module icap_interface_fsm 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 11 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 5 2default:defaulthp x  E %s *synth2- Module i2c_eep_autoread 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 31 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 24 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 22 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 44 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 31 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 24 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 23 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 24 2default:defaulthp x  ? %s *synth2' Module spi_master 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 13 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 8 Input 7 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 20 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 6 2default:defaulthp x  @ %s *synth2( Module system_core 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 7 Input 3 Bit Muxes := 1 2default:defaulthp x  @ %s *synth2( Module TTC_decoder 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 19 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 17 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 11 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 39 Bit Wide XORs := 1 2default:defaulthp x  Z %s *synth2B . 13 Bit Wide XORs := 1 2default:defaulthp x  Z %s *synth2B . 7 Bit Wide XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 39 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 13 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_syndrom__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 385 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 9 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 7 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_lmbddet__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  Y %s *synth2A -Module gbt_rx_decoder_gbtframe_errlcpoly__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 10 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 32 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 6 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 22 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_chnsrch__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 16 Input 4 Bit Muxes := 2 2default:defaulthp x  Y %s *synth2A -Module gbt_rx_decoder_gbtframe_rs2errcor__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 204 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 11 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 60 Bit Muxes := 1 2default:defaulthp x  U %s *synth2= )Module gbt_rx_decoder_gbtframe_rsdec__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 44 Bit Muxes := 1 2default:defaulthp x  T %s *synth2< (Module gbt_rx_decoder_gbtframe_syndrom 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 385 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 9 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 7 2default:defaulthp x  T %s *synth2< (Module gbt_rx_decoder_gbtframe_lmbddet 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  V %s *synth2> *Module gbt_rx_decoder_gbtframe_errlcpoly 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 10 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 32 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 6 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 22 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_rx_decoder_gbtframe_elpeval__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_rx_decoder_gbtframe_elpeval__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  T %s *synth2< (Module gbt_rx_decoder_gbtframe_elpeval 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 15 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  T %s *synth2< (Module gbt_rx_decoder_gbtframe_chnsrch 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 16 Input 4 Bit Muxes := 2 2default:defaulthp x  V %s *synth2> *Module gbt_rx_decoder_gbtframe_rs2errcor 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 204 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 11 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 60 Bit Muxes := 1 2default:defaulthp x  R %s *synth2: &Module gbt_rx_decoder_gbtframe_rsdec 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 44 Bit Muxes := 1 2default:defaulthp x  C %s *synth2+ Module gbt_rx_decoder 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 44 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 40 Bit XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  P %s *synth28 $Module gbt_rx_descrambler_21bit__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 2 2default:defaulthp x  P %s *synth28 $Module gbt_rx_descrambler_21bit__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 2 2default:defaulthp x  P %s *synth28 $Module gbt_rx_descrambler_21bit__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 2 2default:defaulthp x  M %s *synth25 !Module gbt_rx_descrambler_21bit 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 2 2default:defaulthp x  G %s *synth2/ Module gbt_rx_descrambler 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  C %s *synth2+ Module mgt__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 3 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 18 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 6 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 18 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 6 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  N %s *synth26 "Module gbt_tx_scrambler_21bit__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  Y %s *synth2A -Module xlx_k7v7_gbt_ngFEC_design__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 3 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module mgt__parameterized0 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 18 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 10 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 18 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 8 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 4 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  W %s *synth2? +Module gbt_tx_encoder_gbtframe_polydiv__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  ^ %s *synth2F 2Module xlx_k7v7_gbt_ngFEC_design__parameterized1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  G %s *synth2/ Module mgt_bitslipctrl__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  S %s *synth2; 'Module mgt_framealigner_pattsearch__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  8 %s *synth2 Module mgt 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 3 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 18 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 6 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 18 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module gbt_tx_scrambler__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_rx_gearbox__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  F %s *synth2. Module gbt_bank_reset__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  N %s *synth26 "Module xlx_k7v7_gbt_ngFEC_design 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 3 2default:defaulthp x  H %s *synth20 Module mgt_bitslipctrl__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  T %s *synth2< (Module mgt_framealigner_pattsearch__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module mgt_bitslipctrl__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  T %s *synth2< (Module mgt_framealigner_pattsearch__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module mgt_bitslipctrl__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  T %s *synth2< (Module mgt_framealigner_pattsearch__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  D %s *synth2, Module mgt_bitslipctrl 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  P %s *synth28 $Module mgt_framealigner_pattsearch 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module mgt__parameterized1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 4 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 18 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 20 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 3 Input 18 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 3 Input 4 Bit Muxes := 16 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 8 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module gbt_tx_scrambler__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module gbt_tx_scrambler__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module gbt_tx_scrambler__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  O %s *synth27 #Module gbt_tx_scrambler_21bit__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  K %s *synth23 Module gbt_tx_scrambler_21bit 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 21 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 21 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 21 Bit Muxes := 2 2default:defaulthp x  E %s *synth2- Module gbt_tx_scrambler 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module gbt_tx_encoder_gbtframe_polydiv__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  T %s *synth2< (Module gbt_tx_encoder_gbtframe_polydiv 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 44 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 260 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 34 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 92 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit XORs := 6 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  N %s *synth26 "Module gbt_tx_gearbox__xdcDup__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  O %s *synth27 #Module gbt_tx_gearbox__xdcDup__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  O %s *synth27 #Module gbt_tx_gearbox__xdcDup__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  C %s *synth2+ Module gbt_tx_gearbox 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 120 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_gearbox__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_gearbox__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_gearbox__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  C %s *synth2+ Module gbt_rx_gearbox 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 100 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 100 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module gbt_bank_reset__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  G %s *synth2/ Module gbt_bank_reset__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  G %s *synth2/ Module gbt_bank_reset__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  C %s *synth2+ Module gbt_bank_reset 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  ^ %s *synth2F 2Module xlx_k7v7_gbt_ngFEC_design__parameterized4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 4 2default:defaulthp x  J %s *synth22 Module buffer_ngccm_jtag_com 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 11 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 20 2default:defaulthp x  Z %s *synth2B . 3 Input 32 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 31 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 9 2default:defaulthp x  Z %s *synth2B . 7 Input 12 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 12 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 13 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module buffer_server_com 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  V %s *synth2> *Module buffer_server_com__parameterized3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  V %s *synth2> *Module buffer_server_com__parameterized5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  V %s *synth2> *Module buffer_server_com__parameterized7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  V %s *synth2> *Module buffer_server_com__parameterized9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  B %s *synth2* Module Module_RAM__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  C %s *synth2+ Module Module_RAM__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  V %s *synth2> *Module buffer_server_com__parameterized1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  C %s *synth2+ Module Module_RAM__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  H %s *synth20 Module buffer_ngccm_com__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  I %s *synth21 Module buffer_ngccm_com__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  C %s *synth2+ Module Module_RAM__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  C %s *synth2+ Module Module_RAM__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  C %s *synth2+ Module Module_RAM__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  W %s *synth2? +Module buffer_server_com__parameterized11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 3 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 4 2default:defaulthp x  ? %s *synth2' Module Module_RAM 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module buffer_ngccm_com__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  I %s *synth21 Module buffer_ngccm_com__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  I %s *synth21 Module buffer_ngccm_com__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  E %s *synth2- Module buffer_ngccm_com 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 8 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 28 2default:defaulthp x  Z %s *synth2B . 5 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 11 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 26 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 4 2default:defaulthp x  A %s *synth2) Module ngFEC_module 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 30 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 60 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 14 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 30 2default:defaulthp x  = %s *synth2% Module Sync__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__415 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module JTAGMaster__xdcDup__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  P %s *synth28 $Module LocalJTAGBridge__xdcDup__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__274 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__273 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__142 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__142 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__142 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__142 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__276 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__275 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__143 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__143 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__143 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__143 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__278 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__277 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__144 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__144 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__144 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__144 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__280 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__279 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__145 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__145 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__145 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__145 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__282 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__281 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__146 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__146 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__146 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__146 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__284 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__283 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__147 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__147 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__147 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__147 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__286 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__285 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__148 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__148 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__148 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__148 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__288 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__287 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__149 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__149 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__149 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__149 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__290 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__289 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__150 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__150 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__150 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__150 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__292 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__291 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__151 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__151 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__151 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__151 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__294 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__293 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__152 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__152 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__152 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__152 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__296 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__295 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__153 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__153 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__153 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__153 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__272 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__297 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__154 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__154 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__154 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__154 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__414 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__136 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__413 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__137 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__412 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__138 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__411 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__139 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__410 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__140 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__409 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__141 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__408 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__142 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__407 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__143 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__406 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__144 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__405 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__145 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__404 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__146 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__403 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__147 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__402 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__148 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__401 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__149 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__400 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__150 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  F %s *synth2. Module ngCCM__xdcDup__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__399 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module JTAGMaster__xdcDup__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  P %s *synth28 $Module LocalJTAGBridge__xdcDup__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__248 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__247 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__129 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__129 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__129 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__129 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__250 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__249 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__130 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__130 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__130 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__130 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__252 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__251 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__131 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__131 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__131 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__131 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__254 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__253 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__132 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__132 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__132 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__132 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__256 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__255 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__133 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__133 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__133 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__133 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__258 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__257 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__134 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__134 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__134 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__134 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__260 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__259 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__135 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__135 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__135 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__135 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__262 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__261 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__136 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__136 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__136 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__136 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__264 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__263 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__137 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__137 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__137 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__137 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__266 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__265 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__138 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__138 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__138 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__138 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__268 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__267 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__139 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__139 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__139 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__139 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__270 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__269 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__140 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__140 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__140 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__140 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__246 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__271 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__141 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__141 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__141 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__141 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__398 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__151 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__397 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__152 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__396 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__153 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__395 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__154 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__394 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__155 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__393 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__156 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__392 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__157 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__391 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__158 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__390 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__159 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__389 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__160 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__388 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__161 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__387 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__162 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__386 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__163 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__385 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__164 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__384 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__165 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  F %s *synth2. Module ngCCM__xdcDup__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__383 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  ? %s *synth2' Module JTAGMaster 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  D %s *synth2, Module LocalJTAGBridge 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__222 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__221 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__116 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__116 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__116 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__116 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__224 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__223 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__117 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__117 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__117 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__117 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__226 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__225 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__118 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__118 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__118 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__118 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__228 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__227 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__119 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__119 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__119 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__119 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__230 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__229 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__120 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__120 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__120 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__120 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__232 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__231 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__121 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__121 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__121 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__121 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__234 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__233 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__122 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__122 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__122 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__122 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__236 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__235 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__123 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__123 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__123 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__123 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__238 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__237 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__124 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__124 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__124 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__124 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__240 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__239 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__125 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__125 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__125 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__125 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__242 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__241 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__126 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__126 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__126 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__126 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__244 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__243 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__127 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__127 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__127 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__127 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__220 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__245 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__128 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__128 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__128 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__128 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__382 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__166 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__381 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__167 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__380 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__168 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__379 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__169 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__378 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__170 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__377 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__171 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__376 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__172 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__375 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__173 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__374 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__174 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__373 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__175 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__372 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__176 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__371 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__177 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__370 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__178 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__369 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__179 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__368 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  @ %s *synth2( Module IPbus_local 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  : %s *synth2" Module ngCCM 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  F %s *synth2. Module cdce_synchronizer 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 5 2default:defaulthp x  I %s *synth21 Module ipb_user_status_regs 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module ipb_user_control_regs 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 33 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 32 2default:defaulthp x  @ %s *synth2( Module ttc_counter 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 9 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  E %s *synth2- Module clkRateTool32__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  E %s *synth2- Module clkRateTool32__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  F %s *synth2. Module clkRateTool32__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  F %s *synth2. Module clkRateTool32__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  F %s *synth2. Module clkRateTool32__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  F %s *synth2. Module clkRateTool32__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  F %s *synth2. Module clkRateTool32__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  B %s *synth2* Module clkRateTool32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 12 2default:defaulthp x  B %s *synth2* Module global_mux__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module sfp_signal_mux__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module sfp_signal_mux__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module sfp_signal_mux__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module sfp_signal_mux__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module sfp_signal_mux__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module sfp_signal_mux__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  ? %s *synth2' Module global_mux 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module sfp_signal_mux__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  C %s *synth2+ Module sfp_signal_mux 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  E %s *synth2- Module delay_counter__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module delay_counter__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module delay_counter__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  B %s *synth2* Module delay_counter 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__70 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  C %s *synth2+ Module xpm_cdc_single 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__68 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__69 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__66 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__67 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__64 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__65 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__62 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__63 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__60 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__61 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__58 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__59 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__56 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__57 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__54 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__55 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  B %s *synth2* Module pm__xdcDup__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__52 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__53 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  C %s *synth2+ Module pm__xdcDup__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__50 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__51 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  C %s *synth2+ Module pm__xdcDup__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module xpm_cdc_single__49 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  7 %s *synth2 Module pm 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__216 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__217 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__218 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__219 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__220 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__221 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__222 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__223 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__224 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__225 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__226 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__227 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__228 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__229 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__230 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__231 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__232 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__233 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__234 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__235 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__236 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__237 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__238 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__239 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  = %s *synth2% Module Sync__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__255 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__254 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__106 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__253 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__107 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__252 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__108 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__251 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__109 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__250 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__110 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__249 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__111 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__248 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__112 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__247 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__113 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__246 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__114 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__245 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__115 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__244 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__116 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__243 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__117 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__242 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__118 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__241 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__119 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__240 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__120 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__271 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__50 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__49 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__52 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__51 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__54 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__53 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__56 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__55 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__58 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__57 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__60 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__59 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__62 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__61 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__63 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__270 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__91 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__269 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__92 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__268 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__93 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__267 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__94 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__266 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__95 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__265 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__96 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__264 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__97 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__263 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__98 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__262 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__99 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__261 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__100 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__260 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__101 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__259 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__102 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__258 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__103 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__257 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__104 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__256 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__105 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__287 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__66 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__65 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__68 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__67 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__70 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__69 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__72 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__71 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__74 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__73 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__76 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__75 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__78 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__77 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__80 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__79 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__82 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__81 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__84 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__83 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__86 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__85 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__88 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__87 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__49 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__49 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__49 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__49 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__64 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__89 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__50 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__50 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__50 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__50 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__286 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__76 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__285 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__77 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__284 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__78 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__283 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__79 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__282 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__80 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__281 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__81 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__280 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__82 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__279 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__83 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__278 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__84 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__277 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__85 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__276 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__86 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__275 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__87 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__274 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__88 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__273 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__89 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__272 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__90 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__303 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__92 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__91 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__51 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__51 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__51 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__51 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__94 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__93 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__52 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__52 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__52 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__52 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__96 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__95 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__53 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__53 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__53 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__53 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__98 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__97 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__54 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__54 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__54 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__54 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__100 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  F %s *synth2. Module glitch_filter__99 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__55 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__55 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__55 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__55 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__102 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__101 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__56 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__56 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__56 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__56 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__104 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__103 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__57 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__57 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__57 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__57 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__106 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__105 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__58 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__58 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__58 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__58 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__108 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__107 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__59 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__59 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__59 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__59 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__110 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__109 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__60 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__60 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__60 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__60 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__112 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__111 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__61 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__61 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__61 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__61 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__114 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__113 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__62 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__62 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__62 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__62 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  F %s *synth2. Module glitch_filter__90 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__115 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__63 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__63 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__63 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__63 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__302 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__61 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__301 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__62 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__300 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__63 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__299 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__64 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__298 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__65 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__297 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__66 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__296 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__67 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__295 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__68 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__294 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__69 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__293 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__70 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__292 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__71 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__291 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__72 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__290 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__73 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__289 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__74 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__288 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__75 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  M %s *synth25 !Module gc_pulse_synchronizer__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  G %s *synth2/ Module gc_extend_pulse__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  L %s *synth24 Module dmtd_with_deglitcher__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 14 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  J %s *synth22 Module gc_pulse_synchronizer 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_extend_pulse 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module dmtd_with_deglitcher 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 14 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  C %s *synth2+ Module gc_sync_ffs__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module gc_sync_ffs__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  @ %s *synth2( Module gc_sync_ffs 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  D %s *synth2, Module dmtd_phase_meas 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 3 Input 14 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 14 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 8 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 5 2default:defaulthp x  @ %s *synth2( Module clk_divide3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  = %s *synth2% Module Sync__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__319 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__118 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__117 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__64 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__64 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__64 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__64 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__120 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__119 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__65 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__65 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__65 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__65 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__122 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__121 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__66 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__66 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__66 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__66 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__124 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__123 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__67 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__67 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__67 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__67 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__126 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__125 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__68 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__68 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__68 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__68 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__128 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__127 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__69 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__69 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__69 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__69 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__130 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__129 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__70 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__70 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__70 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__70 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__132 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__131 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__71 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__71 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__71 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__71 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__134 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__133 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__72 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__72 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__72 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__72 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__136 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__135 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__73 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__73 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__73 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__73 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__138 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__137 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__74 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__74 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__74 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__74 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__140 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__139 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__75 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__75 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__75 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__75 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__116 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__141 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__76 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__76 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__76 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__76 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__318 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__317 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__47 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__316 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__48 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__315 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__49 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__314 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__50 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__313 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__51 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__312 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__52 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__311 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__53 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__310 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__54 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__309 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__55 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__308 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__56 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__307 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__57 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__306 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__58 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__305 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__59 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__304 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__60 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__335 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__144 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__143 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__77 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__77 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__77 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__77 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__146 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__145 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__78 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__78 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__78 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__78 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__148 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__147 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__79 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__79 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__79 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__79 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__150 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__149 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__80 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__80 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__80 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__80 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__152 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__151 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__81 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__81 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__81 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__81 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__154 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__153 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__82 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__82 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__82 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__82 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__156 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__155 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__83 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__83 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__83 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__83 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__158 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__157 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__84 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__84 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__84 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__84 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__160 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__159 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__85 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__85 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__85 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__85 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__162 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__161 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__86 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__86 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__86 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__86 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__164 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__163 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__87 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__87 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__87 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__87 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__166 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__165 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__88 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__88 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__88 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__88 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__142 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__167 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__89 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__89 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__89 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__89 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__334 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__333 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__332 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__331 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__330 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__329 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__36 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__328 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__37 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__327 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__38 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__326 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__39 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__325 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__40 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__324 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__41 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__323 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__42 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__322 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__43 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__321 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__44 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__320 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__31 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__32 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__351 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__170 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__169 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__90 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__90 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__90 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__90 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__172 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__171 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__91 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__91 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__91 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__91 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__174 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__173 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__92 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__92 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__92 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__92 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__176 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__175 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__93 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__93 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__93 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__93 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__178 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__177 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__94 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__94 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__94 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__94 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__180 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__179 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__95 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__95 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__95 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__95 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__182 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__181 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__96 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__96 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__96 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__96 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__184 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__183 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__97 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__97 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__97 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__97 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__186 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__185 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__98 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__98 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__98 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__98 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__188 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__187 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  L %s *synth24 Module i2c_master_bit_ctrl__99 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  M %s *synth25 !Module i2c_master_byte_ctrl__99 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  G %s *synth2/ Module i2c_master_usr__99 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module LocalI2CBridge__99 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__190 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__189 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__100 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__100 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__100 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__100 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__192 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__191 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__101 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__101 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__101 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__101 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__168 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__193 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__102 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__102 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__102 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__102 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__350 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__16 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__349 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__17 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__348 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__18 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__347 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__346 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__20 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__345 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__21 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__344 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__22 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__343 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__23 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__342 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__24 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__341 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__25 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__340 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__26 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__339 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__27 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__338 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__28 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__337 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__29 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__336 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__30 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__33 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__34 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__35 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module prbs__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  G %s *synth2/ Module gbt_rx_checker__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  I %s *synth21 Module Agnostic_Counter__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  F %s *synth2. Module CrossClock_RX__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  < %s *synth2$ Module RAM__19 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__367 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__196 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__195 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__103 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__103 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__103 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__103 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__198 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__197 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__104 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__104 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__104 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__104 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__200 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__199 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__105 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__105 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__105 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__105 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__202 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__201 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__106 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__106 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__106 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__106 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__204 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__203 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__107 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__107 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__107 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__107 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__206 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__205 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__108 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__108 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__108 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__108 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__208 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__207 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__109 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__109 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__109 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__109 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__210 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__209 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__110 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__110 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__110 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__110 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__212 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__211 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__111 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__111 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__111 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__111 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__214 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__213 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__112 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__112 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__112 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__112 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__216 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__215 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__113 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__113 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__113 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__113 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__218 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__217 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__114 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__114 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__114 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__114 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__194 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__219 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__115 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__115 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__115 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__115 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__366 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__365 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__2 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__364 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__3 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__363 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__4 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__362 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__5 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__361 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__6 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__360 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__7 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__359 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__8 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__358 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  K %s *synth23 Module IPbus_local__xdcDup__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__357 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__10 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__356 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__11 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__355 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__12 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__354 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__13 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__353 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__14 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__352 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  L %s *synth24 Module IPbus_local__xdcDup__15 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  = %s *synth2% Module Sync__45 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  = %s *synth2% Module Sync__46 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! Module Sync 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 2 2default:defaulthp x  9 %s *synth2! Module prbs 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  C %s *synth2+ Module gbt_rx_checker 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 5 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 20 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 19 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 18 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 17 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 14 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 12 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 11 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  E %s *synth2- Module Agnostic_Counter 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 26 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 26 Bit Muxes := 1 2default:defaulthp x  B %s *synth2* Module CrossClock_RX 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 Module RAM 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  Z %s *synth2B . 32K Bit RAMs := 1 2default:defaulthp x  S %s *synth2; 'Module xpm_cdc_single__parameterized1 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  J %s *synth22 Module JTAGMaster__xdcDup__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 15 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 14 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 7 Input 16 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 4 Input 15 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 7 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 12 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 15 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit Muxes := 12 2default:defaulthp x  O %s *synth27 #Module LocalJTAGBridge__xdcDup__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 7 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__300 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__299 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__155 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__155 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__155 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__155 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__302 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__301 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__156 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__156 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__156 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__156 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__304 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__303 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__157 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__157 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__157 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__157 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__306 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__305 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__158 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__158 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__158 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__158 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__308 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__307 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__159 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__159 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__159 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__159 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__310 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__309 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__160 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__160 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__160 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__160 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__312 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__311 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__161 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__161 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__161 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__161 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__314 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__313 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__162 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__162 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__162 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__162 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__316 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__315 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__163 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__163 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__163 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__163 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__318 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__317 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__164 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__164 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__164 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__164 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__320 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__319 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__165 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__165 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__165 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__165 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__322 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  G %s *synth2/ Module glitch_filter__321 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  M %s *synth25 !Module i2c_master_bit_ctrl__166 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  N %s *synth26 "Module i2c_master_byte_ctrl__166 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  H %s *synth20 Module i2c_master_usr__166 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  H %s *synth20 Module LocalI2CBridge__166 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  G %s *synth2/ Module glitch_filter__298 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  B %s *synth2* Module glitch_filter 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  H %s *synth20 Module i2c_master_bit_ctrl 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 15 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 32 Input 5 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 13 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit Muxes := 7 2default:defaulthp x  I %s *synth21 Module i2c_master_byte_ctrl 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 6 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 3 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 15 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 6 Input 1 Bit Muxes := 6 2default:defaulthp x  C %s *synth2+ Module i2c_master_usr 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 6 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 5 Input 32 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 5 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  C %s *synth2+ Module LocalI2CBridge 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__430 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__121 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__429 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__122 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__428 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__123 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__427 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__124 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__426 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__125 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__425 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__126 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__424 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__127 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__423 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__128 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__422 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__129 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__421 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__130 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__420 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__131 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__419 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__132 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__418 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__133 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__417 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__134 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  X %s *synth2@ ,Module xpm_cdc_single__parameterized1__416 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  M %s *synth25 !Module IPbus_local__xdcDup__135 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 5 2default:defaulthp x  E %s *synth2- Module ngCCM__xdcDup__9 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 8 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 15 2default:defaulthp x  Z %s *synth2B . 20 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 84 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 32 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 21 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 25 2default:defaulthp x  @ %s *synth2( Module ngFEC_logic 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Adders := 51 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 84 Bit Registers := 12 2default:defaulthp x  Z %s *synth2B . 32 Bit Registers := 49 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 42 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 16 Bit Muxes := 36 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  [ %s *synth2C /Finished RTL Hierarchical Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  H %s *synth20 Start Part Resource Summary 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2o [Part Resources: DSPs: 1680 (col length:160) BRAMs: 1670 (col length: RAMB18 160 RAMB36 80) 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Finished Part Resource Summary 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  W %s *synth2? +Start Cross Boundary and Area Optimization 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[2]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[3]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[4]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2, k7_master_xpoint_ctrl[5]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2' k7_pcie_clk_ctrl[2]2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2' k7_pcie_clk_ctrl[3]2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2" fmc_l12_pwr_en2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2! fmc_l8_pwr_en2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2 fmc_pg_c2m2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2 sysled1_g2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_spare[6]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_spare[7]2default:default2 12default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_spare[8]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_la_p[15]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2" fmc_l8_la_p[8]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l8_la_n[11]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2" fmc_l8_la_n[4]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2$ fmc_l12_la_p[31]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2$ fmc_l12_la_p[24]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2$ fmc_l12_la_p[15]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l12_la_p[8]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2$ fmc_l12_la_n[27]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2$ fmc_l12_la_n[20]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2$ fmc_l12_la_n[11]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 fc7_top2default:default2# fmc_l12_la_n[4]2default:default2 02default:defaultZ8-3917hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_25_reg[0]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_50_reg[1]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_25_reg[1]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_50_reg[2]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_25_reg[2]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_50_reg[3]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_50_reg[4]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_25_reg[3]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_50_reg[5]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_25_reg[4]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_50_reg[6]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_25_reg[5]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_50_reg[7]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_25_reg[6]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys25 !sys/i2c_m/core/u1/presc_50_reg[8]2default:default2 FDE2default:default25 !sys/i2c_m/core/u1/presc_25_reg[7]2default:defaultZ8-3886hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys22 mac/i_mac/i_rx_CRC32D8/bad_crc2default:default2 322default:default2 252default:defaultZ8-5545hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2# addr_to_set_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2# addr_to_set_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2$ send_special_int2default:defaultZ8-5587hpx  TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2$ send_special_int2default:defaultZ8-5587hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 clocks/timer2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 clocks/rst2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 p_0_out2default:default2 322default:default2 252default:defaultZ8-5545hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-33312default:default2 1002default:defaultZ17-14hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default2( internal_ram/ram_reg2default:defaultZ8-4652hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 82default:default2 ram_reg2default:defaultZ8-4652hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[0]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[1]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[2]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[3]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[4]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[5]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[6]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2< (ipb/udp_if/RARP_block/data_buffer_reg[7]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/RARP_block/we_buffer_reg[0]2default:default2 FDR2default:default2? +ipb/udp_if/RARP_block/rarp_end_addr_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__32default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__32default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__32default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__32default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__62default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__42default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__42default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__62default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__12default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__22default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__62default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__12default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__22default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__62default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__12default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__22default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__62default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__02default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__12default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__22default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__12default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__22default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__12default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__22default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]__02default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]__12default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__02default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__12default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__02default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]__02default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]__12default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__02default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]__02default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]__12default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2? +ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]2default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2C /ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]__02default:default2 FDSE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]__12default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2? +ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]2default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2C /ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]__02default:default2 FDSE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]__12default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2? +ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]2default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2? +ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]2default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2@ ,ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]2default:default2 FDSE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2@ ,ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]2default:default2 FDSE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]__32default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[0]2default:default2 FDRE2default:default2: &ipb/udp_if/status_buffer/header_reg[1]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[1]2default:default2 FDRE2default:default2: &ipb/udp_if/status_buffer/header_reg[2]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[2]2default:default2 FDRE2default:default2: &ipb/udp_if/status_buffer/header_reg[3]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[3]2default:default2 FDRE2default:default2; 'ipb/udp_if/status_buffer/header_reg[24]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[4]2default:default2 FDSE2default:default2: &ipb/udp_if/status_buffer/header_reg[5]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[5]2default:default2 FDSE2default:default2: &ipb/udp_if/status_buffer/header_reg[6]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[6]2default:default2 FDSE2default:default2: &ipb/udp_if/status_buffer/header_reg[7]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[7]2default:default2 FDSE2default:default2; 'ipb/udp_if/status_buffer/header_reg[29]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[8]2default:default2 FDSE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[0]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2: &ipb/udp_if/status_buffer/header_reg[9]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[1]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[10]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[2]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[11]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[3]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[12]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[4]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[13]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[5]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[14]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[6]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[15]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[7]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[16]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[8]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[17]2default:default2 FDRE2default:default2C /ipb/udp_if/status_buffer/next_pkt_id_int_reg[9]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[18]2default:default2 FDRE2default:default2D 0ipb/udp_if/status_buffer/next_pkt_id_int_reg[10]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[19]2default:default2 FDRE2default:default2D 0ipb/udp_if/status_buffer/next_pkt_id_int_reg[11]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[20]2default:default2 FDRE2default:default2D 0ipb/udp_if/status_buffer/next_pkt_id_int_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[21]2default:default2 FDRE2default:default2D 0ipb/udp_if/status_buffer/next_pkt_id_int_reg[13]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[22]2default:default2 FDRE2default:default2D 0ipb/udp_if/status_buffer/next_pkt_id_int_reg[14]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[23]2default:default2 FDRE2default:default2D 0ipb/udp_if/status_buffer/next_pkt_id_int_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[24]2default:default2 FDRE2default:default2; 'ipb/udp_if/status_buffer/header_reg[25]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[25]2default:default2 FDRE2default:default2; 'ipb/udp_if/status_buffer/header_reg[26]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[26]2default:default2 FDRE2default:default2; 'ipb/udp_if/status_buffer/header_reg[27]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[27]2default:default2 FDRE2default:default2; 'ipb/udp_if/status_buffer/header_reg[28]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[28]2default:default2 FDRE2default:default2; 'ipb/udp_if/status_buffer/header_reg[30]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2; 'ipb/udp_if/status_buffer/header_reg[30]2default:default2 FDRE2default:default2; 'ipb/udp_if/status_buffer/header_reg[31]2default:defaultZ8-3886hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[31] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[32] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[33] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[34] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[35] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[36] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[37] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[38] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[39] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[40] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[41] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[42] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[43] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[44] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[45] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[46] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[47] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[48] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[49] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[50] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[51] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[52] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[53] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[54] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[55] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[56] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[57] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[58] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[59] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[60] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[61] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[62] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[63] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[64] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[65] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[66] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[67] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[68] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[69] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[70] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[71] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[72] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[73] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[74] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[75] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[76] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[77] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[78] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[79] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[80] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[81] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[82] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[83] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[84] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[85] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[86] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[87] 2default:defaultZ8-3333hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[6]__52default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[0]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[7]__52default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[0]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[0]__52default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[4]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[1]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[2]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[2]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[3]__52default:defaultZ8-3886hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2D 0ipb/udp_if/rx_packet_parser/\pkt_data_reg[3]__5 2default:defaultZ8-3333hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[4]__52default:default2 FDSE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[5]__52default:defaultZ8-3886hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[88] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[89] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[90] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[91] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[92] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[93] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[94] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[95] 2default:defaultZ8-3333hpx  "merging instance '%s' (%s) to '%s'3436*oasys2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[14]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[8]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[15]__52default:default2 FDRE2default:default2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[8]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[8]__52default:default2 FDRE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[12]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2B .ipb/udp_if/rx_packet_parser/pkt_data_reg[9]__52default:default2 FDRE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[10]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[10]__52default:default2 FDRE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[11]__52default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[12]__52default:default2 FDRE2default:default2C /ipb/udp_if/rx_packet_parser/pkt_data_reg[13]__52default:defaultZ8-3886hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2= )ipb/udp_if/status_buffer/\header_reg[96] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[97] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[98] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2= )ipb/udp_if/status_buffer/\header_reg[99] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2> *ipb/udp_if/status_buffer/\header_reg[100] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2> *ipb/udp_if/status_buffer/\header_reg[101] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2> *ipb/udp_if/status_buffer/\header_reg[102] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2> *ipb/udp_if/status_buffer/\header_reg[103] 2default:defaultZ8-3333hpx  "merging instance '%s' (%s) to '%s'3436*oasys22 ipb/udp_if/RARP_block/y_reg[0]2default:default2 FD2default:default25 !ipb/udp_if/RARP_block/rndm_reg[0]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys22 ipb/udp_if/RARP_block/y_reg[1]2default:default2 FD2default:default25 !ipb/udp_if/RARP_block/rndm_reg[1]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys22 ipb/udp_if/RARP_block/y_reg[2]2default:default2 FD2default:default25 !ipb/udp_if/RARP_block/rndm_reg[2]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys22 ipb/udp_if/RARP_block/y_reg[3]2default:default2 FD2default:default25 !ipb/udp_if/RARP_block/rndm_reg[3]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys22 ipb/udp_if/RARP_block/y_reg[4]2default:default2 FD2default:default25 !ipb/udp_if/RARP_block/rndm_reg[4]2default:defaultZ8-3886hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-38862default:default2 1002default:defaultZ17-14hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-38862default:default2 1002default:defaultZ17-14hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2D 0ipb/udp_if/rx_packet_parser/\pkt_data_reg[3]__4 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[104] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[105] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[106] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[107] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[108] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[109] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[110] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[111] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[112] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[113] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[114] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[115] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[116] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[117] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[118] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[119] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 12default:default2: &ipb/udp_if/RARP_block/\req_end_reg[0] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2D 0ipb/udp_if/rx_packet_parser/\pkt_data_reg[5]__2 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default29 %ipb/udp_if/ARP/\arp_end_addr_reg[12] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2A -ipb/udp_if/RARP_block/\rarp_end_addr_reg[12] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[120] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[121] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[122] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[123] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2> *ipb/udp_if/status_buffer/\header_reg[124] 2default:defaultZ8-3333hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-33332default:default2 1002default:defaultZ17-14hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-33332default:default2 1002default:defaultZ17-14hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-33312default:default2 1002default:defaultZ17-14hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-38862default:default2 1002default:defaultZ17-14hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2+ FSM_onehot_state_reg[3]2default:default2% cdce_synchronizer2default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__82default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__82default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__82default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__72default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__72default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__72default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__62default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__62default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__62default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__52default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__52default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__52default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__42default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__42default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__42default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-55462default:default2 1002default:defaultZ17-14hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__32default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__32default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__32default:defaultZ8-3332hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-55462default:default2 1002default:defaultZ17-14hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-55442default:default2 1002default:defaultZ17-14hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__22default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__22default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__22default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-55442default:default2 1002default:defaultZ17-14hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__12default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__12default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__12default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2& ngccm_bkp_regs[31]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2& ngccm_bkp_regs[30]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2& ngccm_bkp_regs[29]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2& ngccm_bkp_regs[28]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2& ngccm_bkp_regs[27]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2& ngccm_bkp_regs[10]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2% ngccm_bkp_regs[9]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2 ngCCM2default:default2% ngccm_bkp_regs[8]2default:default2 02default:defaultZ8-3917hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2 ngCCM2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2 ngCCM2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2 ngCCM2default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2& ngccm_bkp_regs[31]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2& ngccm_bkp_regs[30]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2& ngccm_bkp_regs[29]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2& ngccm_bkp_regs[28]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2& ngccm_bkp_regs[27]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2& ngccm_bkp_regs[10]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2% ngccm_bkp_regs[9]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__112default:default2% ngccm_bkp_regs[8]2default:default2 02default:defaultZ8-3917hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2% ngCCM__xdcDup__112default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2% ngCCM__xdcDup__112default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2% ngCCM__xdcDup__112default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2& ngccm_bkp_regs[31]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2& ngccm_bkp_regs[30]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2& ngccm_bkp_regs[29]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2& ngccm_bkp_regs[28]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2& ngccm_bkp_regs[27]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2& ngccm_bkp_regs[10]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2% ngccm_bkp_regs[9]2default:default2 02default:defaultZ8-3917hpx  +design %s has port %s driven by constant %s3447*oasys2% ngCCM__xdcDup__102default:default2% ngccm_bkp_regs[8]2default:default2 02default:defaultZ8-3917hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2% ngCCM__xdcDup__102default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2% ngCCM__xdcDup__102default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2% ngCCM__xdcDup__102default:defaultZ8-3332hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 SleepCount2default:default2 322default:default2 252default:defaultZ8-5545hpx  RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26 "CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2 842default:default2 772default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v2default:default2 1022default:default8@Z8-3936hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 jtag_trst_o2default:default2 322default:default2 252default:defaultZ8-5545hpx  PSwapped enable and write-enable on %s RAM instances of RAM %s to conserve power 3784*oasys2 12default:default28 $JTAGMaster_inst/JTAG_BRAM/memory_reg2default:defaultZ8-4652hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2) jtag_bridge_tms_i_reg2default:default2$ ngCCM__xdcDup__92default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2* jtag_bridge_trst_i_reg2default:default2$ ngCCM__xdcDup__92default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys28 $ngccmPinsOutReg_reg[sec_sel_addr][3]2default:default2$ ngCCM__xdcDup__92default:defaultZ8-3332hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:05:28 ; elapsed = 00:05:32 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  2 %s *synth2  ROM: 2default:defaulthp x  l %s *synth2T @+------------+---------------+---------------+----------------+ 2default:defaulthp x  m %s *synth2U A|Module Name | RTL Object | Depth x Width | Implemented As | 2default:defaulthp x  l %s *synth2T @+------------+---------------+---------------+----------------+ 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A|JTAGMaster | stateTrans[0] | 32x4 | LUT | 2default:defaulthp x  m %s *synth2U A+------------+---------------+---------------+----------------+ 2default:defaulthp x  e %s *synth2M 9 Block RAM: Preliminary Mapping Report (see note below) 2default:defaulthp x   %s *synth2 +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 2default:defaulthp x   %s *synth2 +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ 2default:defaulthp x   %s *synth2 |udp_DualPortRAM: | ram_reg | 4 K x 8(NO_CHANGE) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram1_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram2_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram3_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram4_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_tx: | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ 2default:defaulthp x   %s *synth2 Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2> *sysi_1/ipb/udp_if/i_0/internal_ram/ram_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_1/ipbus_rx_ram/ram1_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_1/ipbus_rx_ram/ram1_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_2/ipbus_rx_ram/ram2_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_2/ipbus_rx_ram/ram2_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_3/ipbus_rx_ram/ram3_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_3/ipbus_rx_ram/ram3_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_4/ipbus_rx_ram/ram4_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2M 9sysi_1/ipb/udp_if/ipbus_rx_rami_4/ipbus_rx_ram/ram4_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_22default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_32default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_42default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_52default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_62default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_72default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2m YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2m YngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2m YngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_50/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_51/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_52/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_53/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_54/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_55/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_56/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_57/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2p \ngFECi_58/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q| |RTL Partition |Replication |Instances | 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q|1 |i2c_master_core | 1| 943| 2default:defaulthp x  } %s *synth2e Q|2 |system_core__GC0 | 1| 18862| 2default:defaulthp x  } %s *synth2e Q|3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| 2default:defaulthp x  } %s *synth2e Q|4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q|5 |TTC_decoder__GC0 | 1| 342| 2default:defaulthp x  } %s *synth2e Q|6 |gbt_rx | 12| 4084| 2default:defaulthp x  } %s *synth2e Q|7 |gbt_bank__xdcDup__1__GC0 | 1| 8304| 2default:defaulthp x  } %s *synth2e Q|8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 309| 2default:defaulthp x  } %s *synth2e Q|9 |gbt_bank__parameterized0__GC0 | 1| 5536| 2default:defaulthp x  } %s *synth2e Q|10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 206| 2default:defaulthp x  } %s *synth2e Q|11 |gbt_bank__GC0 | 1| 8304| 2default:defaulthp x  } %s *synth2e Q|12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 309| 2default:defaulthp x  } %s *synth2e Q|13 |gbt_bank__parameterized1__GC0 | 1| 11072| 2default:defaulthp x  } %s *synth2e Q|14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 412| 2default:defaulthp x  } %s *synth2e Q|15 |ngFEC_module__GBM0 | 12| 17290| 2default:defaulthp x  } %s *synth2e Q|16 |ngFEC_module__GBM1 | 12| 6039| 2default:defaulthp x  } %s *synth2e Q|17 |ngFEC_module__GBM2 | 12| 8082| 2default:defaulthp x  } %s *synth2e Q|18 |ngFEC_logic__GCB0 | 1| 18733| 2default:defaulthp x  } %s *synth2e Q|19 |ngFEC_logic__GCB1 | 1| 14322| 2default:defaulthp x  } %s *synth2e Q|20 |ngFEC_logic__GCB2 | 1| 14320| 2default:defaulthp x  } %s *synth2e Q|21 |ngFEC_logic__GCB3 | 1| 14320| 2default:defaulthp x  } %s *synth2e Q|22 |ngFEC_logic__GCB4 | 1| 15442| 2default:defaulthp x  } %s *synth2e Q|23 |ngFEC_logic__GCB5 | 1| 14320| 2default:defaulthp x  } %s *synth2e Q|24 |ngFEC_logic__GCB6 | 1| 14320| 2default:defaulthp x  } %s *synth2e Q|25 |ngFEC_logic__GCB7 | 1| 14320| 2default:defaulthp x  } %s *synth2e Q|26 |ngFEC_logic__GCB8 | 1| 14320| 2default:defaulthp x  } %s *synth2e Q|27 |ngCCM | 1| 14578| 2default:defaulthp x  } %s *synth2e Q|28 |ngCCM__xdcDup__11 | 1| 14578| 2default:defaulthp x  } %s *synth2e Q|29 |ngCCM__xdcDup__10 | 1| 14578| 2default:defaulthp x  } %s *synth2e Q|30 |ngFEC_logic__GCB12 | 1| 14320| 2default:defaulthp x  } %s *synth2e Q|31 |ngFEC_logic__GCB13 | 1| 170| 2default:defaulthp x  } %s *synth2e Q|32 |fc7_top__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  R %s *synth2: &Start Applying XDC Timing Constraints 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2W Cmgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out2default:default2b N{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2] Imgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out2default:default2h T{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2$ eth/phy/rxoutclk2default:default2- eth/phy/bbstub_rxoutclk/O2default:defaultZ8-5578hpx  2Moved timing constraint from pin '%s' to pin '%s' 4028*oasys2$ eth/phy/txoutclk2default:default2- eth/phy/bbstub_txoutclk/O2default:defaultZ8-5578hpx  SMoved %s constraints on hierarchical pins to their respective driving/loading pins 4235*oasys2 182default:defaultZ8-5819hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:05:46 ; elapsed = 00:05:51 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  F %s *synth2. Start Timing Optimization 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   ESequential element (%s) is unused and will be removed from module %s.3332*oasys2' ip_addr_reg[31]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2% ip_addr_reg[31]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2' ip_addr_reg[30]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2% ip_addr_reg[30]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2' ip_addr_reg[23]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2% ip_addr_reg[23]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2' ip_addr_reg[21]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2% ip_addr_reg[21]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2' ip_addr_reg[19]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2% ip_addr_reg[19]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& ip_addr_reg[6]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2$ ip_addr_reg[6]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& ip_addr_reg[4]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2$ ip_addr_reg[4]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[47]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[47]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[45]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[45]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[43]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[43]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[41]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[41]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[39]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[39]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[37]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[37]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[36]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[36]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[35]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[35]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[33]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[33]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[32]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[32]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[31]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[31]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[30]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[30]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[27]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[27]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[26]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[26]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[23]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[23]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[22]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[22]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[20]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[20]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[19]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[19]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[18]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[18]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[16]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[16]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[15]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[15]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[14]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[14]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[13]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[13]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[11]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2& mac_addr_reg[11]_C2default:default2! ip_mac_select2default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2( mac_addr_reg[10]_LDC2default:default2! ip_mac_select2default:defaultZ8-3332hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-33322default:default2 1002default:defaultZ17-14hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 ~Finished Timing Optimization : Time (s): cpu = 00:06:40 ; elapsed = 00:06:46 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  N %s *synth26 " Block RAM: Final Mapping Report 2default:defaulthp x   %s *synth2 +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 2default:defaulthp x   %s *synth2 +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ 2default:defaulthp x   %s *synth2 |udp_DualPortRAM: | ram_reg | 4 K x 8(NO_CHANGE) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram1_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram2_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram3_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_rx: | ram4_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | 2default:defaulthp x   %s *synth2 |udp_DualPortRAM_tx: | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | 2default:defaulthp x   %s *synth2 +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q| |RTL Partition |Replication |Instances | 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q|1 |i2c_master_core | 1| 943| 2default:defaulthp x  } %s *synth2e Q|2 |system_core__GC0 | 1| 18301| 2default:defaulthp x  } %s *synth2e Q|3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| 2default:defaulthp x  } %s *synth2e Q|4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q|5 |TTC_decoder__GC0 | 1| 340| 2default:defaulthp x  } %s *synth2e Q|6 |gbt_rx | 12| 3889| 2default:defaulthp x  } %s *synth2e Q|7 |gbt_bank__xdcDup__1__GC0 | 1| 8025| 2default:defaulthp x  } %s *synth2e Q|8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 309| 2default:defaulthp x  } %s *synth2e Q|9 |gbt_bank__parameterized0__GC0 | 1| 5350| 2default:defaulthp x  } %s *synth2e Q|10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 206| 2default:defaulthp x  } %s *synth2e Q|11 |gbt_bank__GC0 | 1| 8025| 2default:defaulthp x  } %s *synth2e Q|12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 309| 2default:defaulthp x  } %s *synth2e Q|13 |gbt_bank__parameterized1__GC0 | 1| 10700| 2default:defaulthp x  } %s *synth2e Q|14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 412| 2default:defaulthp x  } %s *synth2e Q|15 |ngFEC_module__GBM0 | 12| 17274| 2default:defaulthp x  } %s *synth2e Q|16 |ngFEC_module__GBM1 | 12| 6039| 2default:defaulthp x  } %s *synth2e Q|17 |ngFEC_module__GBM2 | 12| 8082| 2default:defaulthp x  } %s *synth2e Q|18 |ngFEC_logic__GCB0 | 1| 18175| 2default:defaulthp x  } %s *synth2e Q|19 |ngFEC_logic__GCB1 | 1| 14323| 2default:defaulthp x  } %s *synth2e Q|20 |ngFEC_logic__GCB2 | 1| 14321| 2default:defaulthp x  } %s *synth2e Q|21 |ngFEC_logic__GCB3 | 1| 14321| 2default:defaulthp x  } %s *synth2e Q|22 |ngFEC_logic__GCB4 | 1| 15443| 2default:defaulthp x  } %s *synth2e Q|23 |ngFEC_logic__GCB5 | 1| 14321| 2default:defaulthp x  } %s *synth2e Q|24 |ngFEC_logic__GCB6 | 1| 14321| 2default:defaulthp x  } %s *synth2e Q|25 |ngFEC_logic__GCB7 | 1| 14321| 2default:defaulthp x  } %s *synth2e Q|26 |ngFEC_logic__GCB8 | 1| 14321| 2default:defaulthp x  } %s *synth2e Q|27 |ngCCM | 1| 14219| 2default:defaulthp x  } %s *synth2e Q|28 |ngCCM__xdcDup__11 | 1| 14219| 2default:defaulthp x  } %s *synth2e Q|29 |ngCCM__xdcDup__10 | 1| 14219| 2default:defaulthp x  } %s *synth2e Q|30 |ngFEC_logic__GCB12 | 1| 14321| 2default:defaulthp x  } %s *synth2e Q|31 |ngFEC_logic__GCB13 | 1| 170| 2default:defaulthp x  } %s *synth2e Q|32 |fc7_top__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2- Start Technology Mapping 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2> *sysi_1/sys/ipb/udp_if/internal_ram/ram_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2A -sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_22default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_32default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_42default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_52default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_62default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2@ ,sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_72default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_50/ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_51/ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_52/ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_53/ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_54/ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_55/ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_56/ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_57/ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2i UngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2i UngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2i UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2r ^ngFECi_58/ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 }Finished Technology Mapping : Time (s): cpu = 00:07:47 ; elapsed = 00:07:53 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q| |RTL Partition |Replication |Instances | 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  } %s *synth2e Q|1 |i2c_master_core | 1| 517| 2default:defaulthp x  } %s *synth2e Q|2 |system_core__GC0 | 1| 10041| 2default:defaulthp x  } %s *synth2e Q|3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| 2default:defaulthp x  } %s *synth2e Q|4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q|5 |TTC_decoder__GC0 | 1| 156| 2default:defaulthp x  } %s *synth2e Q|6 |gbt_rx | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|7 |gbt_bank__xdcDup__1__GC0 | 1| 3912| 2default:defaulthp x  } %s *synth2e Q|8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 252| 2default:defaulthp x  } %s *synth2e Q|9 |gbt_bank__parameterized0__GC0 | 1| 2608| 2default:defaulthp x  } %s *synth2e Q|10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 168| 2default:defaulthp x  } %s *synth2e Q|11 |gbt_bank__GC0 | 1| 3912| 2default:defaulthp x  } %s *synth2e Q|12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 252| 2default:defaulthp x  } %s *synth2e Q|13 |gbt_bank__parameterized1__GC0 | 1| 5216| 2default:defaulthp x  } %s *synth2e Q|14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 336| 2default:defaulthp x  } %s *synth2e Q|15 |ngFEC_module__GBM0 | 12| 9330| 2default:defaulthp x  } %s *synth2e Q|16 |ngFEC_module__GBM1 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|17 |ngFEC_module__GBM2 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|18 |ngFEC_logic__GCB0 | 1| 10566| 2default:defaulthp x  } %s *synth2e Q|19 |ngFEC_logic__GCB1 | 1| 7930| 2default:defaulthp x  } %s *synth2e Q|20 |ngFEC_logic__GCB2 | 1| 7929| 2default:defaulthp x  } %s *synth2e Q|21 |ngFEC_logic__GCB3 | 1| 7929| 2default:defaulthp x  } %s *synth2e Q|22 |ngFEC_logic__GCB4 | 1| 8695| 2default:defaulthp x  } %s *synth2e Q|23 |ngFEC_logic__GCB5 | 1| 7929| 2default:defaulthp x  } %s *synth2e Q|24 |ngFEC_logic__GCB6 | 1| 7929| 2default:defaulthp x  } %s *synth2e Q|25 |ngFEC_logic__GCB7 | 1| 7929| 2default:defaulthp x  } %s *synth2e Q|26 |ngFEC_logic__GCB8 | 1| 7929| 2default:defaulthp x  } %s *synth2e Q|27 |ngCCM | 1| 7846| 2default:defaulthp x  } %s *synth2e Q|28 |ngCCM__xdcDup__11 | 1| 7846| 2default:defaulthp x  } %s *synth2e Q|29 |ngCCM__xdcDup__10 | 1| 7846| 2default:defaulthp x  } %s *synth2e Q|30 |ngFEC_logic__GCB12 | 1| 7929| 2default:defaulthp x  } %s *synth2e Q|31 |ngFEC_logic__GCB13 | 1| 170| 2default:defaulthp x  } %s *synth2e Q|32 |fc7_top__GC0 | 1| 3| 2default:defaulthp x  } %s *synth2e Q|33 |gbt_rx__4 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|34 |gbt_rx__5 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|35 |gbt_rx__6 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|36 |gbt_rx__7 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|37 |gbt_rx__8 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|38 |gbt_rx__9 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|39 |gbt_rx__10 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|40 |gbt_rx__11 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|41 |gbt_rx__12 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|42 |gbt_rx__13 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|43 |gbt_rx__14 | 1| 1502| 2default:defaulthp x  } %s *synth2e Q|44 |ngFEC_module__GBM1__1 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|45 |ngFEC_module__GBM2__1 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|46 |ngFEC_module__GBM1__2 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|47 |ngFEC_module__GBM2__2 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|48 |ngFEC_module__GBM1__3 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|49 |ngFEC_module__GBM2__3 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|50 |ngFEC_module__GBM1__4 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|51 |ngFEC_module__GBM2__4 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|52 |ngFEC_module__GBM1__5 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|53 |ngFEC_module__GBM2__5 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|54 |ngFEC_module__GBM1__6 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|55 |ngFEC_module__GBM2__6 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|56 |ngFEC_module__GBM1__7 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|57 |ngFEC_module__GBM2__7 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|58 |ngFEC_module__GBM1__8 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|59 |ngFEC_module__GBM2__8 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|60 |ngFEC_module__GBM1__9 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|61 |ngFEC_module__GBM2__9 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|62 |ngFEC_module__GBM1__10 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|63 |ngFEC_module__GBM2__10 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q|64 |ngFEC_module__GBM1__11 | 1| 3413| 2default:defaulthp x  } %s *synth2e Q|65 |ngFEC_module__GBM2__11 | 1| 4537| 2default:defaulthp x  } %s *synth2e Q+------+-----------------------------------------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ? %s *synth2' Start IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Q %s *synth29 %Start Flattening Before IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  T %s *synth2< (Finished Flattening Before IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  H %s *synth20 Start Final Netlist Cleanup 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys27 #sys/ipb/udp_if/internal_ram/ram_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2: &sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_02default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_12default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_22default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_32default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_42default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_52default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_62default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys29 %sys/ipb/udp_if/ipbus_tx_ram/ram_reg_72default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2i UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2i UngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2i UngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  The timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. 4693*oasys2h TngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2 Block2default:defaultZ8-6837hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[1].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[1].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[2].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[2].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[3].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[3].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[4].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[4].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[5].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[5].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[6].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[6].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[7].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[7].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2a MngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]2default:default2e QngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2T @ngFEC/SFP_GEN[8].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]2default:default2X DngFEC/SFP_GEN[8].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  ,Flop %s is being inverted and renamed to %s.3906*oasys2` LngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]2default:default2d PngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv2default:defaultZ8-5365hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-53652default:default2 1002default:defaultZ17-14hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Finished Final Netlist Cleanup 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 832default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 832default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 832default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 832default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 832default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 832default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1732default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1802default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 1222default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2 772default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2 1282default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 CLKBWRCLK2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2 642default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 CLKBWRCLK2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2 642default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 CLKBWRCLK2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2 682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 CLKBWRCLK2default:default2 D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2 682default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 552default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1352default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1352default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1352default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 562default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1332default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1472default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 1362default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 672default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2542default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2592default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  oClock pin %s has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net 3943*oasys2 C2default:default2{ eD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd2default:default2 2692default:default8@Z8-5396hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-53962default:default2 1002default:defaultZ17-14hpx  4design has %s instantiated BUFGs while the %s is %s 3703*oasys2 232default:default2; 'limit set by the -bufg synthesis option2default:default2 122default:defaultZ8-4560hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 wFinished IO Insertion : Time (s): cpu = 00:08:42 ; elapsed = 00:08:52 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  D %s *synth2,  Report Check Netlist: 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I| |Item |Errors |Warnings |Status |Description | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Start Renaming Generated Instances 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Instances : Time (s): cpu = 00:08:45 ; elapsed = 00:08:55 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? +| |RTL Partition |Replication |Instances | 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Start Rebuilding User Hierarchy 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:52 ; elapsed = 00:10:02 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Start Renaming Generated Ports 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Ports : Time (s): cpu = 00:09:55 ; elapsed = 00:10:04 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  M %s *synth25 !Start Handling Custom Attributes 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Handling Custom Attributes : Time (s): cpu = 00:10:02 ; elapsed = 00:10:12 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  J %s *synth22 Start Renaming Generated Nets 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Nets : Time (s): cpu = 00:10:04 ; elapsed = 00:10:13 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23  Static Shift Register Report: 2default:defaulthp x   %s *synth2 +------------+------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | 2default:defaulthp x   %s *synth2 +------------+------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 3 | NO | NO | YES | 3 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 2 | NO | NO | YES | 2 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 3 | NO | NO | YES | 3 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 4 | NO | NO | YES | 4 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4] | 3 | 12 | NO | NO | YES | 12 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/clkRate0/counting_reg | 3 | 1 | NO | NO | YES | 1 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/clkRate1/counting_reg | 3 | 1 | NO | NO | YES | 1 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/clkRate2/counting_reg | 3 | 1 | NO | NO | YES | 1 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/clk_rate_gen[1].clkRate3/counting_reg | 3 | 12 | NO | NO | YES | 12 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | ngFEC/update_toggle_Sync_Regs_reg[2] | 3 | 1 | NO | NO | YES | 1 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/IPADDR/pkt_mask_reg[41] | 22 | 1 | YES | NO | YES | 0 | 1 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[27] | 6 | 3 | YES | NO | YES | 3 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[17] | 4 | 2 | YES | NO | YES | 2 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[35] | 23 | 2 | YES | NO | YES | 0 | 2 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[41]__0 | 12 | 2 | YES | NO | YES | 2 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[15]__4 | 10 | 4 | YES | NO | YES | 4 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/resend/pkt_mask_reg[44] | 31 | 1 | YES | NO | YES | 0 | 1 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[19]__3 | 8 | 1 | YES | NO | YES | 1 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[79] | 6 | 6 | YES | NO | YES | 6 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[67] | 5 | 4 | YES | NO | YES | 4 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[111]__0 | 10 | 5 | YES | NO | YES | 5 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[90]__0 | 4 | 4 | YES | NO | YES | 4 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[119]__0 | 9 | 1 | YES | NO | YES | 1 | 0 | 2default:defaulthp x   %s *synth2 |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[109]__1 | 8 | 2 | YES | NO | YES | 2 | 0 | 2default:defaulthp x   %s *synth2 +------------+------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Start Writing Synthesis Report 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  A %s *synth2)  Report BlackBoxes: 2default:defaulthp x  [ %s *synth2C /+------+--------------------------+----------+ 2default:defaulthp x  [ %s *synth2C /| |BlackBox name |Instances | 2default:defaulthp x  [ %s *synth2C /+------+--------------------------+----------+ 2default:defaulthp x  [ %s *synth2C /|1 |ngFEC_mgt | 12| 2default:defaulthp x  [ %s *synth2C /|2 |gig_ethernet_pcs_pma_16_1 | 1| 2default:defaulthp x  [ %s *synth2C /|3 |sdpram_16x10_32x9 | 2| 2default:defaulthp x  [ %s *synth2C /|4 |sdpram_32x9_16x10 | 2| 2default:defaulthp x  [ %s *synth2C /+------+--------------------------+----------+ 2default:defaulthp x  A %s *synth2)  Report Cell Usage: 2default:defaulthp x  _ %s *synth2G 3+------+----------------------------------+------+ 2default:defaulthp x  _ %s *synth2G 3| |Cell |Count | 2default:defaulthp x  _ %s *synth2G 3+------+----------------------------------+------+ 2default:defaulthp x  _ %s *synth2G 3|1 |gig_ethernet_pcs_pma_16_1_bbox_10 | 1| 2default:defaulthp x  _ %s *synth2G 3|2 |ngFEC_mgt_bbox_15 | 1| 2default:defaulthp x  _ %s *synth2G 3|3 |ngFEC_mgt_bbox_15__2 | 1| 2default:defaulthp x  _ %s *synth2G 3|4 |ngFEC_mgt_bbox_16 | 1| 2default:defaulthp x  _ %s *synth2G 3|5 |ngFEC_mgt_bbox_16__2 | 1| 2default:defaulthp x  _ %s *synth2G 3|6 |ngFEC_mgt_bbox_17 | 1| 2default:defaulthp x  _ %s *synth2G 3|7 |ngFEC_mgt_bbox_17__2 | 1| 2default:defaulthp x  _ %s *synth2G 3|8 |ngFEC_mgt_bbox_18 | 1| 2default:defaulthp x  _ %s *synth2G 3|9 |ngFEC_mgt_bbox_19 | 1| 2default:defaulthp x  _ %s *synth2G 3|10 |ngFEC_mgt_bbox_20 | 1| 2default:defaulthp x  _ %s *synth2G 3|11 |ngFEC_mgt_bbox_21 | 1| 2default:defaulthp x  _ %s *synth2G 3|12 |ngFEC_mgt_bbox_22 | 1| 2default:defaulthp x  _ %s *synth2G 3|13 |ngFEC_mgt_bbox_23 | 1| 2default:defaulthp x  _ %s *synth2G 3|14 |sdpram_16x10_32x9_bbox_11 | 1| 2default:defaulthp x  _ %s *synth2G 3|15 |sdpram_16x10_32x9_bbox_13 | 1| 2default:defaulthp x  _ %s *synth2G 3|16 |sdpram_32x9_16x10_bbox_12 | 1| 2default:defaulthp x  _ %s *synth2G 3|17 |sdpram_32x9_16x10_bbox_14 | 1| 2default:defaulthp x  _ %s *synth2G 3|18 |BUFG | 22| 2default:defaulthp x  _ %s *synth2G 3|19 |BUFGMUX | 1| 2default:defaulthp x  _ %s *synth2G 3|20 |BUFH | 14| 2default:defaulthp x  _ %s *synth2G 3|21 |CARRY4 | 12978| 2default:defaulthp x  _ %s *synth2G 3|22 |IBUFDS_GTE2 | 4| 2default:defaulthp x  _ %s *synth2G 3|23 |ICAPE2 | 1| 2default:defaulthp x  _ %s *synth2G 3|24 |IDDR | 1| 2default:defaulthp x  _ %s *synth2G 3|25 |LUT1 | 9036| 2default:defaulthp x  _ %s *synth2G 3|26 |LUT2 | 28488| 2default:defaulthp x  _ %s *synth2G 3|27 |LUT3 | 40109| 2default:defaulthp x  _ %s *synth2G 3|28 |LUT4 | 25284| 2default:defaulthp x  _ %s *synth2G 3|29 |LUT5 | 33226| 2default:defaulthp x  _ %s *synth2G 3|30 |LUT6 | 60573| 2default:defaulthp x  _ %s *synth2G 3|31 |MMCME2_ADV | 3| 2default:defaulthp x  _ %s *synth2G 3|32 |MUXF7 | 1760| 2default:defaulthp x  _ %s *synth2G 3|33 |MUXF8 | 515| 2default:defaulthp x  _ %s *synth2G 3|34 |ODDR | 1| 2default:defaulthp x  _ %s *synth2G 3|35 |PLLE2_BASE | 1| 2default:defaulthp x  _ %s *synth2G 3|36 |RAMB36E1 | 1| 2default:defaulthp x  _ %s *synth2G 3|37 |RAMB36E1_1 | 16| 2default:defaulthp x  _ %s *synth2G 3|38 |RAMB36E1_2 | 180| 2default:defaulthp x  _ %s *synth2G 3|39 |RAMB36E1_3 | 360| 2default:defaulthp x  _ %s *synth2G 3|40 |RAMB36E1_4 | 12| 2default:defaulthp x  _ %s *synth2G 3|41 |SRL16 | 2| 2default:defaulthp x  _ %s *synth2G 3|42 |SRL16E | 85| 2default:defaulthp x  _ %s *synth2G 3|43 |SRLC32E | 7| 2default:defaulthp x  _ %s *synth2G 3|44 |FDCE | 54897| 2default:defaulthp x  _ %s *synth2G 3|45 |FDPE | 3990| 2default:defaulthp x  _ %s *synth2G 3|46 |FDRE | 85529| 2default:defaulthp x  _ %s *synth2G 3|47 |FDSE | 1230| 2default:defaulthp x  _ %s *synth2G 3|48 |LD | 72| 2default:defaulthp x  _ %s *synth2G 3|49 |LDC | 1| 2default:defaulthp x  _ %s *synth2G 3|50 |IBUF | 85| 2default:defaulthp x  _ %s *synth2G 3|51 |IBUFDS | 1| 2default:defaulthp x  _ %s *synth2G 3|52 |IBUFGDS | 1| 2default:defaulthp x  _ %s *synth2G 3|53 |IOBUF | 42| 2default:defaulthp x  _ %s *synth2G 3|54 |OBUF | 106| 2default:defaulthp x  _ %s *synth2G 3|55 |OBUFDS | 1| 2default:defaulthp x  _ %s *synth2G 3+------+----------------------------------+------+ 2default:defaulthp x  E %s *synth2-  Report Instance Areas: 2default:defaulthp x   %s *synth2 +------+-----------------------------------------------------------------+---------------------------------------------+-------+ 2default:defaulthp x   %s *synth2 | |Instance |Module |Cells | 2default:defaulthp x   %s *synth2 +------+-----------------------------------------------------------------+---------------------------------------------+-------+ 2default:defaulthp x   %s *synth2 |1 |top | | 359677| 2default:defaulthp x   %s *synth2 |2 | ngFEC |ngFEC_logic | 331395| 2default:defaulthp x   %s *synth2 |3 | \g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__216 | 4| 2default:defaulthp x   %s *synth2 |4 | \g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__217 | 4| 2default:defaulthp x   %s *synth2 |5 | \g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__218 | 4| 2default:defaulthp x   %s *synth2 |6 | \g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__219 | 4| 2default:defaulthp x   %s *synth2 |7 | \g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__220 | 4| 2default:defaulthp x   %s *synth2 |8 | \g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__221 | 4| 2default:defaulthp x   %s *synth2 |9 | \g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__222 | 4| 2default:defaulthp x   %s *synth2 |10 | \g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__223 | 4| 2default:defaulthp x   %s *synth2 |11 | \g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__224 | 4| 2default:defaulthp x   %s *synth2 |12 | \g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__225 | 4| 2default:defaulthp x   %s *synth2 |13 | \g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__226 | 4| 2default:defaulthp x   %s *synth2 |14 | \g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__227 | 4| 2default:defaulthp x   %s *synth2 |15 | \g_tx_ready_cnt[0].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__228 | 4| 2default:defaulthp x   %s *synth2 |16 | \g_tx_ready_cnt[1].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__229 | 4| 2default:defaulthp x   %s *synth2 |17 | \g_tx_ready_cnt[2].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__230 | 4| 2default:defaulthp x   %s *synth2 |18 | \g_tx_ready_cnt[3].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__231 | 4| 2default:defaulthp x   %s *synth2 |19 | \g_tx_ready_cnt[4].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__232 | 4| 2default:defaulthp x   %s *synth2 |20 | \g_tx_ready_cnt[5].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__233 | 4| 2default:defaulthp x   %s *synth2 |21 | \g_tx_ready_cnt[6].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__234 | 4| 2default:defaulthp x   %s *synth2 |22 | \g_tx_ready_cnt[7].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__235 | 4| 2default:defaulthp x   %s *synth2 |23 | \g_tx_ready_cnt[8].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__236 | 4| 2default:defaulthp x   %s *synth2 |24 | \g_tx_ready_cnt[9].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__237 | 4| 2default:defaulthp x   %s *synth2 |25 | \g_tx_ready_cnt[10].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__238 | 4| 2default:defaulthp x   %s *synth2 |26 | \g_tx_ready_cnt[11].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__239 | 4| 2default:defaulthp x   %s *synth2 |27 | DTC |DTC_top | 161| 2default:defaulthp x   %s *synth2 |28 | Inst_TTC_decoder |TTC_decoder | 161| 2default:defaulthp x   %s *synth2 |29 | DTC_Counter |ttc_counter | 814| 2default:defaulthp x   %s *synth2 |30 | \SFP_GEN[10].QIE_RESET_DELAY |delay_counter | 40| 2default:defaulthp x   %s *synth2 |31 | \SFP_GEN[10].ngCCM_gbt |ngCCM__xdcDup__10 | 8160| 2default:defaulthp x   %s *synth2 |32 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__136 | 104| 2default:defaulthp x   %s *synth2 |33 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__414 | 4| 2default:defaulthp x   %s *synth2 |34 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__137 | 104| 2default:defaulthp x   %s *synth2 |35 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__413 | 4| 2default:defaulthp x   %s *synth2 |36 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__138 | 104| 2default:defaulthp x   %s *synth2 |37 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__412 | 4| 2default:defaulthp x   %s *synth2 |38 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__139 | 104| 2default:defaulthp x   %s *synth2 |39 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__411 | 4| 2default:defaulthp x   %s *synth2 |40 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__140 | 104| 2default:defaulthp x   %s *synth2 |41 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__410 | 4| 2default:defaulthp x   %s *synth2 |42 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__141 | 104| 2default:defaulthp x   %s *synth2 |43 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__409 | 4| 2default:defaulthp x   %s *synth2 |44 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__142 | 104| 2default:defaulthp x   %s *synth2 |45 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__408 | 4| 2default:defaulthp x   %s *synth2 |46 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__143 | 104| 2default:defaulthp x   %s *synth2 |47 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__407 | 4| 2default:defaulthp x   %s *synth2 |48 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__144 | 104| 2default:defaulthp x   %s *synth2 |49 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__406 | 4| 2default:defaulthp x   %s *synth2 |50 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__145 | 104| 2default:defaulthp x   %s *synth2 |51 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__405 | 4| 2default:defaulthp x   %s *synth2 |52 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__146 | 104| 2default:defaulthp x   %s *synth2 |53 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__404 | 4| 2default:defaulthp x   %s *synth2 |54 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__147 | 104| 2default:defaulthp x   %s *synth2 |55 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__403 | 4| 2default:defaulthp x   %s *synth2 |56 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__148 | 104| 2default:defaulthp x   %s *synth2 |57 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__402 | 4| 2default:defaulthp x   %s *synth2 |58 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__149 | 104| 2default:defaulthp x   %s *synth2 |59 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__401 | 4| 2default:defaulthp x   %s *synth2 |60 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__150 | 104| 2default:defaulthp x   %s *synth2 |61 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__400 | 4| 2default:defaulthp x   %s *synth2 |62 | CrossClock_DV_cnt |CrossClock_RX_2247 | 41| 2default:defaulthp x   %s *synth2 |63 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__10 | 566| 2default:defaulthp x   %s *synth2 |64 | JTAGMaster_inst |JTAGMaster__xdcDup__10 | 417| 2default:defaulthp x   %s *synth2 |65 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__415 | 4| 2default:defaulthp x   %s *synth2 |66 | JTAG_BRAM |RAM_2331 | 85| 2default:defaulthp x   %s *synth2 |67 | Sync_RX_Reset |Sync_2248 | 2| 2default:defaulthp x   %s *synth2 |68 | Sync_TX_Reset |Sync_2249 | 45| 2default:defaulthp x   %s *synth2 |69 | Sync_error_counter_reset |Sync_2250 | 3| 2default:defaulthp x   %s *synth2 |70 | gbt_rx_checker |gbt_rx_checker_2251 | 104| 2default:defaulthp x   %s *synth2 |71 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_2252 | 309| 2default:defaulthp x   %s *synth2 |72 | i2c_master |i2c_master_usr_2326 | 309| 2default:defaulthp x   %s *synth2 |73 | byte_ctrl |i2c_master_byte_ctrl_2327 | 256| 2default:defaulthp x   %s *synth2 |74 | bit_ctrl |i2c_master_bit_ctrl_2328 | 207| 2default:defaulthp x   %s *synth2 |75 | \bus_status_ctrl.gf_scl |glitch_filter_2329 | 18| 2default:defaulthp x   %s *synth2 |76 | \bus_status_ctrl.gf_sda |glitch_filter_2330 | 20| 2default:defaulthp x   %s *synth2 |77 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_2253 | 309| 2default:defaulthp x   %s *synth2 |78 | i2c_master |i2c_master_usr_2321 | 309| 2default:defaulthp x   %s *synth2 |79 | byte_ctrl |i2c_master_byte_ctrl_2322 | 256| 2default:defaulthp x   %s *synth2 |80 | bit_ctrl |i2c_master_bit_ctrl_2323 | 207| 2default:defaulthp x   %s *synth2 |81 | \bus_status_ctrl.gf_scl |glitch_filter_2324 | 18| 2default:defaulthp x   %s *synth2 |82 | \bus_status_ctrl.gf_sda |glitch_filter_2325 | 20| 2default:defaulthp x   %s *synth2 |83 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_2254 | 309| 2default:defaulthp x   %s *synth2 |84 | i2c_master |i2c_master_usr_2316 | 309| 2default:defaulthp x   %s *synth2 |85 | byte_ctrl |i2c_master_byte_ctrl_2317 | 256| 2default:defaulthp x   %s *synth2 |86 | bit_ctrl |i2c_master_bit_ctrl_2318 | 207| 2default:defaulthp x   %s *synth2 |87 | \bus_status_ctrl.gf_scl |glitch_filter_2319 | 18| 2default:defaulthp x   %s *synth2 |88 | \bus_status_ctrl.gf_sda |glitch_filter_2320 | 20| 2default:defaulthp x   %s *synth2 |89 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_2255 | 309| 2default:defaulthp x   %s *synth2 |90 | i2c_master |i2c_master_usr_2311 | 309| 2default:defaulthp x   %s *synth2 |91 | byte_ctrl |i2c_master_byte_ctrl_2312 | 256| 2default:defaulthp x   %s *synth2 |92 | bit_ctrl |i2c_master_bit_ctrl_2313 | 207| 2default:defaulthp x   %s *synth2 |93 | \bus_status_ctrl.gf_scl |glitch_filter_2314 | 18| 2default:defaulthp x   %s *synth2 |94 | \bus_status_ctrl.gf_sda |glitch_filter_2315 | 20| 2default:defaulthp x   %s *synth2 |95 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_2256 | 309| 2default:defaulthp x   %s *synth2 |96 | i2c_master |i2c_master_usr_2306 | 309| 2default:defaulthp x   %s *synth2 |97 | byte_ctrl |i2c_master_byte_ctrl_2307 | 256| 2default:defaulthp x   %s *synth2 |98 | bit_ctrl |i2c_master_bit_ctrl_2308 | 207| 2default:defaulthp x   %s *synth2 |99 | \bus_status_ctrl.gf_scl |glitch_filter_2309 | 18| 2default:defaulthp x   %s *synth2 |100 | \bus_status_ctrl.gf_sda |glitch_filter_2310 | 20| 2default:defaulthp x   %s *synth2 |101 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_2257 | 309| 2default:defaulthp x   %s *synth2 |102 | i2c_master |i2c_master_usr_2301 | 309| 2default:defaulthp x   %s *synth2 |103 | byte_ctrl |i2c_master_byte_ctrl_2302 | 256| 2default:defaulthp x   %s *synth2 |104 | bit_ctrl |i2c_master_bit_ctrl_2303 | 207| 2default:defaulthp x   %s *synth2 |105 | \bus_status_ctrl.gf_scl |glitch_filter_2304 | 18| 2default:defaulthp x   %s *synth2 |106 | \bus_status_ctrl.gf_sda |glitch_filter_2305 | 20| 2default:defaulthp x   %s *synth2 |107 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_2258 | 309| 2default:defaulthp x   %s *synth2 |108 | i2c_master |i2c_master_usr_2296 | 309| 2default:defaulthp x   %s *synth2 |109 | byte_ctrl |i2c_master_byte_ctrl_2297 | 256| 2default:defaulthp x   %s *synth2 |110 | bit_ctrl |i2c_master_bit_ctrl_2298 | 207| 2default:defaulthp x   %s *synth2 |111 | \bus_status_ctrl.gf_scl |glitch_filter_2299 | 18| 2default:defaulthp x   %s *synth2 |112 | \bus_status_ctrl.gf_sda |glitch_filter_2300 | 20| 2default:defaulthp x   %s *synth2 |113 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_2259 | 309| 2default:defaulthp x   %s *synth2 |114 | i2c_master |i2c_master_usr_2291 | 309| 2default:defaulthp x   %s *synth2 |115 | byte_ctrl |i2c_master_byte_ctrl_2292 | 256| 2default:defaulthp x   %s *synth2 |116 | bit_ctrl |i2c_master_bit_ctrl_2293 | 207| 2default:defaulthp x   %s *synth2 |117 | \bus_status_ctrl.gf_scl |glitch_filter_2294 | 18| 2default:defaulthp x   %s *synth2 |118 | \bus_status_ctrl.gf_sda |glitch_filter_2295 | 20| 2default:defaulthp x   %s *synth2 |119 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_2260 | 309| 2default:defaulthp x   %s *synth2 |120 | i2c_master |i2c_master_usr_2286 | 309| 2default:defaulthp x   %s *synth2 |121 | byte_ctrl |i2c_master_byte_ctrl_2287 | 256| 2default:defaulthp x   %s *synth2 |122 | bit_ctrl |i2c_master_bit_ctrl_2288 | 207| 2default:defaulthp x   %s *synth2 |123 | \bus_status_ctrl.gf_scl |glitch_filter_2289 | 18| 2default:defaulthp x   %s *synth2 |124 | \bus_status_ctrl.gf_sda |glitch_filter_2290 | 20| 2default:defaulthp x   %s *synth2 |125 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_2261 | 309| 2default:defaulthp x   %s *synth2 |126 | i2c_master |i2c_master_usr_2281 | 309| 2default:defaulthp x   %s *synth2 |127 | byte_ctrl |i2c_master_byte_ctrl_2282 | 256| 2default:defaulthp x   %s *synth2 |128 | bit_ctrl |i2c_master_bit_ctrl_2283 | 207| 2default:defaulthp x   %s *synth2 |129 | \bus_status_ctrl.gf_scl |glitch_filter_2284 | 18| 2default:defaulthp x   %s *synth2 |130 | \bus_status_ctrl.gf_sda |glitch_filter_2285 | 20| 2default:defaulthp x   %s *synth2 |131 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_2262 | 309| 2default:defaulthp x   %s *synth2 |132 | i2c_master |i2c_master_usr_2276 | 309| 2default:defaulthp x   %s *synth2 |133 | byte_ctrl |i2c_master_byte_ctrl_2277 | 256| 2default:defaulthp x   %s *synth2 |134 | bit_ctrl |i2c_master_bit_ctrl_2278 | 207| 2default:defaulthp x   %s *synth2 |135 | \bus_status_ctrl.gf_scl |glitch_filter_2279 | 18| 2default:defaulthp x   %s *synth2 |136 | \bus_status_ctrl.gf_sda |glitch_filter_2280 | 20| 2default:defaulthp x   %s *synth2 |137 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_2263 | 309| 2default:defaulthp x   %s *synth2 |138 | i2c_master |i2c_master_usr_2271 | 309| 2default:defaulthp x   %s *synth2 |139 | byte_ctrl |i2c_master_byte_ctrl_2272 | 256| 2default:defaulthp x   %s *synth2 |140 | bit_ctrl |i2c_master_bit_ctrl_2273 | 207| 2default:defaulthp x   %s *synth2 |141 | \bus_status_ctrl.gf_scl |glitch_filter_2274 | 18| 2default:defaulthp x   %s *synth2 |142 | \bus_status_ctrl.gf_sda |glitch_filter_2275 | 20| 2default:defaulthp x   %s *synth2 |143 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_2264 | 307| 2default:defaulthp x   %s *synth2 |144 | i2c_master |i2c_master_usr_2266 | 307| 2default:defaulthp x   %s *synth2 |145 | byte_ctrl |i2c_master_byte_ctrl_2267 | 255| 2default:defaulthp x   %s *synth2 |146 | bit_ctrl |i2c_master_bit_ctrl_2268 | 206| 2default:defaulthp x   %s *synth2 |147 | \bus_status_ctrl.gf_scl |glitch_filter_2269 | 17| 2default:defaulthp x   %s *synth2 |148 | \bus_status_ctrl.gf_sda |glitch_filter_2270 | 19| 2default:defaulthp x   %s *synth2 |149 | prbs |prbs_2265 | 20| 2default:defaulthp x   %s *synth2 |150 | \SFP_GEN[10].ngFEC_module |ngFEC_module | 15549| 2default:defaulthp x   %s *synth2 |151 | bkp_buffer_ngccm |buffer_ngccm_com_2157 | 511| 2default:defaulthp x   %s *synth2 |152 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_2158 | 281| 2default:defaulthp x   %s *synth2 |153 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2244 | 194| 2default:defaulthp x   %s *synth2 |154 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2245 | 20| 2default:defaulthp x   %s *synth2 |155 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2246 | 24| 2default:defaulthp x   %s *synth2 |156 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_2159 | 168| 2default:defaulthp x   %s *synth2 |157 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_2160 | 257| 2default:defaulthp x   %s *synth2 |158 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2241 | 167| 2default:defaulthp x   %s *synth2 |159 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2242 | 18| 2default:defaulthp x   %s *synth2 |160 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2243 | 29| 2default:defaulthp x   %s *synth2 |161 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_2161 | 166| 2default:defaulthp x   %s *synth2 |162 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_2162 | 257| 2default:defaulthp x   %s *synth2 |163 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2238 | 167| 2default:defaulthp x   %s *synth2 |164 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2239 | 18| 2default:defaulthp x   %s *synth2 |165 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2240 | 29| 2default:defaulthp x   %s *synth2 |166 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_2163 | 166| 2default:defaulthp x   %s *synth2 |167 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_2164 | 280| 2default:defaulthp x   %s *synth2 |168 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2235 | 188| 2default:defaulthp x   %s *synth2 |169 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2236 | 20| 2default:defaulthp x   %s *synth2 |170 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2237 | 29| 2default:defaulthp x   %s *synth2 |171 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_2165 | 264| 2default:defaulthp x   %s *synth2 |172 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_2166 | 134| 2default:defaulthp x   %s *synth2 |173 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2232 | 69| 2default:defaulthp x   %s *synth2 |174 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2233 | 20| 2default:defaulthp x   %s *synth2 |175 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2234 | 18| 2default:defaulthp x   %s *synth2 |176 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_2167 | 133| 2default:defaulthp x   %s *synth2 |177 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_2168 | 280| 2default:defaulthp x   %s *synth2 |178 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2229 | 188| 2default:defaulthp x   %s *synth2 |179 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2230 | 20| 2default:defaulthp x   %s *synth2 |180 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2231 | 29| 2default:defaulthp x   %s *synth2 |181 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_2169 | 168| 2default:defaulthp x   %s *synth2 |182 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_2170 | 257| 2default:defaulthp x   %s *synth2 |183 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2226 | 167| 2default:defaulthp x   %s *synth2 |184 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2227 | 18| 2default:defaulthp x   %s *synth2 |185 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2228 | 29| 2default:defaulthp x   %s *synth2 |186 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_2171 | 198| 2default:defaulthp x   %s *synth2 |187 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_2172 | 280| 2default:defaulthp x   %s *synth2 |188 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2223 | 188| 2default:defaulthp x   %s *synth2 |189 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2224 | 20| 2default:defaulthp x   %s *synth2 |190 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2225 | 29| 2default:defaulthp x   %s *synth2 |191 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_2173 | 168| 2default:defaulthp x   %s *synth2 |192 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_2174 | 280| 2default:defaulthp x   %s *synth2 |193 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2220 | 188| 2default:defaulthp x   %s *synth2 |194 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2221 | 20| 2default:defaulthp x   %s *synth2 |195 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2222 | 29| 2default:defaulthp x   %s *synth2 |196 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_2175 | 167| 2default:defaulthp x   %s *synth2 |197 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_2176 | 280| 2default:defaulthp x   %s *synth2 |198 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2217 | 188| 2default:defaulthp x   %s *synth2 |199 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2218 | 20| 2default:defaulthp x   %s *synth2 |200 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2219 | 29| 2default:defaulthp x   %s *synth2 |201 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_2177 | 168| 2default:defaulthp x   %s *synth2 |202 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_2178 | 280| 2default:defaulthp x   %s *synth2 |203 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2214 | 188| 2default:defaulthp x   %s *synth2 |204 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2215 | 20| 2default:defaulthp x   %s *synth2 |205 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2216 | 29| 2default:defaulthp x   %s *synth2 |206 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_2179 | 234| 2default:defaulthp x   %s *synth2 |207 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_2180 | 257| 2default:defaulthp x   %s *synth2 |208 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2211 | 167| 2default:defaulthp x   %s *synth2 |209 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2212 | 18| 2default:defaulthp x   %s *synth2 |210 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2213 | 29| 2default:defaulthp x   %s *synth2 |211 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_2181 | 166| 2default:defaulthp x   %s *synth2 |212 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_2182 | 257| 2default:defaulthp x   %s *synth2 |213 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2208 | 167| 2default:defaulthp x   %s *synth2 |214 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2209 | 18| 2default:defaulthp x   %s *synth2 |215 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2210 | 29| 2default:defaulthp x   %s *synth2 |216 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_2183 | 166| 2default:defaulthp x   %s *synth2 |217 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_2184 | 257| 2default:defaulthp x   %s *synth2 |218 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2205 | 167| 2default:defaulthp x   %s *synth2 |219 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2206 | 18| 2default:defaulthp x   %s *synth2 |220 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2207 | 29| 2default:defaulthp x   %s *synth2 |221 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_2185 | 165| 2default:defaulthp x   %s *synth2 |222 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_2186 | 257| 2default:defaulthp x   %s *synth2 |223 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2202 | 167| 2default:defaulthp x   %s *synth2 |224 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2203 | 18| 2default:defaulthp x   %s *synth2 |225 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2204 | 29| 2default:defaulthp x   %s *synth2 |226 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_2187 | 198| 2default:defaulthp x   %s *synth2 |227 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_2188 | 662| 2default:defaulthp x   %s *synth2 |228 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_2189 | 510| 2default:defaulthp x   %s *synth2 |229 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_2190 | 535| 2default:defaulthp x   %s *synth2 |230 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_2191 | 535| 2default:defaulthp x   %s *synth2 |231 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_2192 | 511| 2default:defaulthp x   %s *synth2 |232 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_2193 | 535| 2default:defaulthp x   %s *synth2 |233 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_2194 | 511| 2default:defaulthp x   %s *synth2 |234 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_2195 | 511| 2default:defaulthp x   %s *synth2 |235 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_2196 | 511| 2default:defaulthp x   %s *synth2 |236 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_2197 | 511| 2default:defaulthp x   %s *synth2 |237 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_2198 | 535| 2default:defaulthp x   %s *synth2 |238 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_2199 | 535| 2default:defaulthp x   %s *synth2 |239 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_2200 | 535| 2default:defaulthp x   %s *synth2 |240 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_2201 | 535| 2default:defaulthp x   %s *synth2 |241 | \SFP_GEN[11].QIE_RESET_DELAY |delay_counter_3 | 40| 2default:defaulthp x   %s *synth2 |242 | \SFP_GEN[11].ngCCM_gbt |ngCCM__xdcDup__11 | 8159| 2default:defaulthp x   %s *synth2 |243 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__151 | 104| 2default:defaulthp x   %s *synth2 |244 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__398 | 4| 2default:defaulthp x   %s *synth2 |245 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__152 | 104| 2default:defaulthp x   %s *synth2 |246 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__397 | 4| 2default:defaulthp x   %s *synth2 |247 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__153 | 104| 2default:defaulthp x   %s *synth2 |248 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__396 | 4| 2default:defaulthp x   %s *synth2 |249 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__154 | 104| 2default:defaulthp x   %s *synth2 |250 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__395 | 4| 2default:defaulthp x   %s *synth2 |251 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__155 | 104| 2default:defaulthp x   %s *synth2 |252 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__394 | 4| 2default:defaulthp x   %s *synth2 |253 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__156 | 104| 2default:defaulthp x   %s *synth2 |254 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__393 | 4| 2default:defaulthp x   %s *synth2 |255 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__157 | 104| 2default:defaulthp x   %s *synth2 |256 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__392 | 4| 2default:defaulthp x   %s *synth2 |257 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__158 | 104| 2default:defaulthp x   %s *synth2 |258 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__391 | 4| 2default:defaulthp x   %s *synth2 |259 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__159 | 104| 2default:defaulthp x   %s *synth2 |260 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__390 | 4| 2default:defaulthp x   %s *synth2 |261 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__160 | 104| 2default:defaulthp x   %s *synth2 |262 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__389 | 4| 2default:defaulthp x   %s *synth2 |263 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__161 | 104| 2default:defaulthp x   %s *synth2 |264 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__388 | 4| 2default:defaulthp x   %s *synth2 |265 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__162 | 104| 2default:defaulthp x   %s *synth2 |266 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__387 | 4| 2default:defaulthp x   %s *synth2 |267 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__163 | 104| 2default:defaulthp x   %s *synth2 |268 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__386 | 4| 2default:defaulthp x   %s *synth2 |269 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__164 | 104| 2default:defaulthp x   %s *synth2 |270 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__385 | 4| 2default:defaulthp x   %s *synth2 |271 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__165 | 104| 2default:defaulthp x   %s *synth2 |272 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__384 | 4| 2default:defaulthp x   %s *synth2 |273 | CrossClock_DV_cnt |CrossClock_RX_2072 | 41| 2default:defaulthp x   %s *synth2 |274 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__11 | 566| 2default:defaulthp x   %s *synth2 |275 | JTAGMaster_inst |JTAGMaster__xdcDup__11 | 417| 2default:defaulthp x   %s *synth2 |276 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__399 | 4| 2default:defaulthp x   %s *synth2 |277 | JTAG_BRAM |RAM_2156 | 85| 2default:defaulthp x   %s *synth2 |278 | Sync_RX_Reset |Sync_2073 | 2| 2default:defaulthp x   %s *synth2 |279 | Sync_TX_Reset |Sync_2074 | 45| 2default:defaulthp x   %s *synth2 |280 | Sync_error_counter_reset |Sync_2075 | 3| 2default:defaulthp x   %s *synth2 |281 | gbt_rx_checker |gbt_rx_checker_2076 | 104| 2default:defaulthp x   %s *synth2 |282 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_2077 | 309| 2default:defaulthp x   %s *synth2 |283 | i2c_master |i2c_master_usr_2151 | 309| 2default:defaulthp x   %s *synth2 |284 | byte_ctrl |i2c_master_byte_ctrl_2152 | 256| 2default:defaulthp x   %s *synth2 |285 | bit_ctrl |i2c_master_bit_ctrl_2153 | 207| 2default:defaulthp x   %s *synth2 |286 | \bus_status_ctrl.gf_scl |glitch_filter_2154 | 18| 2default:defaulthp x   %s *synth2 |287 | \bus_status_ctrl.gf_sda |glitch_filter_2155 | 20| 2default:defaulthp x   %s *synth2 |288 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_2078 | 309| 2default:defaulthp x   %s *synth2 |289 | i2c_master |i2c_master_usr_2146 | 309| 2default:defaulthp x   %s *synth2 |290 | byte_ctrl |i2c_master_byte_ctrl_2147 | 256| 2default:defaulthp x   %s *synth2 |291 | bit_ctrl |i2c_master_bit_ctrl_2148 | 207| 2default:defaulthp x   %s *synth2 |292 | \bus_status_ctrl.gf_scl |glitch_filter_2149 | 18| 2default:defaulthp x   %s *synth2 |293 | \bus_status_ctrl.gf_sda |glitch_filter_2150 | 20| 2default:defaulthp x   %s *synth2 |294 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_2079 | 309| 2default:defaulthp x   %s *synth2 |295 | i2c_master |i2c_master_usr_2141 | 309| 2default:defaulthp x   %s *synth2 |296 | byte_ctrl |i2c_master_byte_ctrl_2142 | 256| 2default:defaulthp x   %s *synth2 |297 | bit_ctrl |i2c_master_bit_ctrl_2143 | 207| 2default:defaulthp x   %s *synth2 |298 | \bus_status_ctrl.gf_scl |glitch_filter_2144 | 18| 2default:defaulthp x   %s *synth2 |299 | \bus_status_ctrl.gf_sda |glitch_filter_2145 | 20| 2default:defaulthp x   %s *synth2 |300 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_2080 | 309| 2default:defaulthp x   %s *synth2 |301 | i2c_master |i2c_master_usr_2136 | 309| 2default:defaulthp x   %s *synth2 |302 | byte_ctrl |i2c_master_byte_ctrl_2137 | 256| 2default:defaulthp x   %s *synth2 |303 | bit_ctrl |i2c_master_bit_ctrl_2138 | 207| 2default:defaulthp x   %s *synth2 |304 | \bus_status_ctrl.gf_scl |glitch_filter_2139 | 18| 2default:defaulthp x   %s *synth2 |305 | \bus_status_ctrl.gf_sda |glitch_filter_2140 | 20| 2default:defaulthp x   %s *synth2 |306 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_2081 | 309| 2default:defaulthp x   %s *synth2 |307 | i2c_master |i2c_master_usr_2131 | 309| 2default:defaulthp x   %s *synth2 |308 | byte_ctrl |i2c_master_byte_ctrl_2132 | 256| 2default:defaulthp x   %s *synth2 |309 | bit_ctrl |i2c_master_bit_ctrl_2133 | 207| 2default:defaulthp x   %s *synth2 |310 | \bus_status_ctrl.gf_scl |glitch_filter_2134 | 18| 2default:defaulthp x   %s *synth2 |311 | \bus_status_ctrl.gf_sda |glitch_filter_2135 | 20| 2default:defaulthp x   %s *synth2 |312 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_2082 | 309| 2default:defaulthp x   %s *synth2 |313 | i2c_master |i2c_master_usr_2126 | 309| 2default:defaulthp x   %s *synth2 |314 | byte_ctrl |i2c_master_byte_ctrl_2127 | 256| 2default:defaulthp x   %s *synth2 |315 | bit_ctrl |i2c_master_bit_ctrl_2128 | 207| 2default:defaulthp x   %s *synth2 |316 | \bus_status_ctrl.gf_scl |glitch_filter_2129 | 18| 2default:defaulthp x   %s *synth2 |317 | \bus_status_ctrl.gf_sda |glitch_filter_2130 | 20| 2default:defaulthp x   %s *synth2 |318 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_2083 | 309| 2default:defaulthp x   %s *synth2 |319 | i2c_master |i2c_master_usr_2121 | 309| 2default:defaulthp x   %s *synth2 |320 | byte_ctrl |i2c_master_byte_ctrl_2122 | 256| 2default:defaulthp x   %s *synth2 |321 | bit_ctrl |i2c_master_bit_ctrl_2123 | 207| 2default:defaulthp x   %s *synth2 |322 | \bus_status_ctrl.gf_scl |glitch_filter_2124 | 18| 2default:defaulthp x   %s *synth2 |323 | \bus_status_ctrl.gf_sda |glitch_filter_2125 | 20| 2default:defaulthp x   %s *synth2 |324 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_2084 | 309| 2default:defaulthp x   %s *synth2 |325 | i2c_master |i2c_master_usr_2116 | 309| 2default:defaulthp x   %s *synth2 |326 | byte_ctrl |i2c_master_byte_ctrl_2117 | 256| 2default:defaulthp x   %s *synth2 |327 | bit_ctrl |i2c_master_bit_ctrl_2118 | 207| 2default:defaulthp x   %s *synth2 |328 | \bus_status_ctrl.gf_scl |glitch_filter_2119 | 18| 2default:defaulthp x   %s *synth2 |329 | \bus_status_ctrl.gf_sda |glitch_filter_2120 | 20| 2default:defaulthp x   %s *synth2 |330 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_2085 | 309| 2default:defaulthp x   %s *synth2 |331 | i2c_master |i2c_master_usr_2111 | 309| 2default:defaulthp x   %s *synth2 |332 | byte_ctrl |i2c_master_byte_ctrl_2112 | 256| 2default:defaulthp x   %s *synth2 |333 | bit_ctrl |i2c_master_bit_ctrl_2113 | 207| 2default:defaulthp x   %s *synth2 |334 | \bus_status_ctrl.gf_scl |glitch_filter_2114 | 18| 2default:defaulthp x   %s *synth2 |335 | \bus_status_ctrl.gf_sda |glitch_filter_2115 | 20| 2default:defaulthp x   %s *synth2 |336 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_2086 | 309| 2default:defaulthp x   %s *synth2 |337 | i2c_master |i2c_master_usr_2106 | 309| 2default:defaulthp x   %s *synth2 |338 | byte_ctrl |i2c_master_byte_ctrl_2107 | 256| 2default:defaulthp x   %s *synth2 |339 | bit_ctrl |i2c_master_bit_ctrl_2108 | 207| 2default:defaulthp x   %s *synth2 |340 | \bus_status_ctrl.gf_scl |glitch_filter_2109 | 18| 2default:defaulthp x   %s *synth2 |341 | \bus_status_ctrl.gf_sda |glitch_filter_2110 | 20| 2default:defaulthp x   %s *synth2 |342 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_2087 | 309| 2default:defaulthp x   %s *synth2 |343 | i2c_master |i2c_master_usr_2101 | 309| 2default:defaulthp x   %s *synth2 |344 | byte_ctrl |i2c_master_byte_ctrl_2102 | 256| 2default:defaulthp x   %s *synth2 |345 | bit_ctrl |i2c_master_bit_ctrl_2103 | 207| 2default:defaulthp x   %s *synth2 |346 | \bus_status_ctrl.gf_scl |glitch_filter_2104 | 18| 2default:defaulthp x   %s *synth2 |347 | \bus_status_ctrl.gf_sda |glitch_filter_2105 | 20| 2default:defaulthp x   %s *synth2 |348 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_2088 | 309| 2default:defaulthp x   %s *synth2 |349 | i2c_master |i2c_master_usr_2096 | 309| 2default:defaulthp x   %s *synth2 |350 | byte_ctrl |i2c_master_byte_ctrl_2097 | 256| 2default:defaulthp x   %s *synth2 |351 | bit_ctrl |i2c_master_bit_ctrl_2098 | 207| 2default:defaulthp x   %s *synth2 |352 | \bus_status_ctrl.gf_scl |glitch_filter_2099 | 18| 2default:defaulthp x   %s *synth2 |353 | \bus_status_ctrl.gf_sda |glitch_filter_2100 | 20| 2default:defaulthp x   %s *synth2 |354 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_2089 | 307| 2default:defaulthp x   %s *synth2 |355 | i2c_master |i2c_master_usr_2091 | 307| 2default:defaulthp x   %s *synth2 |356 | byte_ctrl |i2c_master_byte_ctrl_2092 | 255| 2default:defaulthp x   %s *synth2 |357 | bit_ctrl |i2c_master_bit_ctrl_2093 | 206| 2default:defaulthp x   %s *synth2 |358 | \bus_status_ctrl.gf_scl |glitch_filter_2094 | 17| 2default:defaulthp x   %s *synth2 |359 | \bus_status_ctrl.gf_sda |glitch_filter_2095 | 19| 2default:defaulthp x   %s *synth2 |360 | prbs |prbs_2090 | 20| 2default:defaulthp x   %s *synth2 |361 | \SFP_GEN[11].ngFEC_module |ngFEC_module_4 | 15549| 2default:defaulthp x   %s *synth2 |362 | bkp_buffer_ngccm |buffer_ngccm_com_1982 | 511| 2default:defaulthp x   %s *synth2 |363 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1983 | 281| 2default:defaulthp x   %s *synth2 |364 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2069 | 194| 2default:defaulthp x   %s *synth2 |365 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2070 | 20| 2default:defaulthp x   %s *synth2 |366 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2071 | 24| 2default:defaulthp x   %s *synth2 |367 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1984 | 168| 2default:defaulthp x   %s *synth2 |368 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1985 | 257| 2default:defaulthp x   %s *synth2 |369 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2066 | 167| 2default:defaulthp x   %s *synth2 |370 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2067 | 18| 2default:defaulthp x   %s *synth2 |371 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2068 | 29| 2default:defaulthp x   %s *synth2 |372 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1986 | 166| 2default:defaulthp x   %s *synth2 |373 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1987 | 257| 2default:defaulthp x   %s *synth2 |374 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2063 | 167| 2default:defaulthp x   %s *synth2 |375 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2064 | 18| 2default:defaulthp x   %s *synth2 |376 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2065 | 29| 2default:defaulthp x   %s *synth2 |377 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1988 | 166| 2default:defaulthp x   %s *synth2 |378 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1989 | 280| 2default:defaulthp x   %s *synth2 |379 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2060 | 188| 2default:defaulthp x   %s *synth2 |380 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2061 | 20| 2default:defaulthp x   %s *synth2 |381 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2062 | 29| 2default:defaulthp x   %s *synth2 |382 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1990 | 264| 2default:defaulthp x   %s *synth2 |383 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1991 | 134| 2default:defaulthp x   %s *synth2 |384 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2057 | 69| 2default:defaulthp x   %s *synth2 |385 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2058 | 20| 2default:defaulthp x   %s *synth2 |386 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2059 | 18| 2default:defaulthp x   %s *synth2 |387 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1992 | 133| 2default:defaulthp x   %s *synth2 |388 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1993 | 280| 2default:defaulthp x   %s *synth2 |389 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2054 | 188| 2default:defaulthp x   %s *synth2 |390 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2055 | 20| 2default:defaulthp x   %s *synth2 |391 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2056 | 29| 2default:defaulthp x   %s *synth2 |392 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1994 | 168| 2default:defaulthp x   %s *synth2 |393 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1995 | 257| 2default:defaulthp x   %s *synth2 |394 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2051 | 167| 2default:defaulthp x   %s *synth2 |395 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2052 | 18| 2default:defaulthp x   %s *synth2 |396 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2053 | 29| 2default:defaulthp x   %s *synth2 |397 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1996 | 198| 2default:defaulthp x   %s *synth2 |398 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1997 | 280| 2default:defaulthp x   %s *synth2 |399 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2048 | 188| 2default:defaulthp x   %s *synth2 |400 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2049 | 20| 2default:defaulthp x   %s *synth2 |401 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2050 | 29| 2default:defaulthp x   %s *synth2 |402 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1998 | 168| 2default:defaulthp x   %s *synth2 |403 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1999 | 280| 2default:defaulthp x   %s *synth2 |404 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2045 | 188| 2default:defaulthp x   %s *synth2 |405 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2046 | 20| 2default:defaulthp x   %s *synth2 |406 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2047 | 29| 2default:defaulthp x   %s *synth2 |407 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_2000 | 167| 2default:defaulthp x   %s *synth2 |408 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_2001 | 280| 2default:defaulthp x   %s *synth2 |409 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2042 | 188| 2default:defaulthp x   %s *synth2 |410 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2043 | 20| 2default:defaulthp x   %s *synth2 |411 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2044 | 29| 2default:defaulthp x   %s *synth2 |412 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_2002 | 168| 2default:defaulthp x   %s *synth2 |413 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_2003 | 280| 2default:defaulthp x   %s *synth2 |414 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2039 | 188| 2default:defaulthp x   %s *synth2 |415 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2040 | 20| 2default:defaulthp x   %s *synth2 |416 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2041 | 29| 2default:defaulthp x   %s *synth2 |417 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_2004 | 234| 2default:defaulthp x   %s *synth2 |418 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_2005 | 257| 2default:defaulthp x   %s *synth2 |419 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2036 | 167| 2default:defaulthp x   %s *synth2 |420 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2037 | 18| 2default:defaulthp x   %s *synth2 |421 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2038 | 29| 2default:defaulthp x   %s *synth2 |422 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_2006 | 166| 2default:defaulthp x   %s *synth2 |423 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_2007 | 257| 2default:defaulthp x   %s *synth2 |424 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2033 | 167| 2default:defaulthp x   %s *synth2 |425 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2034 | 18| 2default:defaulthp x   %s *synth2 |426 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2035 | 29| 2default:defaulthp x   %s *synth2 |427 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_2008 | 166| 2default:defaulthp x   %s *synth2 |428 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_2009 | 257| 2default:defaulthp x   %s *synth2 |429 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2030 | 167| 2default:defaulthp x   %s *synth2 |430 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2031 | 18| 2default:defaulthp x   %s *synth2 |431 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2032 | 29| 2default:defaulthp x   %s *synth2 |432 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_2010 | 165| 2default:defaulthp x   %s *synth2 |433 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_2011 | 257| 2default:defaulthp x   %s *synth2 |434 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2027 | 167| 2default:defaulthp x   %s *synth2 |435 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2028 | 18| 2default:defaulthp x   %s *synth2 |436 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2029 | 29| 2default:defaulthp x   %s *synth2 |437 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_2012 | 198| 2default:defaulthp x   %s *synth2 |438 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_2013 | 662| 2default:defaulthp x   %s *synth2 |439 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_2014 | 510| 2default:defaulthp x   %s *synth2 |440 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_2015 | 535| 2default:defaulthp x   %s *synth2 |441 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_2016 | 535| 2default:defaulthp x   %s *synth2 |442 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_2017 | 511| 2default:defaulthp x   %s *synth2 |443 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_2018 | 535| 2default:defaulthp x   %s *synth2 |444 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_2019 | 511| 2default:defaulthp x   %s *synth2 |445 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_2020 | 511| 2default:defaulthp x   %s *synth2 |446 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_2021 | 511| 2default:defaulthp x   %s *synth2 |447 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_2022 | 511| 2default:defaulthp x   %s *synth2 |448 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_2023 | 535| 2default:defaulthp x   %s *synth2 |449 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_2024 | 535| 2default:defaulthp x   %s *synth2 |450 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_2025 | 535| 2default:defaulthp x   %s *synth2 |451 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_2026 | 535| 2default:defaulthp x   %s *synth2 |452 | \SFP_GEN[12].QIE_RESET_DELAY |delay_counter_5 | 40| 2default:defaulthp x   %s *synth2 |453 | \SFP_GEN[12].ngCCM_gbt |ngCCM | 8157| 2default:defaulthp x   %s *synth2 |454 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__166 | 104| 2default:defaulthp x   %s *synth2 |455 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__382 | 4| 2default:defaulthp x   %s *synth2 |456 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__167 | 104| 2default:defaulthp x   %s *synth2 |457 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__381 | 4| 2default:defaulthp x   %s *synth2 |458 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__168 | 104| 2default:defaulthp x   %s *synth2 |459 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__380 | 4| 2default:defaulthp x   %s *synth2 |460 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__169 | 104| 2default:defaulthp x   %s *synth2 |461 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__379 | 4| 2default:defaulthp x   %s *synth2 |462 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__170 | 104| 2default:defaulthp x   %s *synth2 |463 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__378 | 4| 2default:defaulthp x   %s *synth2 |464 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__171 | 104| 2default:defaulthp x   %s *synth2 |465 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__377 | 4| 2default:defaulthp x   %s *synth2 |466 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__172 | 104| 2default:defaulthp x   %s *synth2 |467 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__376 | 4| 2default:defaulthp x   %s *synth2 |468 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__173 | 104| 2default:defaulthp x   %s *synth2 |469 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__375 | 4| 2default:defaulthp x   %s *synth2 |470 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__174 | 104| 2default:defaulthp x   %s *synth2 |471 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__374 | 4| 2default:defaulthp x   %s *synth2 |472 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__175 | 104| 2default:defaulthp x   %s *synth2 |473 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__373 | 4| 2default:defaulthp x   %s *synth2 |474 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__176 | 104| 2default:defaulthp x   %s *synth2 |475 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__372 | 4| 2default:defaulthp x   %s *synth2 |476 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__177 | 104| 2default:defaulthp x   %s *synth2 |477 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__371 | 4| 2default:defaulthp x   %s *synth2 |478 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__178 | 104| 2default:defaulthp x   %s *synth2 |479 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__370 | 4| 2default:defaulthp x   %s *synth2 |480 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__179 | 104| 2default:defaulthp x   %s *synth2 |481 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__369 | 4| 2default:defaulthp x   %s *synth2 |482 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local | 104| 2default:defaulthp x   %s *synth2 |483 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__368 | 4| 2default:defaulthp x   %s *synth2 |484 | CrossClock_DV_cnt |CrossClock_RX_1897 | 41| 2default:defaulthp x   %s *synth2 |485 | LocalJTAGBridge_inst |LocalJTAGBridge | 566| 2default:defaulthp x   %s *synth2 |486 | JTAGMaster_inst |JTAGMaster | 417| 2default:defaulthp x   %s *synth2 |487 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__383 | 4| 2default:defaulthp x   %s *synth2 |488 | JTAG_BRAM |RAM_1981 | 85| 2default:defaulthp x   %s *synth2 |489 | Sync_RX_Reset |Sync_1898 | 2| 2default:defaulthp x   %s *synth2 |490 | Sync_TX_Reset |Sync_1899 | 45| 2default:defaulthp x   %s *synth2 |491 | Sync_error_counter_reset |Sync_1900 | 3| 2default:defaulthp x   %s *synth2 |492 | gbt_rx_checker |gbt_rx_checker_1901 | 104| 2default:defaulthp x   %s *synth2 |493 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1902 | 309| 2default:defaulthp x   %s *synth2 |494 | i2c_master |i2c_master_usr_1976 | 309| 2default:defaulthp x   %s *synth2 |495 | byte_ctrl |i2c_master_byte_ctrl_1977 | 256| 2default:defaulthp x   %s *synth2 |496 | bit_ctrl |i2c_master_bit_ctrl_1978 | 207| 2default:defaulthp x   %s *synth2 |497 | \bus_status_ctrl.gf_scl |glitch_filter_1979 | 18| 2default:defaulthp x   %s *synth2 |498 | \bus_status_ctrl.gf_sda |glitch_filter_1980 | 20| 2default:defaulthp x   %s *synth2 |499 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1903 | 309| 2default:defaulthp x   %s *synth2 |500 | i2c_master |i2c_master_usr_1971 | 309| 2default:defaulthp x   %s *synth2 |501 | byte_ctrl |i2c_master_byte_ctrl_1972 | 256| 2default:defaulthp x   %s *synth2 |502 | bit_ctrl |i2c_master_bit_ctrl_1973 | 207| 2default:defaulthp x   %s *synth2 |503 | \bus_status_ctrl.gf_scl |glitch_filter_1974 | 18| 2default:defaulthp x   %s *synth2 |504 | \bus_status_ctrl.gf_sda |glitch_filter_1975 | 20| 2default:defaulthp x   %s *synth2 |505 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1904 | 309| 2default:defaulthp x   %s *synth2 |506 | i2c_master |i2c_master_usr_1966 | 309| 2default:defaulthp x   %s *synth2 |507 | byte_ctrl |i2c_master_byte_ctrl_1967 | 256| 2default:defaulthp x   %s *synth2 |508 | bit_ctrl |i2c_master_bit_ctrl_1968 | 207| 2default:defaulthp x   %s *synth2 |509 | \bus_status_ctrl.gf_scl |glitch_filter_1969 | 18| 2default:defaulthp x   %s *synth2 |510 | \bus_status_ctrl.gf_sda |glitch_filter_1970 | 20| 2default:defaulthp x   %s *synth2 |511 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1905 | 309| 2default:defaulthp x   %s *synth2 |512 | i2c_master |i2c_master_usr_1961 | 309| 2default:defaulthp x   %s *synth2 |513 | byte_ctrl |i2c_master_byte_ctrl_1962 | 256| 2default:defaulthp x   %s *synth2 |514 | bit_ctrl |i2c_master_bit_ctrl_1963 | 207| 2default:defaulthp x   %s *synth2 |515 | \bus_status_ctrl.gf_scl |glitch_filter_1964 | 18| 2default:defaulthp x   %s *synth2 |516 | \bus_status_ctrl.gf_sda |glitch_filter_1965 | 20| 2default:defaulthp x   %s *synth2 |517 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1906 | 309| 2default:defaulthp x   %s *synth2 |518 | i2c_master |i2c_master_usr_1956 | 309| 2default:defaulthp x   %s *synth2 |519 | byte_ctrl |i2c_master_byte_ctrl_1957 | 256| 2default:defaulthp x   %s *synth2 |520 | bit_ctrl |i2c_master_bit_ctrl_1958 | 207| 2default:defaulthp x   %s *synth2 |521 | \bus_status_ctrl.gf_scl |glitch_filter_1959 | 18| 2default:defaulthp x   %s *synth2 |522 | \bus_status_ctrl.gf_sda |glitch_filter_1960 | 20| 2default:defaulthp x   %s *synth2 |523 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1907 | 309| 2default:defaulthp x   %s *synth2 |524 | i2c_master |i2c_master_usr_1951 | 309| 2default:defaulthp x   %s *synth2 |525 | byte_ctrl |i2c_master_byte_ctrl_1952 | 256| 2default:defaulthp x   %s *synth2 |526 | bit_ctrl |i2c_master_bit_ctrl_1953 | 207| 2default:defaulthp x   %s *synth2 |527 | \bus_status_ctrl.gf_scl |glitch_filter_1954 | 18| 2default:defaulthp x   %s *synth2 |528 | \bus_status_ctrl.gf_sda |glitch_filter_1955 | 20| 2default:defaulthp x   %s *synth2 |529 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1908 | 309| 2default:defaulthp x   %s *synth2 |530 | i2c_master |i2c_master_usr_1946 | 309| 2default:defaulthp x   %s *synth2 |531 | byte_ctrl |i2c_master_byte_ctrl_1947 | 256| 2default:defaulthp x   %s *synth2 |532 | bit_ctrl |i2c_master_bit_ctrl_1948 | 207| 2default:defaulthp x   %s *synth2 |533 | \bus_status_ctrl.gf_scl |glitch_filter_1949 | 18| 2default:defaulthp x   %s *synth2 |534 | \bus_status_ctrl.gf_sda |glitch_filter_1950 | 20| 2default:defaulthp x   %s *synth2 |535 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1909 | 309| 2default:defaulthp x   %s *synth2 |536 | i2c_master |i2c_master_usr_1941 | 309| 2default:defaulthp x   %s *synth2 |537 | byte_ctrl |i2c_master_byte_ctrl_1942 | 256| 2default:defaulthp x   %s *synth2 |538 | bit_ctrl |i2c_master_bit_ctrl_1943 | 207| 2default:defaulthp x   %s *synth2 |539 | \bus_status_ctrl.gf_scl |glitch_filter_1944 | 18| 2default:defaulthp x   %s *synth2 |540 | \bus_status_ctrl.gf_sda |glitch_filter_1945 | 20| 2default:defaulthp x   %s *synth2 |541 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1910 | 309| 2default:defaulthp x   %s *synth2 |542 | i2c_master |i2c_master_usr_1936 | 309| 2default:defaulthp x   %s *synth2 |543 | byte_ctrl |i2c_master_byte_ctrl_1937 | 256| 2default:defaulthp x   %s *synth2 |544 | bit_ctrl |i2c_master_bit_ctrl_1938 | 207| 2default:defaulthp x   %s *synth2 |545 | \bus_status_ctrl.gf_scl |glitch_filter_1939 | 18| 2default:defaulthp x   %s *synth2 |546 | \bus_status_ctrl.gf_sda |glitch_filter_1940 | 20| 2default:defaulthp x   %s *synth2 |547 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1911 | 309| 2default:defaulthp x   %s *synth2 |548 | i2c_master |i2c_master_usr_1931 | 309| 2default:defaulthp x   %s *synth2 |549 | byte_ctrl |i2c_master_byte_ctrl_1932 | 256| 2default:defaulthp x   %s *synth2 |550 | bit_ctrl |i2c_master_bit_ctrl_1933 | 207| 2default:defaulthp x   %s *synth2 |551 | \bus_status_ctrl.gf_scl |glitch_filter_1934 | 18| 2default:defaulthp x   %s *synth2 |552 | \bus_status_ctrl.gf_sda |glitch_filter_1935 | 20| 2default:defaulthp x   %s *synth2 |553 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1912 | 309| 2default:defaulthp x   %s *synth2 |554 | i2c_master |i2c_master_usr_1926 | 309| 2default:defaulthp x   %s *synth2 |555 | byte_ctrl |i2c_master_byte_ctrl_1927 | 256| 2default:defaulthp x   %s *synth2 |556 | bit_ctrl |i2c_master_bit_ctrl_1928 | 207| 2default:defaulthp x   %s *synth2 |557 | \bus_status_ctrl.gf_scl |glitch_filter_1929 | 18| 2default:defaulthp x   %s *synth2 |558 | \bus_status_ctrl.gf_sda |glitch_filter_1930 | 20| 2default:defaulthp x   %s *synth2 |559 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1913 | 309| 2default:defaulthp x   %s *synth2 |560 | i2c_master |i2c_master_usr_1921 | 309| 2default:defaulthp x   %s *synth2 |561 | byte_ctrl |i2c_master_byte_ctrl_1922 | 256| 2default:defaulthp x   %s *synth2 |562 | bit_ctrl |i2c_master_bit_ctrl_1923 | 207| 2default:defaulthp x   %s *synth2 |563 | \bus_status_ctrl.gf_scl |glitch_filter_1924 | 18| 2default:defaulthp x   %s *synth2 |564 | \bus_status_ctrl.gf_sda |glitch_filter_1925 | 20| 2default:defaulthp x   %s *synth2 |565 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1914 | 307| 2default:defaulthp x   %s *synth2 |566 | i2c_master |i2c_master_usr_1916 | 307| 2default:defaulthp x   %s *synth2 |567 | byte_ctrl |i2c_master_byte_ctrl_1917 | 255| 2default:defaulthp x   %s *synth2 |568 | bit_ctrl |i2c_master_bit_ctrl_1918 | 206| 2default:defaulthp x   %s *synth2 |569 | \bus_status_ctrl.gf_scl |glitch_filter_1919 | 17| 2default:defaulthp x   %s *synth2 |570 | \bus_status_ctrl.gf_sda |glitch_filter_1920 | 19| 2default:defaulthp x   %s *synth2 |571 | prbs |prbs_1915 | 20| 2default:defaulthp x   %s *synth2 |572 | \SFP_GEN[12].ngFEC_module |ngFEC_module_6 | 15549| 2default:defaulthp x   %s *synth2 |573 | bkp_buffer_ngccm |buffer_ngccm_com_1807 | 511| 2default:defaulthp x   %s *synth2 |574 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1808 | 281| 2default:defaulthp x   %s *synth2 |575 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1894 | 194| 2default:defaulthp x   %s *synth2 |576 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1895 | 20| 2default:defaulthp x   %s *synth2 |577 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1896 | 24| 2default:defaulthp x   %s *synth2 |578 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1809 | 168| 2default:defaulthp x   %s *synth2 |579 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1810 | 257| 2default:defaulthp x   %s *synth2 |580 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1891 | 167| 2default:defaulthp x   %s *synth2 |581 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1892 | 18| 2default:defaulthp x   %s *synth2 |582 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1893 | 29| 2default:defaulthp x   %s *synth2 |583 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1811 | 166| 2default:defaulthp x   %s *synth2 |584 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1812 | 257| 2default:defaulthp x   %s *synth2 |585 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1888 | 167| 2default:defaulthp x   %s *synth2 |586 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1889 | 18| 2default:defaulthp x   %s *synth2 |587 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1890 | 29| 2default:defaulthp x   %s *synth2 |588 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1813 | 166| 2default:defaulthp x   %s *synth2 |589 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1814 | 280| 2default:defaulthp x   %s *synth2 |590 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1885 | 188| 2default:defaulthp x   %s *synth2 |591 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1886 | 20| 2default:defaulthp x   %s *synth2 |592 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1887 | 29| 2default:defaulthp x   %s *synth2 |593 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1815 | 264| 2default:defaulthp x   %s *synth2 |594 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1816 | 134| 2default:defaulthp x   %s *synth2 |595 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1882 | 69| 2default:defaulthp x   %s *synth2 |596 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1883 | 20| 2default:defaulthp x   %s *synth2 |597 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1884 | 18| 2default:defaulthp x   %s *synth2 |598 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1817 | 133| 2default:defaulthp x   %s *synth2 |599 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1818 | 280| 2default:defaulthp x   %s *synth2 |600 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1879 | 188| 2default:defaulthp x   %s *synth2 |601 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1880 | 20| 2default:defaulthp x   %s *synth2 |602 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1881 | 29| 2default:defaulthp x   %s *synth2 |603 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1819 | 168| 2default:defaulthp x   %s *synth2 |604 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1820 | 257| 2default:defaulthp x   %s *synth2 |605 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1876 | 167| 2default:defaulthp x   %s *synth2 |606 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1877 | 18| 2default:defaulthp x   %s *synth2 |607 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1878 | 29| 2default:defaulthp x   %s *synth2 |608 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1821 | 198| 2default:defaulthp x   %s *synth2 |609 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1822 | 280| 2default:defaulthp x   %s *synth2 |610 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1873 | 188| 2default:defaulthp x   %s *synth2 |611 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1874 | 20| 2default:defaulthp x   %s *synth2 |612 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1875 | 29| 2default:defaulthp x   %s *synth2 |613 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1823 | 168| 2default:defaulthp x   %s *synth2 |614 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1824 | 280| 2default:defaulthp x   %s *synth2 |615 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1870 | 188| 2default:defaulthp x   %s *synth2 |616 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1871 | 20| 2default:defaulthp x   %s *synth2 |617 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1872 | 29| 2default:defaulthp x   %s *synth2 |618 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1825 | 167| 2default:defaulthp x   %s *synth2 |619 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1826 | 280| 2default:defaulthp x   %s *synth2 |620 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1867 | 188| 2default:defaulthp x   %s *synth2 |621 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1868 | 20| 2default:defaulthp x   %s *synth2 |622 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1869 | 29| 2default:defaulthp x   %s *synth2 |623 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1827 | 168| 2default:defaulthp x   %s *synth2 |624 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1828 | 280| 2default:defaulthp x   %s *synth2 |625 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1864 | 188| 2default:defaulthp x   %s *synth2 |626 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1865 | 20| 2default:defaulthp x   %s *synth2 |627 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1866 | 29| 2default:defaulthp x   %s *synth2 |628 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1829 | 234| 2default:defaulthp x   %s *synth2 |629 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1830 | 257| 2default:defaulthp x   %s *synth2 |630 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1861 | 167| 2default:defaulthp x   %s *synth2 |631 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1862 | 18| 2default:defaulthp x   %s *synth2 |632 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1863 | 29| 2default:defaulthp x   %s *synth2 |633 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1831 | 166| 2default:defaulthp x   %s *synth2 |634 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1832 | 257| 2default:defaulthp x   %s *synth2 |635 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1858 | 167| 2default:defaulthp x   %s *synth2 |636 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1859 | 18| 2default:defaulthp x   %s *synth2 |637 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1860 | 29| 2default:defaulthp x   %s *synth2 |638 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1833 | 166| 2default:defaulthp x   %s *synth2 |639 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1834 | 257| 2default:defaulthp x   %s *synth2 |640 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1855 | 167| 2default:defaulthp x   %s *synth2 |641 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1856 | 18| 2default:defaulthp x   %s *synth2 |642 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1857 | 29| 2default:defaulthp x   %s *synth2 |643 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1835 | 165| 2default:defaulthp x   %s *synth2 |644 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1836 | 257| 2default:defaulthp x   %s *synth2 |645 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1852 | 167| 2default:defaulthp x   %s *synth2 |646 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1853 | 18| 2default:defaulthp x   %s *synth2 |647 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1854 | 29| 2default:defaulthp x   %s *synth2 |648 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1837 | 198| 2default:defaulthp x   %s *synth2 |649 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1838 | 662| 2default:defaulthp x   %s *synth2 |650 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1839 | 510| 2default:defaulthp x   %s *synth2 |651 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1840 | 535| 2default:defaulthp x   %s *synth2 |652 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1841 | 535| 2default:defaulthp x   %s *synth2 |653 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1842 | 511| 2default:defaulthp x   %s *synth2 |654 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1843 | 535| 2default:defaulthp x   %s *synth2 |655 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1844 | 511| 2default:defaulthp x   %s *synth2 |656 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1845 | 511| 2default:defaulthp x   %s *synth2 |657 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1846 | 511| 2default:defaulthp x   %s *synth2 |658 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1847 | 511| 2default:defaulthp x   %s *synth2 |659 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1848 | 535| 2default:defaulthp x   %s *synth2 |660 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1849 | 535| 2default:defaulthp x   %s *synth2 |661 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1850 | 535| 2default:defaulthp x   %s *synth2 |662 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1851 | 535| 2default:defaulthp x   %s *synth2 |663 | \SFP_GEN[1].QIE_RESET_DELAY |delay_counter_7 | 40| 2default:defaulthp x   %s *synth2 |664 | \SFP_GEN[1].ngCCM_gbt |ngCCM__xdcDup__1 | 8153| 2default:defaulthp x   %s *synth2 |665 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__1 | 104| 2default:defaulthp x   %s *synth2 |666 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__366 | 4| 2default:defaulthp x   %s *synth2 |667 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__2 | 104| 2default:defaulthp x   %s *synth2 |668 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__365 | 4| 2default:defaulthp x   %s *synth2 |669 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__3 | 104| 2default:defaulthp x   %s *synth2 |670 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__364 | 4| 2default:defaulthp x   %s *synth2 |671 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__4 | 104| 2default:defaulthp x   %s *synth2 |672 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__363 | 4| 2default:defaulthp x   %s *synth2 |673 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__5 | 104| 2default:defaulthp x   %s *synth2 |674 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__362 | 4| 2default:defaulthp x   %s *synth2 |675 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__6 | 104| 2default:defaulthp x   %s *synth2 |676 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__361 | 4| 2default:defaulthp x   %s *synth2 |677 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__7 | 104| 2default:defaulthp x   %s *synth2 |678 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__360 | 4| 2default:defaulthp x   %s *synth2 |679 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__8 | 104| 2default:defaulthp x   %s *synth2 |680 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__359 | 4| 2default:defaulthp x   %s *synth2 |681 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__9 | 104| 2default:defaulthp x   %s *synth2 |682 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__358 | 4| 2default:defaulthp x   %s *synth2 |683 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__10 | 104| 2default:defaulthp x   %s *synth2 |684 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__357 | 4| 2default:defaulthp x   %s *synth2 |685 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__11 | 104| 2default:defaulthp x   %s *synth2 |686 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__356 | 4| 2default:defaulthp x   %s *synth2 |687 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__12 | 104| 2default:defaulthp x   %s *synth2 |688 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__355 | 4| 2default:defaulthp x   %s *synth2 |689 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__13 | 104| 2default:defaulthp x   %s *synth2 |690 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__354 | 4| 2default:defaulthp x   %s *synth2 |691 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__14 | 104| 2default:defaulthp x   %s *synth2 |692 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__353 | 4| 2default:defaulthp x   %s *synth2 |693 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__15 | 104| 2default:defaulthp x   %s *synth2 |694 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__352 | 4| 2default:defaulthp x   %s *synth2 |695 | CrossClock_DV_cnt |CrossClock_RX_1722 | 70| 2default:defaulthp x   %s *synth2 |696 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__1 | 629| 2default:defaulthp x   %s *synth2 |697 | JTAGMaster_inst |JTAGMaster__xdcDup__1 | 462| 2default:defaulthp x   %s *synth2 |698 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__367 | 4| 2default:defaulthp x   %s *synth2 |699 | JTAG_BRAM |RAM_1806 | 117| 2default:defaulthp x   %s *synth2 |700 | Sync_RX_Reset |Sync_1723 | 2| 2default:defaulthp x   %s *synth2 |701 | Sync_TX_Reset |Sync_1724 | 114| 2default:defaulthp x   %s *synth2 |702 | Sync_error_counter_reset |Sync_1725 | 2| 2default:defaulthp x   %s *synth2 |703 | gbt_rx_checker |gbt_rx_checker_1726 | 106| 2default:defaulthp x   %s *synth2 |704 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1727 | 332| 2default:defaulthp x   %s *synth2 |705 | i2c_master |i2c_master_usr_1801 | 332| 2default:defaulthp x   %s *synth2 |706 | byte_ctrl |i2c_master_byte_ctrl_1802 | 279| 2default:defaulthp x   %s *synth2 |707 | bit_ctrl |i2c_master_bit_ctrl_1803 | 224| 2default:defaulthp x   %s *synth2 |708 | \bus_status_ctrl.gf_scl |glitch_filter_1804 | 18| 2default:defaulthp x   %s *synth2 |709 | \bus_status_ctrl.gf_sda |glitch_filter_1805 | 20| 2default:defaulthp x   %s *synth2 |710 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1728 | 332| 2default:defaulthp x   %s *synth2 |711 | i2c_master |i2c_master_usr_1796 | 332| 2default:defaulthp x   %s *synth2 |712 | byte_ctrl |i2c_master_byte_ctrl_1797 | 279| 2default:defaulthp x   %s *synth2 |713 | bit_ctrl |i2c_master_bit_ctrl_1798 | 224| 2default:defaulthp x   %s *synth2 |714 | \bus_status_ctrl.gf_scl |glitch_filter_1799 | 18| 2default:defaulthp x   %s *synth2 |715 | \bus_status_ctrl.gf_sda |glitch_filter_1800 | 20| 2default:defaulthp x   %s *synth2 |716 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1729 | 332| 2default:defaulthp x   %s *synth2 |717 | i2c_master |i2c_master_usr_1791 | 332| 2default:defaulthp x   %s *synth2 |718 | byte_ctrl |i2c_master_byte_ctrl_1792 | 279| 2default:defaulthp x   %s *synth2 |719 | bit_ctrl |i2c_master_bit_ctrl_1793 | 224| 2default:defaulthp x   %s *synth2 |720 | \bus_status_ctrl.gf_scl |glitch_filter_1794 | 18| 2default:defaulthp x   %s *synth2 |721 | \bus_status_ctrl.gf_sda |glitch_filter_1795 | 20| 2default:defaulthp x   %s *synth2 |722 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1730 | 332| 2default:defaulthp x   %s *synth2 |723 | i2c_master |i2c_master_usr_1786 | 332| 2default:defaulthp x   %s *synth2 |724 | byte_ctrl |i2c_master_byte_ctrl_1787 | 279| 2default:defaulthp x   %s *synth2 |725 | bit_ctrl |i2c_master_bit_ctrl_1788 | 224| 2default:defaulthp x   %s *synth2 |726 | \bus_status_ctrl.gf_scl |glitch_filter_1789 | 18| 2default:defaulthp x   %s *synth2 |727 | \bus_status_ctrl.gf_sda |glitch_filter_1790 | 20| 2default:defaulthp x   %s *synth2 |728 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1731 | 332| 2default:defaulthp x   %s *synth2 |729 | i2c_master |i2c_master_usr_1781 | 332| 2default:defaulthp x   %s *synth2 |730 | byte_ctrl |i2c_master_byte_ctrl_1782 | 279| 2default:defaulthp x   %s *synth2 |731 | bit_ctrl |i2c_master_bit_ctrl_1783 | 224| 2default:defaulthp x   %s *synth2 |732 | \bus_status_ctrl.gf_scl |glitch_filter_1784 | 18| 2default:defaulthp x   %s *synth2 |733 | \bus_status_ctrl.gf_sda |glitch_filter_1785 | 20| 2default:defaulthp x   %s *synth2 |734 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1732 | 332| 2default:defaulthp x   %s *synth2 |735 | i2c_master |i2c_master_usr_1776 | 332| 2default:defaulthp x   %s *synth2 |736 | byte_ctrl |i2c_master_byte_ctrl_1777 | 279| 2default:defaulthp x   %s *synth2 |737 | bit_ctrl |i2c_master_bit_ctrl_1778 | 224| 2default:defaulthp x   %s *synth2 |738 | \bus_status_ctrl.gf_scl |glitch_filter_1779 | 18| 2default:defaulthp x   %s *synth2 |739 | \bus_status_ctrl.gf_sda |glitch_filter_1780 | 20| 2default:defaulthp x   %s *synth2 |740 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1733 | 332| 2default:defaulthp x   %s *synth2 |741 | i2c_master |i2c_master_usr_1771 | 332| 2default:defaulthp x   %s *synth2 |742 | byte_ctrl |i2c_master_byte_ctrl_1772 | 279| 2default:defaulthp x   %s *synth2 |743 | bit_ctrl |i2c_master_bit_ctrl_1773 | 224| 2default:defaulthp x   %s *synth2 |744 | \bus_status_ctrl.gf_scl |glitch_filter_1774 | 18| 2default:defaulthp x   %s *synth2 |745 | \bus_status_ctrl.gf_sda |glitch_filter_1775 | 20| 2default:defaulthp x   %s *synth2 |746 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1734 | 332| 2default:defaulthp x   %s *synth2 |747 | i2c_master |i2c_master_usr_1766 | 332| 2default:defaulthp x   %s *synth2 |748 | byte_ctrl |i2c_master_byte_ctrl_1767 | 279| 2default:defaulthp x   %s *synth2 |749 | bit_ctrl |i2c_master_bit_ctrl_1768 | 224| 2default:defaulthp x   %s *synth2 |750 | \bus_status_ctrl.gf_scl |glitch_filter_1769 | 18| 2default:defaulthp x   %s *synth2 |751 | \bus_status_ctrl.gf_sda |glitch_filter_1770 | 20| 2default:defaulthp x   %s *synth2 |752 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1735 | 332| 2default:defaulthp x   %s *synth2 |753 | i2c_master |i2c_master_usr_1761 | 332| 2default:defaulthp x   %s *synth2 |754 | byte_ctrl |i2c_master_byte_ctrl_1762 | 279| 2default:defaulthp x   %s *synth2 |755 | bit_ctrl |i2c_master_bit_ctrl_1763 | 224| 2default:defaulthp x   %s *synth2 |756 | \bus_status_ctrl.gf_scl |glitch_filter_1764 | 18| 2default:defaulthp x   %s *synth2 |757 | \bus_status_ctrl.gf_sda |glitch_filter_1765 | 20| 2default:defaulthp x   %s *synth2 |758 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1736 | 332| 2default:defaulthp x   %s *synth2 |759 | i2c_master |i2c_master_usr_1756 | 332| 2default:defaulthp x   %s *synth2 |760 | byte_ctrl |i2c_master_byte_ctrl_1757 | 279| 2default:defaulthp x   %s *synth2 |761 | bit_ctrl |i2c_master_bit_ctrl_1758 | 224| 2default:defaulthp x   %s *synth2 |762 | \bus_status_ctrl.gf_scl |glitch_filter_1759 | 18| 2default:defaulthp x   %s *synth2 |763 | \bus_status_ctrl.gf_sda |glitch_filter_1760 | 20| 2default:defaulthp x   %s *synth2 |764 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1737 | 332| 2default:defaulthp x   %s *synth2 |765 | i2c_master |i2c_master_usr_1751 | 332| 2default:defaulthp x   %s *synth2 |766 | byte_ctrl |i2c_master_byte_ctrl_1752 | 279| 2default:defaulthp x   %s *synth2 |767 | bit_ctrl |i2c_master_bit_ctrl_1753 | 224| 2default:defaulthp x   %s *synth2 |768 | \bus_status_ctrl.gf_scl |glitch_filter_1754 | 18| 2default:defaulthp x   %s *synth2 |769 | \bus_status_ctrl.gf_sda |glitch_filter_1755 | 20| 2default:defaulthp x   %s *synth2 |770 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1738 | 332| 2default:defaulthp x   %s *synth2 |771 | i2c_master |i2c_master_usr_1746 | 332| 2default:defaulthp x   %s *synth2 |772 | byte_ctrl |i2c_master_byte_ctrl_1747 | 279| 2default:defaulthp x   %s *synth2 |773 | bit_ctrl |i2c_master_bit_ctrl_1748 | 224| 2default:defaulthp x   %s *synth2 |774 | \bus_status_ctrl.gf_scl |glitch_filter_1749 | 18| 2default:defaulthp x   %s *synth2 |775 | \bus_status_ctrl.gf_sda |glitch_filter_1750 | 20| 2default:defaulthp x   %s *synth2 |776 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1739 | 331| 2default:defaulthp x   %s *synth2 |777 | i2c_master |i2c_master_usr_1741 | 331| 2default:defaulthp x   %s *synth2 |778 | byte_ctrl |i2c_master_byte_ctrl_1742 | 279| 2default:defaulthp x   %s *synth2 |779 | bit_ctrl |i2c_master_bit_ctrl_1743 | 224| 2default:defaulthp x   %s *synth2 |780 | \bus_status_ctrl.gf_scl |glitch_filter_1744 | 18| 2default:defaulthp x   %s *synth2 |781 | \bus_status_ctrl.gf_sda |glitch_filter_1745 | 20| 2default:defaulthp x   %s *synth2 |782 | prbs |prbs_1740 | 25| 2default:defaulthp x   %s *synth2 |783 | \SFP_GEN[1].ngFEC_module |ngFEC_module_8 | 15549| 2default:defaulthp x   %s *synth2 |784 | bkp_buffer_ngccm |buffer_ngccm_com_1632 | 511| 2default:defaulthp x   %s *synth2 |785 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1633 | 281| 2default:defaulthp x   %s *synth2 |786 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1719 | 194| 2default:defaulthp x   %s *synth2 |787 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1720 | 20| 2default:defaulthp x   %s *synth2 |788 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1721 | 24| 2default:defaulthp x   %s *synth2 |789 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1634 | 168| 2default:defaulthp x   %s *synth2 |790 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1635 | 257| 2default:defaulthp x   %s *synth2 |791 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1716 | 167| 2default:defaulthp x   %s *synth2 |792 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1717 | 18| 2default:defaulthp x   %s *synth2 |793 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1718 | 29| 2default:defaulthp x   %s *synth2 |794 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1636 | 166| 2default:defaulthp x   %s *synth2 |795 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1637 | 257| 2default:defaulthp x   %s *synth2 |796 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1713 | 167| 2default:defaulthp x   %s *synth2 |797 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1714 | 18| 2default:defaulthp x   %s *synth2 |798 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1715 | 29| 2default:defaulthp x   %s *synth2 |799 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1638 | 166| 2default:defaulthp x   %s *synth2 |800 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1639 | 280| 2default:defaulthp x   %s *synth2 |801 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1710 | 188| 2default:defaulthp x   %s *synth2 |802 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1711 | 20| 2default:defaulthp x   %s *synth2 |803 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1712 | 29| 2default:defaulthp x   %s *synth2 |804 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1640 | 264| 2default:defaulthp x   %s *synth2 |805 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1641 | 134| 2default:defaulthp x   %s *synth2 |806 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1707 | 69| 2default:defaulthp x   %s *synth2 |807 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1708 | 20| 2default:defaulthp x   %s *synth2 |808 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1709 | 18| 2default:defaulthp x   %s *synth2 |809 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1642 | 133| 2default:defaulthp x   %s *synth2 |810 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1643 | 280| 2default:defaulthp x   %s *synth2 |811 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1704 | 188| 2default:defaulthp x   %s *synth2 |812 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1705 | 20| 2default:defaulthp x   %s *synth2 |813 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1706 | 29| 2default:defaulthp x   %s *synth2 |814 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1644 | 168| 2default:defaulthp x   %s *synth2 |815 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1645 | 257| 2default:defaulthp x   %s *synth2 |816 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1701 | 167| 2default:defaulthp x   %s *synth2 |817 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1702 | 18| 2default:defaulthp x   %s *synth2 |818 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1703 | 29| 2default:defaulthp x   %s *synth2 |819 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1646 | 198| 2default:defaulthp x   %s *synth2 |820 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1647 | 280| 2default:defaulthp x   %s *synth2 |821 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1698 | 188| 2default:defaulthp x   %s *synth2 |822 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1699 | 20| 2default:defaulthp x   %s *synth2 |823 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1700 | 29| 2default:defaulthp x   %s *synth2 |824 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1648 | 168| 2default:defaulthp x   %s *synth2 |825 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1649 | 280| 2default:defaulthp x   %s *synth2 |826 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1695 | 188| 2default:defaulthp x   %s *synth2 |827 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1696 | 20| 2default:defaulthp x   %s *synth2 |828 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1697 | 29| 2default:defaulthp x   %s *synth2 |829 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1650 | 167| 2default:defaulthp x   %s *synth2 |830 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1651 | 280| 2default:defaulthp x   %s *synth2 |831 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1692 | 188| 2default:defaulthp x   %s *synth2 |832 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1693 | 20| 2default:defaulthp x   %s *synth2 |833 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1694 | 29| 2default:defaulthp x   %s *synth2 |834 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1652 | 168| 2default:defaulthp x   %s *synth2 |835 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1653 | 280| 2default:defaulthp x   %s *synth2 |836 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1689 | 188| 2default:defaulthp x   %s *synth2 |837 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1690 | 20| 2default:defaulthp x   %s *synth2 |838 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1691 | 29| 2default:defaulthp x   %s *synth2 |839 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1654 | 234| 2default:defaulthp x   %s *synth2 |840 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1655 | 257| 2default:defaulthp x   %s *synth2 |841 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1686 | 167| 2default:defaulthp x   %s *synth2 |842 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1687 | 18| 2default:defaulthp x   %s *synth2 |843 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1688 | 29| 2default:defaulthp x   %s *synth2 |844 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1656 | 166| 2default:defaulthp x   %s *synth2 |845 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1657 | 257| 2default:defaulthp x   %s *synth2 |846 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1683 | 167| 2default:defaulthp x   %s *synth2 |847 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1684 | 18| 2default:defaulthp x   %s *synth2 |848 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1685 | 29| 2default:defaulthp x   %s *synth2 |849 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1658 | 166| 2default:defaulthp x   %s *synth2 |850 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1659 | 257| 2default:defaulthp x   %s *synth2 |851 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1680 | 167| 2default:defaulthp x   %s *synth2 |852 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1681 | 18| 2default:defaulthp x   %s *synth2 |853 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1682 | 29| 2default:defaulthp x   %s *synth2 |854 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1660 | 165| 2default:defaulthp x   %s *synth2 |855 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1661 | 257| 2default:defaulthp x   %s *synth2 |856 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1677 | 167| 2default:defaulthp x   %s *synth2 |857 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1678 | 18| 2default:defaulthp x   %s *synth2 |858 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1679 | 29| 2default:defaulthp x   %s *synth2 |859 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1662 | 198| 2default:defaulthp x   %s *synth2 |860 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1663 | 662| 2default:defaulthp x   %s *synth2 |861 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1664 | 510| 2default:defaulthp x   %s *synth2 |862 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1665 | 535| 2default:defaulthp x   %s *synth2 |863 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1666 | 535| 2default:defaulthp x   %s *synth2 |864 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1667 | 511| 2default:defaulthp x   %s *synth2 |865 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1668 | 535| 2default:defaulthp x   %s *synth2 |866 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1669 | 511| 2default:defaulthp x   %s *synth2 |867 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1670 | 511| 2default:defaulthp x   %s *synth2 |868 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1671 | 511| 2default:defaulthp x   %s *synth2 |869 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1672 | 511| 2default:defaulthp x   %s *synth2 |870 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1673 | 535| 2default:defaulthp x   %s *synth2 |871 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1674 | 535| 2default:defaulthp x   %s *synth2 |872 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1675 | 535| 2default:defaulthp x   %s *synth2 |873 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1676 | 535| 2default:defaulthp x   %s *synth2 |874 | \SFP_GEN[2].QIE_RESET_DELAY |delay_counter_9 | 40| 2default:defaulthp x   %s *synth2 |875 | \SFP_GEN[2].ngCCM_gbt |ngCCM__xdcDup__2 | 8153| 2default:defaulthp x   %s *synth2 |876 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__16 | 104| 2default:defaulthp x   %s *synth2 |877 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__350 | 4| 2default:defaulthp x   %s *synth2 |878 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__17 | 104| 2default:defaulthp x   %s *synth2 |879 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__349 | 4| 2default:defaulthp x   %s *synth2 |880 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__18 | 104| 2default:defaulthp x   %s *synth2 |881 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__348 | 4| 2default:defaulthp x   %s *synth2 |882 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__19 | 104| 2default:defaulthp x   %s *synth2 |883 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__347 | 4| 2default:defaulthp x   %s *synth2 |884 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__20 | 104| 2default:defaulthp x   %s *synth2 |885 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__346 | 4| 2default:defaulthp x   %s *synth2 |886 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__21 | 104| 2default:defaulthp x   %s *synth2 |887 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__345 | 4| 2default:defaulthp x   %s *synth2 |888 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__22 | 104| 2default:defaulthp x   %s *synth2 |889 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__344 | 4| 2default:defaulthp x   %s *synth2 |890 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__23 | 104| 2default:defaulthp x   %s *synth2 |891 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__343 | 4| 2default:defaulthp x   %s *synth2 |892 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__24 | 104| 2default:defaulthp x   %s *synth2 |893 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__342 | 4| 2default:defaulthp x   %s *synth2 |894 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__25 | 104| 2default:defaulthp x   %s *synth2 |895 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__341 | 4| 2default:defaulthp x   %s *synth2 |896 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__26 | 104| 2default:defaulthp x   %s *synth2 |897 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__340 | 4| 2default:defaulthp x   %s *synth2 |898 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__27 | 104| 2default:defaulthp x   %s *synth2 |899 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__339 | 4| 2default:defaulthp x   %s *synth2 |900 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__28 | 104| 2default:defaulthp x   %s *synth2 |901 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__338 | 4| 2default:defaulthp x   %s *synth2 |902 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__29 | 104| 2default:defaulthp x   %s *synth2 |903 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__337 | 4| 2default:defaulthp x   %s *synth2 |904 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__30 | 104| 2default:defaulthp x   %s *synth2 |905 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__336 | 4| 2default:defaulthp x   %s *synth2 |906 | CrossClock_DV_cnt |CrossClock_RX_1547 | 70| 2default:defaulthp x   %s *synth2 |907 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__2 | 629| 2default:defaulthp x   %s *synth2 |908 | JTAGMaster_inst |JTAGMaster__xdcDup__2 | 462| 2default:defaulthp x   %s *synth2 |909 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__351 | 4| 2default:defaulthp x   %s *synth2 |910 | JTAG_BRAM |RAM_1631 | 117| 2default:defaulthp x   %s *synth2 |911 | Sync_RX_Reset |Sync_1548 | 2| 2default:defaulthp x   %s *synth2 |912 | Sync_TX_Reset |Sync_1549 | 114| 2default:defaulthp x   %s *synth2 |913 | Sync_error_counter_reset |Sync_1550 | 2| 2default:defaulthp x   %s *synth2 |914 | gbt_rx_checker |gbt_rx_checker_1551 | 106| 2default:defaulthp x   %s *synth2 |915 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1552 | 332| 2default:defaulthp x   %s *synth2 |916 | i2c_master |i2c_master_usr_1626 | 332| 2default:defaulthp x   %s *synth2 |917 | byte_ctrl |i2c_master_byte_ctrl_1627 | 279| 2default:defaulthp x   %s *synth2 |918 | bit_ctrl |i2c_master_bit_ctrl_1628 | 224| 2default:defaulthp x   %s *synth2 |919 | \bus_status_ctrl.gf_scl |glitch_filter_1629 | 18| 2default:defaulthp x   %s *synth2 |920 | \bus_status_ctrl.gf_sda |glitch_filter_1630 | 20| 2default:defaulthp x   %s *synth2 |921 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1553 | 332| 2default:defaulthp x   %s *synth2 |922 | i2c_master |i2c_master_usr_1621 | 332| 2default:defaulthp x   %s *synth2 |923 | byte_ctrl |i2c_master_byte_ctrl_1622 | 279| 2default:defaulthp x   %s *synth2 |924 | bit_ctrl |i2c_master_bit_ctrl_1623 | 224| 2default:defaulthp x   %s *synth2 |925 | \bus_status_ctrl.gf_scl |glitch_filter_1624 | 18| 2default:defaulthp x   %s *synth2 |926 | \bus_status_ctrl.gf_sda |glitch_filter_1625 | 20| 2default:defaulthp x   %s *synth2 |927 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1554 | 332| 2default:defaulthp x   %s *synth2 |928 | i2c_master |i2c_master_usr_1616 | 332| 2default:defaulthp x   %s *synth2 |929 | byte_ctrl |i2c_master_byte_ctrl_1617 | 279| 2default:defaulthp x   %s *synth2 |930 | bit_ctrl |i2c_master_bit_ctrl_1618 | 224| 2default:defaulthp x   %s *synth2 |931 | \bus_status_ctrl.gf_scl |glitch_filter_1619 | 18| 2default:defaulthp x   %s *synth2 |932 | \bus_status_ctrl.gf_sda |glitch_filter_1620 | 20| 2default:defaulthp x   %s *synth2 |933 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1555 | 332| 2default:defaulthp x   %s *synth2 |934 | i2c_master |i2c_master_usr_1611 | 332| 2default:defaulthp x   %s *synth2 |935 | byte_ctrl |i2c_master_byte_ctrl_1612 | 279| 2default:defaulthp x   %s *synth2 |936 | bit_ctrl |i2c_master_bit_ctrl_1613 | 224| 2default:defaulthp x   %s *synth2 |937 | \bus_status_ctrl.gf_scl |glitch_filter_1614 | 18| 2default:defaulthp x   %s *synth2 |938 | \bus_status_ctrl.gf_sda |glitch_filter_1615 | 20| 2default:defaulthp x   %s *synth2 |939 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1556 | 332| 2default:defaulthp x   %s *synth2 |940 | i2c_master |i2c_master_usr_1606 | 332| 2default:defaulthp x   %s *synth2 |941 | byte_ctrl |i2c_master_byte_ctrl_1607 | 279| 2default:defaulthp x   %s *synth2 |942 | bit_ctrl |i2c_master_bit_ctrl_1608 | 224| 2default:defaulthp x   %s *synth2 |943 | \bus_status_ctrl.gf_scl |glitch_filter_1609 | 18| 2default:defaulthp x   %s *synth2 |944 | \bus_status_ctrl.gf_sda |glitch_filter_1610 | 20| 2default:defaulthp x   %s *synth2 |945 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1557 | 332| 2default:defaulthp x   %s *synth2 |946 | i2c_master |i2c_master_usr_1601 | 332| 2default:defaulthp x   %s *synth2 |947 | byte_ctrl |i2c_master_byte_ctrl_1602 | 279| 2default:defaulthp x   %s *synth2 |948 | bit_ctrl |i2c_master_bit_ctrl_1603 | 224| 2default:defaulthp x   %s *synth2 |949 | \bus_status_ctrl.gf_scl |glitch_filter_1604 | 18| 2default:defaulthp x   %s *synth2 |950 | \bus_status_ctrl.gf_sda |glitch_filter_1605 | 20| 2default:defaulthp x   %s *synth2 |951 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1558 | 332| 2default:defaulthp x   %s *synth2 |952 | i2c_master |i2c_master_usr_1596 | 332| 2default:defaulthp x   %s *synth2 |953 | byte_ctrl |i2c_master_byte_ctrl_1597 | 279| 2default:defaulthp x   %s *synth2 |954 | bit_ctrl |i2c_master_bit_ctrl_1598 | 224| 2default:defaulthp x   %s *synth2 |955 | \bus_status_ctrl.gf_scl |glitch_filter_1599 | 18| 2default:defaulthp x   %s *synth2 |956 | \bus_status_ctrl.gf_sda |glitch_filter_1600 | 20| 2default:defaulthp x   %s *synth2 |957 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1559 | 332| 2default:defaulthp x   %s *synth2 |958 | i2c_master |i2c_master_usr_1591 | 332| 2default:defaulthp x   %s *synth2 |959 | byte_ctrl |i2c_master_byte_ctrl_1592 | 279| 2default:defaulthp x   %s *synth2 |960 | bit_ctrl |i2c_master_bit_ctrl_1593 | 224| 2default:defaulthp x   %s *synth2 |961 | \bus_status_ctrl.gf_scl |glitch_filter_1594 | 18| 2default:defaulthp x   %s *synth2 |962 | \bus_status_ctrl.gf_sda |glitch_filter_1595 | 20| 2default:defaulthp x   %s *synth2 |963 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1560 | 332| 2default:defaulthp x   %s *synth2 |964 | i2c_master |i2c_master_usr_1586 | 332| 2default:defaulthp x   %s *synth2 |965 | byte_ctrl |i2c_master_byte_ctrl_1587 | 279| 2default:defaulthp x   %s *synth2 |966 | bit_ctrl |i2c_master_bit_ctrl_1588 | 224| 2default:defaulthp x   %s *synth2 |967 | \bus_status_ctrl.gf_scl |glitch_filter_1589 | 18| 2default:defaulthp x   %s *synth2 |968 | \bus_status_ctrl.gf_sda |glitch_filter_1590 | 20| 2default:defaulthp x   %s *synth2 |969 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1561 | 332| 2default:defaulthp x   %s *synth2 |970 | i2c_master |i2c_master_usr_1581 | 332| 2default:defaulthp x   %s *synth2 |971 | byte_ctrl |i2c_master_byte_ctrl_1582 | 279| 2default:defaulthp x   %s *synth2 |972 | bit_ctrl |i2c_master_bit_ctrl_1583 | 224| 2default:defaulthp x   %s *synth2 |973 | \bus_status_ctrl.gf_scl |glitch_filter_1584 | 18| 2default:defaulthp x   %s *synth2 |974 | \bus_status_ctrl.gf_sda |glitch_filter_1585 | 20| 2default:defaulthp x   %s *synth2 |975 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1562 | 332| 2default:defaulthp x   %s *synth2 |976 | i2c_master |i2c_master_usr_1576 | 332| 2default:defaulthp x   %s *synth2 |977 | byte_ctrl |i2c_master_byte_ctrl_1577 | 279| 2default:defaulthp x   %s *synth2 |978 | bit_ctrl |i2c_master_bit_ctrl_1578 | 224| 2default:defaulthp x   %s *synth2 |979 | \bus_status_ctrl.gf_scl |glitch_filter_1579 | 18| 2default:defaulthp x   %s *synth2 |980 | \bus_status_ctrl.gf_sda |glitch_filter_1580 | 20| 2default:defaulthp x   %s *synth2 |981 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1563 | 332| 2default:defaulthp x   %s *synth2 |982 | i2c_master |i2c_master_usr_1571 | 332| 2default:defaulthp x   %s *synth2 |983 | byte_ctrl |i2c_master_byte_ctrl_1572 | 279| 2default:defaulthp x   %s *synth2 |984 | bit_ctrl |i2c_master_bit_ctrl_1573 | 224| 2default:defaulthp x   %s *synth2 |985 | \bus_status_ctrl.gf_scl |glitch_filter_1574 | 18| 2default:defaulthp x   %s *synth2 |986 | \bus_status_ctrl.gf_sda |glitch_filter_1575 | 20| 2default:defaulthp x   %s *synth2 |987 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1564 | 331| 2default:defaulthp x   %s *synth2 |988 | i2c_master |i2c_master_usr_1566 | 331| 2default:defaulthp x   %s *synth2 |989 | byte_ctrl |i2c_master_byte_ctrl_1567 | 279| 2default:defaulthp x   %s *synth2 |990 | bit_ctrl |i2c_master_bit_ctrl_1568 | 224| 2default:defaulthp x   %s *synth2 |991 | \bus_status_ctrl.gf_scl |glitch_filter_1569 | 18| 2default:defaulthp x   %s *synth2 |992 | \bus_status_ctrl.gf_sda |glitch_filter_1570 | 20| 2default:defaulthp x   %s *synth2 |993 | prbs |prbs_1565 | 25| 2default:defaulthp x   %s *synth2 |994 | \SFP_GEN[2].ngFEC_module |ngFEC_module_10 | 15549| 2default:defaulthp x   %s *synth2 |995 | bkp_buffer_ngccm |buffer_ngccm_com_1457 | 511| 2default:defaulthp x   %s *synth2 |996 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1458 | 281| 2default:defaulthp x   %s *synth2 |997 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1544 | 194| 2default:defaulthp x   %s *synth2 |998 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1545 | 20| 2default:defaulthp x   %s *synth2 |999 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1546 | 24| 2default:defaulthp x   %s *synth2 |1000 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1459 | 168| 2default:defaulthp x   %s *synth2 |1001 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1460 | 257| 2default:defaulthp x   %s *synth2 |1002 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1541 | 167| 2default:defaulthp x   %s *synth2 |1003 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1542 | 18| 2default:defaulthp x   %s *synth2 |1004 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1543 | 29| 2default:defaulthp x   %s *synth2 |1005 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1461 | 166| 2default:defaulthp x   %s *synth2 |1006 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1462 | 257| 2default:defaulthp x   %s *synth2 |1007 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1538 | 167| 2default:defaulthp x   %s *synth2 |1008 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1539 | 18| 2default:defaulthp x   %s *synth2 |1009 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1540 | 29| 2default:defaulthp x   %s *synth2 |1010 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1463 | 166| 2default:defaulthp x   %s *synth2 |1011 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1464 | 280| 2default:defaulthp x   %s *synth2 |1012 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1535 | 188| 2default:defaulthp x   %s *synth2 |1013 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1536 | 20| 2default:defaulthp x   %s *synth2 |1014 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1537 | 29| 2default:defaulthp x   %s *synth2 |1015 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1465 | 264| 2default:defaulthp x   %s *synth2 |1016 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1466 | 134| 2default:defaulthp x   %s *synth2 |1017 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1532 | 69| 2default:defaulthp x   %s *synth2 |1018 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1533 | 20| 2default:defaulthp x   %s *synth2 |1019 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1534 | 18| 2default:defaulthp x   %s *synth2 |1020 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1467 | 133| 2default:defaulthp x   %s *synth2 |1021 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1468 | 280| 2default:defaulthp x   %s *synth2 |1022 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1529 | 188| 2default:defaulthp x   %s *synth2 |1023 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1530 | 20| 2default:defaulthp x   %s *synth2 |1024 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1531 | 29| 2default:defaulthp x   %s *synth2 |1025 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1469 | 168| 2default:defaulthp x   %s *synth2 |1026 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1470 | 257| 2default:defaulthp x   %s *synth2 |1027 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1526 | 167| 2default:defaulthp x   %s *synth2 |1028 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1527 | 18| 2default:defaulthp x   %s *synth2 |1029 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1528 | 29| 2default:defaulthp x   %s *synth2 |1030 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1471 | 198| 2default:defaulthp x   %s *synth2 |1031 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1472 | 280| 2default:defaulthp x   %s *synth2 |1032 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1523 | 188| 2default:defaulthp x   %s *synth2 |1033 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1524 | 20| 2default:defaulthp x   %s *synth2 |1034 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1525 | 29| 2default:defaulthp x   %s *synth2 |1035 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1473 | 168| 2default:defaulthp x   %s *synth2 |1036 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1474 | 280| 2default:defaulthp x   %s *synth2 |1037 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1520 | 188| 2default:defaulthp x   %s *synth2 |1038 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1521 | 20| 2default:defaulthp x   %s *synth2 |1039 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1522 | 29| 2default:defaulthp x   %s *synth2 |1040 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1475 | 167| 2default:defaulthp x   %s *synth2 |1041 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1476 | 280| 2default:defaulthp x   %s *synth2 |1042 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1517 | 188| 2default:defaulthp x   %s *synth2 |1043 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1518 | 20| 2default:defaulthp x   %s *synth2 |1044 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1519 | 29| 2default:defaulthp x   %s *synth2 |1045 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1477 | 168| 2default:defaulthp x   %s *synth2 |1046 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1478 | 280| 2default:defaulthp x   %s *synth2 |1047 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1514 | 188| 2default:defaulthp x   %s *synth2 |1048 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1515 | 20| 2default:defaulthp x   %s *synth2 |1049 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1516 | 29| 2default:defaulthp x   %s *synth2 |1050 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1479 | 234| 2default:defaulthp x   %s *synth2 |1051 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1480 | 257| 2default:defaulthp x   %s *synth2 |1052 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1511 | 167| 2default:defaulthp x   %s *synth2 |1053 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1512 | 18| 2default:defaulthp x   %s *synth2 |1054 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1513 | 29| 2default:defaulthp x   %s *synth2 |1055 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1481 | 166| 2default:defaulthp x   %s *synth2 |1056 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1482 | 257| 2default:defaulthp x   %s *synth2 |1057 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1508 | 167| 2default:defaulthp x   %s *synth2 |1058 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1509 | 18| 2default:defaulthp x   %s *synth2 |1059 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1510 | 29| 2default:defaulthp x   %s *synth2 |1060 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1483 | 166| 2default:defaulthp x   %s *synth2 |1061 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1484 | 257| 2default:defaulthp x   %s *synth2 |1062 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1505 | 167| 2default:defaulthp x   %s *synth2 |1063 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1506 | 18| 2default:defaulthp x   %s *synth2 |1064 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1507 | 29| 2default:defaulthp x   %s *synth2 |1065 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1485 | 165| 2default:defaulthp x   %s *synth2 |1066 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1486 | 257| 2default:defaulthp x   %s *synth2 |1067 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1502 | 167| 2default:defaulthp x   %s *synth2 |1068 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1503 | 18| 2default:defaulthp x   %s *synth2 |1069 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1504 | 29| 2default:defaulthp x   %s *synth2 |1070 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1487 | 198| 2default:defaulthp x   %s *synth2 |1071 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1488 | 662| 2default:defaulthp x   %s *synth2 |1072 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1489 | 510| 2default:defaulthp x   %s *synth2 |1073 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1490 | 535| 2default:defaulthp x   %s *synth2 |1074 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1491 | 535| 2default:defaulthp x   %s *synth2 |1075 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1492 | 511| 2default:defaulthp x   %s *synth2 |1076 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1493 | 535| 2default:defaulthp x   %s *synth2 |1077 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1494 | 511| 2default:defaulthp x   %s *synth2 |1078 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1495 | 511| 2default:defaulthp x   %s *synth2 |1079 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1496 | 511| 2default:defaulthp x   %s *synth2 |1080 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1497 | 511| 2default:defaulthp x   %s *synth2 |1081 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1498 | 535| 2default:defaulthp x   %s *synth2 |1082 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1499 | 535| 2default:defaulthp x   %s *synth2 |1083 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1500 | 535| 2default:defaulthp x   %s *synth2 |1084 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1501 | 535| 2default:defaulthp x   %s *synth2 |1085 | \SFP_GEN[3].QIE_RESET_DELAY |delay_counter_11 | 40| 2default:defaulthp x   %s *synth2 |1086 | \SFP_GEN[3].ngCCM_gbt |ngCCM__xdcDup__3 | 8153| 2default:defaulthp x   %s *synth2 |1087 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__31 | 104| 2default:defaulthp x   %s *synth2 |1088 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__334 | 4| 2default:defaulthp x   %s *synth2 |1089 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__32 | 104| 2default:defaulthp x   %s *synth2 |1090 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__333 | 4| 2default:defaulthp x   %s *synth2 |1091 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__33 | 104| 2default:defaulthp x   %s *synth2 |1092 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__332 | 4| 2default:defaulthp x   %s *synth2 |1093 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__34 | 104| 2default:defaulthp x   %s *synth2 |1094 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__331 | 4| 2default:defaulthp x   %s *synth2 |1095 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__35 | 104| 2default:defaulthp x   %s *synth2 |1096 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__330 | 4| 2default:defaulthp x   %s *synth2 |1097 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__36 | 104| 2default:defaulthp x   %s *synth2 |1098 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__329 | 4| 2default:defaulthp x   %s *synth2 |1099 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__37 | 104| 2default:defaulthp x   %s *synth2 |1100 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__328 | 4| 2default:defaulthp x   %s *synth2 |1101 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__38 | 104| 2default:defaulthp x   %s *synth2 |1102 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__327 | 4| 2default:defaulthp x   %s *synth2 |1103 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__39 | 104| 2default:defaulthp x   %s *synth2 |1104 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__326 | 4| 2default:defaulthp x   %s *synth2 |1105 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__40 | 104| 2default:defaulthp x   %s *synth2 |1106 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__325 | 4| 2default:defaulthp x   %s *synth2 |1107 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__41 | 104| 2default:defaulthp x   %s *synth2 |1108 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__324 | 4| 2default:defaulthp x   %s *synth2 |1109 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__42 | 104| 2default:defaulthp x   %s *synth2 |1110 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__323 | 4| 2default:defaulthp x   %s *synth2 |1111 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__43 | 104| 2default:defaulthp x   %s *synth2 |1112 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__322 | 4| 2default:defaulthp x   %s *synth2 |1113 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__44 | 104| 2default:defaulthp x   %s *synth2 |1114 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__321 | 4| 2default:defaulthp x   %s *synth2 |1115 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__45 | 104| 2default:defaulthp x   %s *synth2 |1116 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__320 | 4| 2default:defaulthp x   %s *synth2 |1117 | CrossClock_DV_cnt |CrossClock_RX_1372 | 70| 2default:defaulthp x   %s *synth2 |1118 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__3 | 629| 2default:defaulthp x   %s *synth2 |1119 | JTAGMaster_inst |JTAGMaster__xdcDup__3 | 462| 2default:defaulthp x   %s *synth2 |1120 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__335 | 4| 2default:defaulthp x   %s *synth2 |1121 | JTAG_BRAM |RAM_1456 | 117| 2default:defaulthp x   %s *synth2 |1122 | Sync_RX_Reset |Sync_1373 | 2| 2default:defaulthp x   %s *synth2 |1123 | Sync_TX_Reset |Sync_1374 | 114| 2default:defaulthp x   %s *synth2 |1124 | Sync_error_counter_reset |Sync_1375 | 2| 2default:defaulthp x   %s *synth2 |1125 | gbt_rx_checker |gbt_rx_checker_1376 | 106| 2default:defaulthp x   %s *synth2 |1126 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1377 | 332| 2default:defaulthp x   %s *synth2 |1127 | i2c_master |i2c_master_usr_1451 | 332| 2default:defaulthp x   %s *synth2 |1128 | byte_ctrl |i2c_master_byte_ctrl_1452 | 279| 2default:defaulthp x   %s *synth2 |1129 | bit_ctrl |i2c_master_bit_ctrl_1453 | 224| 2default:defaulthp x   %s *synth2 |1130 | \bus_status_ctrl.gf_scl |glitch_filter_1454 | 18| 2default:defaulthp x   %s *synth2 |1131 | \bus_status_ctrl.gf_sda |glitch_filter_1455 | 20| 2default:defaulthp x   %s *synth2 |1132 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1378 | 332| 2default:defaulthp x   %s *synth2 |1133 | i2c_master |i2c_master_usr_1446 | 332| 2default:defaulthp x   %s *synth2 |1134 | byte_ctrl |i2c_master_byte_ctrl_1447 | 279| 2default:defaulthp x   %s *synth2 |1135 | bit_ctrl |i2c_master_bit_ctrl_1448 | 224| 2default:defaulthp x   %s *synth2 |1136 | \bus_status_ctrl.gf_scl |glitch_filter_1449 | 18| 2default:defaulthp x   %s *synth2 |1137 | \bus_status_ctrl.gf_sda |glitch_filter_1450 | 20| 2default:defaulthp x   %s *synth2 |1138 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1379 | 332| 2default:defaulthp x   %s *synth2 |1139 | i2c_master |i2c_master_usr_1441 | 332| 2default:defaulthp x   %s *synth2 |1140 | byte_ctrl |i2c_master_byte_ctrl_1442 | 279| 2default:defaulthp x   %s *synth2 |1141 | bit_ctrl |i2c_master_bit_ctrl_1443 | 224| 2default:defaulthp x   %s *synth2 |1142 | \bus_status_ctrl.gf_scl |glitch_filter_1444 | 18| 2default:defaulthp x   %s *synth2 |1143 | \bus_status_ctrl.gf_sda |glitch_filter_1445 | 20| 2default:defaulthp x   %s *synth2 |1144 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1380 | 332| 2default:defaulthp x   %s *synth2 |1145 | i2c_master |i2c_master_usr_1436 | 332| 2default:defaulthp x   %s *synth2 |1146 | byte_ctrl |i2c_master_byte_ctrl_1437 | 279| 2default:defaulthp x   %s *synth2 |1147 | bit_ctrl |i2c_master_bit_ctrl_1438 | 224| 2default:defaulthp x   %s *synth2 |1148 | \bus_status_ctrl.gf_scl |glitch_filter_1439 | 18| 2default:defaulthp x   %s *synth2 |1149 | \bus_status_ctrl.gf_sda |glitch_filter_1440 | 20| 2default:defaulthp x   %s *synth2 |1150 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1381 | 332| 2default:defaulthp x   %s *synth2 |1151 | i2c_master |i2c_master_usr_1431 | 332| 2default:defaulthp x   %s *synth2 |1152 | byte_ctrl |i2c_master_byte_ctrl_1432 | 279| 2default:defaulthp x   %s *synth2 |1153 | bit_ctrl |i2c_master_bit_ctrl_1433 | 224| 2default:defaulthp x   %s *synth2 |1154 | \bus_status_ctrl.gf_scl |glitch_filter_1434 | 18| 2default:defaulthp x   %s *synth2 |1155 | \bus_status_ctrl.gf_sda |glitch_filter_1435 | 20| 2default:defaulthp x   %s *synth2 |1156 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1382 | 332| 2default:defaulthp x   %s *synth2 |1157 | i2c_master |i2c_master_usr_1426 | 332| 2default:defaulthp x   %s *synth2 |1158 | byte_ctrl |i2c_master_byte_ctrl_1427 | 279| 2default:defaulthp x   %s *synth2 |1159 | bit_ctrl |i2c_master_bit_ctrl_1428 | 224| 2default:defaulthp x   %s *synth2 |1160 | \bus_status_ctrl.gf_scl |glitch_filter_1429 | 18| 2default:defaulthp x   %s *synth2 |1161 | \bus_status_ctrl.gf_sda |glitch_filter_1430 | 20| 2default:defaulthp x   %s *synth2 |1162 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1383 | 332| 2default:defaulthp x   %s *synth2 |1163 | i2c_master |i2c_master_usr_1421 | 332| 2default:defaulthp x   %s *synth2 |1164 | byte_ctrl |i2c_master_byte_ctrl_1422 | 279| 2default:defaulthp x   %s *synth2 |1165 | bit_ctrl |i2c_master_bit_ctrl_1423 | 224| 2default:defaulthp x   %s *synth2 |1166 | \bus_status_ctrl.gf_scl |glitch_filter_1424 | 18| 2default:defaulthp x   %s *synth2 |1167 | \bus_status_ctrl.gf_sda |glitch_filter_1425 | 20| 2default:defaulthp x   %s *synth2 |1168 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1384 | 332| 2default:defaulthp x   %s *synth2 |1169 | i2c_master |i2c_master_usr_1416 | 332| 2default:defaulthp x   %s *synth2 |1170 | byte_ctrl |i2c_master_byte_ctrl_1417 | 279| 2default:defaulthp x   %s *synth2 |1171 | bit_ctrl |i2c_master_bit_ctrl_1418 | 224| 2default:defaulthp x   %s *synth2 |1172 | \bus_status_ctrl.gf_scl |glitch_filter_1419 | 18| 2default:defaulthp x   %s *synth2 |1173 | \bus_status_ctrl.gf_sda |glitch_filter_1420 | 20| 2default:defaulthp x   %s *synth2 |1174 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1385 | 332| 2default:defaulthp x   %s *synth2 |1175 | i2c_master |i2c_master_usr_1411 | 332| 2default:defaulthp x   %s *synth2 |1176 | byte_ctrl |i2c_master_byte_ctrl_1412 | 279| 2default:defaulthp x   %s *synth2 |1177 | bit_ctrl |i2c_master_bit_ctrl_1413 | 224| 2default:defaulthp x   %s *synth2 |1178 | \bus_status_ctrl.gf_scl |glitch_filter_1414 | 18| 2default:defaulthp x   %s *synth2 |1179 | \bus_status_ctrl.gf_sda |glitch_filter_1415 | 20| 2default:defaulthp x   %s *synth2 |1180 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1386 | 332| 2default:defaulthp x   %s *synth2 |1181 | i2c_master |i2c_master_usr_1406 | 332| 2default:defaulthp x   %s *synth2 |1182 | byte_ctrl |i2c_master_byte_ctrl_1407 | 279| 2default:defaulthp x   %s *synth2 |1183 | bit_ctrl |i2c_master_bit_ctrl_1408 | 224| 2default:defaulthp x   %s *synth2 |1184 | \bus_status_ctrl.gf_scl |glitch_filter_1409 | 18| 2default:defaulthp x   %s *synth2 |1185 | \bus_status_ctrl.gf_sda |glitch_filter_1410 | 20| 2default:defaulthp x   %s *synth2 |1186 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1387 | 332| 2default:defaulthp x   %s *synth2 |1187 | i2c_master |i2c_master_usr_1401 | 332| 2default:defaulthp x   %s *synth2 |1188 | byte_ctrl |i2c_master_byte_ctrl_1402 | 279| 2default:defaulthp x   %s *synth2 |1189 | bit_ctrl |i2c_master_bit_ctrl_1403 | 224| 2default:defaulthp x   %s *synth2 |1190 | \bus_status_ctrl.gf_scl |glitch_filter_1404 | 18| 2default:defaulthp x   %s *synth2 |1191 | \bus_status_ctrl.gf_sda |glitch_filter_1405 | 20| 2default:defaulthp x   %s *synth2 |1192 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1388 | 332| 2default:defaulthp x   %s *synth2 |1193 | i2c_master |i2c_master_usr_1396 | 332| 2default:defaulthp x   %s *synth2 |1194 | byte_ctrl |i2c_master_byte_ctrl_1397 | 279| 2default:defaulthp x   %s *synth2 |1195 | bit_ctrl |i2c_master_bit_ctrl_1398 | 224| 2default:defaulthp x   %s *synth2 |1196 | \bus_status_ctrl.gf_scl |glitch_filter_1399 | 18| 2default:defaulthp x   %s *synth2 |1197 | \bus_status_ctrl.gf_sda |glitch_filter_1400 | 20| 2default:defaulthp x   %s *synth2 |1198 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1389 | 331| 2default:defaulthp x   %s *synth2 |1199 | i2c_master |i2c_master_usr_1391 | 331| 2default:defaulthp x   %s *synth2 |1200 | byte_ctrl |i2c_master_byte_ctrl_1392 | 279| 2default:defaulthp x   %s *synth2 |1201 | bit_ctrl |i2c_master_bit_ctrl_1393 | 224| 2default:defaulthp x   %s *synth2 |1202 | \bus_status_ctrl.gf_scl |glitch_filter_1394 | 18| 2default:defaulthp x   %s *synth2 |1203 | \bus_status_ctrl.gf_sda |glitch_filter_1395 | 20| 2default:defaulthp x   %s *synth2 |1204 | prbs |prbs_1390 | 25| 2default:defaulthp x   %s *synth2 |1205 | \SFP_GEN[3].ngFEC_module |ngFEC_module_12 | 15549| 2default:defaulthp x   %s *synth2 |1206 | bkp_buffer_ngccm |buffer_ngccm_com_1282 | 511| 2default:defaulthp x   %s *synth2 |1207 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1283 | 281| 2default:defaulthp x   %s *synth2 |1208 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1369 | 194| 2default:defaulthp x   %s *synth2 |1209 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1370 | 20| 2default:defaulthp x   %s *synth2 |1210 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1371 | 24| 2default:defaulthp x   %s *synth2 |1211 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1284 | 168| 2default:defaulthp x   %s *synth2 |1212 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1285 | 257| 2default:defaulthp x   %s *synth2 |1213 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1366 | 167| 2default:defaulthp x   %s *synth2 |1214 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1367 | 18| 2default:defaulthp x   %s *synth2 |1215 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1368 | 29| 2default:defaulthp x   %s *synth2 |1216 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1286 | 166| 2default:defaulthp x   %s *synth2 |1217 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1287 | 257| 2default:defaulthp x   %s *synth2 |1218 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1363 | 167| 2default:defaulthp x   %s *synth2 |1219 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1364 | 18| 2default:defaulthp x   %s *synth2 |1220 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1365 | 29| 2default:defaulthp x   %s *synth2 |1221 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1288 | 166| 2default:defaulthp x   %s *synth2 |1222 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1289 | 280| 2default:defaulthp x   %s *synth2 |1223 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1360 | 188| 2default:defaulthp x   %s *synth2 |1224 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1361 | 20| 2default:defaulthp x   %s *synth2 |1225 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1362 | 29| 2default:defaulthp x   %s *synth2 |1226 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1290 | 264| 2default:defaulthp x   %s *synth2 |1227 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1291 | 134| 2default:defaulthp x   %s *synth2 |1228 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1357 | 69| 2default:defaulthp x   %s *synth2 |1229 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1358 | 20| 2default:defaulthp x   %s *synth2 |1230 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1359 | 18| 2default:defaulthp x   %s *synth2 |1231 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1292 | 133| 2default:defaulthp x   %s *synth2 |1232 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1293 | 280| 2default:defaulthp x   %s *synth2 |1233 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1354 | 188| 2default:defaulthp x   %s *synth2 |1234 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1355 | 20| 2default:defaulthp x   %s *synth2 |1235 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1356 | 29| 2default:defaulthp x   %s *synth2 |1236 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1294 | 168| 2default:defaulthp x   %s *synth2 |1237 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1295 | 257| 2default:defaulthp x   %s *synth2 |1238 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1351 | 167| 2default:defaulthp x   %s *synth2 |1239 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1352 | 18| 2default:defaulthp x   %s *synth2 |1240 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1353 | 29| 2default:defaulthp x   %s *synth2 |1241 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1296 | 198| 2default:defaulthp x   %s *synth2 |1242 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1297 | 280| 2default:defaulthp x   %s *synth2 |1243 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1348 | 188| 2default:defaulthp x   %s *synth2 |1244 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1349 | 20| 2default:defaulthp x   %s *synth2 |1245 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1350 | 29| 2default:defaulthp x   %s *synth2 |1246 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1298 | 168| 2default:defaulthp x   %s *synth2 |1247 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1299 | 280| 2default:defaulthp x   %s *synth2 |1248 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1345 | 188| 2default:defaulthp x   %s *synth2 |1249 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1346 | 20| 2default:defaulthp x   %s *synth2 |1250 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1347 | 29| 2default:defaulthp x   %s *synth2 |1251 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1300 | 167| 2default:defaulthp x   %s *synth2 |1252 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1301 | 280| 2default:defaulthp x   %s *synth2 |1253 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1342 | 188| 2default:defaulthp x   %s *synth2 |1254 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1343 | 20| 2default:defaulthp x   %s *synth2 |1255 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1344 | 29| 2default:defaulthp x   %s *synth2 |1256 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1302 | 168| 2default:defaulthp x   %s *synth2 |1257 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1303 | 280| 2default:defaulthp x   %s *synth2 |1258 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1339 | 188| 2default:defaulthp x   %s *synth2 |1259 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1340 | 20| 2default:defaulthp x   %s *synth2 |1260 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1341 | 29| 2default:defaulthp x   %s *synth2 |1261 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1304 | 234| 2default:defaulthp x   %s *synth2 |1262 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1305 | 257| 2default:defaulthp x   %s *synth2 |1263 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1336 | 167| 2default:defaulthp x   %s *synth2 |1264 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1337 | 18| 2default:defaulthp x   %s *synth2 |1265 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1338 | 29| 2default:defaulthp x   %s *synth2 |1266 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1306 | 166| 2default:defaulthp x   %s *synth2 |1267 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1307 | 257| 2default:defaulthp x   %s *synth2 |1268 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1333 | 167| 2default:defaulthp x   %s *synth2 |1269 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1334 | 18| 2default:defaulthp x   %s *synth2 |1270 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1335 | 29| 2default:defaulthp x   %s *synth2 |1271 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1308 | 166| 2default:defaulthp x   %s *synth2 |1272 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1309 | 257| 2default:defaulthp x   %s *synth2 |1273 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1330 | 167| 2default:defaulthp x   %s *synth2 |1274 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1331 | 18| 2default:defaulthp x   %s *synth2 |1275 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1332 | 29| 2default:defaulthp x   %s *synth2 |1276 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1310 | 165| 2default:defaulthp x   %s *synth2 |1277 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1311 | 257| 2default:defaulthp x   %s *synth2 |1278 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1327 | 167| 2default:defaulthp x   %s *synth2 |1279 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1328 | 18| 2default:defaulthp x   %s *synth2 |1280 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1329 | 29| 2default:defaulthp x   %s *synth2 |1281 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1312 | 198| 2default:defaulthp x   %s *synth2 |1282 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1313 | 662| 2default:defaulthp x   %s *synth2 |1283 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1314 | 510| 2default:defaulthp x   %s *synth2 |1284 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1315 | 535| 2default:defaulthp x   %s *synth2 |1285 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1316 | 535| 2default:defaulthp x   %s *synth2 |1286 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1317 | 511| 2default:defaulthp x   %s *synth2 |1287 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1318 | 535| 2default:defaulthp x   %s *synth2 |1288 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1319 | 511| 2default:defaulthp x   %s *synth2 |1289 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1320 | 511| 2default:defaulthp x   %s *synth2 |1290 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1321 | 511| 2default:defaulthp x   %s *synth2 |1291 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1322 | 511| 2default:defaulthp x   %s *synth2 |1292 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1323 | 535| 2default:defaulthp x   %s *synth2 |1293 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1324 | 535| 2default:defaulthp x   %s *synth2 |1294 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1325 | 535| 2default:defaulthp x   %s *synth2 |1295 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1326 | 535| 2default:defaulthp x   %s *synth2 |1296 | \SFP_GEN[4].QIE_RESET_DELAY |delay_counter_13 | 40| 2default:defaulthp x   %s *synth2 |1297 | \SFP_GEN[4].ngCCM_gbt |ngCCM__xdcDup__4 | 8153| 2default:defaulthp x   %s *synth2 |1298 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__46 | 104| 2default:defaulthp x   %s *synth2 |1299 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__318 | 4| 2default:defaulthp x   %s *synth2 |1300 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__47 | 104| 2default:defaulthp x   %s *synth2 |1301 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__317 | 4| 2default:defaulthp x   %s *synth2 |1302 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__48 | 104| 2default:defaulthp x   %s *synth2 |1303 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__316 | 4| 2default:defaulthp x   %s *synth2 |1304 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__49 | 104| 2default:defaulthp x   %s *synth2 |1305 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__315 | 4| 2default:defaulthp x   %s *synth2 |1306 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__50 | 104| 2default:defaulthp x   %s *synth2 |1307 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__314 | 4| 2default:defaulthp x   %s *synth2 |1308 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__51 | 104| 2default:defaulthp x   %s *synth2 |1309 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__313 | 4| 2default:defaulthp x   %s *synth2 |1310 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__52 | 104| 2default:defaulthp x   %s *synth2 |1311 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__312 | 4| 2default:defaulthp x   %s *synth2 |1312 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__53 | 104| 2default:defaulthp x   %s *synth2 |1313 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__311 | 4| 2default:defaulthp x   %s *synth2 |1314 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__54 | 104| 2default:defaulthp x   %s *synth2 |1315 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__310 | 4| 2default:defaulthp x   %s *synth2 |1316 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__55 | 104| 2default:defaulthp x   %s *synth2 |1317 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__309 | 4| 2default:defaulthp x   %s *synth2 |1318 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__56 | 104| 2default:defaulthp x   %s *synth2 |1319 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__308 | 4| 2default:defaulthp x   %s *synth2 |1320 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__57 | 104| 2default:defaulthp x   %s *synth2 |1321 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__307 | 4| 2default:defaulthp x   %s *synth2 |1322 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__58 | 104| 2default:defaulthp x   %s *synth2 |1323 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__306 | 4| 2default:defaulthp x   %s *synth2 |1324 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__59 | 104| 2default:defaulthp x   %s *synth2 |1325 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__305 | 4| 2default:defaulthp x   %s *synth2 |1326 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__60 | 104| 2default:defaulthp x   %s *synth2 |1327 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__304 | 4| 2default:defaulthp x   %s *synth2 |1328 | CrossClock_DV_cnt |CrossClock_RX_1197 | 70| 2default:defaulthp x   %s *synth2 |1329 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__4 | 629| 2default:defaulthp x   %s *synth2 |1330 | JTAGMaster_inst |JTAGMaster__xdcDup__4 | 462| 2default:defaulthp x   %s *synth2 |1331 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__319 | 4| 2default:defaulthp x   %s *synth2 |1332 | JTAG_BRAM |RAM_1281 | 117| 2default:defaulthp x   %s *synth2 |1333 | Sync_RX_Reset |Sync_1198 | 2| 2default:defaulthp x   %s *synth2 |1334 | Sync_TX_Reset |Sync_1199 | 114| 2default:defaulthp x   %s *synth2 |1335 | Sync_error_counter_reset |Sync_1200 | 2| 2default:defaulthp x   %s *synth2 |1336 | gbt_rx_checker |gbt_rx_checker_1201 | 106| 2default:defaulthp x   %s *synth2 |1337 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1202 | 332| 2default:defaulthp x   %s *synth2 |1338 | i2c_master |i2c_master_usr_1276 | 332| 2default:defaulthp x   %s *synth2 |1339 | byte_ctrl |i2c_master_byte_ctrl_1277 | 279| 2default:defaulthp x   %s *synth2 |1340 | bit_ctrl |i2c_master_bit_ctrl_1278 | 224| 2default:defaulthp x   %s *synth2 |1341 | \bus_status_ctrl.gf_scl |glitch_filter_1279 | 18| 2default:defaulthp x   %s *synth2 |1342 | \bus_status_ctrl.gf_sda |glitch_filter_1280 | 20| 2default:defaulthp x   %s *synth2 |1343 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1203 | 332| 2default:defaulthp x   %s *synth2 |1344 | i2c_master |i2c_master_usr_1271 | 332| 2default:defaulthp x   %s *synth2 |1345 | byte_ctrl |i2c_master_byte_ctrl_1272 | 279| 2default:defaulthp x   %s *synth2 |1346 | bit_ctrl |i2c_master_bit_ctrl_1273 | 224| 2default:defaulthp x   %s *synth2 |1347 | \bus_status_ctrl.gf_scl |glitch_filter_1274 | 18| 2default:defaulthp x   %s *synth2 |1348 | \bus_status_ctrl.gf_sda |glitch_filter_1275 | 20| 2default:defaulthp x   %s *synth2 |1349 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1204 | 332| 2default:defaulthp x   %s *synth2 |1350 | i2c_master |i2c_master_usr_1266 | 332| 2default:defaulthp x   %s *synth2 |1351 | byte_ctrl |i2c_master_byte_ctrl_1267 | 279| 2default:defaulthp x   %s *synth2 |1352 | bit_ctrl |i2c_master_bit_ctrl_1268 | 224| 2default:defaulthp x   %s *synth2 |1353 | \bus_status_ctrl.gf_scl |glitch_filter_1269 | 18| 2default:defaulthp x   %s *synth2 |1354 | \bus_status_ctrl.gf_sda |glitch_filter_1270 | 20| 2default:defaulthp x   %s *synth2 |1355 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1205 | 332| 2default:defaulthp x   %s *synth2 |1356 | i2c_master |i2c_master_usr_1261 | 332| 2default:defaulthp x   %s *synth2 |1357 | byte_ctrl |i2c_master_byte_ctrl_1262 | 279| 2default:defaulthp x   %s *synth2 |1358 | bit_ctrl |i2c_master_bit_ctrl_1263 | 224| 2default:defaulthp x   %s *synth2 |1359 | \bus_status_ctrl.gf_scl |glitch_filter_1264 | 18| 2default:defaulthp x   %s *synth2 |1360 | \bus_status_ctrl.gf_sda |glitch_filter_1265 | 20| 2default:defaulthp x   %s *synth2 |1361 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1206 | 332| 2default:defaulthp x   %s *synth2 |1362 | i2c_master |i2c_master_usr_1256 | 332| 2default:defaulthp x   %s *synth2 |1363 | byte_ctrl |i2c_master_byte_ctrl_1257 | 279| 2default:defaulthp x   %s *synth2 |1364 | bit_ctrl |i2c_master_bit_ctrl_1258 | 224| 2default:defaulthp x   %s *synth2 |1365 | \bus_status_ctrl.gf_scl |glitch_filter_1259 | 18| 2default:defaulthp x   %s *synth2 |1366 | \bus_status_ctrl.gf_sda |glitch_filter_1260 | 20| 2default:defaulthp x   %s *synth2 |1367 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1207 | 332| 2default:defaulthp x   %s *synth2 |1368 | i2c_master |i2c_master_usr_1251 | 332| 2default:defaulthp x   %s *synth2 |1369 | byte_ctrl |i2c_master_byte_ctrl_1252 | 279| 2default:defaulthp x   %s *synth2 |1370 | bit_ctrl |i2c_master_bit_ctrl_1253 | 224| 2default:defaulthp x   %s *synth2 |1371 | \bus_status_ctrl.gf_scl |glitch_filter_1254 | 18| 2default:defaulthp x   %s *synth2 |1372 | \bus_status_ctrl.gf_sda |glitch_filter_1255 | 20| 2default:defaulthp x   %s *synth2 |1373 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1208 | 332| 2default:defaulthp x   %s *synth2 |1374 | i2c_master |i2c_master_usr_1246 | 332| 2default:defaulthp x   %s *synth2 |1375 | byte_ctrl |i2c_master_byte_ctrl_1247 | 279| 2default:defaulthp x   %s *synth2 |1376 | bit_ctrl |i2c_master_bit_ctrl_1248 | 224| 2default:defaulthp x   %s *synth2 |1377 | \bus_status_ctrl.gf_scl |glitch_filter_1249 | 18| 2default:defaulthp x   %s *synth2 |1378 | \bus_status_ctrl.gf_sda |glitch_filter_1250 | 20| 2default:defaulthp x   %s *synth2 |1379 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1209 | 332| 2default:defaulthp x   %s *synth2 |1380 | i2c_master |i2c_master_usr_1241 | 332| 2default:defaulthp x   %s *synth2 |1381 | byte_ctrl |i2c_master_byte_ctrl_1242 | 279| 2default:defaulthp x   %s *synth2 |1382 | bit_ctrl |i2c_master_bit_ctrl_1243 | 224| 2default:defaulthp x   %s *synth2 |1383 | \bus_status_ctrl.gf_scl |glitch_filter_1244 | 18| 2default:defaulthp x   %s *synth2 |1384 | \bus_status_ctrl.gf_sda |glitch_filter_1245 | 20| 2default:defaulthp x   %s *synth2 |1385 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1210 | 332| 2default:defaulthp x   %s *synth2 |1386 | i2c_master |i2c_master_usr_1236 | 332| 2default:defaulthp x   %s *synth2 |1387 | byte_ctrl |i2c_master_byte_ctrl_1237 | 279| 2default:defaulthp x   %s *synth2 |1388 | bit_ctrl |i2c_master_bit_ctrl_1238 | 224| 2default:defaulthp x   %s *synth2 |1389 | \bus_status_ctrl.gf_scl |glitch_filter_1239 | 18| 2default:defaulthp x   %s *synth2 |1390 | \bus_status_ctrl.gf_sda |glitch_filter_1240 | 20| 2default:defaulthp x   %s *synth2 |1391 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1211 | 332| 2default:defaulthp x   %s *synth2 |1392 | i2c_master |i2c_master_usr_1231 | 332| 2default:defaulthp x   %s *synth2 |1393 | byte_ctrl |i2c_master_byte_ctrl_1232 | 279| 2default:defaulthp x   %s *synth2 |1394 | bit_ctrl |i2c_master_bit_ctrl_1233 | 224| 2default:defaulthp x   %s *synth2 |1395 | \bus_status_ctrl.gf_scl |glitch_filter_1234 | 18| 2default:defaulthp x   %s *synth2 |1396 | \bus_status_ctrl.gf_sda |glitch_filter_1235 | 20| 2default:defaulthp x   %s *synth2 |1397 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1212 | 332| 2default:defaulthp x   %s *synth2 |1398 | i2c_master |i2c_master_usr_1226 | 332| 2default:defaulthp x   %s *synth2 |1399 | byte_ctrl |i2c_master_byte_ctrl_1227 | 279| 2default:defaulthp x   %s *synth2 |1400 | bit_ctrl |i2c_master_bit_ctrl_1228 | 224| 2default:defaulthp x   %s *synth2 |1401 | \bus_status_ctrl.gf_scl |glitch_filter_1229 | 18| 2default:defaulthp x   %s *synth2 |1402 | \bus_status_ctrl.gf_sda |glitch_filter_1230 | 20| 2default:defaulthp x   %s *synth2 |1403 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1213 | 332| 2default:defaulthp x   %s *synth2 |1404 | i2c_master |i2c_master_usr_1221 | 332| 2default:defaulthp x   %s *synth2 |1405 | byte_ctrl |i2c_master_byte_ctrl_1222 | 279| 2default:defaulthp x   %s *synth2 |1406 | bit_ctrl |i2c_master_bit_ctrl_1223 | 224| 2default:defaulthp x   %s *synth2 |1407 | \bus_status_ctrl.gf_scl |glitch_filter_1224 | 18| 2default:defaulthp x   %s *synth2 |1408 | \bus_status_ctrl.gf_sda |glitch_filter_1225 | 20| 2default:defaulthp x   %s *synth2 |1409 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1214 | 331| 2default:defaulthp x   %s *synth2 |1410 | i2c_master |i2c_master_usr_1216 | 331| 2default:defaulthp x   %s *synth2 |1411 | byte_ctrl |i2c_master_byte_ctrl_1217 | 279| 2default:defaulthp x   %s *synth2 |1412 | bit_ctrl |i2c_master_bit_ctrl_1218 | 224| 2default:defaulthp x   %s *synth2 |1413 | \bus_status_ctrl.gf_scl |glitch_filter_1219 | 18| 2default:defaulthp x   %s *synth2 |1414 | \bus_status_ctrl.gf_sda |glitch_filter_1220 | 20| 2default:defaulthp x   %s *synth2 |1415 | prbs |prbs_1215 | 25| 2default:defaulthp x   %s *synth2 |1416 | \SFP_GEN[4].ngFEC_module |ngFEC_module_14 | 15549| 2default:defaulthp x   %s *synth2 |1417 | bkp_buffer_ngccm |buffer_ngccm_com_1107 | 511| 2default:defaulthp x   %s *synth2 |1418 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1108 | 281| 2default:defaulthp x   %s *synth2 |1419 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1194 | 194| 2default:defaulthp x   %s *synth2 |1420 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1195 | 20| 2default:defaulthp x   %s *synth2 |1421 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1196 | 24| 2default:defaulthp x   %s *synth2 |1422 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1109 | 168| 2default:defaulthp x   %s *synth2 |1423 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1110 | 257| 2default:defaulthp x   %s *synth2 |1424 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1191 | 167| 2default:defaulthp x   %s *synth2 |1425 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1192 | 18| 2default:defaulthp x   %s *synth2 |1426 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1193 | 29| 2default:defaulthp x   %s *synth2 |1427 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1111 | 166| 2default:defaulthp x   %s *synth2 |1428 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1112 | 257| 2default:defaulthp x   %s *synth2 |1429 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1188 | 167| 2default:defaulthp x   %s *synth2 |1430 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1189 | 18| 2default:defaulthp x   %s *synth2 |1431 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1190 | 29| 2default:defaulthp x   %s *synth2 |1432 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1113 | 166| 2default:defaulthp x   %s *synth2 |1433 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1114 | 280| 2default:defaulthp x   %s *synth2 |1434 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1185 | 188| 2default:defaulthp x   %s *synth2 |1435 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1186 | 20| 2default:defaulthp x   %s *synth2 |1436 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1187 | 29| 2default:defaulthp x   %s *synth2 |1437 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1115 | 264| 2default:defaulthp x   %s *synth2 |1438 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1116 | 134| 2default:defaulthp x   %s *synth2 |1439 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1182 | 69| 2default:defaulthp x   %s *synth2 |1440 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1183 | 20| 2default:defaulthp x   %s *synth2 |1441 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1184 | 18| 2default:defaulthp x   %s *synth2 |1442 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1117 | 133| 2default:defaulthp x   %s *synth2 |1443 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1118 | 280| 2default:defaulthp x   %s *synth2 |1444 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1179 | 188| 2default:defaulthp x   %s *synth2 |1445 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1180 | 20| 2default:defaulthp x   %s *synth2 |1446 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1181 | 29| 2default:defaulthp x   %s *synth2 |1447 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1119 | 168| 2default:defaulthp x   %s *synth2 |1448 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1120 | 257| 2default:defaulthp x   %s *synth2 |1449 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1176 | 167| 2default:defaulthp x   %s *synth2 |1450 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1177 | 18| 2default:defaulthp x   %s *synth2 |1451 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1178 | 29| 2default:defaulthp x   %s *synth2 |1452 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1121 | 198| 2default:defaulthp x   %s *synth2 |1453 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1122 | 280| 2default:defaulthp x   %s *synth2 |1454 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1173 | 188| 2default:defaulthp x   %s *synth2 |1455 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1174 | 20| 2default:defaulthp x   %s *synth2 |1456 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1175 | 29| 2default:defaulthp x   %s *synth2 |1457 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1123 | 168| 2default:defaulthp x   %s *synth2 |1458 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1124 | 280| 2default:defaulthp x   %s *synth2 |1459 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1170 | 188| 2default:defaulthp x   %s *synth2 |1460 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1171 | 20| 2default:defaulthp x   %s *synth2 |1461 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1172 | 29| 2default:defaulthp x   %s *synth2 |1462 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1125 | 167| 2default:defaulthp x   %s *synth2 |1463 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1126 | 280| 2default:defaulthp x   %s *synth2 |1464 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1167 | 188| 2default:defaulthp x   %s *synth2 |1465 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1168 | 20| 2default:defaulthp x   %s *synth2 |1466 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1169 | 29| 2default:defaulthp x   %s *synth2 |1467 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1127 | 168| 2default:defaulthp x   %s *synth2 |1468 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1128 | 280| 2default:defaulthp x   %s *synth2 |1469 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1164 | 188| 2default:defaulthp x   %s *synth2 |1470 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1165 | 20| 2default:defaulthp x   %s *synth2 |1471 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1166 | 29| 2default:defaulthp x   %s *synth2 |1472 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1129 | 234| 2default:defaulthp x   %s *synth2 |1473 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1130 | 257| 2default:defaulthp x   %s *synth2 |1474 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1161 | 167| 2default:defaulthp x   %s *synth2 |1475 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1162 | 18| 2default:defaulthp x   %s *synth2 |1476 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1163 | 29| 2default:defaulthp x   %s *synth2 |1477 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1131 | 166| 2default:defaulthp x   %s *synth2 |1478 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1132 | 257| 2default:defaulthp x   %s *synth2 |1479 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1158 | 167| 2default:defaulthp x   %s *synth2 |1480 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1159 | 18| 2default:defaulthp x   %s *synth2 |1481 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1160 | 29| 2default:defaulthp x   %s *synth2 |1482 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1133 | 166| 2default:defaulthp x   %s *synth2 |1483 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1134 | 257| 2default:defaulthp x   %s *synth2 |1484 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1155 | 167| 2default:defaulthp x   %s *synth2 |1485 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1156 | 18| 2default:defaulthp x   %s *synth2 |1486 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1157 | 29| 2default:defaulthp x   %s *synth2 |1487 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1135 | 165| 2default:defaulthp x   %s *synth2 |1488 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1136 | 257| 2default:defaulthp x   %s *synth2 |1489 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1152 | 167| 2default:defaulthp x   %s *synth2 |1490 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1153 | 18| 2default:defaulthp x   %s *synth2 |1491 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1154 | 29| 2default:defaulthp x   %s *synth2 |1492 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1137 | 198| 2default:defaulthp x   %s *synth2 |1493 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1138 | 662| 2default:defaulthp x   %s *synth2 |1494 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1139 | 510| 2default:defaulthp x   %s *synth2 |1495 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1140 | 535| 2default:defaulthp x   %s *synth2 |1496 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1141 | 535| 2default:defaulthp x   %s *synth2 |1497 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1142 | 511| 2default:defaulthp x   %s *synth2 |1498 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1143 | 535| 2default:defaulthp x   %s *synth2 |1499 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1144 | 511| 2default:defaulthp x   %s *synth2 |1500 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1145 | 511| 2default:defaulthp x   %s *synth2 |1501 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1146 | 511| 2default:defaulthp x   %s *synth2 |1502 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1147 | 511| 2default:defaulthp x   %s *synth2 |1503 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1148 | 535| 2default:defaulthp x   %s *synth2 |1504 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1149 | 535| 2default:defaulthp x   %s *synth2 |1505 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1150 | 535| 2default:defaulthp x   %s *synth2 |1506 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1151 | 535| 2default:defaulthp x   %s *synth2 |1507 | \SFP_GEN[5].QIE_RESET_DELAY |delay_counter_15 | 40| 2default:defaulthp x   %s *synth2 |1508 | \SFP_GEN[5].ngCCM_gbt |ngCCM__xdcDup__5 | 8153| 2default:defaulthp x   %s *synth2 |1509 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__61 | 104| 2default:defaulthp x   %s *synth2 |1510 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__302 | 4| 2default:defaulthp x   %s *synth2 |1511 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__62 | 104| 2default:defaulthp x   %s *synth2 |1512 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__301 | 4| 2default:defaulthp x   %s *synth2 |1513 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__63 | 104| 2default:defaulthp x   %s *synth2 |1514 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__300 | 4| 2default:defaulthp x   %s *synth2 |1515 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__64 | 104| 2default:defaulthp x   %s *synth2 |1516 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__299 | 4| 2default:defaulthp x   %s *synth2 |1517 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__65 | 104| 2default:defaulthp x   %s *synth2 |1518 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__298 | 4| 2default:defaulthp x   %s *synth2 |1519 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__66 | 104| 2default:defaulthp x   %s *synth2 |1520 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__297 | 4| 2default:defaulthp x   %s *synth2 |1521 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__67 | 104| 2default:defaulthp x   %s *synth2 |1522 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__296 | 4| 2default:defaulthp x   %s *synth2 |1523 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__68 | 104| 2default:defaulthp x   %s *synth2 |1524 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__295 | 4| 2default:defaulthp x   %s *synth2 |1525 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__69 | 104| 2default:defaulthp x   %s *synth2 |1526 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__294 | 4| 2default:defaulthp x   %s *synth2 |1527 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__70 | 104| 2default:defaulthp x   %s *synth2 |1528 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__293 | 4| 2default:defaulthp x   %s *synth2 |1529 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__71 | 104| 2default:defaulthp x   %s *synth2 |1530 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__292 | 4| 2default:defaulthp x   %s *synth2 |1531 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__72 | 104| 2default:defaulthp x   %s *synth2 |1532 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__291 | 4| 2default:defaulthp x   %s *synth2 |1533 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__73 | 104| 2default:defaulthp x   %s *synth2 |1534 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__290 | 4| 2default:defaulthp x   %s *synth2 |1535 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__74 | 104| 2default:defaulthp x   %s *synth2 |1536 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__289 | 4| 2default:defaulthp x   %s *synth2 |1537 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__75 | 104| 2default:defaulthp x   %s *synth2 |1538 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__288 | 4| 2default:defaulthp x   %s *synth2 |1539 | CrossClock_DV_cnt |CrossClock_RX_1022 | 70| 2default:defaulthp x   %s *synth2 |1540 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__5 | 629| 2default:defaulthp x   %s *synth2 |1541 | JTAGMaster_inst |JTAGMaster__xdcDup__5 | 462| 2default:defaulthp x   %s *synth2 |1542 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__303 | 4| 2default:defaulthp x   %s *synth2 |1543 | JTAG_BRAM |RAM_1106 | 117| 2default:defaulthp x   %s *synth2 |1544 | Sync_RX_Reset |Sync_1023 | 2| 2default:defaulthp x   %s *synth2 |1545 | Sync_TX_Reset |Sync_1024 | 114| 2default:defaulthp x   %s *synth2 |1546 | Sync_error_counter_reset |Sync_1025 | 2| 2default:defaulthp x   %s *synth2 |1547 | gbt_rx_checker |gbt_rx_checker_1026 | 106| 2default:defaulthp x   %s *synth2 |1548 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1027 | 332| 2default:defaulthp x   %s *synth2 |1549 | i2c_master |i2c_master_usr_1101 | 332| 2default:defaulthp x   %s *synth2 |1550 | byte_ctrl |i2c_master_byte_ctrl_1102 | 279| 2default:defaulthp x   %s *synth2 |1551 | bit_ctrl |i2c_master_bit_ctrl_1103 | 224| 2default:defaulthp x   %s *synth2 |1552 | \bus_status_ctrl.gf_scl |glitch_filter_1104 | 18| 2default:defaulthp x   %s *synth2 |1553 | \bus_status_ctrl.gf_sda |glitch_filter_1105 | 20| 2default:defaulthp x   %s *synth2 |1554 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1028 | 332| 2default:defaulthp x   %s *synth2 |1555 | i2c_master |i2c_master_usr_1096 | 332| 2default:defaulthp x   %s *synth2 |1556 | byte_ctrl |i2c_master_byte_ctrl_1097 | 279| 2default:defaulthp x   %s *synth2 |1557 | bit_ctrl |i2c_master_bit_ctrl_1098 | 224| 2default:defaulthp x   %s *synth2 |1558 | \bus_status_ctrl.gf_scl |glitch_filter_1099 | 18| 2default:defaulthp x   %s *synth2 |1559 | \bus_status_ctrl.gf_sda |glitch_filter_1100 | 20| 2default:defaulthp x   %s *synth2 |1560 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1029 | 332| 2default:defaulthp x   %s *synth2 |1561 | i2c_master |i2c_master_usr_1091 | 332| 2default:defaulthp x   %s *synth2 |1562 | byte_ctrl |i2c_master_byte_ctrl_1092 | 279| 2default:defaulthp x   %s *synth2 |1563 | bit_ctrl |i2c_master_bit_ctrl_1093 | 224| 2default:defaulthp x   %s *synth2 |1564 | \bus_status_ctrl.gf_scl |glitch_filter_1094 | 18| 2default:defaulthp x   %s *synth2 |1565 | \bus_status_ctrl.gf_sda |glitch_filter_1095 | 20| 2default:defaulthp x   %s *synth2 |1566 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1030 | 332| 2default:defaulthp x   %s *synth2 |1567 | i2c_master |i2c_master_usr_1086 | 332| 2default:defaulthp x   %s *synth2 |1568 | byte_ctrl |i2c_master_byte_ctrl_1087 | 279| 2default:defaulthp x   %s *synth2 |1569 | bit_ctrl |i2c_master_bit_ctrl_1088 | 224| 2default:defaulthp x   %s *synth2 |1570 | \bus_status_ctrl.gf_scl |glitch_filter_1089 | 18| 2default:defaulthp x   %s *synth2 |1571 | \bus_status_ctrl.gf_sda |glitch_filter_1090 | 20| 2default:defaulthp x   %s *synth2 |1572 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1031 | 332| 2default:defaulthp x   %s *synth2 |1573 | i2c_master |i2c_master_usr_1081 | 332| 2default:defaulthp x   %s *synth2 |1574 | byte_ctrl |i2c_master_byte_ctrl_1082 | 279| 2default:defaulthp x   %s *synth2 |1575 | bit_ctrl |i2c_master_bit_ctrl_1083 | 224| 2default:defaulthp x   %s *synth2 |1576 | \bus_status_ctrl.gf_scl |glitch_filter_1084 | 18| 2default:defaulthp x   %s *synth2 |1577 | \bus_status_ctrl.gf_sda |glitch_filter_1085 | 20| 2default:defaulthp x   %s *synth2 |1578 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1032 | 332| 2default:defaulthp x   %s *synth2 |1579 | i2c_master |i2c_master_usr_1076 | 332| 2default:defaulthp x   %s *synth2 |1580 | byte_ctrl |i2c_master_byte_ctrl_1077 | 279| 2default:defaulthp x   %s *synth2 |1581 | bit_ctrl |i2c_master_bit_ctrl_1078 | 224| 2default:defaulthp x   %s *synth2 |1582 | \bus_status_ctrl.gf_scl |glitch_filter_1079 | 18| 2default:defaulthp x   %s *synth2 |1583 | \bus_status_ctrl.gf_sda |glitch_filter_1080 | 20| 2default:defaulthp x   %s *synth2 |1584 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1033 | 332| 2default:defaulthp x   %s *synth2 |1585 | i2c_master |i2c_master_usr_1071 | 332| 2default:defaulthp x   %s *synth2 |1586 | byte_ctrl |i2c_master_byte_ctrl_1072 | 279| 2default:defaulthp x   %s *synth2 |1587 | bit_ctrl |i2c_master_bit_ctrl_1073 | 224| 2default:defaulthp x   %s *synth2 |1588 | \bus_status_ctrl.gf_scl |glitch_filter_1074 | 18| 2default:defaulthp x   %s *synth2 |1589 | \bus_status_ctrl.gf_sda |glitch_filter_1075 | 20| 2default:defaulthp x   %s *synth2 |1590 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1034 | 332| 2default:defaulthp x   %s *synth2 |1591 | i2c_master |i2c_master_usr_1066 | 332| 2default:defaulthp x   %s *synth2 |1592 | byte_ctrl |i2c_master_byte_ctrl_1067 | 279| 2default:defaulthp x   %s *synth2 |1593 | bit_ctrl |i2c_master_bit_ctrl_1068 | 224| 2default:defaulthp x   %s *synth2 |1594 | \bus_status_ctrl.gf_scl |glitch_filter_1069 | 18| 2default:defaulthp x   %s *synth2 |1595 | \bus_status_ctrl.gf_sda |glitch_filter_1070 | 20| 2default:defaulthp x   %s *synth2 |1596 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1035 | 332| 2default:defaulthp x   %s *synth2 |1597 | i2c_master |i2c_master_usr_1061 | 332| 2default:defaulthp x   %s *synth2 |1598 | byte_ctrl |i2c_master_byte_ctrl_1062 | 279| 2default:defaulthp x   %s *synth2 |1599 | bit_ctrl |i2c_master_bit_ctrl_1063 | 224| 2default:defaulthp x   %s *synth2 |1600 | \bus_status_ctrl.gf_scl |glitch_filter_1064 | 18| 2default:defaulthp x   %s *synth2 |1601 | \bus_status_ctrl.gf_sda |glitch_filter_1065 | 20| 2default:defaulthp x   %s *synth2 |1602 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1036 | 332| 2default:defaulthp x   %s *synth2 |1603 | i2c_master |i2c_master_usr_1056 | 332| 2default:defaulthp x   %s *synth2 |1604 | byte_ctrl |i2c_master_byte_ctrl_1057 | 279| 2default:defaulthp x   %s *synth2 |1605 | bit_ctrl |i2c_master_bit_ctrl_1058 | 224| 2default:defaulthp x   %s *synth2 |1606 | \bus_status_ctrl.gf_scl |glitch_filter_1059 | 18| 2default:defaulthp x   %s *synth2 |1607 | \bus_status_ctrl.gf_sda |glitch_filter_1060 | 20| 2default:defaulthp x   %s *synth2 |1608 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1037 | 332| 2default:defaulthp x   %s *synth2 |1609 | i2c_master |i2c_master_usr_1051 | 332| 2default:defaulthp x   %s *synth2 |1610 | byte_ctrl |i2c_master_byte_ctrl_1052 | 279| 2default:defaulthp x   %s *synth2 |1611 | bit_ctrl |i2c_master_bit_ctrl_1053 | 224| 2default:defaulthp x   %s *synth2 |1612 | \bus_status_ctrl.gf_scl |glitch_filter_1054 | 18| 2default:defaulthp x   %s *synth2 |1613 | \bus_status_ctrl.gf_sda |glitch_filter_1055 | 20| 2default:defaulthp x   %s *synth2 |1614 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1038 | 332| 2default:defaulthp x   %s *synth2 |1615 | i2c_master |i2c_master_usr_1046 | 332| 2default:defaulthp x   %s *synth2 |1616 | byte_ctrl |i2c_master_byte_ctrl_1047 | 279| 2default:defaulthp x   %s *synth2 |1617 | bit_ctrl |i2c_master_bit_ctrl_1048 | 224| 2default:defaulthp x   %s *synth2 |1618 | \bus_status_ctrl.gf_scl |glitch_filter_1049 | 18| 2default:defaulthp x   %s *synth2 |1619 | \bus_status_ctrl.gf_sda |glitch_filter_1050 | 20| 2default:defaulthp x   %s *synth2 |1620 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1039 | 331| 2default:defaulthp x   %s *synth2 |1621 | i2c_master |i2c_master_usr_1041 | 331| 2default:defaulthp x   %s *synth2 |1622 | byte_ctrl |i2c_master_byte_ctrl_1042 | 279| 2default:defaulthp x   %s *synth2 |1623 | bit_ctrl |i2c_master_bit_ctrl_1043 | 224| 2default:defaulthp x   %s *synth2 |1624 | \bus_status_ctrl.gf_scl |glitch_filter_1044 | 18| 2default:defaulthp x   %s *synth2 |1625 | \bus_status_ctrl.gf_sda |glitch_filter_1045 | 20| 2default:defaulthp x   %s *synth2 |1626 | prbs |prbs_1040 | 25| 2default:defaulthp x   %s *synth2 |1627 | \SFP_GEN[5].ngFEC_module |ngFEC_module_16 | 15549| 2default:defaulthp x   %s *synth2 |1628 | bkp_buffer_ngccm |buffer_ngccm_com_932 | 511| 2default:defaulthp x   %s *synth2 |1629 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_933 | 281| 2default:defaulthp x   %s *synth2 |1630 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1019 | 194| 2default:defaulthp x   %s *synth2 |1631 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1020 | 20| 2default:defaulthp x   %s *synth2 |1632 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1021 | 24| 2default:defaulthp x   %s *synth2 |1633 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_934 | 168| 2default:defaulthp x   %s *synth2 |1634 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_935 | 257| 2default:defaulthp x   %s *synth2 |1635 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1016 | 167| 2default:defaulthp x   %s *synth2 |1636 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1017 | 18| 2default:defaulthp x   %s *synth2 |1637 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1018 | 29| 2default:defaulthp x   %s *synth2 |1638 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_936 | 166| 2default:defaulthp x   %s *synth2 |1639 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_937 | 257| 2default:defaulthp x   %s *synth2 |1640 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1013 | 167| 2default:defaulthp x   %s *synth2 |1641 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1014 | 18| 2default:defaulthp x   %s *synth2 |1642 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1015 | 29| 2default:defaulthp x   %s *synth2 |1643 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_938 | 166| 2default:defaulthp x   %s *synth2 |1644 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_939 | 280| 2default:defaulthp x   %s *synth2 |1645 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1010 | 188| 2default:defaulthp x   %s *synth2 |1646 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1011 | 20| 2default:defaulthp x   %s *synth2 |1647 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1012 | 29| 2default:defaulthp x   %s *synth2 |1648 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_940 | 264| 2default:defaulthp x   %s *synth2 |1649 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_941 | 134| 2default:defaulthp x   %s *synth2 |1650 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1007 | 69| 2default:defaulthp x   %s *synth2 |1651 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1008 | 20| 2default:defaulthp x   %s *synth2 |1652 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1009 | 18| 2default:defaulthp x   %s *synth2 |1653 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_942 | 133| 2default:defaulthp x   %s *synth2 |1654 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_943 | 280| 2default:defaulthp x   %s *synth2 |1655 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1004 | 188| 2default:defaulthp x   %s *synth2 |1656 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1005 | 20| 2default:defaulthp x   %s *synth2 |1657 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1006 | 29| 2default:defaulthp x   %s *synth2 |1658 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_944 | 168| 2default:defaulthp x   %s *synth2 |1659 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_945 | 257| 2default:defaulthp x   %s *synth2 |1660 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1001 | 167| 2default:defaulthp x   %s *synth2 |1661 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1002 | 18| 2default:defaulthp x   %s *synth2 |1662 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1003 | 29| 2default:defaulthp x   %s *synth2 |1663 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_946 | 198| 2default:defaulthp x   %s *synth2 |1664 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_947 | 280| 2default:defaulthp x   %s *synth2 |1665 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_998 | 188| 2default:defaulthp x   %s *synth2 |1666 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_999 | 20| 2default:defaulthp x   %s *synth2 |1667 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1000 | 29| 2default:defaulthp x   %s *synth2 |1668 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_948 | 168| 2default:defaulthp x   %s *synth2 |1669 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_949 | 280| 2default:defaulthp x   %s *synth2 |1670 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_995 | 188| 2default:defaulthp x   %s *synth2 |1671 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_996 | 20| 2default:defaulthp x   %s *synth2 |1672 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_997 | 29| 2default:defaulthp x   %s *synth2 |1673 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_950 | 167| 2default:defaulthp x   %s *synth2 |1674 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_951 | 280| 2default:defaulthp x   %s *synth2 |1675 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_992 | 188| 2default:defaulthp x   %s *synth2 |1676 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_993 | 20| 2default:defaulthp x   %s *synth2 |1677 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_994 | 29| 2default:defaulthp x   %s *synth2 |1678 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_952 | 168| 2default:defaulthp x   %s *synth2 |1679 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_953 | 280| 2default:defaulthp x   %s *synth2 |1680 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_989 | 188| 2default:defaulthp x   %s *synth2 |1681 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_990 | 20| 2default:defaulthp x   %s *synth2 |1682 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_991 | 29| 2default:defaulthp x   %s *synth2 |1683 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_954 | 234| 2default:defaulthp x   %s *synth2 |1684 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_955 | 257| 2default:defaulthp x   %s *synth2 |1685 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_986 | 167| 2default:defaulthp x   %s *synth2 |1686 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_987 | 18| 2default:defaulthp x   %s *synth2 |1687 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_988 | 29| 2default:defaulthp x   %s *synth2 |1688 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_956 | 166| 2default:defaulthp x   %s *synth2 |1689 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_957 | 257| 2default:defaulthp x   %s *synth2 |1690 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_983 | 167| 2default:defaulthp x   %s *synth2 |1691 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_984 | 18| 2default:defaulthp x   %s *synth2 |1692 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_985 | 29| 2default:defaulthp x   %s *synth2 |1693 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_958 | 166| 2default:defaulthp x   %s *synth2 |1694 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_959 | 257| 2default:defaulthp x   %s *synth2 |1695 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_980 | 167| 2default:defaulthp x   %s *synth2 |1696 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_981 | 18| 2default:defaulthp x   %s *synth2 |1697 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_982 | 29| 2default:defaulthp x   %s *synth2 |1698 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_960 | 165| 2default:defaulthp x   %s *synth2 |1699 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_961 | 257| 2default:defaulthp x   %s *synth2 |1700 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_977 | 167| 2default:defaulthp x   %s *synth2 |1701 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_978 | 18| 2default:defaulthp x   %s *synth2 |1702 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_979 | 29| 2default:defaulthp x   %s *synth2 |1703 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_962 | 198| 2default:defaulthp x   %s *synth2 |1704 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_963 | 662| 2default:defaulthp x   %s *synth2 |1705 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_964 | 510| 2default:defaulthp x   %s *synth2 |1706 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_965 | 535| 2default:defaulthp x   %s *synth2 |1707 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_966 | 535| 2default:defaulthp x   %s *synth2 |1708 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_967 | 511| 2default:defaulthp x   %s *synth2 |1709 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_968 | 535| 2default:defaulthp x   %s *synth2 |1710 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_969 | 511| 2default:defaulthp x   %s *synth2 |1711 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_970 | 511| 2default:defaulthp x   %s *synth2 |1712 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_971 | 511| 2default:defaulthp x   %s *synth2 |1713 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_972 | 511| 2default:defaulthp x   %s *synth2 |1714 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_973 | 535| 2default:defaulthp x   %s *synth2 |1715 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_974 | 535| 2default:defaulthp x   %s *synth2 |1716 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_975 | 535| 2default:defaulthp x   %s *synth2 |1717 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_976 | 535| 2default:defaulthp x   %s *synth2 |1718 | \SFP_GEN[6].QIE_RESET_DELAY |delay_counter_17 | 40| 2default:defaulthp x   %s *synth2 |1719 | \SFP_GEN[6].ngCCM_gbt |ngCCM__xdcDup__6 | 8153| 2default:defaulthp x   %s *synth2 |1720 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__76 | 104| 2default:defaulthp x   %s *synth2 |1721 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__286 | 4| 2default:defaulthp x   %s *synth2 |1722 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__77 | 104| 2default:defaulthp x   %s *synth2 |1723 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__285 | 4| 2default:defaulthp x   %s *synth2 |1724 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__78 | 104| 2default:defaulthp x   %s *synth2 |1725 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__284 | 4| 2default:defaulthp x   %s *synth2 |1726 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__79 | 104| 2default:defaulthp x   %s *synth2 |1727 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__283 | 4| 2default:defaulthp x   %s *synth2 |1728 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__80 | 104| 2default:defaulthp x   %s *synth2 |1729 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__282 | 4| 2default:defaulthp x   %s *synth2 |1730 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__81 | 104| 2default:defaulthp x   %s *synth2 |1731 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__281 | 4| 2default:defaulthp x   %s *synth2 |1732 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__82 | 104| 2default:defaulthp x   %s *synth2 |1733 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__280 | 4| 2default:defaulthp x   %s *synth2 |1734 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__83 | 104| 2default:defaulthp x   %s *synth2 |1735 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__279 | 4| 2default:defaulthp x   %s *synth2 |1736 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__84 | 104| 2default:defaulthp x   %s *synth2 |1737 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__278 | 4| 2default:defaulthp x   %s *synth2 |1738 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__85 | 104| 2default:defaulthp x   %s *synth2 |1739 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__277 | 4| 2default:defaulthp x   %s *synth2 |1740 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__86 | 104| 2default:defaulthp x   %s *synth2 |1741 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__276 | 4| 2default:defaulthp x   %s *synth2 |1742 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__87 | 104| 2default:defaulthp x   %s *synth2 |1743 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__275 | 4| 2default:defaulthp x   %s *synth2 |1744 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__88 | 104| 2default:defaulthp x   %s *synth2 |1745 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__274 | 4| 2default:defaulthp x   %s *synth2 |1746 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__89 | 104| 2default:defaulthp x   %s *synth2 |1747 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__273 | 4| 2default:defaulthp x   %s *synth2 |1748 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__90 | 104| 2default:defaulthp x   %s *synth2 |1749 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__272 | 4| 2default:defaulthp x   %s *synth2 |1750 | CrossClock_DV_cnt |CrossClock_RX_847 | 70| 2default:defaulthp x   %s *synth2 |1751 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__6 | 629| 2default:defaulthp x   %s *synth2 |1752 | JTAGMaster_inst |JTAGMaster__xdcDup__6 | 462| 2default:defaulthp x   %s *synth2 |1753 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__287 | 4| 2default:defaulthp x   %s *synth2 |1754 | JTAG_BRAM |RAM_931 | 117| 2default:defaulthp x   %s *synth2 |1755 | Sync_RX_Reset |Sync_848 | 2| 2default:defaulthp x   %s *synth2 |1756 | Sync_TX_Reset |Sync_849 | 114| 2default:defaulthp x   %s *synth2 |1757 | Sync_error_counter_reset |Sync_850 | 2| 2default:defaulthp x   %s *synth2 |1758 | gbt_rx_checker |gbt_rx_checker_851 | 106| 2default:defaulthp x   %s *synth2 |1759 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_852 | 332| 2default:defaulthp x   %s *synth2 |1760 | i2c_master |i2c_master_usr_926 | 332| 2default:defaulthp x   %s *synth2 |1761 | byte_ctrl |i2c_master_byte_ctrl_927 | 279| 2default:defaulthp x   %s *synth2 |1762 | bit_ctrl |i2c_master_bit_ctrl_928 | 224| 2default:defaulthp x   %s *synth2 |1763 | \bus_status_ctrl.gf_scl |glitch_filter_929 | 18| 2default:defaulthp x   %s *synth2 |1764 | \bus_status_ctrl.gf_sda |glitch_filter_930 | 20| 2default:defaulthp x   %s *synth2 |1765 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_853 | 332| 2default:defaulthp x   %s *synth2 |1766 | i2c_master |i2c_master_usr_921 | 332| 2default:defaulthp x   %s *synth2 |1767 | byte_ctrl |i2c_master_byte_ctrl_922 | 279| 2default:defaulthp x   %s *synth2 |1768 | bit_ctrl |i2c_master_bit_ctrl_923 | 224| 2default:defaulthp x   %s *synth2 |1769 | \bus_status_ctrl.gf_scl |glitch_filter_924 | 18| 2default:defaulthp x   %s *synth2 |1770 | \bus_status_ctrl.gf_sda |glitch_filter_925 | 20| 2default:defaulthp x   %s *synth2 |1771 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_854 | 332| 2default:defaulthp x   %s *synth2 |1772 | i2c_master |i2c_master_usr_916 | 332| 2default:defaulthp x   %s *synth2 |1773 | byte_ctrl |i2c_master_byte_ctrl_917 | 279| 2default:defaulthp x   %s *synth2 |1774 | bit_ctrl |i2c_master_bit_ctrl_918 | 224| 2default:defaulthp x   %s *synth2 |1775 | \bus_status_ctrl.gf_scl |glitch_filter_919 | 18| 2default:defaulthp x   %s *synth2 |1776 | \bus_status_ctrl.gf_sda |glitch_filter_920 | 20| 2default:defaulthp x   %s *synth2 |1777 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_855 | 332| 2default:defaulthp x   %s *synth2 |1778 | i2c_master |i2c_master_usr_911 | 332| 2default:defaulthp x   %s *synth2 |1779 | byte_ctrl |i2c_master_byte_ctrl_912 | 279| 2default:defaulthp x   %s *synth2 |1780 | bit_ctrl |i2c_master_bit_ctrl_913 | 224| 2default:defaulthp x   %s *synth2 |1781 | \bus_status_ctrl.gf_scl |glitch_filter_914 | 18| 2default:defaulthp x   %s *synth2 |1782 | \bus_status_ctrl.gf_sda |glitch_filter_915 | 20| 2default:defaulthp x   %s *synth2 |1783 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_856 | 332| 2default:defaulthp x   %s *synth2 |1784 | i2c_master |i2c_master_usr_906 | 332| 2default:defaulthp x   %s *synth2 |1785 | byte_ctrl |i2c_master_byte_ctrl_907 | 279| 2default:defaulthp x   %s *synth2 |1786 | bit_ctrl |i2c_master_bit_ctrl_908 | 224| 2default:defaulthp x   %s *synth2 |1787 | \bus_status_ctrl.gf_scl |glitch_filter_909 | 18| 2default:defaulthp x   %s *synth2 |1788 | \bus_status_ctrl.gf_sda |glitch_filter_910 | 20| 2default:defaulthp x   %s *synth2 |1789 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_857 | 332| 2default:defaulthp x   %s *synth2 |1790 | i2c_master |i2c_master_usr_901 | 332| 2default:defaulthp x   %s *synth2 |1791 | byte_ctrl |i2c_master_byte_ctrl_902 | 279| 2default:defaulthp x   %s *synth2 |1792 | bit_ctrl |i2c_master_bit_ctrl_903 | 224| 2default:defaulthp x   %s *synth2 |1793 | \bus_status_ctrl.gf_scl |glitch_filter_904 | 18| 2default:defaulthp x   %s *synth2 |1794 | \bus_status_ctrl.gf_sda |glitch_filter_905 | 20| 2default:defaulthp x   %s *synth2 |1795 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_858 | 332| 2default:defaulthp x   %s *synth2 |1796 | i2c_master |i2c_master_usr_896 | 332| 2default:defaulthp x   %s *synth2 |1797 | byte_ctrl |i2c_master_byte_ctrl_897 | 279| 2default:defaulthp x   %s *synth2 |1798 | bit_ctrl |i2c_master_bit_ctrl_898 | 224| 2default:defaulthp x   %s *synth2 |1799 | \bus_status_ctrl.gf_scl |glitch_filter_899 | 18| 2default:defaulthp x   %s *synth2 |1800 | \bus_status_ctrl.gf_sda |glitch_filter_900 | 20| 2default:defaulthp x   %s *synth2 |1801 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_859 | 332| 2default:defaulthp x   %s *synth2 |1802 | i2c_master |i2c_master_usr_891 | 332| 2default:defaulthp x   %s *synth2 |1803 | byte_ctrl |i2c_master_byte_ctrl_892 | 279| 2default:defaulthp x   %s *synth2 |1804 | bit_ctrl |i2c_master_bit_ctrl_893 | 224| 2default:defaulthp x   %s *synth2 |1805 | \bus_status_ctrl.gf_scl |glitch_filter_894 | 18| 2default:defaulthp x   %s *synth2 |1806 | \bus_status_ctrl.gf_sda |glitch_filter_895 | 20| 2default:defaulthp x   %s *synth2 |1807 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_860 | 332| 2default:defaulthp x   %s *synth2 |1808 | i2c_master |i2c_master_usr_886 | 332| 2default:defaulthp x   %s *synth2 |1809 | byte_ctrl |i2c_master_byte_ctrl_887 | 279| 2default:defaulthp x   %s *synth2 |1810 | bit_ctrl |i2c_master_bit_ctrl_888 | 224| 2default:defaulthp x   %s *synth2 |1811 | \bus_status_ctrl.gf_scl |glitch_filter_889 | 18| 2default:defaulthp x   %s *synth2 |1812 | \bus_status_ctrl.gf_sda |glitch_filter_890 | 20| 2default:defaulthp x   %s *synth2 |1813 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_861 | 332| 2default:defaulthp x   %s *synth2 |1814 | i2c_master |i2c_master_usr_881 | 332| 2default:defaulthp x   %s *synth2 |1815 | byte_ctrl |i2c_master_byte_ctrl_882 | 279| 2default:defaulthp x   %s *synth2 |1816 | bit_ctrl |i2c_master_bit_ctrl_883 | 224| 2default:defaulthp x   %s *synth2 |1817 | \bus_status_ctrl.gf_scl |glitch_filter_884 | 18| 2default:defaulthp x   %s *synth2 |1818 | \bus_status_ctrl.gf_sda |glitch_filter_885 | 20| 2default:defaulthp x   %s *synth2 |1819 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_862 | 332| 2default:defaulthp x   %s *synth2 |1820 | i2c_master |i2c_master_usr_876 | 332| 2default:defaulthp x   %s *synth2 |1821 | byte_ctrl |i2c_master_byte_ctrl_877 | 279| 2default:defaulthp x   %s *synth2 |1822 | bit_ctrl |i2c_master_bit_ctrl_878 | 224| 2default:defaulthp x   %s *synth2 |1823 | \bus_status_ctrl.gf_scl |glitch_filter_879 | 18| 2default:defaulthp x   %s *synth2 |1824 | \bus_status_ctrl.gf_sda |glitch_filter_880 | 20| 2default:defaulthp x   %s *synth2 |1825 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_863 | 332| 2default:defaulthp x   %s *synth2 |1826 | i2c_master |i2c_master_usr_871 | 332| 2default:defaulthp x   %s *synth2 |1827 | byte_ctrl |i2c_master_byte_ctrl_872 | 279| 2default:defaulthp x   %s *synth2 |1828 | bit_ctrl |i2c_master_bit_ctrl_873 | 224| 2default:defaulthp x   %s *synth2 |1829 | \bus_status_ctrl.gf_scl |glitch_filter_874 | 18| 2default:defaulthp x   %s *synth2 |1830 | \bus_status_ctrl.gf_sda |glitch_filter_875 | 20| 2default:defaulthp x   %s *synth2 |1831 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_864 | 331| 2default:defaulthp x   %s *synth2 |1832 | i2c_master |i2c_master_usr_866 | 331| 2default:defaulthp x   %s *synth2 |1833 | byte_ctrl |i2c_master_byte_ctrl_867 | 279| 2default:defaulthp x   %s *synth2 |1834 | bit_ctrl |i2c_master_bit_ctrl_868 | 224| 2default:defaulthp x   %s *synth2 |1835 | \bus_status_ctrl.gf_scl |glitch_filter_869 | 18| 2default:defaulthp x   %s *synth2 |1836 | \bus_status_ctrl.gf_sda |glitch_filter_870 | 20| 2default:defaulthp x   %s *synth2 |1837 | prbs |prbs_865 | 25| 2default:defaulthp x   %s *synth2 |1838 | \SFP_GEN[6].ngFEC_module |ngFEC_module_18 | 15549| 2default:defaulthp x   %s *synth2 |1839 | bkp_buffer_ngccm |buffer_ngccm_com_757 | 511| 2default:defaulthp x   %s *synth2 |1840 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_758 | 281| 2default:defaulthp x   %s *synth2 |1841 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_844 | 194| 2default:defaulthp x   %s *synth2 |1842 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_845 | 20| 2default:defaulthp x   %s *synth2 |1843 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_846 | 24| 2default:defaulthp x   %s *synth2 |1844 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_759 | 168| 2default:defaulthp x   %s *synth2 |1845 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_760 | 257| 2default:defaulthp x   %s *synth2 |1846 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_841 | 167| 2default:defaulthp x   %s *synth2 |1847 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_842 | 18| 2default:defaulthp x   %s *synth2 |1848 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_843 | 29| 2default:defaulthp x   %s *synth2 |1849 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_761 | 166| 2default:defaulthp x   %s *synth2 |1850 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_762 | 257| 2default:defaulthp x   %s *synth2 |1851 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_838 | 167| 2default:defaulthp x   %s *synth2 |1852 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_839 | 18| 2default:defaulthp x   %s *synth2 |1853 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_840 | 29| 2default:defaulthp x   %s *synth2 |1854 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_763 | 166| 2default:defaulthp x   %s *synth2 |1855 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_764 | 280| 2default:defaulthp x   %s *synth2 |1856 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_835 | 188| 2default:defaulthp x   %s *synth2 |1857 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_836 | 20| 2default:defaulthp x   %s *synth2 |1858 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_837 | 29| 2default:defaulthp x   %s *synth2 |1859 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_765 | 264| 2default:defaulthp x   %s *synth2 |1860 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_766 | 134| 2default:defaulthp x   %s *synth2 |1861 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_832 | 69| 2default:defaulthp x   %s *synth2 |1862 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_833 | 20| 2default:defaulthp x   %s *synth2 |1863 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_834 | 18| 2default:defaulthp x   %s *synth2 |1864 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_767 | 133| 2default:defaulthp x   %s *synth2 |1865 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_768 | 280| 2default:defaulthp x   %s *synth2 |1866 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_829 | 188| 2default:defaulthp x   %s *synth2 |1867 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_830 | 20| 2default:defaulthp x   %s *synth2 |1868 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_831 | 29| 2default:defaulthp x   %s *synth2 |1869 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_769 | 168| 2default:defaulthp x   %s *synth2 |1870 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_770 | 257| 2default:defaulthp x   %s *synth2 |1871 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_826 | 167| 2default:defaulthp x   %s *synth2 |1872 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_827 | 18| 2default:defaulthp x   %s *synth2 |1873 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_828 | 29| 2default:defaulthp x   %s *synth2 |1874 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_771 | 198| 2default:defaulthp x   %s *synth2 |1875 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_772 | 280| 2default:defaulthp x   %s *synth2 |1876 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_823 | 188| 2default:defaulthp x   %s *synth2 |1877 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_824 | 20| 2default:defaulthp x   %s *synth2 |1878 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_825 | 29| 2default:defaulthp x   %s *synth2 |1879 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_773 | 168| 2default:defaulthp x   %s *synth2 |1880 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_774 | 280| 2default:defaulthp x   %s *synth2 |1881 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_820 | 188| 2default:defaulthp x   %s *synth2 |1882 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_821 | 20| 2default:defaulthp x   %s *synth2 |1883 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_822 | 29| 2default:defaulthp x   %s *synth2 |1884 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_775 | 167| 2default:defaulthp x   %s *synth2 |1885 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_776 | 280| 2default:defaulthp x   %s *synth2 |1886 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_817 | 188| 2default:defaulthp x   %s *synth2 |1887 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_818 | 20| 2default:defaulthp x   %s *synth2 |1888 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_819 | 29| 2default:defaulthp x   %s *synth2 |1889 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_777 | 168| 2default:defaulthp x   %s *synth2 |1890 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_778 | 280| 2default:defaulthp x   %s *synth2 |1891 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_814 | 188| 2default:defaulthp x   %s *synth2 |1892 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_815 | 20| 2default:defaulthp x   %s *synth2 |1893 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_816 | 29| 2default:defaulthp x   %s *synth2 |1894 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_779 | 234| 2default:defaulthp x   %s *synth2 |1895 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_780 | 257| 2default:defaulthp x   %s *synth2 |1896 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_811 | 167| 2default:defaulthp x   %s *synth2 |1897 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_812 | 18| 2default:defaulthp x   %s *synth2 |1898 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_813 | 29| 2default:defaulthp x   %s *synth2 |1899 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_781 | 166| 2default:defaulthp x   %s *synth2 |1900 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_782 | 257| 2default:defaulthp x   %s *synth2 |1901 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_808 | 167| 2default:defaulthp x   %s *synth2 |1902 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_809 | 18| 2default:defaulthp x   %s *synth2 |1903 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_810 | 29| 2default:defaulthp x   %s *synth2 |1904 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_783 | 166| 2default:defaulthp x   %s *synth2 |1905 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_784 | 257| 2default:defaulthp x   %s *synth2 |1906 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_805 | 167| 2default:defaulthp x   %s *synth2 |1907 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_806 | 18| 2default:defaulthp x   %s *synth2 |1908 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_807 | 29| 2default:defaulthp x   %s *synth2 |1909 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_785 | 165| 2default:defaulthp x   %s *synth2 |1910 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_786 | 257| 2default:defaulthp x   %s *synth2 |1911 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_802 | 167| 2default:defaulthp x   %s *synth2 |1912 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_803 | 18| 2default:defaulthp x   %s *synth2 |1913 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_804 | 29| 2default:defaulthp x   %s *synth2 |1914 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_787 | 198| 2default:defaulthp x   %s *synth2 |1915 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_788 | 662| 2default:defaulthp x   %s *synth2 |1916 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_789 | 510| 2default:defaulthp x   %s *synth2 |1917 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_790 | 535| 2default:defaulthp x   %s *synth2 |1918 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_791 | 535| 2default:defaulthp x   %s *synth2 |1919 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_792 | 511| 2default:defaulthp x   %s *synth2 |1920 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_793 | 535| 2default:defaulthp x   %s *synth2 |1921 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_794 | 511| 2default:defaulthp x   %s *synth2 |1922 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_795 | 511| 2default:defaulthp x   %s *synth2 |1923 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_796 | 511| 2default:defaulthp x   %s *synth2 |1924 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_797 | 511| 2default:defaulthp x   %s *synth2 |1925 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_798 | 535| 2default:defaulthp x   %s *synth2 |1926 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_799 | 535| 2default:defaulthp x   %s *synth2 |1927 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_800 | 535| 2default:defaulthp x   %s *synth2 |1928 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_801 | 535| 2default:defaulthp x   %s *synth2 |1929 | \SFP_GEN[7].QIE_RESET_DELAY |delay_counter_19 | 40| 2default:defaulthp x   %s *synth2 |1930 | \SFP_GEN[7].ngCCM_gbt |ngCCM__xdcDup__7 | 8153| 2default:defaulthp x   %s *synth2 |1931 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__91 | 104| 2default:defaulthp x   %s *synth2 |1932 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__270 | 4| 2default:defaulthp x   %s *synth2 |1933 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__92 | 104| 2default:defaulthp x   %s *synth2 |1934 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__269 | 4| 2default:defaulthp x   %s *synth2 |1935 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__93 | 104| 2default:defaulthp x   %s *synth2 |1936 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__268 | 4| 2default:defaulthp x   %s *synth2 |1937 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__94 | 104| 2default:defaulthp x   %s *synth2 |1938 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__267 | 4| 2default:defaulthp x   %s *synth2 |1939 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__95 | 104| 2default:defaulthp x   %s *synth2 |1940 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__266 | 4| 2default:defaulthp x   %s *synth2 |1941 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__96 | 104| 2default:defaulthp x   %s *synth2 |1942 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__265 | 4| 2default:defaulthp x   %s *synth2 |1943 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__97 | 104| 2default:defaulthp x   %s *synth2 |1944 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__264 | 4| 2default:defaulthp x   %s *synth2 |1945 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__98 | 104| 2default:defaulthp x   %s *synth2 |1946 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__263 | 4| 2default:defaulthp x   %s *synth2 |1947 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__99 | 104| 2default:defaulthp x   %s *synth2 |1948 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__262 | 4| 2default:defaulthp x   %s *synth2 |1949 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__100 | 104| 2default:defaulthp x   %s *synth2 |1950 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__261 | 4| 2default:defaulthp x   %s *synth2 |1951 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__101 | 104| 2default:defaulthp x   %s *synth2 |1952 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__260 | 4| 2default:defaulthp x   %s *synth2 |1953 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__102 | 104| 2default:defaulthp x   %s *synth2 |1954 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__259 | 4| 2default:defaulthp x   %s *synth2 |1955 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__103 | 104| 2default:defaulthp x   %s *synth2 |1956 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__258 | 4| 2default:defaulthp x   %s *synth2 |1957 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__104 | 104| 2default:defaulthp x   %s *synth2 |1958 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__257 | 4| 2default:defaulthp x   %s *synth2 |1959 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__105 | 104| 2default:defaulthp x   %s *synth2 |1960 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__256 | 4| 2default:defaulthp x   %s *synth2 |1961 | CrossClock_DV_cnt |CrossClock_RX_672 | 70| 2default:defaulthp x   %s *synth2 |1962 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__7 | 629| 2default:defaulthp x   %s *synth2 |1963 | JTAGMaster_inst |JTAGMaster__xdcDup__7 | 462| 2default:defaulthp x   %s *synth2 |1964 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__271 | 4| 2default:defaulthp x   %s *synth2 |1965 | JTAG_BRAM |RAM_756 | 117| 2default:defaulthp x   %s *synth2 |1966 | Sync_RX_Reset |Sync_673 | 2| 2default:defaulthp x   %s *synth2 |1967 | Sync_TX_Reset |Sync_674 | 114| 2default:defaulthp x   %s *synth2 |1968 | Sync_error_counter_reset |Sync_675 | 2| 2default:defaulthp x   %s *synth2 |1969 | gbt_rx_checker |gbt_rx_checker_676 | 106| 2default:defaulthp x   %s *synth2 |1970 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_677 | 332| 2default:defaulthp x   %s *synth2 |1971 | i2c_master |i2c_master_usr_751 | 332| 2default:defaulthp x   %s *synth2 |1972 | byte_ctrl |i2c_master_byte_ctrl_752 | 279| 2default:defaulthp x   %s *synth2 |1973 | bit_ctrl |i2c_master_bit_ctrl_753 | 224| 2default:defaulthp x   %s *synth2 |1974 | \bus_status_ctrl.gf_scl |glitch_filter_754 | 18| 2default:defaulthp x   %s *synth2 |1975 | \bus_status_ctrl.gf_sda |glitch_filter_755 | 20| 2default:defaulthp x   %s *synth2 |1976 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_678 | 332| 2default:defaulthp x   %s *synth2 |1977 | i2c_master |i2c_master_usr_746 | 332| 2default:defaulthp x   %s *synth2 |1978 | byte_ctrl |i2c_master_byte_ctrl_747 | 279| 2default:defaulthp x   %s *synth2 |1979 | bit_ctrl |i2c_master_bit_ctrl_748 | 224| 2default:defaulthp x   %s *synth2 |1980 | \bus_status_ctrl.gf_scl |glitch_filter_749 | 18| 2default:defaulthp x   %s *synth2 |1981 | \bus_status_ctrl.gf_sda |glitch_filter_750 | 20| 2default:defaulthp x   %s *synth2 |1982 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_679 | 332| 2default:defaulthp x   %s *synth2 |1983 | i2c_master |i2c_master_usr_741 | 332| 2default:defaulthp x   %s *synth2 |1984 | byte_ctrl |i2c_master_byte_ctrl_742 | 279| 2default:defaulthp x   %s *synth2 |1985 | bit_ctrl |i2c_master_bit_ctrl_743 | 224| 2default:defaulthp x   %s *synth2 |1986 | \bus_status_ctrl.gf_scl |glitch_filter_744 | 18| 2default:defaulthp x   %s *synth2 |1987 | \bus_status_ctrl.gf_sda |glitch_filter_745 | 20| 2default:defaulthp x   %s *synth2 |1988 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_680 | 332| 2default:defaulthp x   %s *synth2 |1989 | i2c_master |i2c_master_usr_736 | 332| 2default:defaulthp x   %s *synth2 |1990 | byte_ctrl |i2c_master_byte_ctrl_737 | 279| 2default:defaulthp x   %s *synth2 |1991 | bit_ctrl |i2c_master_bit_ctrl_738 | 224| 2default:defaulthp x   %s *synth2 |1992 | \bus_status_ctrl.gf_scl |glitch_filter_739 | 18| 2default:defaulthp x   %s *synth2 |1993 | \bus_status_ctrl.gf_sda |glitch_filter_740 | 20| 2default:defaulthp x   %s *synth2 |1994 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_681 | 332| 2default:defaulthp x   %s *synth2 |1995 | i2c_master |i2c_master_usr_731 | 332| 2default:defaulthp x   %s *synth2 |1996 | byte_ctrl |i2c_master_byte_ctrl_732 | 279| 2default:defaulthp x   %s *synth2 |1997 | bit_ctrl |i2c_master_bit_ctrl_733 | 224| 2default:defaulthp x   %s *synth2 |1998 | \bus_status_ctrl.gf_scl |glitch_filter_734 | 18| 2default:defaulthp x   %s *synth2 |1999 | \bus_status_ctrl.gf_sda |glitch_filter_735 | 20| 2default:defaulthp x   %s *synth2 |2000 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_682 | 332| 2default:defaulthp x   %s *synth2 |2001 | i2c_master |i2c_master_usr_726 | 332| 2default:defaulthp x   %s *synth2 |2002 | byte_ctrl |i2c_master_byte_ctrl_727 | 279| 2default:defaulthp x   %s *synth2 |2003 | bit_ctrl |i2c_master_bit_ctrl_728 | 224| 2default:defaulthp x   %s *synth2 |2004 | \bus_status_ctrl.gf_scl |glitch_filter_729 | 18| 2default:defaulthp x   %s *synth2 |2005 | \bus_status_ctrl.gf_sda |glitch_filter_730 | 20| 2default:defaulthp x   %s *synth2 |2006 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_683 | 332| 2default:defaulthp x   %s *synth2 |2007 | i2c_master |i2c_master_usr_721 | 332| 2default:defaulthp x   %s *synth2 |2008 | byte_ctrl |i2c_master_byte_ctrl_722 | 279| 2default:defaulthp x   %s *synth2 |2009 | bit_ctrl |i2c_master_bit_ctrl_723 | 224| 2default:defaulthp x   %s *synth2 |2010 | \bus_status_ctrl.gf_scl |glitch_filter_724 | 18| 2default:defaulthp x   %s *synth2 |2011 | \bus_status_ctrl.gf_sda |glitch_filter_725 | 20| 2default:defaulthp x   %s *synth2 |2012 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_684 | 332| 2default:defaulthp x   %s *synth2 |2013 | i2c_master |i2c_master_usr_716 | 332| 2default:defaulthp x   %s *synth2 |2014 | byte_ctrl |i2c_master_byte_ctrl_717 | 279| 2default:defaulthp x   %s *synth2 |2015 | bit_ctrl |i2c_master_bit_ctrl_718 | 224| 2default:defaulthp x   %s *synth2 |2016 | \bus_status_ctrl.gf_scl |glitch_filter_719 | 18| 2default:defaulthp x   %s *synth2 |2017 | \bus_status_ctrl.gf_sda |glitch_filter_720 | 20| 2default:defaulthp x   %s *synth2 |2018 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_685 | 332| 2default:defaulthp x   %s *synth2 |2019 | i2c_master |i2c_master_usr_711 | 332| 2default:defaulthp x   %s *synth2 |2020 | byte_ctrl |i2c_master_byte_ctrl_712 | 279| 2default:defaulthp x   %s *synth2 |2021 | bit_ctrl |i2c_master_bit_ctrl_713 | 224| 2default:defaulthp x   %s *synth2 |2022 | \bus_status_ctrl.gf_scl |glitch_filter_714 | 18| 2default:defaulthp x   %s *synth2 |2023 | \bus_status_ctrl.gf_sda |glitch_filter_715 | 20| 2default:defaulthp x   %s *synth2 |2024 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_686 | 332| 2default:defaulthp x   %s *synth2 |2025 | i2c_master |i2c_master_usr_706 | 332| 2default:defaulthp x   %s *synth2 |2026 | byte_ctrl |i2c_master_byte_ctrl_707 | 279| 2default:defaulthp x   %s *synth2 |2027 | bit_ctrl |i2c_master_bit_ctrl_708 | 224| 2default:defaulthp x   %s *synth2 |2028 | \bus_status_ctrl.gf_scl |glitch_filter_709 | 18| 2default:defaulthp x   %s *synth2 |2029 | \bus_status_ctrl.gf_sda |glitch_filter_710 | 20| 2default:defaulthp x   %s *synth2 |2030 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_687 | 332| 2default:defaulthp x   %s *synth2 |2031 | i2c_master |i2c_master_usr_701 | 332| 2default:defaulthp x   %s *synth2 |2032 | byte_ctrl |i2c_master_byte_ctrl_702 | 279| 2default:defaulthp x   %s *synth2 |2033 | bit_ctrl |i2c_master_bit_ctrl_703 | 224| 2default:defaulthp x   %s *synth2 |2034 | \bus_status_ctrl.gf_scl |glitch_filter_704 | 18| 2default:defaulthp x   %s *synth2 |2035 | \bus_status_ctrl.gf_sda |glitch_filter_705 | 20| 2default:defaulthp x   %s *synth2 |2036 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_688 | 332| 2default:defaulthp x   %s *synth2 |2037 | i2c_master |i2c_master_usr_696 | 332| 2default:defaulthp x   %s *synth2 |2038 | byte_ctrl |i2c_master_byte_ctrl_697 | 279| 2default:defaulthp x   %s *synth2 |2039 | bit_ctrl |i2c_master_bit_ctrl_698 | 224| 2default:defaulthp x   %s *synth2 |2040 | \bus_status_ctrl.gf_scl |glitch_filter_699 | 18| 2default:defaulthp x   %s *synth2 |2041 | \bus_status_ctrl.gf_sda |glitch_filter_700 | 20| 2default:defaulthp x   %s *synth2 |2042 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_689 | 331| 2default:defaulthp x   %s *synth2 |2043 | i2c_master |i2c_master_usr_691 | 331| 2default:defaulthp x   %s *synth2 |2044 | byte_ctrl |i2c_master_byte_ctrl_692 | 279| 2default:defaulthp x   %s *synth2 |2045 | bit_ctrl |i2c_master_bit_ctrl_693 | 224| 2default:defaulthp x   %s *synth2 |2046 | \bus_status_ctrl.gf_scl |glitch_filter_694 | 18| 2default:defaulthp x   %s *synth2 |2047 | \bus_status_ctrl.gf_sda |glitch_filter_695 | 20| 2default:defaulthp x   %s *synth2 |2048 | prbs |prbs_690 | 25| 2default:defaulthp x   %s *synth2 |2049 | \SFP_GEN[7].ngFEC_module |ngFEC_module_20 | 15549| 2default:defaulthp x   %s *synth2 |2050 | bkp_buffer_ngccm |buffer_ngccm_com_582 | 511| 2default:defaulthp x   %s *synth2 |2051 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_583 | 281| 2default:defaulthp x   %s *synth2 |2052 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_669 | 194| 2default:defaulthp x   %s *synth2 |2053 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_670 | 20| 2default:defaulthp x   %s *synth2 |2054 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_671 | 24| 2default:defaulthp x   %s *synth2 |2055 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_584 | 168| 2default:defaulthp x   %s *synth2 |2056 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_585 | 257| 2default:defaulthp x   %s *synth2 |2057 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_666 | 167| 2default:defaulthp x   %s *synth2 |2058 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_667 | 18| 2default:defaulthp x   %s *synth2 |2059 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_668 | 29| 2default:defaulthp x   %s *synth2 |2060 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_586 | 166| 2default:defaulthp x   %s *synth2 |2061 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_587 | 257| 2default:defaulthp x   %s *synth2 |2062 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_663 | 167| 2default:defaulthp x   %s *synth2 |2063 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_664 | 18| 2default:defaulthp x   %s *synth2 |2064 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_665 | 29| 2default:defaulthp x   %s *synth2 |2065 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_588 | 166| 2default:defaulthp x   %s *synth2 |2066 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_589 | 280| 2default:defaulthp x   %s *synth2 |2067 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_660 | 188| 2default:defaulthp x   %s *synth2 |2068 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_661 | 20| 2default:defaulthp x   %s *synth2 |2069 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_662 | 29| 2default:defaulthp x   %s *synth2 |2070 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_590 | 264| 2default:defaulthp x   %s *synth2 |2071 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_591 | 134| 2default:defaulthp x   %s *synth2 |2072 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_657 | 69| 2default:defaulthp x   %s *synth2 |2073 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_658 | 20| 2default:defaulthp x   %s *synth2 |2074 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_659 | 18| 2default:defaulthp x   %s *synth2 |2075 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_592 | 133| 2default:defaulthp x   %s *synth2 |2076 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_593 | 280| 2default:defaulthp x   %s *synth2 |2077 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_654 | 188| 2default:defaulthp x   %s *synth2 |2078 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_655 | 20| 2default:defaulthp x   %s *synth2 |2079 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_656 | 29| 2default:defaulthp x   %s *synth2 |2080 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_594 | 168| 2default:defaulthp x   %s *synth2 |2081 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_595 | 257| 2default:defaulthp x   %s *synth2 |2082 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_651 | 167| 2default:defaulthp x   %s *synth2 |2083 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_652 | 18| 2default:defaulthp x   %s *synth2 |2084 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_653 | 29| 2default:defaulthp x   %s *synth2 |2085 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_596 | 198| 2default:defaulthp x   %s *synth2 |2086 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_597 | 280| 2default:defaulthp x   %s *synth2 |2087 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_648 | 188| 2default:defaulthp x   %s *synth2 |2088 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_649 | 20| 2default:defaulthp x   %s *synth2 |2089 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_650 | 29| 2default:defaulthp x   %s *synth2 |2090 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_598 | 168| 2default:defaulthp x   %s *synth2 |2091 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_599 | 280| 2default:defaulthp x   %s *synth2 |2092 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_645 | 188| 2default:defaulthp x   %s *synth2 |2093 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_646 | 20| 2default:defaulthp x   %s *synth2 |2094 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_647 | 29| 2default:defaulthp x   %s *synth2 |2095 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_600 | 167| 2default:defaulthp x   %s *synth2 |2096 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_601 | 280| 2default:defaulthp x   %s *synth2 |2097 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_642 | 188| 2default:defaulthp x   %s *synth2 |2098 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_643 | 20| 2default:defaulthp x   %s *synth2 |2099 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_644 | 29| 2default:defaulthp x   %s *synth2 |2100 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_602 | 168| 2default:defaulthp x   %s *synth2 |2101 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_603 | 280| 2default:defaulthp x   %s *synth2 |2102 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_639 | 188| 2default:defaulthp x   %s *synth2 |2103 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_640 | 20| 2default:defaulthp x   %s *synth2 |2104 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_641 | 29| 2default:defaulthp x   %s *synth2 |2105 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_604 | 234| 2default:defaulthp x   %s *synth2 |2106 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_605 | 257| 2default:defaulthp x   %s *synth2 |2107 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_636 | 167| 2default:defaulthp x   %s *synth2 |2108 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_637 | 18| 2default:defaulthp x   %s *synth2 |2109 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_638 | 29| 2default:defaulthp x   %s *synth2 |2110 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_606 | 166| 2default:defaulthp x   %s *synth2 |2111 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_607 | 257| 2default:defaulthp x   %s *synth2 |2112 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_633 | 167| 2default:defaulthp x   %s *synth2 |2113 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_634 | 18| 2default:defaulthp x   %s *synth2 |2114 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_635 | 29| 2default:defaulthp x   %s *synth2 |2115 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_608 | 166| 2default:defaulthp x   %s *synth2 |2116 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_609 | 257| 2default:defaulthp x   %s *synth2 |2117 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_630 | 167| 2default:defaulthp x   %s *synth2 |2118 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_631 | 18| 2default:defaulthp x   %s *synth2 |2119 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_632 | 29| 2default:defaulthp x   %s *synth2 |2120 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_610 | 165| 2default:defaulthp x   %s *synth2 |2121 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_611 | 257| 2default:defaulthp x   %s *synth2 |2122 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_627 | 167| 2default:defaulthp x   %s *synth2 |2123 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_628 | 18| 2default:defaulthp x   %s *synth2 |2124 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_629 | 29| 2default:defaulthp x   %s *synth2 |2125 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_612 | 198| 2default:defaulthp x   %s *synth2 |2126 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_613 | 662| 2default:defaulthp x   %s *synth2 |2127 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_614 | 510| 2default:defaulthp x   %s *synth2 |2128 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_615 | 535| 2default:defaulthp x   %s *synth2 |2129 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_616 | 535| 2default:defaulthp x   %s *synth2 |2130 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_617 | 511| 2default:defaulthp x   %s *synth2 |2131 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_618 | 535| 2default:defaulthp x   %s *synth2 |2132 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_619 | 511| 2default:defaulthp x   %s *synth2 |2133 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_620 | 511| 2default:defaulthp x   %s *synth2 |2134 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_621 | 511| 2default:defaulthp x   %s *synth2 |2135 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_622 | 511| 2default:defaulthp x   %s *synth2 |2136 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_623 | 535| 2default:defaulthp x   %s *synth2 |2137 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_624 | 535| 2default:defaulthp x   %s *synth2 |2138 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_625 | 535| 2default:defaulthp x   %s *synth2 |2139 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_626 | 535| 2default:defaulthp x   %s *synth2 |2140 | \SFP_GEN[8].QIE_RESET_DELAY |delay_counter_21 | 40| 2default:defaulthp x   %s *synth2 |2141 | \SFP_GEN[8].ngCCM_gbt |ngCCM__xdcDup__8 | 8153| 2default:defaulthp x   %s *synth2 |2142 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__106 | 104| 2default:defaulthp x   %s *synth2 |2143 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__254 | 4| 2default:defaulthp x   %s *synth2 |2144 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__107 | 104| 2default:defaulthp x   %s *synth2 |2145 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__253 | 4| 2default:defaulthp x   %s *synth2 |2146 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__108 | 104| 2default:defaulthp x   %s *synth2 |2147 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__252 | 4| 2default:defaulthp x   %s *synth2 |2148 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__109 | 104| 2default:defaulthp x   %s *synth2 |2149 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__251 | 4| 2default:defaulthp x   %s *synth2 |2150 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__110 | 104| 2default:defaulthp x   %s *synth2 |2151 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__250 | 4| 2default:defaulthp x   %s *synth2 |2152 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__111 | 104| 2default:defaulthp x   %s *synth2 |2153 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__249 | 4| 2default:defaulthp x   %s *synth2 |2154 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__112 | 104| 2default:defaulthp x   %s *synth2 |2155 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__248 | 4| 2default:defaulthp x   %s *synth2 |2156 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__113 | 104| 2default:defaulthp x   %s *synth2 |2157 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__247 | 4| 2default:defaulthp x   %s *synth2 |2158 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__114 | 104| 2default:defaulthp x   %s *synth2 |2159 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__246 | 4| 2default:defaulthp x   %s *synth2 |2160 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__115 | 104| 2default:defaulthp x   %s *synth2 |2161 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__245 | 4| 2default:defaulthp x   %s *synth2 |2162 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__116 | 104| 2default:defaulthp x   %s *synth2 |2163 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__244 | 4| 2default:defaulthp x   %s *synth2 |2164 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__117 | 104| 2default:defaulthp x   %s *synth2 |2165 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__243 | 4| 2default:defaulthp x   %s *synth2 |2166 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__118 | 104| 2default:defaulthp x   %s *synth2 |2167 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__242 | 4| 2default:defaulthp x   %s *synth2 |2168 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__119 | 104| 2default:defaulthp x   %s *synth2 |2169 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__241 | 4| 2default:defaulthp x   %s *synth2 |2170 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__120 | 104| 2default:defaulthp x   %s *synth2 |2171 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__240 | 4| 2default:defaulthp x   %s *synth2 |2172 | CrossClock_DV_cnt |CrossClock_RX_497 | 70| 2default:defaulthp x   %s *synth2 |2173 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__8 | 629| 2default:defaulthp x   %s *synth2 |2174 | JTAGMaster_inst |JTAGMaster__xdcDup__8 | 462| 2default:defaulthp x   %s *synth2 |2175 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__255 | 4| 2default:defaulthp x   %s *synth2 |2176 | JTAG_BRAM |RAM_581 | 117| 2default:defaulthp x   %s *synth2 |2177 | Sync_RX_Reset |Sync_498 | 2| 2default:defaulthp x   %s *synth2 |2178 | Sync_TX_Reset |Sync_499 | 114| 2default:defaulthp x   %s *synth2 |2179 | Sync_error_counter_reset |Sync_500 | 2| 2default:defaulthp x   %s *synth2 |2180 | gbt_rx_checker |gbt_rx_checker_501 | 106| 2default:defaulthp x   %s *synth2 |2181 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_502 | 332| 2default:defaulthp x   %s *synth2 |2182 | i2c_master |i2c_master_usr_576 | 332| 2default:defaulthp x   %s *synth2 |2183 | byte_ctrl |i2c_master_byte_ctrl_577 | 279| 2default:defaulthp x   %s *synth2 |2184 | bit_ctrl |i2c_master_bit_ctrl_578 | 224| 2default:defaulthp x   %s *synth2 |2185 | \bus_status_ctrl.gf_scl |glitch_filter_579 | 18| 2default:defaulthp x   %s *synth2 |2186 | \bus_status_ctrl.gf_sda |glitch_filter_580 | 20| 2default:defaulthp x   %s *synth2 |2187 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_503 | 332| 2default:defaulthp x   %s *synth2 |2188 | i2c_master |i2c_master_usr_571 | 332| 2default:defaulthp x   %s *synth2 |2189 | byte_ctrl |i2c_master_byte_ctrl_572 | 279| 2default:defaulthp x   %s *synth2 |2190 | bit_ctrl |i2c_master_bit_ctrl_573 | 224| 2default:defaulthp x   %s *synth2 |2191 | \bus_status_ctrl.gf_scl |glitch_filter_574 | 18| 2default:defaulthp x   %s *synth2 |2192 | \bus_status_ctrl.gf_sda |glitch_filter_575 | 20| 2default:defaulthp x   %s *synth2 |2193 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_504 | 332| 2default:defaulthp x   %s *synth2 |2194 | i2c_master |i2c_master_usr_566 | 332| 2default:defaulthp x   %s *synth2 |2195 | byte_ctrl |i2c_master_byte_ctrl_567 | 279| 2default:defaulthp x   %s *synth2 |2196 | bit_ctrl |i2c_master_bit_ctrl_568 | 224| 2default:defaulthp x   %s *synth2 |2197 | \bus_status_ctrl.gf_scl |glitch_filter_569 | 18| 2default:defaulthp x   %s *synth2 |2198 | \bus_status_ctrl.gf_sda |glitch_filter_570 | 20| 2default:defaulthp x   %s *synth2 |2199 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_505 | 332| 2default:defaulthp x   %s *synth2 |2200 | i2c_master |i2c_master_usr_561 | 332| 2default:defaulthp x   %s *synth2 |2201 | byte_ctrl |i2c_master_byte_ctrl_562 | 279| 2default:defaulthp x   %s *synth2 |2202 | bit_ctrl |i2c_master_bit_ctrl_563 | 224| 2default:defaulthp x   %s *synth2 |2203 | \bus_status_ctrl.gf_scl |glitch_filter_564 | 18| 2default:defaulthp x   %s *synth2 |2204 | \bus_status_ctrl.gf_sda |glitch_filter_565 | 20| 2default:defaulthp x   %s *synth2 |2205 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_506 | 332| 2default:defaulthp x   %s *synth2 |2206 | i2c_master |i2c_master_usr_556 | 332| 2default:defaulthp x   %s *synth2 |2207 | byte_ctrl |i2c_master_byte_ctrl_557 | 279| 2default:defaulthp x   %s *synth2 |2208 | bit_ctrl |i2c_master_bit_ctrl_558 | 224| 2default:defaulthp x   %s *synth2 |2209 | \bus_status_ctrl.gf_scl |glitch_filter_559 | 18| 2default:defaulthp x   %s *synth2 |2210 | \bus_status_ctrl.gf_sda |glitch_filter_560 | 20| 2default:defaulthp x   %s *synth2 |2211 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_507 | 332| 2default:defaulthp x   %s *synth2 |2212 | i2c_master |i2c_master_usr_551 | 332| 2default:defaulthp x   %s *synth2 |2213 | byte_ctrl |i2c_master_byte_ctrl_552 | 279| 2default:defaulthp x   %s *synth2 |2214 | bit_ctrl |i2c_master_bit_ctrl_553 | 224| 2default:defaulthp x   %s *synth2 |2215 | \bus_status_ctrl.gf_scl |glitch_filter_554 | 18| 2default:defaulthp x   %s *synth2 |2216 | \bus_status_ctrl.gf_sda |glitch_filter_555 | 20| 2default:defaulthp x   %s *synth2 |2217 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_508 | 332| 2default:defaulthp x   %s *synth2 |2218 | i2c_master |i2c_master_usr_546 | 332| 2default:defaulthp x   %s *synth2 |2219 | byte_ctrl |i2c_master_byte_ctrl_547 | 279| 2default:defaulthp x   %s *synth2 |2220 | bit_ctrl |i2c_master_bit_ctrl_548 | 224| 2default:defaulthp x   %s *synth2 |2221 | \bus_status_ctrl.gf_scl |glitch_filter_549 | 18| 2default:defaulthp x   %s *synth2 |2222 | \bus_status_ctrl.gf_sda |glitch_filter_550 | 20| 2default:defaulthp x   %s *synth2 |2223 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_509 | 332| 2default:defaulthp x   %s *synth2 |2224 | i2c_master |i2c_master_usr_541 | 332| 2default:defaulthp x   %s *synth2 |2225 | byte_ctrl |i2c_master_byte_ctrl_542 | 279| 2default:defaulthp x   %s *synth2 |2226 | bit_ctrl |i2c_master_bit_ctrl_543 | 224| 2default:defaulthp x   %s *synth2 |2227 | \bus_status_ctrl.gf_scl |glitch_filter_544 | 18| 2default:defaulthp x   %s *synth2 |2228 | \bus_status_ctrl.gf_sda |glitch_filter_545 | 20| 2default:defaulthp x   %s *synth2 |2229 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_510 | 332| 2default:defaulthp x   %s *synth2 |2230 | i2c_master |i2c_master_usr_536 | 332| 2default:defaulthp x   %s *synth2 |2231 | byte_ctrl |i2c_master_byte_ctrl_537 | 279| 2default:defaulthp x   %s *synth2 |2232 | bit_ctrl |i2c_master_bit_ctrl_538 | 224| 2default:defaulthp x   %s *synth2 |2233 | \bus_status_ctrl.gf_scl |glitch_filter_539 | 18| 2default:defaulthp x   %s *synth2 |2234 | \bus_status_ctrl.gf_sda |glitch_filter_540 | 20| 2default:defaulthp x   %s *synth2 |2235 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_511 | 332| 2default:defaulthp x   %s *synth2 |2236 | i2c_master |i2c_master_usr_531 | 332| 2default:defaulthp x   %s *synth2 |2237 | byte_ctrl |i2c_master_byte_ctrl_532 | 279| 2default:defaulthp x   %s *synth2 |2238 | bit_ctrl |i2c_master_bit_ctrl_533 | 224| 2default:defaulthp x   %s *synth2 |2239 | \bus_status_ctrl.gf_scl |glitch_filter_534 | 18| 2default:defaulthp x   %s *synth2 |2240 | \bus_status_ctrl.gf_sda |glitch_filter_535 | 20| 2default:defaulthp x   %s *synth2 |2241 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_512 | 332| 2default:defaulthp x   %s *synth2 |2242 | i2c_master |i2c_master_usr_526 | 332| 2default:defaulthp x   %s *synth2 |2243 | byte_ctrl |i2c_master_byte_ctrl_527 | 279| 2default:defaulthp x   %s *synth2 |2244 | bit_ctrl |i2c_master_bit_ctrl_528 | 224| 2default:defaulthp x   %s *synth2 |2245 | \bus_status_ctrl.gf_scl |glitch_filter_529 | 18| 2default:defaulthp x   %s *synth2 |2246 | \bus_status_ctrl.gf_sda |glitch_filter_530 | 20| 2default:defaulthp x   %s *synth2 |2247 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_513 | 332| 2default:defaulthp x   %s *synth2 |2248 | i2c_master |i2c_master_usr_521 | 332| 2default:defaulthp x   %s *synth2 |2249 | byte_ctrl |i2c_master_byte_ctrl_522 | 279| 2default:defaulthp x   %s *synth2 |2250 | bit_ctrl |i2c_master_bit_ctrl_523 | 224| 2default:defaulthp x   %s *synth2 |2251 | \bus_status_ctrl.gf_scl |glitch_filter_524 | 18| 2default:defaulthp x   %s *synth2 |2252 | \bus_status_ctrl.gf_sda |glitch_filter_525 | 20| 2default:defaulthp x   %s *synth2 |2253 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_514 | 331| 2default:defaulthp x   %s *synth2 |2254 | i2c_master |i2c_master_usr_516 | 331| 2default:defaulthp x   %s *synth2 |2255 | byte_ctrl |i2c_master_byte_ctrl_517 | 279| 2default:defaulthp x   %s *synth2 |2256 | bit_ctrl |i2c_master_bit_ctrl_518 | 224| 2default:defaulthp x   %s *synth2 |2257 | \bus_status_ctrl.gf_scl |glitch_filter_519 | 18| 2default:defaulthp x   %s *synth2 |2258 | \bus_status_ctrl.gf_sda |glitch_filter_520 | 20| 2default:defaulthp x   %s *synth2 |2259 | prbs |prbs_515 | 25| 2default:defaulthp x   %s *synth2 |2260 | \SFP_GEN[8].ngFEC_module |ngFEC_module_22 | 15549| 2default:defaulthp x   %s *synth2 |2261 | bkp_buffer_ngccm |buffer_ngccm_com_407 | 511| 2default:defaulthp x   %s *synth2 |2262 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_408 | 281| 2default:defaulthp x   %s *synth2 |2263 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_494 | 194| 2default:defaulthp x   %s *synth2 |2264 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_495 | 20| 2default:defaulthp x   %s *synth2 |2265 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_496 | 24| 2default:defaulthp x   %s *synth2 |2266 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_409 | 168| 2default:defaulthp x   %s *synth2 |2267 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_410 | 257| 2default:defaulthp x   %s *synth2 |2268 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_491 | 167| 2default:defaulthp x   %s *synth2 |2269 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_492 | 18| 2default:defaulthp x   %s *synth2 |2270 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_493 | 29| 2default:defaulthp x   %s *synth2 |2271 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_411 | 166| 2default:defaulthp x   %s *synth2 |2272 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_412 | 257| 2default:defaulthp x   %s *synth2 |2273 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_488 | 167| 2default:defaulthp x   %s *synth2 |2274 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_489 | 18| 2default:defaulthp x   %s *synth2 |2275 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_490 | 29| 2default:defaulthp x   %s *synth2 |2276 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_413 | 166| 2default:defaulthp x   %s *synth2 |2277 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_414 | 280| 2default:defaulthp x   %s *synth2 |2278 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_485 | 188| 2default:defaulthp x   %s *synth2 |2279 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_486 | 20| 2default:defaulthp x   %s *synth2 |2280 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_487 | 29| 2default:defaulthp x   %s *synth2 |2281 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_415 | 264| 2default:defaulthp x   %s *synth2 |2282 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_416 | 134| 2default:defaulthp x   %s *synth2 |2283 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_482 | 69| 2default:defaulthp x   %s *synth2 |2284 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_483 | 20| 2default:defaulthp x   %s *synth2 |2285 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_484 | 18| 2default:defaulthp x   %s *synth2 |2286 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_417 | 133| 2default:defaulthp x   %s *synth2 |2287 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_418 | 280| 2default:defaulthp x   %s *synth2 |2288 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_479 | 188| 2default:defaulthp x   %s *synth2 |2289 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_480 | 20| 2default:defaulthp x   %s *synth2 |2290 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_481 | 29| 2default:defaulthp x   %s *synth2 |2291 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_419 | 168| 2default:defaulthp x   %s *synth2 |2292 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_420 | 257| 2default:defaulthp x   %s *synth2 |2293 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_476 | 167| 2default:defaulthp x   %s *synth2 |2294 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_477 | 18| 2default:defaulthp x   %s *synth2 |2295 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_478 | 29| 2default:defaulthp x   %s *synth2 |2296 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_421 | 198| 2default:defaulthp x   %s *synth2 |2297 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_422 | 280| 2default:defaulthp x   %s *synth2 |2298 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_473 | 188| 2default:defaulthp x   %s *synth2 |2299 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_474 | 20| 2default:defaulthp x   %s *synth2 |2300 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_475 | 29| 2default:defaulthp x   %s *synth2 |2301 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_423 | 168| 2default:defaulthp x   %s *synth2 |2302 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_424 | 280| 2default:defaulthp x   %s *synth2 |2303 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_470 | 188| 2default:defaulthp x   %s *synth2 |2304 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_471 | 20| 2default:defaulthp x   %s *synth2 |2305 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_472 | 29| 2default:defaulthp x   %s *synth2 |2306 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_425 | 167| 2default:defaulthp x   %s *synth2 |2307 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_426 | 280| 2default:defaulthp x   %s *synth2 |2308 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_467 | 188| 2default:defaulthp x   %s *synth2 |2309 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_468 | 20| 2default:defaulthp x   %s *synth2 |2310 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_469 | 29| 2default:defaulthp x   %s *synth2 |2311 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_427 | 168| 2default:defaulthp x   %s *synth2 |2312 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_428 | 280| 2default:defaulthp x   %s *synth2 |2313 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_464 | 188| 2default:defaulthp x   %s *synth2 |2314 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_465 | 20| 2default:defaulthp x   %s *synth2 |2315 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_466 | 29| 2default:defaulthp x   %s *synth2 |2316 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_429 | 234| 2default:defaulthp x   %s *synth2 |2317 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_430 | 257| 2default:defaulthp x   %s *synth2 |2318 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_461 | 167| 2default:defaulthp x   %s *synth2 |2319 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_462 | 18| 2default:defaulthp x   %s *synth2 |2320 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_463 | 29| 2default:defaulthp x   %s *synth2 |2321 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_431 | 166| 2default:defaulthp x   %s *synth2 |2322 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_432 | 257| 2default:defaulthp x   %s *synth2 |2323 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_458 | 167| 2default:defaulthp x   %s *synth2 |2324 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_459 | 18| 2default:defaulthp x   %s *synth2 |2325 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_460 | 29| 2default:defaulthp x   %s *synth2 |2326 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_433 | 166| 2default:defaulthp x   %s *synth2 |2327 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_434 | 257| 2default:defaulthp x   %s *synth2 |2328 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_455 | 167| 2default:defaulthp x   %s *synth2 |2329 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_456 | 18| 2default:defaulthp x   %s *synth2 |2330 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_457 | 29| 2default:defaulthp x   %s *synth2 |2331 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_435 | 165| 2default:defaulthp x   %s *synth2 |2332 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_436 | 257| 2default:defaulthp x   %s *synth2 |2333 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_452 | 167| 2default:defaulthp x   %s *synth2 |2334 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_453 | 18| 2default:defaulthp x   %s *synth2 |2335 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_454 | 29| 2default:defaulthp x   %s *synth2 |2336 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_437 | 198| 2default:defaulthp x   %s *synth2 |2337 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_438 | 662| 2default:defaulthp x   %s *synth2 |2338 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_439 | 510| 2default:defaulthp x   %s *synth2 |2339 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_440 | 535| 2default:defaulthp x   %s *synth2 |2340 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_441 | 535| 2default:defaulthp x   %s *synth2 |2341 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_442 | 511| 2default:defaulthp x   %s *synth2 |2342 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_443 | 535| 2default:defaulthp x   %s *synth2 |2343 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_444 | 511| 2default:defaulthp x   %s *synth2 |2344 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_445 | 511| 2default:defaulthp x   %s *synth2 |2345 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_446 | 511| 2default:defaulthp x   %s *synth2 |2346 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_447 | 511| 2default:defaulthp x   %s *synth2 |2347 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_448 | 535| 2default:defaulthp x   %s *synth2 |2348 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_449 | 535| 2default:defaulthp x   %s *synth2 |2349 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_450 | 535| 2default:defaulthp x   %s *synth2 |2350 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_451 | 535| 2default:defaulthp x   %s *synth2 |2351 | \SFP_GEN[9].QIE_RESET_DELAY |delay_counter_23 | 40| 2default:defaulthp x   %s *synth2 |2352 | \SFP_GEN[9].ngCCM_gbt |ngCCM__xdcDup__9 | 8153| 2default:defaulthp x   %s *synth2 |2353 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__121 | 104| 2default:defaulthp x   %s *synth2 |2354 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__430 | 4| 2default:defaulthp x   %s *synth2 |2355 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__122 | 104| 2default:defaulthp x   %s *synth2 |2356 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__429 | 4| 2default:defaulthp x   %s *synth2 |2357 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__123 | 104| 2default:defaulthp x   %s *synth2 |2358 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__428 | 4| 2default:defaulthp x   %s *synth2 |2359 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__124 | 104| 2default:defaulthp x   %s *synth2 |2360 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__427 | 4| 2default:defaulthp x   %s *synth2 |2361 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__125 | 104| 2default:defaulthp x   %s *synth2 |2362 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__426 | 4| 2default:defaulthp x   %s *synth2 |2363 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__126 | 104| 2default:defaulthp x   %s *synth2 |2364 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__425 | 4| 2default:defaulthp x   %s *synth2 |2365 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__127 | 104| 2default:defaulthp x   %s *synth2 |2366 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__424 | 4| 2default:defaulthp x   %s *synth2 |2367 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__128 | 104| 2default:defaulthp x   %s *synth2 |2368 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__423 | 4| 2default:defaulthp x   %s *synth2 |2369 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__129 | 104| 2default:defaulthp x   %s *synth2 |2370 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__422 | 4| 2default:defaulthp x   %s *synth2 |2371 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__130 | 104| 2default:defaulthp x   %s *synth2 |2372 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__421 | 4| 2default:defaulthp x   %s *synth2 |2373 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__131 | 104| 2default:defaulthp x   %s *synth2 |2374 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__420 | 4| 2default:defaulthp x   %s *synth2 |2375 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__132 | 104| 2default:defaulthp x   %s *synth2 |2376 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__419 | 4| 2default:defaulthp x   %s *synth2 |2377 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__133 | 104| 2default:defaulthp x   %s *synth2 |2378 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__418 | 4| 2default:defaulthp x   %s *synth2 |2379 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__134 | 104| 2default:defaulthp x   %s *synth2 |2380 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__417 | 4| 2default:defaulthp x   %s *synth2 |2381 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__135 | 104| 2default:defaulthp x   %s *synth2 |2382 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__416 | 4| 2default:defaulthp x   %s *synth2 |2383 | CrossClock_DV_cnt |CrossClock_RX | 70| 2default:defaulthp x   %s *synth2 |2384 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__9 | 629| 2default:defaulthp x   %s *synth2 |2385 | JTAGMaster_inst |JTAGMaster__xdcDup__9 | 462| 2default:defaulthp x   %s *synth2 |2386 | tck_in_Sync_inst |xpm_cdc_single__parameterized1 | 4| 2default:defaulthp x   %s *synth2 |2387 | JTAG_BRAM |RAM | 117| 2default:defaulthp x   %s *synth2 |2388 | Sync_RX_Reset |Sync | 2| 2default:defaulthp x   %s *synth2 |2389 | Sync_TX_Reset |Sync_332 | 114| 2default:defaulthp x   %s *synth2 |2390 | Sync_error_counter_reset |Sync_333 | 2| 2default:defaulthp x   %s *synth2 |2391 | gbt_rx_checker |gbt_rx_checker | 106| 2default:defaulthp x   %s *synth2 |2392 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge | 332| 2default:defaulthp x   %s *synth2 |2393 | i2c_master |i2c_master_usr_402 | 332| 2default:defaulthp x   %s *synth2 |2394 | byte_ctrl |i2c_master_byte_ctrl_403 | 279| 2default:defaulthp x   %s *synth2 |2395 | bit_ctrl |i2c_master_bit_ctrl_404 | 224| 2default:defaulthp x   %s *synth2 |2396 | \bus_status_ctrl.gf_scl |glitch_filter_405 | 18| 2default:defaulthp x   %s *synth2 |2397 | \bus_status_ctrl.gf_sda |glitch_filter_406 | 20| 2default:defaulthp x   %s *synth2 |2398 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_334 | 332| 2default:defaulthp x   %s *synth2 |2399 | i2c_master |i2c_master_usr_397 | 332| 2default:defaulthp x   %s *synth2 |2400 | byte_ctrl |i2c_master_byte_ctrl_398 | 279| 2default:defaulthp x   %s *synth2 |2401 | bit_ctrl |i2c_master_bit_ctrl_399 | 224| 2default:defaulthp x   %s *synth2 |2402 | \bus_status_ctrl.gf_scl |glitch_filter_400 | 18| 2default:defaulthp x   %s *synth2 |2403 | \bus_status_ctrl.gf_sda |glitch_filter_401 | 20| 2default:defaulthp x   %s *synth2 |2404 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_335 | 332| 2default:defaulthp x   %s *synth2 |2405 | i2c_master |i2c_master_usr_392 | 332| 2default:defaulthp x   %s *synth2 |2406 | byte_ctrl |i2c_master_byte_ctrl_393 | 279| 2default:defaulthp x   %s *synth2 |2407 | bit_ctrl |i2c_master_bit_ctrl_394 | 224| 2default:defaulthp x   %s *synth2 |2408 | \bus_status_ctrl.gf_scl |glitch_filter_395 | 18| 2default:defaulthp x   %s *synth2 |2409 | \bus_status_ctrl.gf_sda |glitch_filter_396 | 20| 2default:defaulthp x   %s *synth2 |2410 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_336 | 332| 2default:defaulthp x   %s *synth2 |2411 | i2c_master |i2c_master_usr_387 | 332| 2default:defaulthp x   %s *synth2 |2412 | byte_ctrl |i2c_master_byte_ctrl_388 | 279| 2default:defaulthp x   %s *synth2 |2413 | bit_ctrl |i2c_master_bit_ctrl_389 | 224| 2default:defaulthp x   %s *synth2 |2414 | \bus_status_ctrl.gf_scl |glitch_filter_390 | 18| 2default:defaulthp x   %s *synth2 |2415 | \bus_status_ctrl.gf_sda |glitch_filter_391 | 20| 2default:defaulthp x   %s *synth2 |2416 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_337 | 332| 2default:defaulthp x   %s *synth2 |2417 | i2c_master |i2c_master_usr_382 | 332| 2default:defaulthp x   %s *synth2 |2418 | byte_ctrl |i2c_master_byte_ctrl_383 | 279| 2default:defaulthp x   %s *synth2 |2419 | bit_ctrl |i2c_master_bit_ctrl_384 | 224| 2default:defaulthp x   %s *synth2 |2420 | \bus_status_ctrl.gf_scl |glitch_filter_385 | 18| 2default:defaulthp x   %s *synth2 |2421 | \bus_status_ctrl.gf_sda |glitch_filter_386 | 20| 2default:defaulthp x   %s *synth2 |2422 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_338 | 332| 2default:defaulthp x   %s *synth2 |2423 | i2c_master |i2c_master_usr_377 | 332| 2default:defaulthp x   %s *synth2 |2424 | byte_ctrl |i2c_master_byte_ctrl_378 | 279| 2default:defaulthp x   %s *synth2 |2425 | bit_ctrl |i2c_master_bit_ctrl_379 | 224| 2default:defaulthp x   %s *synth2 |2426 | \bus_status_ctrl.gf_scl |glitch_filter_380 | 18| 2default:defaulthp x   %s *synth2 |2427 | \bus_status_ctrl.gf_sda |glitch_filter_381 | 20| 2default:defaulthp x   %s *synth2 |2428 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_339 | 332| 2default:defaulthp x   %s *synth2 |2429 | i2c_master |i2c_master_usr_372 | 332| 2default:defaulthp x   %s *synth2 |2430 | byte_ctrl |i2c_master_byte_ctrl_373 | 279| 2default:defaulthp x   %s *synth2 |2431 | bit_ctrl |i2c_master_bit_ctrl_374 | 224| 2default:defaulthp x   %s *synth2 |2432 | \bus_status_ctrl.gf_scl |glitch_filter_375 | 18| 2default:defaulthp x   %s *synth2 |2433 | \bus_status_ctrl.gf_sda |glitch_filter_376 | 20| 2default:defaulthp x   %s *synth2 |2434 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_340 | 332| 2default:defaulthp x   %s *synth2 |2435 | i2c_master |i2c_master_usr_367 | 332| 2default:defaulthp x   %s *synth2 |2436 | byte_ctrl |i2c_master_byte_ctrl_368 | 279| 2default:defaulthp x   %s *synth2 |2437 | bit_ctrl |i2c_master_bit_ctrl_369 | 224| 2default:defaulthp x   %s *synth2 |2438 | \bus_status_ctrl.gf_scl |glitch_filter_370 | 18| 2default:defaulthp x   %s *synth2 |2439 | \bus_status_ctrl.gf_sda |glitch_filter_371 | 20| 2default:defaulthp x   %s *synth2 |2440 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_341 | 332| 2default:defaulthp x   %s *synth2 |2441 | i2c_master |i2c_master_usr_362 | 332| 2default:defaulthp x   %s *synth2 |2442 | byte_ctrl |i2c_master_byte_ctrl_363 | 279| 2default:defaulthp x   %s *synth2 |2443 | bit_ctrl |i2c_master_bit_ctrl_364 | 224| 2default:defaulthp x   %s *synth2 |2444 | \bus_status_ctrl.gf_scl |glitch_filter_365 | 18| 2default:defaulthp x   %s *synth2 |2445 | \bus_status_ctrl.gf_sda |glitch_filter_366 | 20| 2default:defaulthp x   %s *synth2 |2446 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_342 | 332| 2default:defaulthp x   %s *synth2 |2447 | i2c_master |i2c_master_usr_357 | 332| 2default:defaulthp x   %s *synth2 |2448 | byte_ctrl |i2c_master_byte_ctrl_358 | 279| 2default:defaulthp x   %s *synth2 |2449 | bit_ctrl |i2c_master_bit_ctrl_359 | 224| 2default:defaulthp x   %s *synth2 |2450 | \bus_status_ctrl.gf_scl |glitch_filter_360 | 18| 2default:defaulthp x   %s *synth2 |2451 | \bus_status_ctrl.gf_sda |glitch_filter_361 | 20| 2default:defaulthp x   %s *synth2 |2452 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_343 | 332| 2default:defaulthp x   %s *synth2 |2453 | i2c_master |i2c_master_usr_352 | 332| 2default:defaulthp x   %s *synth2 |2454 | byte_ctrl |i2c_master_byte_ctrl_353 | 279| 2default:defaulthp x   %s *synth2 |2455 | bit_ctrl |i2c_master_bit_ctrl_354 | 224| 2default:defaulthp x   %s *synth2 |2456 | \bus_status_ctrl.gf_scl |glitch_filter_355 | 18| 2default:defaulthp x   %s *synth2 |2457 | \bus_status_ctrl.gf_sda |glitch_filter_356 | 20| 2default:defaulthp x   %s *synth2 |2458 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_344 | 332| 2default:defaulthp x   %s *synth2 |2459 | i2c_master |i2c_master_usr_347 | 332| 2default:defaulthp x   %s *synth2 |2460 | byte_ctrl |i2c_master_byte_ctrl_348 | 279| 2default:defaulthp x   %s *synth2 |2461 | bit_ctrl |i2c_master_bit_ctrl_349 | 224| 2default:defaulthp x   %s *synth2 |2462 | \bus_status_ctrl.gf_scl |glitch_filter_350 | 18| 2default:defaulthp x   %s *synth2 |2463 | \bus_status_ctrl.gf_sda |glitch_filter_351 | 20| 2default:defaulthp x   %s *synth2 |2464 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_345 | 331| 2default:defaulthp x   %s *synth2 |2465 | i2c_master |i2c_master_usr | 331| 2default:defaulthp x   %s *synth2 |2466 | byte_ctrl |i2c_master_byte_ctrl | 279| 2default:defaulthp x   %s *synth2 |2467 | bit_ctrl |i2c_master_bit_ctrl | 224| 2default:defaulthp x   %s *synth2 |2468 | \bus_status_ctrl.gf_scl |glitch_filter | 18| 2default:defaulthp x   %s *synth2 |2469 | \bus_status_ctrl.gf_sda |glitch_filter_346 | 20| 2default:defaulthp x   %s *synth2 |2470 | prbs |prbs | 25| 2default:defaulthp x   %s *synth2 |2471 | \SFP_GEN[9].ngFEC_module |ngFEC_module_24 | 15549| 2default:defaulthp x   %s *synth2 |2472 | bkp_buffer_ngccm |buffer_ngccm_com | 511| 2default:defaulthp x   %s *synth2 |2473 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM | 281| 2default:defaulthp x   %s *synth2 |2474 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_329 | 194| 2default:defaulthp x   %s *synth2 |2475 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_330 | 20| 2default:defaulthp x   %s *synth2 |2476 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_331 | 24| 2default:defaulthp x   %s *synth2 |2477 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com | 168| 2default:defaulthp x   %s *synth2 |2478 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_262 | 257| 2default:defaulthp x   %s *synth2 |2479 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_326 | 167| 2default:defaulthp x   %s *synth2 |2480 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_327 | 18| 2default:defaulthp x   %s *synth2 |2481 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_328 | 29| 2default:defaulthp x   %s *synth2 |2482 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19 | 166| 2default:defaulthp x   %s *synth2 |2483 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_263 | 257| 2default:defaulthp x   %s *synth2 |2484 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_323 | 167| 2default:defaulthp x   %s *synth2 |2485 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_324 | 18| 2default:defaulthp x   %s *synth2 |2486 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_325 | 29| 2default:defaulthp x   %s *synth2 |2487 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21 | 166| 2default:defaulthp x   %s *synth2 |2488 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_264 | 280| 2default:defaulthp x   %s *synth2 |2489 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_320 | 188| 2default:defaulthp x   %s *synth2 |2490 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_321 | 20| 2default:defaulthp x   %s *synth2 |2491 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_322 | 29| 2default:defaulthp x   %s *synth2 |2492 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23 | 264| 2default:defaulthp x   %s *synth2 |2493 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_265 | 134| 2default:defaulthp x   %s *synth2 |2494 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_317 | 69| 2default:defaulthp x   %s *synth2 |2495 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_318 | 20| 2default:defaulthp x   %s *synth2 |2496 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_319 | 18| 2default:defaulthp x   %s *synth2 |2497 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25 | 133| 2default:defaulthp x   %s *synth2 |2498 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_266 | 280| 2default:defaulthp x   %s *synth2 |2499 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_314 | 188| 2default:defaulthp x   %s *synth2 |2500 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_315 | 20| 2default:defaulthp x   %s *synth2 |2501 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_316 | 29| 2default:defaulthp x   %s *synth2 |2502 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27 | 168| 2default:defaulthp x   %s *synth2 |2503 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_267 | 257| 2default:defaulthp x   %s *synth2 |2504 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_311 | 167| 2default:defaulthp x   %s *synth2 |2505 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_312 | 18| 2default:defaulthp x   %s *synth2 |2506 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_313 | 29| 2default:defaulthp x   %s *synth2 |2507 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1 | 198| 2default:defaulthp x   %s *synth2 |2508 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_268 | 280| 2default:defaulthp x   %s *synth2 |2509 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_308 | 188| 2default:defaulthp x   %s *synth2 |2510 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_309 | 20| 2default:defaulthp x   %s *synth2 |2511 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_310 | 29| 2default:defaulthp x   %s *synth2 |2512 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3 | 168| 2default:defaulthp x   %s *synth2 |2513 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_269 | 280| 2default:defaulthp x   %s *synth2 |2514 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_305 | 188| 2default:defaulthp x   %s *synth2 |2515 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_306 | 20| 2default:defaulthp x   %s *synth2 |2516 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_307 | 29| 2default:defaulthp x   %s *synth2 |2517 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5 | 167| 2default:defaulthp x   %s *synth2 |2518 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_270 | 280| 2default:defaulthp x   %s *synth2 |2519 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_302 | 188| 2default:defaulthp x   %s *synth2 |2520 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_303 | 20| 2default:defaulthp x   %s *synth2 |2521 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_304 | 29| 2default:defaulthp x   %s *synth2 |2522 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7 | 168| 2default:defaulthp x   %s *synth2 |2523 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_271 | 280| 2default:defaulthp x   %s *synth2 |2524 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_299 | 188| 2default:defaulthp x   %s *synth2 |2525 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_300 | 20| 2default:defaulthp x   %s *synth2 |2526 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_301 | 29| 2default:defaulthp x   %s *synth2 |2527 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9 | 234| 2default:defaulthp x   %s *synth2 |2528 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_272 | 257| 2default:defaulthp x   %s *synth2 |2529 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_296 | 167| 2default:defaulthp x   %s *synth2 |2530 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_297 | 18| 2default:defaulthp x   %s *synth2 |2531 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_298 | 29| 2default:defaulthp x   %s *synth2 |2532 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11 | 166| 2default:defaulthp x   %s *synth2 |2533 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_273 | 257| 2default:defaulthp x   %s *synth2 |2534 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_293 | 167| 2default:defaulthp x   %s *synth2 |2535 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_294 | 18| 2default:defaulthp x   %s *synth2 |2536 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_295 | 29| 2default:defaulthp x   %s *synth2 |2537 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13 | 166| 2default:defaulthp x   %s *synth2 |2538 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_274 | 257| 2default:defaulthp x   %s *synth2 |2539 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_290 | 167| 2default:defaulthp x   %s *synth2 |2540 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_291 | 18| 2default:defaulthp x   %s *synth2 |2541 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_292 | 29| 2default:defaulthp x   %s *synth2 |2542 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15 | 165| 2default:defaulthp x   %s *synth2 |2543 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_275 | 257| 2default:defaulthp x   %s *synth2 |2544 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0 | 167| 2default:defaulthp x   %s *synth2 |2545 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO | 18| 2default:defaulthp x   %s *synth2 |2546 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_289 | 29| 2default:defaulthp x   %s *synth2 |2547 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17 | 198| 2default:defaulthp x   %s *synth2 |2548 | buffer_ngccm_jtag |buffer_ngccm_jtag_com | 662| 2default:defaulthp x   %s *synth2 |2549 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_276 | 510| 2default:defaulthp x   %s *synth2 |2550 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_277 | 535| 2default:defaulthp x   %s *synth2 |2551 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_278 | 535| 2default:defaulthp x   %s *synth2 |2552 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_279 | 511| 2default:defaulthp x   %s *synth2 |2553 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_280 | 535| 2default:defaulthp x   %s *synth2 |2554 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_281 | 511| 2default:defaulthp x   %s *synth2 |2555 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_282 | 511| 2default:defaulthp x   %s *synth2 |2556 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_283 | 511| 2default:defaulthp x   %s *synth2 |2557 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_284 | 511| 2default:defaulthp x   %s *synth2 |2558 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_285 | 535| 2default:defaulthp x   %s *synth2 |2559 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_286 | 535| 2default:defaulthp x   %s *synth2 |2560 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_287 | 535| 2default:defaulthp x   %s *synth2 |2561 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_288 | 535| 2default:defaulthp x   %s *synth2 |2562 | cdce_synch |cdce_synchronizer | 82| 2default:defaulthp x   %s *synth2 |2563 | clkRate0 |clkRateTool32 | 110| 2default:defaulthp x   %s *synth2 |2564 | clkRate1 |clkRateTool32_25 | 110| 2default:defaulthp x   %s *synth2 |2565 | clkRate2 |clkRateTool32_26 | 110| 2default:defaulthp x   %s *synth2 |2566 | \clk_rate_gen[10].clkRate3 |clkRateTool32_27 | 109| 2default:defaulthp x   %s *synth2 |2567 | \clk_rate_gen[11].clkRate3 |clkRateTool32_28 | 109| 2default:defaulthp x   %s *synth2 |2568 | \clk_rate_gen[12].clkRate3 |clkRateTool32_29 | 109| 2default:defaulthp x   %s *synth2 |2569 | \clk_rate_gen[1].clkRate3 |clkRateTool32_30 | 109| 2default:defaulthp x   %s *synth2 |2570 | \clk_rate_gen[2].clkRate3 |clkRateTool32_31 | 109| 2default:defaulthp x   %s *synth2 |2571 | \clk_rate_gen[3].clkRate3 |clkRateTool32_32 | 109| 2default:defaulthp x   %s *synth2 |2572 | \clk_rate_gen[4].clkRate3 |clkRateTool32_33 | 109| 2default:defaulthp x   %s *synth2 |2573 | \clk_rate_gen[5].clkRate3 |clkRateTool32_34 | 109| 2default:defaulthp x   %s *synth2 |2574 | \clk_rate_gen[6].clkRate3 |clkRateTool32_35 | 109| 2default:defaulthp x   %s *synth2 |2575 | \clk_rate_gen[7].clkRate3 |clkRateTool32_36 | 109| 2default:defaulthp x   %s *synth2 |2576 | \clk_rate_gen[8].clkRate3 |clkRateTool32_37 | 109| 2default:defaulthp x   %s *synth2 |2577 | \clk_rate_gen[9].clkRate3 |clkRateTool32_38 | 109| 2default:defaulthp x   %s *synth2 |2578 | ctrl_regs_inst |ipb_user_control_regs | 1980| 2default:defaulthp x   %s *synth2 |2579 | dmdt_clk |dmdt_clock_gen | 7| 2default:defaulthp x   %s *synth2 |2580 | mmcm1 |phase_mon_mmcm_1 | 3| 2default:defaulthp x   %s *synth2 |2581 | U0 |phase_mon_mmcm_1_clk_wiz | 3| 2default:defaulthp x   %s *synth2 |2582 | mmcm2 |phase_mon_mmcm_2 | 4| 2default:defaulthp x   %s *synth2 |2583 | U0 |phase_mon_mmcm_2_clk_wiz | 4| 2default:defaulthp x   %s *synth2 |2584 | dmdt_meas |dmtd_phase_meas | 784| 2default:defaulthp x   %s *synth2 |2585 | DMTD_A |dmtd_with_deglitcher | 146| 2default:defaulthp x   %s *synth2 |2586 | U_Sync_Resync_Done |gc_sync_ffs_259 | 2| 2default:defaulthp x   %s *synth2 |2587 | U_Sync_Resync_Pulse |gc_sync_ffs_260 | 2| 2default:defaulthp x   %s *synth2 |2588 | U_sync_tag_strobe |gc_sync_ffs_261 | 10| 2default:defaulthp x   %s *synth2 |2589 | DMTD_B |dmtd_with_deglitcher_221 | 141| 2default:defaulthp x   %s *synth2 |2590 | U_Sync_Resync_Done |gc_sync_ffs_256 | 2| 2default:defaulthp x   %s *synth2 |2591 | U_Sync_Resync_Pulse |gc_sync_ffs_257 | 2| 2default:defaulthp x   %s *synth2 |2592 | U_sync_tag_strobe |gc_sync_ffs_258 | 5| 2default:defaulthp x   %s *synth2 |2593 | sync_busy_clka |gc_sync_ffs | 3| 2default:defaulthp x   %s *synth2 |2594 | sync_done_clka |gc_sync_ffs_222 | 6| 2default:defaulthp x   %s *synth2 |2595 | sync_reset_dmtdclk |gc_sync_ffs_223 | 4| 2default:defaulthp x   %s *synth2 |2596 | \t[0].o |gc_sync_ffs_224 | 3| 2default:defaulthp x   %s *synth2 |2597 | \t[10].o |gc_sync_ffs_225 | 3| 2default:defaulthp x   %s *synth2 |2598 | \t[11].o |gc_sync_ffs_226 | 3| 2default:defaulthp x   %s *synth2 |2599 | \t[12].o |gc_sync_ffs_227 | 3| 2default:defaulthp x   %s *synth2 |2600 | \t[13].o |gc_sync_ffs_228 | 3| 2default:defaulthp x   %s *synth2 |2601 | \t[14].o |gc_sync_ffs_229 | 3| 2default:defaulthp x   %s *synth2 |2602 | \t[15].o |gc_sync_ffs_230 | 3| 2default:defaulthp x   %s *synth2 |2603 | \t[16].o |gc_sync_ffs_231 | 3| 2default:defaulthp x   %s *synth2 |2604 | \t[17].o |gc_sync_ffs_232 | 3| 2default:defaulthp x   %s *synth2 |2605 | \t[18].o |gc_sync_ffs_233 | 3| 2default:defaulthp x   %s *synth2 |2606 | \t[19].o |gc_sync_ffs_234 | 3| 2default:defaulthp x   %s *synth2 |2607 | \t[1].o |gc_sync_ffs_235 | 3| 2default:defaulthp x   %s *synth2 |2608 | \t[20].o |gc_sync_ffs_236 | 3| 2default:defaulthp x   %s *synth2 |2609 | \t[21].o |gc_sync_ffs_237 | 3| 2default:defaulthp x   %s *synth2 |2610 | \t[22].o |gc_sync_ffs_238 | 3| 2default:defaulthp x   %s *synth2 |2611 | \t[23].o |gc_sync_ffs_239 | 3| 2default:defaulthp x   %s *synth2 |2612 | \t[24].o |gc_sync_ffs_240 | 3| 2default:defaulthp x   %s *synth2 |2613 | \t[25].o |gc_sync_ffs_241 | 3| 2default:defaulthp x   %s *synth2 |2614 | \t[26].o |gc_sync_ffs_242 | 3| 2default:defaulthp x   %s *synth2 |2615 | \t[27].o |gc_sync_ffs_243 | 3| 2default:defaulthp x   %s *synth2 |2616 | \t[28].o |gc_sync_ffs_244 | 3| 2default:defaulthp x   %s *synth2 |2617 | \t[29].o |gc_sync_ffs_245 | 3| 2default:defaulthp x   %s *synth2 |2618 | \t[2].o |gc_sync_ffs_246 | 3| 2default:defaulthp x   %s *synth2 |2619 | \t[30].o |gc_sync_ffs_247 | 3| 2default:defaulthp x   %s *synth2 |2620 | \t[31].o |gc_sync_ffs_248 | 3| 2default:defaulthp x   %s *synth2 |2621 | \t[3].o |gc_sync_ffs_249 | 3| 2default:defaulthp x   %s *synth2 |2622 | \t[4].o |gc_sync_ffs_250 | 3| 2default:defaulthp x   %s *synth2 |2623 | \t[5].o |gc_sync_ffs_251 | 3| 2default:defaulthp x   %s *synth2 |2624 | \t[6].o |gc_sync_ffs_252 | 3| 2default:defaulthp x   %s *synth2 |2625 | \t[7].o |gc_sync_ffs_253 | 3| 2default:defaulthp x   %s *synth2 |2626 | \t[8].o |gc_sync_ffs_254 | 3| 2default:defaulthp x   %s *synth2 |2627 | \t[9].o |gc_sync_ffs_255 | 3| 2default:defaulthp x   %s *synth2 |2628 | \g_pm[10].phase_mon |pm__xdcDup__10 | 97| 2default:defaulthp x   %s *synth2 |2629 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__52 | 5| 2default:defaulthp x   %s *synth2 |2630 | sample_PS_Sync_inst |xpm_cdc_single__53 | 5| 2default:defaulthp x   %s *synth2 |2631 | \g_pm[11].phase_mon |pm__xdcDup__11 | 97| 2default:defaulthp x   %s *synth2 |2632 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__50 | 5| 2default:defaulthp x   %s *synth2 |2633 | sample_PS_Sync_inst |xpm_cdc_single__51 | 5| 2default:defaulthp x   %s *synth2 |2634 | \g_pm[12].phase_mon |pm | 97| 2default:defaulthp x   %s *synth2 |2635 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__48 | 5| 2default:defaulthp x   %s *synth2 |2636 | sample_PS_Sync_inst |xpm_cdc_single__49 | 5| 2default:defaulthp x   %s *synth2 |2637 | \g_pm[1].phase_mon |pm__xdcDup__1 | 97| 2default:defaulthp x   %s *synth2 |2638 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__70 | 5| 2default:defaulthp x   %s *synth2 |2639 | sample_PS_Sync_inst |xpm_cdc_single | 5| 2default:defaulthp x   %s *synth2 |2640 | \g_pm[2].phase_mon |pm__xdcDup__2 | 97| 2default:defaulthp x   %s *synth2 |2641 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__68 | 5| 2default:defaulthp x   %s *synth2 |2642 | sample_PS_Sync_inst |xpm_cdc_single__69 | 5| 2default:defaulthp x   %s *synth2 |2643 | \g_pm[3].phase_mon |pm__xdcDup__3 | 97| 2default:defaulthp x   %s *synth2 |2644 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__66 | 5| 2default:defaulthp x   %s *synth2 |2645 | sample_PS_Sync_inst |xpm_cdc_single__67 | 5| 2default:defaulthp x   %s *synth2 |2646 | \g_pm[4].phase_mon |pm__xdcDup__4 | 97| 2default:defaulthp x   %s *synth2 |2647 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__64 | 5| 2default:defaulthp x   %s *synth2 |2648 | sample_PS_Sync_inst |xpm_cdc_single__65 | 5| 2default:defaulthp x   %s *synth2 |2649 | \g_pm[5].phase_mon |pm__xdcDup__5 | 97| 2default:defaulthp x   %s *synth2 |2650 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__62 | 5| 2default:defaulthp x   %s *synth2 |2651 | sample_PS_Sync_inst |xpm_cdc_single__63 | 5| 2default:defaulthp x   %s *synth2 |2652 | \g_pm[6].phase_mon |pm__xdcDup__6 | 97| 2default:defaulthp x   %s *synth2 |2653 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__60 | 5| 2default:defaulthp x   %s *synth2 |2654 | sample_PS_Sync_inst |xpm_cdc_single__61 | 5| 2default:defaulthp x   %s *synth2 |2655 | \g_pm[7].phase_mon |pm__xdcDup__7 | 97| 2default:defaulthp x   %s *synth2 |2656 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__58 | 5| 2default:defaulthp x   %s *synth2 |2657 | sample_PS_Sync_inst |xpm_cdc_single__59 | 5| 2default:defaulthp x   %s *synth2 |2658 | \g_pm[8].phase_mon |pm__xdcDup__8 | 97| 2default:defaulthp x   %s *synth2 |2659 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__56 | 5| 2default:defaulthp x   %s *synth2 |2660 | sample_PS_Sync_inst |xpm_cdc_single__57 | 5| 2default:defaulthp x   %s *synth2 |2661 | \g_pm[9].phase_mon |pm__xdcDup__9 | 97| 2default:defaulthp x   %s *synth2 |2662 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__54 | 5| 2default:defaulthp x   %s *synth2 |2663 | sample_PS_Sync_inst |xpm_cdc_single__55 | 5| 2default:defaulthp x   %s *synth2 |2664 | gbtbank1_l12_118 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1 | 8778| 2default:defaulthp x   %s *synth2 |2665 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset_173 | 68| 2default:defaulthp x   %s *synth2 |2666 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_174 | 68| 2default:defaulthp x   %s *synth2 |2667 | \gbtBank_rst_gen[3].gbtBank_gbtBankRst |gbt_bank_reset_175 | 68| 2default:defaulthp x   %s *synth2 |2668 | gbt_inst |gbt_bank__xdcDup__1 | 8454| 2default:defaulthp x   %s *synth2 |2669 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx_176 | 546| 2default:defaulthp x   %s *synth2 |2670 | decoder |gbt_rx_decoder_215 | 1| 2default:defaulthp x   %s *synth2 |2671 | descrambler |gbt_rx_descrambler_216 | 247| 2default:defaulthp x   %s *synth2 |2672 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_217 | 61| 2default:defaulthp x   %s *synth2 |2673 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_218 | 61| 2default:defaulthp x   %s *synth2 |2674 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_219 | 60| 2default:defaulthp x   %s *synth2 |2675 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_220 | 61| 2default:defaulthp x   %s *synth2 |2676 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_177 | 546| 2default:defaulthp x   %s *synth2 |2677 | decoder |gbt_rx_decoder_209 | 1| 2default:defaulthp x   %s *synth2 |2678 | descrambler |gbt_rx_descrambler_210 | 247| 2default:defaulthp x   %s *synth2 |2679 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_211 | 61| 2default:defaulthp x   %s *synth2 |2680 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_212 | 61| 2default:defaulthp x   %s *synth2 |2681 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_213 | 60| 2default:defaulthp x   %s *synth2 |2682 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_214 | 61| 2default:defaulthp x   %s *synth2 |2683 | \gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst |gbt_rx_178 | 546| 2default:defaulthp x   %s *synth2 |2684 | decoder |gbt_rx_decoder_203 | 1| 2default:defaulthp x   %s *synth2 |2685 | descrambler |gbt_rx_descrambler_204 | 247| 2default:defaulthp x   %s *synth2 |2686 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_205 | 61| 2default:defaulthp x   %s *synth2 |2687 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_206 | 61| 2default:defaulthp x   %s *synth2 |2688 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_207 | 60| 2default:defaulthp x   %s *synth2 |2689 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_208 | 61| 2default:defaulthp x   %s *synth2 |2690 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox_179 | 1316| 2default:defaulthp x   %s *synth2 |2691 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_180 | 1316| 2default:defaulthp x   %s *synth2 |2692 | \gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst |gbt_rx_gearbox_181 | 1316| 2default:defaulthp x   %s *synth2 |2693 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx_182 | 328| 2default:defaulthp x   %s *synth2 |2694 | scrambler |gbt_tx_scrambler_198 | 328| 2default:defaulthp x   %s *synth2 |2695 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_199 | 83| 2default:defaulthp x   %s *synth2 |2696 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_200 | 82| 2default:defaulthp x   %s *synth2 |2697 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_201 | 80| 2default:defaulthp x   %s *synth2 |2698 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_202 | 82| 2default:defaulthp x   %s *synth2 |2699 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_183 | 328| 2default:defaulthp x   %s *synth2 |2700 | scrambler |gbt_tx_scrambler_193 | 328| 2default:defaulthp x   %s *synth2 |2701 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_194 | 83| 2default:defaulthp x   %s *synth2 |2702 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_195 | 82| 2default:defaulthp x   %s *synth2 |2703 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_196 | 80| 2default:defaulthp x   %s *synth2 |2704 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_197 | 82| 2default:defaulthp x   %s *synth2 |2705 | \gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst |gbt_tx_184 | 328| 2default:defaulthp x   %s *synth2 |2706 | scrambler |gbt_tx_scrambler_188 | 328| 2default:defaulthp x   %s *synth2 |2707 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_189 | 83| 2default:defaulthp x   %s *synth2 |2708 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_190 | 82| 2default:defaulthp x   %s *synth2 |2709 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_191 | 80| 2default:defaulthp x   %s *synth2 |2710 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_192 | 82| 2default:defaulthp x   %s *synth2 |2711 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__1 | 195| 2default:defaulthp x   %s *synth2 |2712 | xpm_cdc_single_inst |xpm_cdc_single__38 | 5| 2default:defaulthp x   %s *synth2 |2713 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__2 | 195| 2default:defaulthp x   %s *synth2 |2714 | xpm_cdc_single_inst |xpm_cdc_single__37 | 5| 2default:defaulthp x   %s *synth2 |2715 | \gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__3 | 195| 2default:defaulthp x   %s *synth2 |2716 | xpm_cdc_single_inst |xpm_cdc_single__36 | 5| 2default:defaulthp x   %s *synth2 |2717 | mgt_inst |mgt__xdcDup__1 | 1299| 2default:defaulthp x   %s *synth2 |2718 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__2 | 29| 2default:defaulthp x   %s *synth2 |2719 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__3 | 29| 2default:defaulthp x   %s *synth2 |2720 | \gtxLatOpt_gen[3].rxBitSlipControl |mgt_bitslipctrl__4 | 29| 2default:defaulthp x   %s *synth2 |2721 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch_185 | 122| 2default:defaulthp x   %s *synth2 |2722 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_186 | 122| 2default:defaulthp x   %s *synth2 |2723 | \gtxLatOpt_gen[3].patternSearch |mgt_framealigner_pattsearch_187 | 122| 2default:defaulthp x   %s *synth2 |2724 | gbtbank2_l12_117 |xlx_k7v7_gbt_ngFEC_design__parameterized1 | 5852| 2default:defaulthp x   %s *synth2 |2725 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset_141 | 68| 2default:defaulthp x   %s *synth2 |2726 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_142 | 68| 2default:defaulthp x   %s *synth2 |2727 | gbt_inst |gbt_bank__parameterized0 | 5636| 2default:defaulthp x   %s *synth2 |2728 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx_143 | 546| 2default:defaulthp x   %s *synth2 |2729 | decoder |gbt_rx_decoder_167 | 1| 2default:defaulthp x   %s *synth2 |2730 | descrambler |gbt_rx_descrambler_168 | 247| 2default:defaulthp x   %s *synth2 |2731 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_169 | 61| 2default:defaulthp x   %s *synth2 |2732 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_170 | 61| 2default:defaulthp x   %s *synth2 |2733 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_171 | 60| 2default:defaulthp x   %s *synth2 |2734 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_172 | 61| 2default:defaulthp x   %s *synth2 |2735 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_144 | 546| 2default:defaulthp x   %s *synth2 |2736 | decoder |gbt_rx_decoder_161 | 1| 2default:defaulthp x   %s *synth2 |2737 | descrambler |gbt_rx_descrambler_162 | 247| 2default:defaulthp x   %s *synth2 |2738 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_163 | 61| 2default:defaulthp x   %s *synth2 |2739 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_164 | 61| 2default:defaulthp x   %s *synth2 |2740 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_165 | 60| 2default:defaulthp x   %s *synth2 |2741 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_166 | 61| 2default:defaulthp x   %s *synth2 |2742 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox_145 | 1316| 2default:defaulthp x   %s *synth2 |2743 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_146 | 1316| 2default:defaulthp x   %s *synth2 |2744 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx_147 | 328| 2default:defaulthp x   %s *synth2 |2745 | scrambler |gbt_tx_scrambler_156 | 328| 2default:defaulthp x   %s *synth2 |2746 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_157 | 83| 2default:defaulthp x   %s *synth2 |2747 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_158 | 82| 2default:defaulthp x   %s *synth2 |2748 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_159 | 80| 2default:defaulthp x   %s *synth2 |2749 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_160 | 82| 2default:defaulthp x   %s *synth2 |2750 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_148 | 328| 2default:defaulthp x   %s *synth2 |2751 | scrambler |gbt_tx_scrambler_151 | 328| 2default:defaulthp x   %s *synth2 |2752 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_152 | 83| 2default:defaulthp x   %s *synth2 |2753 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_153 | 82| 2default:defaulthp x   %s *synth2 |2754 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_154 | 80| 2default:defaulthp x   %s *synth2 |2755 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_155 | 82| 2default:defaulthp x   %s *synth2 |2756 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__4 | 195| 2default:defaulthp x   %s *synth2 |2757 | xpm_cdc_single_inst |xpm_cdc_single__40 | 5| 2default:defaulthp x   %s *synth2 |2758 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__5 | 195| 2default:defaulthp x   %s *synth2 |2759 | xpm_cdc_single_inst |xpm_cdc_single__39 | 5| 2default:defaulthp x   %s *synth2 |2760 | mgt_inst |mgt__parameterized0 | 866| 2default:defaulthp x   %s *synth2 |2761 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__5 | 29| 2default:defaulthp x   %s *synth2 |2762 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__6 | 29| 2default:defaulthp x   %s *synth2 |2763 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch_149 | 122| 2default:defaulthp x   %s *synth2 |2764 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_150 | 122| 2default:defaulthp x   %s *synth2 |2765 | gbtbank3_l12_116 |xlx_k7v7_gbt_ngFEC_design | 8778| 2default:defaulthp x   %s *synth2 |2766 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset_93 | 68| 2default:defaulthp x   %s *synth2 |2767 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_94 | 68| 2default:defaulthp x   %s *synth2 |2768 | \gbtBank_rst_gen[3].gbtBank_gbtBankRst |gbt_bank_reset_95 | 68| 2default:defaulthp x   %s *synth2 |2769 | gbt_inst |gbt_bank | 8454| 2default:defaulthp x   %s *synth2 |2770 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx_96 | 546| 2default:defaulthp x   %s *synth2 |2771 | decoder |gbt_rx_decoder_135 | 1| 2default:defaulthp x   %s *synth2 |2772 | descrambler |gbt_rx_descrambler_136 | 247| 2default:defaulthp x   %s *synth2 |2773 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_137 | 61| 2default:defaulthp x   %s *synth2 |2774 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_138 | 61| 2default:defaulthp x   %s *synth2 |2775 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_139 | 60| 2default:defaulthp x   %s *synth2 |2776 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_140 | 61| 2default:defaulthp x   %s *synth2 |2777 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_97 | 546| 2default:defaulthp x   %s *synth2 |2778 | decoder |gbt_rx_decoder_129 | 1| 2default:defaulthp x   %s *synth2 |2779 | descrambler |gbt_rx_descrambler_130 | 247| 2default:defaulthp x   %s *synth2 |2780 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_131 | 61| 2default:defaulthp x   %s *synth2 |2781 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_132 | 61| 2default:defaulthp x   %s *synth2 |2782 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_133 | 60| 2default:defaulthp x   %s *synth2 |2783 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_134 | 61| 2default:defaulthp x   %s *synth2 |2784 | \gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst |gbt_rx_98 | 546| 2default:defaulthp x   %s *synth2 |2785 | decoder |gbt_rx_decoder_123 | 1| 2default:defaulthp x   %s *synth2 |2786 | descrambler |gbt_rx_descrambler_124 | 247| 2default:defaulthp x   %s *synth2 |2787 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_125 | 61| 2default:defaulthp x   %s *synth2 |2788 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_126 | 61| 2default:defaulthp x   %s *synth2 |2789 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_127 | 60| 2default:defaulthp x   %s *synth2 |2790 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_128 | 61| 2default:defaulthp x   %s *synth2 |2791 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox_99 | 1316| 2default:defaulthp x   %s *synth2 |2792 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_100 | 1316| 2default:defaulthp x   %s *synth2 |2793 | \gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst |gbt_rx_gearbox_101 | 1316| 2default:defaulthp x   %s *synth2 |2794 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx_102 | 328| 2default:defaulthp x   %s *synth2 |2795 | scrambler |gbt_tx_scrambler_118 | 328| 2default:defaulthp x   %s *synth2 |2796 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_119 | 83| 2default:defaulthp x   %s *synth2 |2797 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_120 | 82| 2default:defaulthp x   %s *synth2 |2798 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_121 | 80| 2default:defaulthp x   %s *synth2 |2799 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_122 | 82| 2default:defaulthp x   %s *synth2 |2800 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_103 | 328| 2default:defaulthp x   %s *synth2 |2801 | scrambler |gbt_tx_scrambler_113 | 328| 2default:defaulthp x   %s *synth2 |2802 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_114 | 83| 2default:defaulthp x   %s *synth2 |2803 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_115 | 82| 2default:defaulthp x   %s *synth2 |2804 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_116 | 80| 2default:defaulthp x   %s *synth2 |2805 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_117 | 82| 2default:defaulthp x   %s *synth2 |2806 | \gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst |gbt_tx_104 | 328| 2default:defaulthp x   %s *synth2 |2807 | scrambler |gbt_tx_scrambler_108 | 328| 2default:defaulthp x   %s *synth2 |2808 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_109 | 83| 2default:defaulthp x   %s *synth2 |2809 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_110 | 82| 2default:defaulthp x   %s *synth2 |2810 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_111 | 80| 2default:defaulthp x   %s *synth2 |2811 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_112 | 82| 2default:defaulthp x   %s *synth2 |2812 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__6 | 195| 2default:defaulthp x   %s *synth2 |2813 | xpm_cdc_single_inst |xpm_cdc_single__43 | 5| 2default:defaulthp x   %s *synth2 |2814 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__7 | 195| 2default:defaulthp x   %s *synth2 |2815 | xpm_cdc_single_inst |xpm_cdc_single__42 | 5| 2default:defaulthp x   %s *synth2 |2816 | \gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__8 | 195| 2default:defaulthp x   %s *synth2 |2817 | xpm_cdc_single_inst |xpm_cdc_single__41 | 5| 2default:defaulthp x   %s *synth2 |2818 | mgt_inst |mgt | 1299| 2default:defaulthp x   %s *synth2 |2819 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__7 | 29| 2default:defaulthp x   %s *synth2 |2820 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__8 | 29| 2default:defaulthp x   %s *synth2 |2821 | \gtxLatOpt_gen[3].rxBitSlipControl |mgt_bitslipctrl__9 | 29| 2default:defaulthp x   %s *synth2 |2822 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch_105 | 122| 2default:defaulthp x   %s *synth2 |2823 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_106 | 122| 2default:defaulthp x   %s *synth2 |2824 | \gtxLatOpt_gen[3].patternSearch |mgt_framealigner_pattsearch_107 | 122| 2default:defaulthp x   %s *synth2 |2825 | gbtbank4_l8_112 |xlx_k7v7_gbt_ngFEC_design__parameterized4 | 11704| 2default:defaulthp x   %s *synth2 |2826 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset | 68| 2default:defaulthp x   %s *synth2 |2827 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_39 | 68| 2default:defaulthp x   %s *synth2 |2828 | \gbtBank_rst_gen[3].gbtBank_gbtBankRst |gbt_bank_reset_40 | 68| 2default:defaulthp x   %s *synth2 |2829 | \gbtBank_rst_gen[4].gbtBank_gbtBankRst |gbt_bank_reset_41 | 68| 2default:defaulthp x   %s *synth2 |2830 | gbt_inst |gbt_bank__parameterized1 | 11272| 2default:defaulthp x   %s *synth2 |2831 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx | 472| 2default:defaulthp x   %s *synth2 |2832 | decoder |gbt_rx_decoder_87 | 1| 2default:defaulthp x   %s *synth2 |2833 | descrambler |gbt_rx_descrambler_88 | 247| 2default:defaulthp x   %s *synth2 |2834 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_89 | 61| 2default:defaulthp x   %s *synth2 |2835 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_90 | 61| 2default:defaulthp x   %s *synth2 |2836 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_91 | 60| 2default:defaulthp x   %s *synth2 |2837 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_92 | 61| 2default:defaulthp x   %s *synth2 |2838 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_42 | 472| 2default:defaulthp x   %s *synth2 |2839 | decoder |gbt_rx_decoder_81 | 1| 2default:defaulthp x   %s *synth2 |2840 | descrambler |gbt_rx_descrambler_82 | 247| 2default:defaulthp x   %s *synth2 |2841 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_83 | 61| 2default:defaulthp x   %s *synth2 |2842 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_84 | 61| 2default:defaulthp x   %s *synth2 |2843 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_85 | 60| 2default:defaulthp x   %s *synth2 |2844 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_86 | 61| 2default:defaulthp x   %s *synth2 |2845 | \gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst |gbt_rx_43 | 472| 2default:defaulthp x   %s *synth2 |2846 | decoder |gbt_rx_decoder_75 | 1| 2default:defaulthp x   %s *synth2 |2847 | descrambler |gbt_rx_descrambler_76 | 247| 2default:defaulthp x   %s *synth2 |2848 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_77 | 61| 2default:defaulthp x   %s *synth2 |2849 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_78 | 61| 2default:defaulthp x   %s *synth2 |2850 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_79 | 60| 2default:defaulthp x   %s *synth2 |2851 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_80 | 61| 2default:defaulthp x   %s *synth2 |2852 | \gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst |gbt_rx_44 | 472| 2default:defaulthp x   %s *synth2 |2853 | decoder |gbt_rx_decoder | 1| 2default:defaulthp x   %s *synth2 |2854 | descrambler |gbt_rx_descrambler | 247| 2default:defaulthp x   %s *synth2 |2855 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit | 61| 2default:defaulthp x   %s *synth2 |2856 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_72 | 61| 2default:defaulthp x   %s *synth2 |2857 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_73 | 60| 2default:defaulthp x   %s *synth2 |2858 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_74 | 61| 2default:defaulthp x   %s *synth2 |2859 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox | 1390| 2default:defaulthp x   %s *synth2 |2860 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_45 | 1390| 2default:defaulthp x   %s *synth2 |2861 | \gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst |gbt_rx_gearbox_46 | 1390| 2default:defaulthp x   %s *synth2 |2862 | \gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst |gbt_rx_gearbox_47 | 1390| 2default:defaulthp x   %s *synth2 |2863 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx | 328| 2default:defaulthp x   %s *synth2 |2864 | scrambler |gbt_tx_scrambler_67 | 328| 2default:defaulthp x   %s *synth2 |2865 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_68 | 83| 2default:defaulthp x   %s *synth2 |2866 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_69 | 82| 2default:defaulthp x   %s *synth2 |2867 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_70 | 80| 2default:defaulthp x   %s *synth2 |2868 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_71 | 82| 2default:defaulthp x   %s *synth2 |2869 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_48 | 328| 2default:defaulthp x   %s *synth2 |2870 | scrambler |gbt_tx_scrambler_62 | 328| 2default:defaulthp x   %s *synth2 |2871 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_63 | 83| 2default:defaulthp x   %s *synth2 |2872 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_64 | 82| 2default:defaulthp x   %s *synth2 |2873 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_65 | 80| 2default:defaulthp x   %s *synth2 |2874 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_66 | 82| 2default:defaulthp x   %s *synth2 |2875 | \gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst |gbt_tx_49 | 328| 2default:defaulthp x   %s *synth2 |2876 | scrambler |gbt_tx_scrambler_57 | 328| 2default:defaulthp x   %s *synth2 |2877 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_58 | 83| 2default:defaulthp x   %s *synth2 |2878 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_59 | 82| 2default:defaulthp x   %s *synth2 |2879 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_60 | 80| 2default:defaulthp x   %s *synth2 |2880 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_61 | 82| 2default:defaulthp x   %s *synth2 |2881 | \gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst |gbt_tx_50 | 328| 2default:defaulthp x   %s *synth2 |2882 | scrambler |gbt_tx_scrambler | 328| 2default:defaulthp x   %s *synth2 |2883 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit | 83| 2default:defaulthp x   %s *synth2 |2884 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_54 | 82| 2default:defaulthp x   %s *synth2 |2885 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_55 | 80| 2default:defaulthp x   %s *synth2 |2886 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_56 | 82| 2default:defaulthp x   %s *synth2 |2887 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__9 | 195| 2default:defaulthp x   %s *synth2 |2888 | xpm_cdc_single_inst |xpm_cdc_single__47 | 5| 2default:defaulthp x   %s *synth2 |2889 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__10 | 195| 2default:defaulthp x   %s *synth2 |2890 | xpm_cdc_single_inst |xpm_cdc_single__46 | 5| 2default:defaulthp x   %s *synth2 |2891 | \gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__11 | 195| 2default:defaulthp x   %s *synth2 |2892 | xpm_cdc_single_inst |xpm_cdc_single__45 | 5| 2default:defaulthp x   %s *synth2 |2893 | \gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst |gbt_tx_gearbox | 195| 2default:defaulthp x   %s *synth2 |2894 | xpm_cdc_single_inst |xpm_cdc_single__44 | 5| 2default:defaulthp x   %s *synth2 |2895 | mgt_inst |mgt__parameterized1 | 1732| 2default:defaulthp x   %s *synth2 |2896 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__10 | 29| 2default:defaulthp x   %s *synth2 |2897 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__11 | 29| 2default:defaulthp x   %s *synth2 |2898 | \gtxLatOpt_gen[3].rxBitSlipControl |mgt_bitslipctrl__12 | 29| 2default:defaulthp x   %s *synth2 |2899 | \gtxLatOpt_gen[4].rxBitSlipControl |mgt_bitslipctrl | 29| 2default:defaulthp x   %s *synth2 |2900 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch | 122| 2default:defaulthp x   %s *synth2 |2901 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_51 | 122| 2default:defaulthp x   %s *synth2 |2902 | \gtxLatOpt_gen[3].patternSearch |mgt_framealigner_pattsearch_52 | 122| 2default:defaulthp x   %s *synth2 |2903 | \gtxLatOpt_gen[4].patternSearch |mgt_framealigner_pattsearch_53 | 122| 2default:defaulthp x   %s *synth2 |2904 | phmon |clk_divide3 | 10| 2default:defaulthp x   %s *synth2 |2905 | stat_regs_inst |ipb_user_status_regs | 2117| 2default:defaulthp x   %s *synth2 |2906 | sys |system_core | 28063| 2default:defaulthp x   %s *synth2 |2907 | clocks |clocks_7s_serdes | 148| 2default:defaulthp x   %s *synth2 |2908 | clkdiv |ipbus_clock_div | 38| 2default:defaulthp x   %s *synth2 |2909 | eth |eth_7s_1000basex | 461| 2default:defaulthp x   %s *synth2 |2910 | mac |tri_mode_eth_mac_v5_5 | 426| 2default:defaulthp x   %s *synth2 |2911 | i_mac |soft_emac | 426| 2default:defaulthp x   %s *synth2 |2912 | i_rx_CRC32D8 |EthernetCRC | 103| 2default:defaulthp x   %s *synth2 |2913 | i_tx_CRC32D8 |EthernetCRC_2 | 107| 2default:defaulthp x   %s *synth2 |2914 | i2c_eep |i2c_eep_autoread | 320| 2default:defaulthp x   %s *synth2 |2915 | i2c_m |i2c_master_top | 511| 2default:defaulthp x   %s *synth2 |2916 | core |i2c_master_core | 509| 2default:defaulthp x   %s *synth2 |2917 | u1 |i2c_bitwise | 144| 2default:defaulthp x   %s *synth2 |2918 | u2 |i2c_ctrl | 330| 2default:defaulthp x   %s *synth2 |2919 | icap_if |icap_interface_wrapper | 192| 2default:defaulthp x   %s *synth2 |2920 | confFsm |icap_interface_fsm | 83| 2default:defaulthp x   %s *synth2 |2921 | icapInterface |icap_interface | 109| 2default:defaulthp x   %s *synth2 |2922 | ip_mac |ip_mac_select | 197| 2default:defaulthp x   %s *synth2 |2923 | ipb |ipbus_ctrl | 6789| 2default:defaulthp x   %s *synth2 |2924 | \arb_gen.arb |trans_arb | 38| 2default:defaulthp x   %s *synth2 |2925 | trans |transactor | 1097| 2default:defaulthp x   %s *synth2 |2926 | cfg__0 |transactor_cfg | 1| 2default:defaulthp x   %s *synth2 |2927 | iface |transactor_if | 317| 2default:defaulthp x   %s *synth2 |2928 | sm |transactor_sm | 779| 2default:defaulthp x   %s *synth2 |2929 | udp_if |UDP_if | 5654| 2default:defaulthp x   %s *synth2 |2930 | ipbus_rx_ram |udp_DualPortRAM_rx | 8| 2default:defaulthp x   %s *synth2 |2931 | ARP |udp_build_arp | 275| 2default:defaulthp x   %s *synth2 |2932 | IPADDR |udp_ipaddr_block | 185| 2default:defaulthp x   %s *synth2 |2933 | RARP_block |udp_rarp_block | 885| 2default:defaulthp x   %s *synth2 |2934 | clock_crossing_if |udp_clock_crossing_if | 89| 2default:defaulthp x   %s *synth2 |2935 | internal_ram |udp_DualPortRAM | 1| 2default:defaulthp x   %s *synth2 |2936 | internal_ram_selector |udp_buffer_selector | 19| 2default:defaulthp x   %s *synth2 |2937 | internal_ram_shim |udp_rxram_shim | 69| 2default:defaulthp x   %s *synth2 |2938 | ipbus_tx_ram |udp_DualPortRAM_tx | 18| 2default:defaulthp x   %s *synth2 |2939 | payload |udp_build_payload | 413| 2default:defaulthp x   %s *synth2 |2940 | ping |udp_build_ping | 241| 2default:defaulthp x   %s *synth2 |2941 | resend |udp_build_resend | 39| 2default:defaulthp x   %s *synth2 |2942 | rx_byte_sum |udp_byte_sum | 89| 2default:defaulthp x   %s *synth2 |2943 | rx_packet_parser |udp_packet_parser | 680| 2default:defaulthp x   %s *synth2 |2944 | rx_ram_mux |udp_rxram_mux | 40| 2default:defaulthp x   %s *synth2 |2945 | rx_ram_selector |udp_buffer_selector__parameterized0 | 125| 2default:defaulthp x   %s *synth2 |2946 | rx_reset_block |udp_do_rx_reset | 116| 2default:defaulthp x   %s *synth2 |2947 | rx_transactor |udp_rxtransactor_if | 7| 2default:defaulthp x   %s *synth2 |2948 | status |udp_build_status | 325| 2default:defaulthp x   %s *synth2 |2949 | status_buffer |udp_status_buffer | 818| 2default:defaulthp x   %s *synth2 |2950 | tx_byte_sum |udp_byte_sum_0 | 76| 2default:defaulthp x   %s *synth2 |2951 | tx_main |udp_tx_mux | 488| 2default:defaulthp x   %s *synth2 |2952 | tx_ram_selector |udp_buffer_selector__parameterized0_1 | 201| 2default:defaulthp x   %s *synth2 |2953 | tx_transactor |udp_txtransactor_if | 446| 2default:defaulthp x   %s *synth2 |2954 | ipb_fabric |ipbus_sys_fabric | 6| 2default:defaulthp x   %s *synth2 |2955 | ipb_sys_regs |system_regs | 945| 2default:defaulthp x   %s *synth2 |2956 | spi |spi_master | 310| 2default:defaulthp x   %s *synth2 |2957 | uc_if |uc_if | 454| 2default:defaulthp x   %s *synth2 |2958 | spi |spi_interface | 118| 2default:defaulthp x   %s *synth2 |2959 | uc_pipe_if |uc_pipe_interface | 256| 2default:defaulthp x   %s *synth2 |2960 | uc_trans |trans_buffer | 80| 2default:defaulthp x   %s *synth2 +------+-----------------------------------------------------------------+---------------------------------------------+-------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Writing Synthesis Report : Time (s): cpu = 00:10:04 ; elapsed = 00:10:14 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  u %s *synth2] ISynthesis finished with 0 errors, 0 critical warnings and 3566 warnings. 2default:defaulthp x   %s *synth2 Synthesis Optimization Runtime : Time (s): cpu = 00:07:38 ; elapsed = 00:08:26 . Memory (MB): peak = 2456.355 ; gain = 406.770 2default:defaulthp x   %s *synth2 Synthesis Optimization Complete : Time (s): cpu = 00:10:04 ; elapsed = 00:10:15 . Memory (MB): peak = 2456.355 ; gain = 2082.438 2default:defaulthp x  B Translating synthesized netlist 350*projectZ1-571hpx  Release 14.7 - ngc2edif P_INT.20180726 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Reading design sdpram_16x10_32x9.ngc ... WARNING:NetListWriters:298 - No output is written to sdpram_16x10_32x9.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file sdpram_16x10_32x9.edif ... ngc2edif: Total memory usage is 4321768 kilobytes *commonhpx  BUFGCTRL (inverted pins: CE0): 1 instances IBUFGDS => IBUFDS: 1 instances IOBUF => IOBUF (IBUF, OBUFT): 42 instances LD => LDCE: 72 instances LDC => LDCE: 1 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances PLLE2_BASE => PLLE2_ADV: 1 instances SRL16 => SRL16E: 2 instances 2default:defaultZ1-111hpx U Releasing license: %s 83*common2 Synthesis2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 15802default:default2 8592default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 synth_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" synth_design: 2default:default2 00:11:392default:default2 00:11:512default:default2 3048.0392default:default2 2684.5632default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1432default:default2 3048.0392default:default2 0.0002default:defaultZ17-268hp x  K "No constraints selected for write.1103* constraintsZ18-5210hpx  The %s '%s' has been generated. 621*common2 checkpoint2default:default2W CD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/fc7_top.dcp2default:defaultZ17-1381hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2& write_checkpoint: 2default:default2 00:01:042default:default2 00:00:462default:default2 3048.0392default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2x dExecuting : report_utilization -file fc7_top_utilization_synth.rpt -pb fc7_top_utilization_synth.pb 2default:defaulthpx  Exiting %s at %s... 206*common2 Vivado2default:default2, Mon May 18 09:12:41 20202default:defaultZ17-206hpx  End Record