*** Running vivado with args -log fc7_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fc7_top.tcl ****** Vivado v2018.3 (64-bit) **** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source fc7_top.tcl -notrace Command: synth_design -top fc7_top -part xc7k420tffg1156-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k420t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k420t' INFO: [Common 17-1540] The version limit for your license is '2020.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4504 WARNING: [Synth 8-2507] parameter declaration becomes local in CrossClock_RX with formal parameter declaration list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:42] WARNING: [Synth 8-2507] parameter declaration becomes local in clkRateTool32 with formal parameter declaration list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:11] WARNING: [Synth 8-2507] parameter declaration becomes local in clkRateTool32 with formal parameter declaration list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:31] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 486.211 ; gain = 112.293 --------------------------------------------------------------------------------- WARNING: [Synth 8-2488] overwriting existing primary unit ipbus [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/ipbus_package.vhd:30] WARNING: [Synth 8-1565] actual for formal port slaveaddress is neither a static name nor a globally static expression [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_core.vhd:172] WARNING: [Synth 8-1565] actual for formal port divider_i is neither a static name nor a globally static expression [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd:47] WARNING: [Synth 8-1565] actual for formal port tx_common_frame_i is neither a static name nor a globally static expression [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd:96] WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd:73] INFO: [Synth 8-638] synthesizing module 'fc7_top' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd:167] Parameter DDR_CLK_EDGE bound to: OPPOSITE_EDGE - type: string Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: SYNC - type: string INFO: [Synth 8-113] binding component instance 'clk_oddr' to cell 'ODDR' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd:220] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'clk_obuf' to cell 'OBUFDS' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd:223] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'cdce_sync_r1_fdre' to cell 'FDRE' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd:236] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'cdce_sync_r0_fdre' to cell 'FDRE' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd:248] INFO: [Synth 8-638] synthesizing module 'system_core' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:101] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'osc125a_gtebuf' to cell 'IBUFDS_GTE2' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:213] INFO: [Synth 8-113] binding component instance 'osc125a_clkbuf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:214] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'osc125b_gtebuf' to cell 'IBUFDS_GTE2' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:215] INFO: [Synth 8-113] binding component instance 'osc125b_clkbuf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:216] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:224] INFO: [Synth 8-638] synthesizing module 'clocks_7s_serdes' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd:38] Parameter powerup_delay bound to: 3125000 - type: integer Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT bound to: 12 - type: integer Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKIN1_PERIOD bound to: 8.000000 - type: float Parameter CLKOUT0_DIVIDE bound to: 48 - type: integer Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_DIVIDE bound to: 24 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter REF_JITTER1 bound to: 0.010000 - type: float Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'PLLE2_BASE_inst' to cell 'PLLE2_BASE' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd:71] INFO: [Synth 8-113] binding component instance 'clk_ipb_buf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd:93] INFO: [Synth 8-113] binding component instance 'clk62_5_buf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd:94] INFO: [Synth 8-113] binding component instance 'clk125_buf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd:95] INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:50] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:57] INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (1#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:50] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_serdes' (2#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/clocks_7s_serdes_fc7.vhd:38] INFO: [Synth 8-638] synthesizing module 'eth_7s_1000basex' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd:49] INFO: [Synth 8-3491] module 'tri_mode_eth_mac_v5_5' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd:3' bound to instance 'mac' of component 'tri_mode_eth_mac_v5_5' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd:145] INFO: [Synth 8-638] synthesizing module 'tri_mode_eth_mac_v5_5' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd:40] INFO: [Synth 8-3491] module 'soft_emac' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:40' bound to instance 'i_mac' of component 'soft_emac' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd:72] INFO: [Synth 8-638] synthesizing module 'soft_emac' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:62] INFO: [Synth 8-3491] module 'EthernetCRC' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd:55' bound to instance 'i_tx_CRC32D8' of component 'EthernetCRC' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:208] INFO: [Synth 8-638] synthesizing module 'EthernetCRC' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd:65] INFO: [Synth 8-256] done synthesizing module 'EthernetCRC' (3#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd:65] WARNING: [Synth 8-614] signal 'rx_crc_d' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:217] WARNING: [Synth 8-614] signal 'phyemacrxd' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:217] INFO: [Synth 8-3491] module 'EthernetCRC' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/EthernetCRC.vhd:55' bound to instance 'i_rx_CRC32D8' of component 'EthernetCRC' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:267] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:277] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'i_ce_rx_crc_dl' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:289] INFO: [Synth 8-256] done synthesizing module 'soft_emac' (4#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/soft_emac_AXI4.vhd:62] INFO: [Synth 8-256] done synthesizing module 'tri_mode_eth_mac_v5_5' (5#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/tri_mode_eth_mac_v5_5.vhd:40] INFO: [Synth 8-3491] module 'gig_ethernet_pcs_pma_16_1' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/gig_ethernet_pcs_pma_16_1_stub.vhdl:5' bound to instance 'phy' of component 'gig_ethernet_pcs_pma_16_1' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd:193] INFO: [Synth 8-638] synthesizing module 'gig_ethernet_pcs_pma_16_1' [D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/gig_ethernet_pcs_pma_16_1_stub.vhdl:42] INFO: [Synth 8-256] done synthesizing module 'eth_7s_1000basex' (6#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/eth_7s_1000basex.vhd:49] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:90] Parameter MAC_CFG bound to: 1'b0 Parameter IP_CFG bound to: 1'b0 Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter IPBUSPORT bound to: 16'b1100001101010001 Parameter SECONDARYPORT bound to: 1'b0 Parameter N_OOB bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'UDP_if' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:90] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter IPBUSPORT bound to: 16'b1100001101010001 Parameter SECONDARYPORT bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_block' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:54] INFO: [Synth 8-4471] merging register 'IP_addr_rx_reg[31:0]' into 'IP_addr_rx_int_reg[31:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:100] WARNING: [Synth 8-6014] Unused sequential element IP_addr_rx_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:100] INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_block' (7#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_rarp_block' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:50] WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:68] WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:69] WARNING: [Synth 8-6014] Unused sequential element addr_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:140] WARNING: [Synth 8-6014] Unused sequential element tick_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:159] WARNING: [Synth 8-6014] Unused sequential element t_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:190] WARNING: [Synth 8-6014] Unused sequential element rarp_req_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:215] INFO: [Synth 8-256] done synthesizing module 'udp_rarp_block' (8#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:50] INFO: [Synth 8-638] synthesizing module 'udp_build_arp' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:71] WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:73] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:107] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:108] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:251] INFO: [Synth 8-4471] merging register 'arp_we_sig_reg' into 'arp_we_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:63] INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:202] INFO: [Synth 8-4471] merging register 'buf_to_load_reg[47:0]' into 'buf_to_load_int_reg[47:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:207] INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:212] INFO: [Synth 8-4471] merging register 'address_reg[5:0]' into 'addr_int_reg[5:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:64] WARNING: [Synth 8-6014] Unused sequential element arp_we_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:63] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:202] WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:207] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:212] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:64] INFO: [Synth 8-256] done synthesizing module 'udp_build_arp' (9#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] WARNING: [Synth 8-6014] Unused sequential element state_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:84] WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:87] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:139] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:140] WARNING: [Synth 8-6014] Unused sequential element next_low_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:433] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:510] INFO: [Synth 8-4471] merging register 'send_pending_reg' into 'send_pending_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:110] INFO: [Synth 8-4471] merging register 'payload_we_sig_reg' into 'payload_we_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:69] INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:292] INFO: [Synth 8-4471] merging register 'buf_to_load_reg[15:0]' into 'buf_to_load_int_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:297] INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:302] INFO: [Synth 8-4471] merging register 'do_sum_payload_reg' into 'do_sum_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:386] INFO: [Synth 8-4471] merging register 'clr_sum_payload_reg' into 'clr_sum_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:391] INFO: [Synth 8-4471] merging register 'int_data_payload_reg[7:0]' into 'int_data_int_reg[7:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:396] INFO: [Synth 8-4471] merging register 'int_valid_payload_reg' into 'int_valid_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:401] INFO: [Synth 8-4471] merging register 'cksum_reg' into 'cksum_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:406] INFO: [Synth 8-4471] merging register 'next_addr_reg[12:0]' into 'next_addr_int_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:432] INFO: [Synth 8-4471] merging register 'address_reg[12:0]' into 'addr_int_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:150] INFO: [Synth 8-4471] merging register 'low_addr_reg' into 'low_addr_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:147] INFO: [Synth 8-4471] merging register 'byteswap_reg' into 'byteswap_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:497] INFO: [Synth 8-4471] merging register 'ipbus_in_hdr_reg[31:0]' into 'ipbus_hdr_int_reg[31:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:539] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:110] WARNING: [Synth 8-6014] Unused sequential element payload_we_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:69] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:292] WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:297] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:302] WARNING: [Synth 8-6014] Unused sequential element do_sum_payload_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:386] WARNING: [Synth 8-6014] Unused sequential element clr_sum_payload_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:391] WARNING: [Synth 8-6014] Unused sequential element int_data_payload_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:396] WARNING: [Synth 8-6014] Unused sequential element int_valid_payload_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:401] WARNING: [Synth 8-6014] Unused sequential element cksum_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:406] WARNING: [Synth 8-6014] Unused sequential element next_addr_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:432] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:150] WARNING: [Synth 8-6014] Unused sequential element low_addr_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:147] WARNING: [Synth 8-6014] Unused sequential element byteswap_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:497] WARNING: [Synth 8-6014] Unused sequential element ipbus_in_hdr_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:539] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (10#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-638] synthesizing module 'udp_build_ping' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] WARNING: [Synth 8-6014] Unused sequential element state_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:78] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:138] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:139] WARNING: [Synth 8-6014] Unused sequential element ping_we_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:203] WARNING: [Synth 8-6014] Unused sequential element clr_sum_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:275] WARNING: [Synth 8-6014] Unused sequential element int_valid_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:276] WARNING: [Synth 8-6014] Unused sequential element int_data_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:277] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:375] INFO: [Synth 8-4471] merging register 'ping_end_addr_reg[12:0]' into 'end_addr_i_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:101] INFO: [Synth 8-4471] merging register 'ping_send_reg' into 'send_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:106] INFO: [Synth 8-4471] merging register 'send_pending_reg' into 'send_pending_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:111] INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:250] INFO: [Synth 8-4471] merging register 'buf_to_load_reg[15:0]' into 'buf_to_load_int_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:255] INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:260] INFO: [Synth 8-4471] merging register 'do_sum_ping_reg' into 'do_sum_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:309] INFO: [Synth 8-4471] merging register 'address_reg[12:0]' into 'addr_int_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:67] INFO: [Synth 8-4471] merging register 'low_addr_reg' into 'low_addr_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:145] WARNING: [Synth 8-6014] Unused sequential element ping_end_addr_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:101] WARNING: [Synth 8-6014] Unused sequential element ping_send_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:106] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:111] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:250] WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:255] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:260] WARNING: [Synth 8-6014] Unused sequential element do_sum_ping_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:309] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:67] WARNING: [Synth 8-6014] Unused sequential element low_addr_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:145] INFO: [Synth 8-256] done synthesizing module 'udp_build_ping' (11#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-4471] merging register 'resend_pkt_id_reg[15:0]' into 'resend_pkt_id_int_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:91] WARNING: [Synth 8-6014] Unused sequential element resend_pkt_id_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:91] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (12#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:69] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:123] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:124] WARNING: [Synth 8-6014] Unused sequential element request_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:209] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:273] INFO: [Synth 8-4471] merging register 'address_reg[6:0]' into 'addr_int_reg[6:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:62] INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:245] INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:250] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:62] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:245] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:250] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (13#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer WARNING: [Synth 8-6014] Unused sequential element bufsize_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:114] WARNING: [Synth 8-6014] Unused sequential element nbuf_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:115] WARNING: [Synth 8-6014] Unused sequential element new_event_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:162] WARNING: [Synth 8-6014] Unused sequential element async_ready_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:163] WARNING: [Synth 8-6014] Unused sequential element rarp_arp_ping_ipbus_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:169] WARNING: [Synth 8-6014] Unused sequential element payload_status_resend_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:171] WARNING: [Synth 8-6014] Unused sequential element got_event_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:252] WARNING: [Synth 8-6014] Unused sequential element event_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:253] INFO: [Synth 8-4471] merging register 'next_pkt_id_reg[15:0]' into 'next_pkt_id_int_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:136] WARNING: [Synth 8-6014] Unused sequential element next_pkt_id_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:136] INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (14#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-4471] merging register 'carry_bit_reg' into 'carry_bit_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:114] INFO: [Synth 8-4471] merging register 'hi_byte_reg[8:0]' into 'hi_byte_int_reg[8:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:58] WARNING: [Synth 8-6014] Unused sequential element carry_bit_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:114] WARNING: [Synth 8-6014] Unused sequential element hi_byte_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:58] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (15#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:45] INFO: [Synth 8-4471] merging register 'rx_reset_sig_reg' into 'reset_latch_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:51] WARNING: [Synth 8-6014] Unused sequential element rx_reset_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:51] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (16#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:45] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:61] Parameter IPBUSPORT bound to: 16'b1100001101010001 Parameter SECONDARYPORT bound to: 1'b0 INFO: [Synth 8-4471] merging register 'pkt_drop_arp_sig_reg' into 'pkt_drop_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:71] INFO: [Synth 8-4471] merging register 'pkt_drop_rarp_sig_reg' into 'pkt_drop_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:72] INFO: [Synth 8-4471] merging register 'pkt_drop_ip_sig_reg' into 'pkt_drop_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:198] INFO: [Synth 8-4471] merging register 'pkt_drop_ping_sig_reg' into 'pkt_drop_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:73] INFO: [Synth 8-4471] merging register 'pkt_drop_ipbus_sig_reg' into 'pkt_drop_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:74] INFO: [Synth 8-4471] merging register 'ipbus_status_mask_reg' into 'last_mask_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:312] INFO: [Synth 8-4471] merging register 'pkt_drop_reliable_sig_reg' into 'pkt_drop_reliable_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:76] INFO: [Synth 8-4471] merging register 'pkt_reliable_drop_sig_reg' into 'pkt_drop_reliable_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:76] INFO: [Synth 8-4471] merging register 'pkt_drop_status_reg' into 'pkt_drop_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:431] INFO: [Synth 8-4471] merging register 'pkt_drop_resend_reg' into 'pkt_drop_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:464] INFO: [Synth 8-4471] merging register 'pkt_broadcast_reg' into 'broadcast_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:486] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_arp_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:71] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_rarp_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:72] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ip_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:198] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ping_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:73] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ipbus_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:74] WARNING: [Synth 8-6014] Unused sequential element ipbus_status_mask_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:312] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_reliable_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:76] WARNING: [Synth 8-6014] Unused sequential element pkt_reliable_drop_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:76] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_status_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:431] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_resend_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:464] WARNING: [Synth 8-6014] Unused sequential element pkt_broadcast_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:486] INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (17#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:80] WARNING: [Synth 8-6014] Unused sequential element rxram_dropped_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:98] WARNING: [Synth 8-6014] Unused sequential element rxram_end_addr_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:121] WARNING: [Synth 8-6014] Unused sequential element rxram_send_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:122] WARNING: [Synth 8-6014] Unused sequential element dia_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:157] WARNING: [Synth 8-6014] Unused sequential element addra_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:158] WARNING: [Synth 8-6014] Unused sequential element wea_int_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:159] INFO: [Synth 8-4471] merging register 'ram_ready_reg' into 'ram_ready_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:86] WARNING: [Synth 8-6014] Unused sequential element ram_ready_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:86] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (18#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:80] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (19#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 1 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:167] INFO: [Synth 8-4471] merging register 'free_reg[1:0]' into 'free_i_reg[1:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:88] INFO: [Synth 8-4471] merging register 'clean_reg[1:0]' into 'clean_i_reg[1:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:69] INFO: [Synth 8-4471] merging register 'send_pending_reg[1:0]' into 'send_pending_i_reg[1:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:134] INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:68] INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:171] INFO: [Synth 8-4471] merging register 'write_sig_reg[0:0]' into 'write_i_reg[0:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:66] INFO: [Synth 8-4471] merging register 'send_sig_reg[0:0]' into 'send_i_reg[0:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:67] WARNING: [Synth 8-6014] Unused sequential element free_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:88] WARNING: [Synth 8-6014] Unused sequential element clean_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:69] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:134] WARNING: [Synth 8-6014] Unused sequential element busy_sig_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:68] WARNING: [Synth 8-6014] Unused sequential element sending_reg was removed. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:171] INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (20#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (21#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:62] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (22#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-4471] merging register 'free_reg[15:0]' into 'free_i_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:88] INFO: [Synth 8-4471] merging register 'clean_reg[15:0]' into 'clean_i_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:69] INFO: [Synth 8-4471] merging register 'send_pending_reg[15:0]' into 'send_pending_i_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:134] INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:68] INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:171] INFO: [Synth 8-4471] merging register 'write_sig_reg[3:0]' into 'write_i_reg[3:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:66] INFO: [Synth 8-4471] merging register 'send_sig_reg[3:0]' into 'send_i_reg[3:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:67] INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (22#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:83] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (23#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-4471] merging register 'ram_ok_reg' into 'ram_ok_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:55] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (24#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:71] INFO: [Synth 8-4471] merging register 'rxram_busy_sig_reg' into 'rxram_busy_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:90] INFO: [Synth 8-4471] merging register 'rxram_end_addr_sig_reg[12:0]' into 'rxram_end_addr_int_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:124] INFO: [Synth 8-4471] merging register 'udpram_busy_sig_reg' into 'udpram_busy_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:91] INFO: [Synth 8-4471] merging register 'udp_short_sig_reg' into 'short_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:97] INFO: [Synth 8-4471] merging register 'send_special_reg' into 'send_special_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:233] INFO: [Synth 8-4471] merging register 'special_reg[7:0]' into 'special_int_reg[7:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:238] INFO: [Synth 8-4471] merging register 'last_udpram_active_reg' into 'last_udpram_active_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:261] INFO: [Synth 8-4471] merging register 'udp_counting_reg' into 'counting_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:266] INFO: [Synth 8-4471] merging register 'udp_counter_reg[4:0]' into 'counter_reg[4:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:271] INFO: [Synth 8-4471] merging register 'cksum_reg' into 'cksum_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:340] INFO: [Synth 8-4471] merging register 'clr_sum_reg' into 'clr_sum_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:345] INFO: [Synth 8-4471] merging register 'do_sum_reg' into 'do_sum_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:350] INFO: [Synth 8-4471] merging register 'int_valid_reg' into 'int_valid_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:355] INFO: [Synth 8-4471] merging register 'udpram_end_addr_sig_reg[12:0]' into 'udpram_end_addr_int_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:429] INFO: [Synth 8-4471] merging register 'int_data_reg[7:0]' into 'int_data_int_reg[7:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:434] INFO: [Synth 8-4471] merging register 'ip_len_reg[15:0]' into 'ip_len_int_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:193] INFO: [Synth 8-4471] merging register 'ip_cksum_reg[15:0]' into 'ip_cksum_int_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:198] INFO: [Synth 8-4471] merging register 'udp_len_reg[15:0]' into 'udp_len_int_reg[15:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:223] INFO: [Synth 8-4471] merging register 'addr_sig_reg[12:0]' into 'addr_int_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:161] INFO: [Synth 8-4471] merging register 'byteswapping_reg' into 'byteswapping_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:486] INFO: [Synth 8-4471] merging register 'mac_tx_data_sig_reg[7:0]' into 'mac_tx_data_int_reg[7:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:93] INFO: [Synth 8-4471] merging register 'ipbus_out_hdr_reg[31:0]' into 'ipbus_hdr_int_reg[31:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:572] INFO: [Synth 8-4471] merging register 'byteswap_sig_reg' into 'byteswap_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:476] INFO: [Synth 8-4471] merging register 'next_state_reg[2:0]' into 'state_reg[2:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:606] INFO: [Synth 8-4471] merging register 'rxram_active_reg' into 'rxram_active_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:114] INFO: [Synth 8-4471] merging register 'udpram_active_reg' into 'udpram_active_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:140] INFO: [Synth 8-4471] merging register 'counting_reg' into 'counting_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:465] INFO: [Synth 8-4471] merging register 'prefetch_reg' into 'prefetch_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:519] INFO: [Synth 8-4471] merging register 'mac_tx_last_sig_reg' into 'mac_tx_last_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:94] INFO: [Synth 8-4471] merging register 'mac_tx_valid_sig_reg' into 'mac_tx_valid_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:95] INFO: [Synth 8-4471] merging register 'set_addr_reg' into 'set_addr_int_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:462] INFO: [Synth 8-4471] merging register 'addr_to_set_reg[12:0]' into 'addr_to_set_int_reg[12:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:463] INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (25#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:71] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (26#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:72] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:72] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:72] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:72] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:73] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:73] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:73] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:73] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:74] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:75] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:75] INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (27#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (28#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:90] INFO: [Synth 8-638] synthesizing module 'trans_arb' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/trans_arb.vhd:55] Parameter NSRC bound to: 2 - type: integer WARNING: [Synth 8-5858] RAM buf_out_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'trans_arb' (29#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/trans_arb.vhd:55] INFO: [Synth 8-638] synthesizing module 'transactor' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-638] synthesizing module 'transactor_if' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (30#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (31#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (32#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor' (33#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (34#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:90] INFO: [Synth 8-638] synthesizing module 'uc_if' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_if.vhd:40] INFO: [Synth 8-638] synthesizing module 'trans_buffer' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd:62] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd:88] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd:89] INFO: [Synth 8-637] synthesizing blackbox instance 'ram_in' of component 'sdpram_16x10_32x9' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd:153] INFO: [Synth 8-637] synthesizing blackbox instance 'ram_out' of component 'sdpram_32x9_16x10' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd:166] INFO: [Synth 8-256] done synthesizing module 'trans_buffer' (35#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/trans_buffer.vhd:62] INFO: [Synth 8-638] synthesizing module 'spi_interface' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd:53] Parameter width bound to: 16 - type: integer INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd:122] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd:194] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd:287] INFO: [Synth 8-256] done synthesizing module 'spi_interface' (36#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_spi_interface.vhd:53] INFO: [Synth 8-638] synthesizing module 'uc_pipe_interface' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd:43] INFO: [Synth 8-637] synthesizing blackbox instance 'ram_pipe_to_ipbus' of component 'sdpram_16x10_32x9' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd:209] INFO: [Synth 8-637] synthesizing blackbox instance 'ram_ipbus_to_pipe' of component 'sdpram_32x9_16x10' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd:222] INFO: [Synth 8-256] done synthesizing module 'uc_pipe_interface' (37#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_pipe_interface.vhd:43] INFO: [Synth 8-256] done synthesizing module 'uc_if' (38#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/uc_if.vhd:40] INFO: [Synth 8-638] synthesizing module 'ip_mac_select' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd:42] WARNING: [Synth 8-614] signal 'user_mac_addr_i' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd:73] WARNING: [Synth 8-614] signal 'user_ip_addr_i' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ip_mac_select' (39#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ip_mac_select.vhd:42] INFO: [Synth 8-638] synthesizing module 'ipbus_sys_fabric' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ipbus_sys_fabric.vhd:28] Parameter n_sys_slv bound to: 3 - type: integer Parameter n_usr_slv bound to: 15 - type: integer Parameter usr_base_addr bound to: 32'b01000000000000000000000000000000 Parameter strobe_gap bound to: 0 - type: bool WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_sys_fabric' (40#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ipbus_sys_fabric.vhd:28] INFO: [Synth 8-638] synthesizing module 'system_regs' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/regs/system_regs.vhd:26] Parameter addr_width bound to: 6 - type: integer WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'regs_reg[13]' in module 'system_regs' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/regs/system_regs.vhd:42] INFO: [Synth 8-256] done synthesizing module 'system_regs' (41#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/regs/system_regs.vhd:26] INFO: [Synth 8-638] synthesizing module 'icap_interface_wrapper' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_wrapper.vhd:47] INFO: [Synth 8-638] synthesizing module 'flashIcap_ioControl' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_ioControl.vhd:55] INFO: [Synth 8-256] done synthesizing module 'flashIcap_ioControl' (42#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_ioControl.vhd:55] INFO: [Synth 8-638] synthesizing module 'icap_interface' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd:26] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd:29] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd:35] Parameter DEVICE_ID bound to: 32'b00000100001001001010000010010011 Parameter ICAP_WIDTH bound to: x32 - type: string Parameter SIM_CFG_FILE_NAME bound to: none - type: string INFO: [Synth 8-113] binding component instance 'icap' to cell 'ICAPE2' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd:173] INFO: [Synth 8-256] done synthesizing module 'icap_interface' (43#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface.vhd:26] INFO: [Synth 8-638] synthesizing module 'icap_interface_fsm' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_fsm.vhd:48] INFO: [Synth 8-256] done synthesizing module 'icap_interface_fsm' (44#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_fsm.vhd:48] INFO: [Synth 8-256] done synthesizing module 'icap_interface_wrapper' (45#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/icap/icap_interface_wrapper.vhd:47] INFO: [Synth 8-638] synthesizing module 'i2c_master_top' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd:31] Parameter nbr_of_busses bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'i2c_master_core' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_core.vhd:33] Parameter nbr_of_busses bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'i2c_bitwise' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_bitwise.vhd:44] INFO: [Synth 8-256] done synthesizing module 'i2c_bitwise' (46#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_bitwise.vhd:44] INFO: [Synth 8-638] synthesizing module 'i2c_ctrl' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_ctrl.vhd:53] INFO: [Synth 8-256] done synthesizing module 'i2c_ctrl' (47#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_ctrl.vhd:53] INFO: [Synth 8-256] done synthesizing module 'i2c_master_core' (48#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_core.vhd:33] Parameter DRIVE bound to: 4 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: slow - type: string INFO: [Synth 8-113] binding component instance 'scl_buf' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd:70] Parameter DRIVE bound to: 4 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: slow - type: string INFO: [Synth 8-113] binding component instance 'sda_buf' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd:74] INFO: [Synth 8-256] done synthesizing module 'i2c_master_top' (49#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_master_top.vhd:31] INFO: [Synth 8-638] synthesizing module 'i2c_eep_autoread' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_eep_autoread.vhd:30] INFO: [Synth 8-256] done synthesizing module 'i2c_eep_autoread' (50#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/i2c/i2c_eep_autoread.vhd:30] INFO: [Synth 8-638] synthesizing module 'spi_master' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:43] Parameter dwidth bound to: 32 - type: integer INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:72] WARNING: [Synth 8-614] signal 'cpol_i' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:58] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:135] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:172] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:259] INFO: [Synth 8-256] done synthesizing module 'spi_master' (51#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:43] WARNING: [Synth 8-3848] Net regs_to_ipbus[0] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[1] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[2] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[3] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[4] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[5] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net reg_status_2 in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:166] WARNING: [Synth 8-3848] Net regs_to_ipbus[8] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net reg_status_sram in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:168] WARNING: [Synth 8-3848] Net regs_to_ipbus[10] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[11] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[14] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[16] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[17] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[18] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[19] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[20] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[21] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[22] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[23] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[24] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[25] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[26] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] WARNING: [Synth 8-3848] Net regs_to_ipbus[27] in module/entity system_core does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:160] INFO: [Synth 8-256] done synthesizing module 'system_core' (52#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:101] INFO: [Synth 8-638] synthesizing module 'ngFEC_logic' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:168] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'fclk_ibuf' to cell 'IBUFGDS' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:561] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 18.000000 - type: float Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool Parameter CLKIN1_PERIOD bound to: 24.999000 - type: float Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float Parameter CLKOUT0_DIVIDE_F bound to: 18.000000 - type: float Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT0_USE_FINE_PS bound to: 1 - type: bool Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool Parameter COMPENSATION bound to: EXTERNAL - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.000000 - type: float Parameter REF_JITTER2 bound to: 0.000000 - type: float Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'fabric_clk_MMCME2' to cell 'MMCME2_ADV' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:562] INFO: [Synth 8-113] binding component instance 'fclk_bufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:604] INFO: [Synth 8-113] binding component instance 'fabric_clk_PS_bufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:605] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'i_PSDONE_dl32' to cell 'SRLC32E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:632] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'cdceOut1IbufdsAGtxe2' to cell 'IBUFDS_GTE2' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:639] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'cdceOut0IbufdsCGtxe2' to cell 'IBUFDS_GTE2' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:647] INFO: [Synth 8-113] binding component instance 'i_ttcMgtXpoint_from_ibufdsCGtxe2_buf' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:661] INFO: [Synth 8-113] binding component instance 'i_ttcMgtXpoint_from_ibufdsAGtxe2_buf' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:662] INFO: [Synth 8-638] synthesizing module 'clk_divide3' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clk_divide3.vhd:42] INFO: [Synth 8-256] done synthesizing module 'clk_divide3' (53#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clk_divide3.vhd:42] INFO: [Synth 8-638] synthesizing module 'dmdt_clock_gen' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/dmdt_clock_gen.vhd:18] INFO: [Synth 8-638] synthesizing module 'phase_mon_mmcm_1' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1.vhd:86] INFO: [Synth 8-3491] module 'phase_mon_mmcm_1_clk_wiz' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd:74' bound to instance 'U0' of component 'phase_mon_mmcm_1_clk_wiz' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1.vhd:104] INFO: [Synth 8-638] synthesizing module 'phase_mon_mmcm_1_clk_wiz' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd:86] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'clkin1_ibufg' to cell 'IBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd:120] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 62.625000 - type: float Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool Parameter CLKIN1_PERIOD bound to: 25.000000 - type: float Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float Parameter CLKOUT0_DIVIDE_F bound to: 31.250000 - type: float Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 2 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.000000 - type: float Parameter REF_JITTER2 bound to: 0.000000 - type: float Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd:132] INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd:203] INFO: [Synth 8-256] done synthesizing module 'phase_mon_mmcm_1_clk_wiz' (54#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1_clk_wiz.vhd:86] INFO: [Synth 8-256] done synthesizing module 'phase_mon_mmcm_1' (55#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_1.vhd:86] INFO: [Synth 8-638] synthesizing module 'phase_mon_mmcm_2' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2.vhd:86] INFO: [Synth 8-3491] module 'phase_mon_mmcm_2_clk_wiz' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd:74' bound to instance 'U0' of component 'phase_mon_mmcm_2_clk_wiz' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2.vhd:104] INFO: [Synth 8-638] synthesizing module 'phase_mon_mmcm_2_clk_wiz' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd:86] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'clkin1_ibufg' to cell 'IBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd:120] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 60.250000 - type: float Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool Parameter CLKIN1_PERIOD bound to: 24.950000 - type: float Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float Parameter CLKOUT0_DIVIDE_F bound to: 20.125000 - type: float Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 3 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.000000 - type: float Parameter REF_JITTER2 bound to: 0.000000 - type: float Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd:132] INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd:195] INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd:202] INFO: [Synth 8-256] done synthesizing module 'phase_mon_mmcm_2_clk_wiz' (56#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2_clk_wiz.vhd:86] INFO: [Synth 8-256] done synthesizing module 'phase_mon_mmcm_2' (57#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/phase_mon_mmcm_2.vhd:86] INFO: [Synth 8-256] done synthesizing module 'dmdt_clock_gen' (58#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/clk_gen/dmdt_clock_gen.vhd:18] INFO: [Synth 8-638] synthesizing module 'dmtd_phase_meas' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd:73] Parameter g_deglitcher_threshold bound to: 2000 - type: integer Parameter g_counter_bits bound to: 14 - type: integer INFO: [Synth 8-638] synthesizing module 'gc_sync_ffs' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd:59] Parameter g_sync_edge bound to: positive - type: string INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd:60] INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd:60] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd:60] INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd:60] INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd:60] INFO: [Synth 8-256] done synthesizing module 'gc_sync_ffs' (59#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_sync_ffs.vhd:59] INFO: [Synth 8-638] synthesizing module 'dmtd_with_deglitcher' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd:126] Parameter g_counter_bits bound to: 14 - type: integer Parameter g_chipscope bound to: 0 - type: bool Parameter g_divide_input_by_2 bound to: 0 - type: bool Parameter g_reverse bound to: 0 - type: bool INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd:138] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd:139] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd:139] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd:139] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd:139] INFO: [Synth 8-638] synthesizing module 'gc_pulse_synchronizer' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_pulse_synchronizer.vhd:65] INFO: [Synth 8-256] done synthesizing module 'gc_pulse_synchronizer' (60#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_pulse_synchronizer.vhd:65] INFO: [Synth 8-638] synthesizing module 'gc_extend_pulse' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_extend_pulse.vhd:65] Parameter g_width bound to: 3000 - type: integer INFO: [Synth 8-256] done synthesizing module 'gc_extend_pulse' (61#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/gc_extend_pulse.vhd:65] INFO: [Synth 8-256] done synthesizing module 'dmtd_with_deglitcher' (62#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/ohwr/dmtd_with_deglitcher.vhd:126] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd:197] INFO: [Synth 8-4471] merging register 'done_reg' into 'phase_meas_p_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd:268] INFO: [Synth 8-256] done synthesizing module 'dmtd_phase_meas' (63#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/dmdt_phase_meas/phese/dmtd_phase_meas_modified.vhd:73] INFO: [Synth 8-638] synthesizing module 'cdce_synchronizer' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd:66] Parameter pwrdown_delay bound to: 1000 - type: integer Parameter sync_delay bound to: 1000000 - type: integer INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd:150] Parameter CLK_SEL_TYPE bound to: SYNC - type: string INFO: [Synth 8-113] binding component instance 'bufg_mux' to cell 'BUFGMUX' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd:199] INFO: [Synth 8-256] done synthesizing module 'cdce_synchronizer' (64#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/cdce_synchronizer.vhd:66] INFO: [Synth 8-638] synthesizing module 'ipb_user_status_regs' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_status_regsX12.vhd:21] Parameter addr_width bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipb_user_status_regs' (65#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_status_regsX12.vhd:21] INFO: [Synth 8-638] synthesizing module 'ipb_user_control_regs' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_control_regs.vhd:21] Parameter addr_width bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipb_user_control_regs' (66#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ipb/ipb_user_control_regs.vhd:21] INFO: [Synth 8-3491] module 'DTC_top' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd:32' bound to instance 'DTC' of component 'DTC_top' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:778] INFO: [Synth 8-638] synthesizing module 'DTC_top' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd:51] WARNING: [Synth 8-5640] Port 'ttcready' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd:52] INFO: [Synth 8-3491] module 'TTC_decoder' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:47' bound to instance 'Inst_TTC_decoder' of component 'TTC_decoder' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd:71] INFO: [Synth 8-638] synthesizing module 'TTC_decoder' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:64] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 1 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: LVDS_25 - type: string INFO: [Synth 8-113] binding component instance 'i_TTC_data_in' to cell 'IBUFDS' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:120] Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string Parameter INIT_Q1 bound to: 1'b0 Parameter INIT_Q2 bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: SYNC - type: string INFO: [Synth 8-113] binding component instance 'i_TTC_data' to cell 'IDDR' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:160] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'i_L1Accept' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:448] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'i_brcst_str1' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:459] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'i_brcst_str3' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:470] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'i_indiv_str1' to cell 'SRL16E' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:481] INFO: [Synth 8-256] done synthesizing module 'TTC_decoder' (67#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC.vhdl:64] WARNING: [Synth 8-3848] Net TTCready in module/entity DTC_top does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd:41] INFO: [Synth 8-256] done synthesizing module 'DTC_top' (68#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/DTC_v6/DTC_top.vhd:51] INFO: [Synth 8-3491] module 'ttc_counter' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ttc_counter.vhd:29' bound to instance 'DTC_Counter' of component 'ttc_counter' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:794] INFO: [Synth 8-638] synthesizing module 'ttc_counter' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ttc_counter.vhd:43] INFO: [Synth 8-256] done synthesizing module 'ttc_counter' (69#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ttc_counter.vhd:43] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate0' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:815] INFO: [Synth 8-6157] synthesizing module 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer Parameter REFCTR_SIZE bound to: 23 - type: integer Parameter REFCTR_TERMINAL bound to: 1249999 - type: integer INFO: [Synth 8-6155] done synthesizing module 'clkRateTool32' (70#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate1' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:824] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate2' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:833] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter CLKREF_RATE_IN_MHZ bound to: 125 - type: integer INFO: [Synth 8-3491] module 'clkRateTool32' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/clkRateTool32.v:1' bound to instance 'clkRate3' of component 'clkRateTool32' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:843] Parameter NUM_LINKS bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-3491] module 'xlx_k7v7_gbt_ngFEC_design' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:70' bound to instance 'gbtbank1_l12_118' of component 'xlx_k7v7_gbt_ngFEC_design' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:887] INFO: [Synth 8-638] synthesizing module 'xlx_k7v7_gbt_ngFEC_design' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:172] Parameter NUM_LINKS bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] INFO: [Synth 8-638] synthesizing module 'gbt_bank_reset' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd:114] Parameter INITIAL_DELAY bound to: 40000000 - type: integer INFO: [Synth 8-256] done synthesizing module 'gbt_bank_reset' (71#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd:114] INFO: [Synth 8-638] synthesizing module 'gbt_bank' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:107] Parameter NUM_LINKS bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_tx' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd:41] Parameter TX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_tx_scrambler' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd:78] Parameter TX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_tx_scrambler_21bit' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd:58] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_scrambler_21bit' (72#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd:58] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_scrambler' (73#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd:78] INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd:69] Parameter TX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder_gbtframe_rsencode' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd:31] INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder_gbtframe_polydiv' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd:33] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder_gbtframe_polydiv' (74#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd:33] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder_gbtframe_rsencode' (75#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd:31] INFO: [Synth 8-638] synthesizing module 'gbt_tx_encoder_gbtframe_intlver' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd:28] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder_gbtframe_intlver' (76#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd:28] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_encoder' (77#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd:69] INFO: [Synth 8-256] done synthesizing module 'gbt_tx' (78#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd:41] INFO: [Synth 8-638] synthesizing module 'gbt_tx_gearbox' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd:65] Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 1 - type: integer INFO: [Synth 8-3491] module 'xpm_cdc_single' declared at 'D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153' bound to instance 'xpm_cdc_single_inst' of component 'xpm_cdc_single' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd:108] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 1 - type: integer Parameter VERSION bound to: 0 - type: integer INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (79#1) [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-256] done synthesizing module 'gbt_tx_gearbox' (80#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd:65] INFO: [Synth 8-638] synthesizing module 'mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:83] Parameter NUM_LINKS bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:201] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:217] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:218] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:220] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:221] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:233] INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-638] synthesizing module 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:75] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] INFO: [Synth 8-638] synthesizing module 'mgt_bitslipctrl' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd:58] INFO: [Synth 8-256] done synthesizing module 'mgt_bitslipctrl' (81#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd:58] INFO: [Synth 8-638] synthesizing module 'mgt_framealigner_pattsearch' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd:59] INFO: [Synth 8-256] done synthesizing module 'mgt_framealigner_pattsearch' (82#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd:59] INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gtxLatOpt_gen[3].rxBitSlipControl'. This will prevent further optimization [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:459] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gtxLatOpt_gen[2].rxBitSlipControl'. This will prevent further optimization [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:459] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gtxLatOpt_gen[1].rxBitSlipControl'. This will prevent further optimization [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:459] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[1].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[1].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[2].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[2].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[3].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[3].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rxCdrLock] in module/entity mgt does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rx_phMonitor][4] in module/entity mgt does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rx_phSlipMonitor][4] in module/entity mgt does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[drp_do][4] in module/entity mgt does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[prbs_rxErr] in module/entity mgt does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] INFO: [Synth 8-256] done synthesizing module 'mgt' (83#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:83] INFO: [Synth 8-638] synthesizing module 'gbt_rx_gearbox' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd:51] Parameter RX_OPTIMIZATION bound to: 1 - type: integer INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd:54] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_gearbox' (84#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd:51] INFO: [Synth 8-638] synthesizing module 'gbt_rx' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd:54] Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd:57] Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_deintlver' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd:35] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_deintlver' (85#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd:35] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_rsdec' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd:46] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_syndrom' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd:42] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_syndrom' (86#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd:42] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_lmbddet' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd:42] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_lmbddet' (87#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd:42] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_errlcpoly' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd:44] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_errlcpoly' (88#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd:44] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_chnsrch' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd:44] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_elpeval' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd:41] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_elpeval' (89#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd:41] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_chnsrch' (90#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd:44] INFO: [Synth 8-638] synthesizing module 'gbt_rx_decoder_gbtframe_rs2errcor' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd:45] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:128] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:153] INFO: [Synth 8-226] default block is never used [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_bank_package.vhd:153] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_rs2errcor' (91#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd:45] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder_gbtframe_rsdec' (92#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd:46] WARNING: [Synth 8-614] signal 'RX_RESET_I' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd:124] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_decoder' (93#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd:57] INFO: [Synth 8-638] synthesizing module 'gbt_rx_descrambler' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd:57] Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'gbt_rx_descrambler_21bit' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd:56] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_descrambler_21bit' (94#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd:56] INFO: [Synth 8-256] done synthesizing module 'gbt_rx_descrambler' (95#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd:57] INFO: [Synth 8-256] done synthesizing module 'gbt_rx' (96#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd:54] WARNING: [Synth 8-3848] Net GBT_ERRORDETECTED_o in module/entity gbt_bank does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:72] INFO: [Synth 8-256] done synthesizing module 'gbt_bank' (97#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:107] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[loopBack][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[tx_reset] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[rx_reset] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_diffCtrl][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_postCursor][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_preCursor][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[drp_addr][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[drp_di][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[prbs_txSel][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[prbs_rxSel][4] in module/entity xlx_k7v7_gbt_ngFEC_design does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] INFO: [Synth 8-256] done synthesizing module 'xlx_k7v7_gbt_ngFEC_design' (98#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:172] Parameter NUM_LINKS bound to: 2 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-3491] module 'xlx_k7v7_gbt_ngFEC_design' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:70' bound to instance 'gbtbank2_l12_117' of component 'xlx_k7v7_gbt_ngFEC_design' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:977] INFO: [Synth 8-638] synthesizing module 'xlx_k7v7_gbt_ngFEC_design__parameterized1' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:172] Parameter NUM_LINKS bound to: 2 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] INFO: [Synth 8-638] synthesizing module 'gbt_bank__parameterized0' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:107] Parameter NUM_LINKS bound to: 2 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt__parameterized0' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:83] Parameter NUM_LINKS bound to: 2 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[1].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt__parameterized0' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[1].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt__parameterized0' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[2].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt__parameterized0' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[2].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt__parameterized0' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rxCdrLock] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rx_phMonitor][3] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rx_phMonitor][4] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rx_phSlipMonitor][3] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rx_phSlipMonitor][4] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[drp_do][3] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[drp_do][4] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[prbs_rxErr] in module/entity mgt__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] INFO: [Synth 8-256] done synthesizing module 'mgt__parameterized0' (98#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:83] WARNING: [Synth 8-3848] Net GBT_ERRORDETECTED_o in module/entity gbt_bank__parameterized0 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:72] INFO: [Synth 8-256] done synthesizing module 'gbt_bank__parameterized0' (98#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:107] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[loopBack][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[loopBack][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[tx_reset] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[rx_reset] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_diffCtrl][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_diffCtrl][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_postCursor][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_postCursor][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_preCursor][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[conf_preCursor][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[drp_addr][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[drp_addr][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[drp_di][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[drp_di][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[prbs_txSel][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[prbs_txSel][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[prbs_rxSel][3] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[prbs_rxSel][4] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] INFO: [Synth 8-256] done synthesizing module 'xlx_k7v7_gbt_ngFEC_design__parameterized1' (98#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:172] Parameter NUM_LINKS bound to: 3 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-3491] module 'xlx_k7v7_gbt_ngFEC_design' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:70' bound to instance 'gbtbank3_l12_116' of component 'xlx_k7v7_gbt_ngFEC_design' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1067] Parameter NUM_LINKS bound to: 4 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-3491] module 'xlx_k7v7_gbt_ngFEC_design' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:70' bound to instance 'gbtbank4_l8_112' of component 'xlx_k7v7_gbt_ngFEC_design' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1157] INFO: [Synth 8-638] synthesizing module 'xlx_k7v7_gbt_ngFEC_design__parameterized4' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:172] Parameter NUM_LINKS bound to: 4 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] WARNING: [Synth 8-614] signal 'mgt_txready_s' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:237] INFO: [Synth 8-638] synthesizing module 'gbt_bank__parameterized1' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:107] Parameter NUM_LINKS bound to: 4 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt__parameterized1' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:83] Parameter NUM_LINKS bound to: 4 - type: integer Parameter TX_OPTIMIZATION bound to: 1 - type: integer Parameter RX_OPTIMIZATION bound to: 1 - type: integer Parameter TX_ENCODING bound to: 0 - type: integer Parameter RX_ENCODING bound to: 0 - type: integer INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] INFO: [Synth 8-3491] module 'ngFEC_mgt' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/.Xil/Vivado-17976-baby/realtime/ngFEC_mgt_stub.vhdl:5' bound to instance 'xlx_k7v7_mgt_latopt_inst' of component 'ngFEC_mgt' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:264] INFO: [Synth 8-113] binding component instance 'rxWordClkBufg' to cell 'BUFH' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:365] INFO: [Synth 8-113] binding component instance 'txWordClkBufg' to cell 'BUFG' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:370] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[1].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[1].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[2].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[2].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[3].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[3].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[4].resetGtxRx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:260] WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'gtxLatOpt_gen[4].resetGtxTx_from_rxBitSlipControl_reg' in module 'mgt__parameterized1' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:261] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[rxCdrLock] in module/entity mgt__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] WARNING: [Synth 8-3848] Net MGT_DEVSPEC_o[prbs_rxErr] in module/entity mgt__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:74] INFO: [Synth 8-256] done synthesizing module 'mgt__parameterized1' (98#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/xlx_k7v7_mgt.vhd:83] WARNING: [Synth 8-3848] Net GBT_ERRORDETECTED_o in module/entity gbt_bank__parameterized1 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:72] INFO: [Synth 8-256] done synthesizing module 'gbt_bank__parameterized1' (98#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/gbt_fpga6_1_0_patch/gbt_bank.vhd:107] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[tx_reset] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized4 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] WARNING: [Synth 8-3848] Net mgt_devspecific_to_s[rx_reset] in module/entity xlx_k7v7_gbt_ngFEC_design__parameterized4 does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:197] INFO: [Synth 8-256] done synthesizing module 'xlx_k7v7_gbt_ngFEC_design__parameterized4' (98#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/xlx_k7v7_gbt_ngFEC_design.vhd:172] INFO: [Synth 8-3491] module 'debug_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:93' bound to instance 'debug_mux_inst' of component 'debug_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1259] INFO: [Synth 8-638] synthesizing module 'debug_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:117] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-638] synthesizing module 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:46] INFO: [Synth 8-256] done synthesizing module 'sfp_signal_mux' (99#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:46] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-3491] module 'sfp_signal_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:29' bound to instance 'debug_sfp_signal_mux' of component 'sfp_signal_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:155] INFO: [Synth 8-3491] module 'global_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:66' bound to instance 'debug_global_mux' of component 'global_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:175] INFO: [Synth 8-638] synthesizing module 'global_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:77] INFO: [Synth 8-256] done synthesizing module 'global_mux' (100#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:77] INFO: [Synth 8-256] done synthesizing module 'debug_mux' (101#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:117] INFO: [Synth 8-3491] module 'debug_mux' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/debug_mux.vhd:93' bound to instance 'debug_mux_inst' of component 'debug_mux' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1259] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_1' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1327] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_2' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1328] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_3' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1329] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_4' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1330] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_5' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1331] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_6' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1332] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_7' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1333] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_8' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1334] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_9' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1335] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_10' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1336] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_11' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1337] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_sda_12' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1338] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_1' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1339] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_2' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1340] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_3' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1341] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_4' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1342] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_5' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1343] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_6' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1344] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_7' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1345] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_8' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1346] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_9' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1347] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_10' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1348] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_11' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1349] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'i_sfp_scl_12' to cell 'IOBUF' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1350] INFO: [Synth 8-638] synthesizing module 'ngFEC_module' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:60] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] INFO: [Synth 8-638] synthesizing module 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:49] Parameter BRAM_SIZE bound to: 36Kb - type: string Parameter DEVICE bound to: 7SERIES - type: string Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter READ_WIDTH_A bound to: 16 - type: integer Parameter READ_WIDTH_B bound to: 16 - type: integer Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_MODE bound to: SAFE - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 16 - type: integer Parameter WRITE_WIDTH_B bound to: 16 - type: integer INFO: [Synth 8-3491] module 'BRAM_TDP_MACRO' declared at 'D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:36' bound to instance 'BRAM_l' of component 'BRAM_TDP_MACRO' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:108] INFO: [Synth 8-638] synthesizing module 'unimacro_BRAM_TDP_MACRO' [D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:224] Parameter BRAM_SIZE bound to: 36Kb - type: string Parameter DEVICE bound to: 7SERIES - type: string Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter READ_WIDTH_A bound to: 16 - type: integer Parameter READ_WIDTH_B bound to: 16 - type: integer Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_MODE bound to: SAFE - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 16 - type: integer Parameter WRITE_WIDTH_B bound to: 16 - type: integer Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: 0 - type: bool Parameter EN_ECC_WRITE bound to: 0 - type: bool Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 18 - type: integer Parameter READ_WIDTH_B bound to: 18 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 18 - type: integer Parameter WRITE_WIDTH_B bound to: 18 - type: integer INFO: [Synth 8-113] binding component instance 'ram36_bl' to cell 'RAMB36E1' [D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:2260] INFO: [Synth 8-256] done synthesizing module 'unimacro_BRAM_TDP_MACRO' (102#1) [D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:224] Parameter BRAM_SIZE bound to: 36Kb - type: string Parameter DEVICE bound to: 7SERIES - type: string Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter READ_WIDTH_A bound to: 16 - type: integer Parameter READ_WIDTH_B bound to: 16 - type: integer Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_MODE bound to: SAFE - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 16 - type: integer Parameter WRITE_WIDTH_B bound to: 16 - type: integer INFO: [Synth 8-3491] module 'BRAM_TDP_MACRO' declared at 'D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:36' bound to instance 'BRAM_l' of component 'BRAM_TDP_MACRO' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:108] Parameter BRAM_SIZE bound to: 36Kb - type: string Parameter DEVICE bound to: 7SERIES - type: string Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter READ_WIDTH_A bound to: 32 - type: integer Parameter READ_WIDTH_B bound to: 32 - type: integer Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_MODE bound to: SAFE - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 32 - type: integer Parameter WRITE_WIDTH_B bound to: 32 - type: integer INFO: [Synth 8-3491] module 'BRAM_TDP_MACRO' declared at 'D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:36' bound to instance 'BRAM_h' of component 'BRAM_TDP_MACRO' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:135] INFO: [Synth 8-638] synthesizing module 'unimacro_BRAM_TDP_MACRO__parameterized0' [D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:224] Parameter BRAM_SIZE bound to: 36Kb - type: string Parameter DEVICE bound to: 7SERIES - type: string Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter READ_WIDTH_A bound to: 32 - type: integer Parameter READ_WIDTH_B bound to: 32 - type: integer Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_MODE bound to: SAFE - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 32 - type: integer Parameter WRITE_WIDTH_B bound to: 32 - type: integer Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: 0 - type: bool Parameter EN_ECC_WRITE bound to: 0 - type: bool Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 36 - type: integer Parameter READ_WIDTH_B bound to: 36 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 36 - type: integer Parameter WRITE_WIDTH_B bound to: 36 - type: integer INFO: [Synth 8-113] binding component instance 'ram36_bl' to cell 'RAMB36E1' [D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:2260] INFO: [Synth 8-256] done synthesizing module 'unimacro_BRAM_TDP_MACRO__parameterized0' (102#1) [D:/Xilinx/Vivado/2018.3/data/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd:224] INFO: [Synth 8-256] done synthesizing module 'Module_RAM' (103#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:49] Parameter partition bound to: 5'b00000 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00000 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b00001 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized1' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00001 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized1' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b00010 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized3' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00010 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized3' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b00011 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized5' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00011 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized5' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b00100 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized7' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00100 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized7' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b00101 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized9' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00101 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized9' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b00110 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized11' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00110 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized11' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b00111 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized13' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b00111 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized13' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b01000 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized15' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b01000 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized15' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b01001 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized17' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b01001 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized17' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b01010 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized19' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b01010 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized19' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b01011 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized21' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b01011 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized21' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b11101 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized23' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b11101 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized23' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b01111 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized25' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b01111 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized25' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'Module_RAM' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/Module_RAM.vhd:28' bound to instance 'RAM' of component 'Module_RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:154] Parameter partition bound to: 5'b11111 INFO: [Synth 8-3491] module 'buffer_server_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:31' bound to instance 'buffer_server' of component 'buffer_server_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:194] INFO: [Synth 8-638] synthesizing module 'buffer_server_com__parameterized27' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] Parameter partition bound to: 5'b11111 INFO: [Synth 8-256] done synthesizing module 'buffer_server_com__parameterized27' (104#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_server_com.vhd:51] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-638] synthesizing module 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:50] INFO: [Synth 8-256] done synthesizing module 'buffer_ngccm_com' (105#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:50] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:217] INFO: [Synth 8-3491] module 'buffer_ngccm_jtag_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_jtag_com.vhd:31' bound to instance 'buffer_ngccm_jtag' of component 'buffer_ngccm_jtag_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:237] INFO: [Synth 8-638] synthesizing module 'buffer_ngccm_jtag_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_jtag_com.vhd:50] INFO: [Synth 8-256] done synthesizing module 'buffer_ngccm_jtag_com' (106#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_jtag_com.vhd:50] INFO: [Synth 8-3491] module 'buffer_ngccm_com' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:30' bound to instance 'bkp_buffer_ngccm' of component 'buffer_ngccm_com' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:254] WARNING: [Synth 8-5858] RAM ram_mosi_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers WARNING: [Synth 8-3848] Net ngccm_mosi[13][ipb_addr] in module/entity ngFEC_module does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:57] WARNING: [Synth 8-3848] Net ngccm_mosi[13][ipb_wdata] in module/entity ngFEC_module does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:57] WARNING: [Synth 8-3848] Net ngccm_mosi[13][ipb_strobe] in module/entity ngFEC_module does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:57] WARNING: [Synth 8-3848] Net ngccm_mosi[13][ipb_write] in module/entity ngFEC_module does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:57] INFO: [Synth 8-256] done synthesizing module 'ngFEC_module' (107#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/ngFEC_module.vhd:60] Parameter orbit bound to: 3564 - type: integer INFO: [Synth 8-3491] module 'delay_counter' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/qie_reset_shifter/delay_counter.vhd:32' bound to instance 'QIE_RESET_DELAY' of component 'delay_counter' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:1454] INFO: [Synth 8-638] synthesizing module 'delay_counter' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/qie_reset_shifter/delay_counter.vhd:41] Parameter orbit bound to: 3564 - type: integer INFO: [Synth 8-256] done synthesizing module 'delay_counter' (108#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/qie_reset_shifter/delay_counter.vhd:41] INFO: [Synth 8-638] synthesizing module 'ngCCM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:95] INFO: [Synth 8-3491] module 'Sync' declared at 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Sync.vhd:25' bound to instance 'Sync_TX_Reset' of component 'Sync' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:398] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'Sync' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Sync.vhd:34] INFO: [Synth 8-256] done synthesizing module 'Sync' (109#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Sync.vhd:34] INFO: [Synth 8-638] synthesizing module 'prbs' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/prbs.vhd:43] Parameter seed bound to: 20'b00101010001000000001 Parameter inverter bound to: 0 - type: bool Parameter hbhehf bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'prbs' (110#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/prbs.vhd:43] INFO: [Synth 8-638] synthesizing module 'gbt_rx_checker' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/gbt_rx_checker.vhd:44] Parameter seed_length bound to: 20 - type: integer Parameter nobReg bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'gbt_rx_checker' (111#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/GBT_tools/gbt_rx_checker.vhd:44] WARNING: [Synth 8-614] signal 'error_counter_reset' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:731] Parameter gCOUNTER_SIZE bound to: 26 - type: integer Parameter gCOUNTER_TERM bound to: 26'b11111111111111111111111111 INFO: [Synth 8-638] synthesizing module 'Agnostic_Counter' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Agnostic_counter.vhd:37] Parameter gCOUNTER_SIZE bound to: 26 - type: integer Parameter gCOUNTER_TERM bound to: 26'b11111111111111111111111111 INFO: [Synth 8-256] done synthesizing module 'Agnostic_Counter' (112#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/Agnostic_counter.vhd:37] Parameter DataBtoA_SZ bound to: 1 - type: integer Parameter DataAtoB_SZ bound to: 84 - type: integer Parameter WAIT_STATES_A bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'CrossClock_RX' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:20] Parameter DataBtoA_SZ bound to: 1 - type: integer Parameter DataAtoB_SZ bound to: 84 - type: integer Parameter WAIT_STATES_A bound to: 0 - type: integer Parameter SHIFTA_MSB bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'CrossClock_RX' (113#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:20] Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'IPbus_local' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:58] Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:44] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:45] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:50] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:51] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:61] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:62] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (113#1) [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-256] done synthesizing module 'IPbus_local' (114#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/IPbus_local.vhd:58] Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer Parameter ADDR_MSB bound to: 11 - type: integer Parameter WAIT_STATES bound to: 10 - type: integer Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] INFO: [Synth 8-638] synthesizing module 'LocalI2CBridge' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalI2CBridge.vhd:78] Parameter ARST_LVL bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'i2c_master_usr' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_top.vhd:112] Parameter ARST_LVL bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'i2c_master_byte_ctrl' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd:113] INFO: [Synth 8-638] synthesizing module 'i2c_master_bit_ctrl' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd:178] Parameter SIZE bound to: 8 - type: integer Parameter DOUT_RST bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'glitch_filter' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/glitch_filter.v:57] Parameter SIZE bound to: 8 - type: integer Parameter DOUT_RST bound to: 1'b1 Parameter BUFSIZE bound to: 7 - type: integer INFO: [Synth 8-5534] Detected attribute (* KEEP = "TRUE" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/glitch_filter.v:85] INFO: [Synth 8-6155] done synthesizing module 'glitch_filter' (115#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/glitch_filter.v:57] Parameter SIZE bound to: 8 - type: integer Parameter DOUT_RST bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'i2c_master_bit_ctrl' (116#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd:178] INFO: [Synth 8-256] done synthesizing module 'i2c_master_byte_ctrl' (117#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd:113] INFO: [Synth 8-256] done synthesizing module 'i2c_master_usr' (118#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/i2c/rtl/vhdl/i2c_master_top.vhd:112] WARNING: [Synth 8-3848] Net I2C_ack_o in module/entity LocalI2CBridge does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalI2CBridge.vhd:64] INFO: [Synth 8-256] done synthesizing module 'LocalI2CBridge' (119#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalI2CBridge.vhd:78] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] WARNING: [Synth 8-5640] Port 'i2c_ack_o' is missing in component declaration [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:170] INFO: [Synth 8-638] synthesizing module 'LocalJTAGBridge' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalJTAGBridge.vhd:94] Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'JTAGMaster' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd:92] Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer INFO: [Synth 8-5534] Detected attribute (* fsm_encoding = "one-hot" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd:224] INFO: [Synth 8-5534] Detected attribute (* fsm_encoding = "one-hot" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd:231] INFO: [Synth 8-5534] Detected attribute (* fsm_encoding = "one-hot" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd:236] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd:285] Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'RAM' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagBram.vhd:66] Parameter gADDR_BITS bound to: 10 - type: integer Parameter gDATA_BITS bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAM' (120#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagBram.vhd:66] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'TCKi_sync_reg' in module 'JTAGMaster' in the same process may cause logic issues. Please split the sync and async parts into different processes [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd:630] INFO: [Synth 8-256] done synthesizing module 'JTAGMaster' (121#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/jtagMaster.vhd:92] INFO: [Synth 8-256] done synthesizing module 'LocalJTAGBridge' (122#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/LocalJTAGBridge.vhd:94] WARNING: [Synth 8-614] signal 'sel_sec_jtag' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'jtag_bridge_tck_o' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'jtag_bridge_tdi_o' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'jtag_bridge_tms_o' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'jtag_bridge_trst_o' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'sec_jtag_tck_o' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'sec_jtag_tdi_o' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'sec_jtag_tms_o' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-614] signal 'ngccmPinsInRx' is read in the process but is not in the sensitivity list [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:1021] WARNING: [Synth 8-3848] Net ipb_miso[15][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[14][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[13][ipb_rdata] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[13][ipb_ack] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[13][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[12][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[11][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[10][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[9][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[8][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[7][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[6][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[5][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[4][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[3][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[2][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[1][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net ipb_miso[0][ipb_err] in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:77] WARNING: [Synth 8-3848] Net reg_ngccmio_sec_i2c in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:260] WARNING: [Synth 8-3848] Net heartBeat_Enable in module/entity ngCCM does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:275] INFO: [Synth 8-256] done synthesizing module 'ngCCM' (123#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:95] Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer Parameter orbit bound to: 3564 - type: integer INFO: [Synth 8-638] synthesizing module 'pm' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/pm.vhd:48] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 1 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'pm' (124#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/pm.vhd:48] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer WARNING: [Synth 8-3848] Net usrled1_r in module/entity ngFEC_logic does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:81] WARNING: [Synth 8-3848] Net usrled1_g in module/entity ngFEC_logic does not have driver. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:82] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'ngFEC_logic' (125#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/new/ngFEC_logicX12.vhd:168] INFO: [Synth 8-256] done synthesizing module 'fc7_top' (126#1) [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/fc7_top.vhd:167] WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[2] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[3] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[4] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[5] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_pcie_clk_ctrl[2] driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port k7_pcie_clk_ctrl[3] driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_pwr_en driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_pwr_en driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_pg_c2m driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_spare[6] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_spare[7] driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_spare[8] driven by constant 0 WARNING: [Synth 8-3331] design xpm_cdc_single__parameterized1 has unconnected port src_clk WARNING: [Synth 8-3331] design IPbus_local has unconnected port reset_local WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[31] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[30] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[29] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[28] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[27] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[26] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[25] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[24] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[23] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[22] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[21] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[20] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[19] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[18] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[17] WARNING: [Synth 8-3331] design i2c_master_usr has unconnected port wb_dat_i[16] WARNING: [Synth 8-3331] design LocalI2CBridge has unconnected port I2C_ack_o WARNING: [Synth 8-3331] design LocalI2CBridge has unconnected port addr_local[3] WARNING: [Synth 8-3331] design LocalJTAGBridge has unconnected port jtag_reg_i[11] WARNING: [Synth 8-3331] design LocalJTAGBridge has unconnected port jtag_reg_i[10] WARNING: [Synth 8-3331] design LocalJTAGBridge has unconnected port tms_i WARNING: [Synth 8-3331] design LocalJTAGBridge has unconnected port trst_i WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[15][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[14][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][31] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][30] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][29] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][28] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][27] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][26] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][25] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][24] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][23] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][22] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][21] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][20] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][19] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][18] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][17] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][16] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][15] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][14] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][13] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][12] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][11] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][10] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][9] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][8] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][7] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][6] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][5] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][4] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][3] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][2] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][1] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_rdata][0] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_ack] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[13][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[12][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[11][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[10][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[9][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[8][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[7][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[6][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[5][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[4][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[3][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[2][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[1][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_miso[0][ipb_err] WARNING: [Synth 8-3331] design ngCCM has unconnected port sfp_sda_i[1] WARNING: [Synth 8-3331] design ngCCM has unconnected port sfp_scl_i[1] WARNING: [Synth 8-3331] design ngCCM has unconnected port sfp_sda_o[1] WARNING: [Synth 8-3331] design ngCCM has unconnected port sfp_scl_o[1] WARNING: [Synth 8-3331] design ngCCM has unconnected port reset_partition[15] WARNING: [Synth 8-3331] design ngCCM has unconnected port reset_partition[13] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][31] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][30] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][29] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][28] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][27] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][26] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][25] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][24] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][23] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][22] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][21] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][20] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][19] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][18] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][17] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][16] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][15] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][14] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][13] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[15][ipb_addr][12] WARNING: [Synth 8-3331] design ngCCM has unconnected port ipb_mosi[14][ipb_addr][31] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 780.688 ; gain = 406.770 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][31] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][30] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][29] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][28] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][27] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][26] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][25] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][24] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][23] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][22] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][21] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][20] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][19] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][18] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][17] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][16] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][15] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][14] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][13] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][12] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][11] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][10] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][9] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][8] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][7] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][6] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][5] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][4] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][3] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][2] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][1] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[7][0] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][31] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][30] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][29] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][28] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][27] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][26] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][25] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][24] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][23] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][22] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][21] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][20] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][19] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][18] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][17] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][16] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][15] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][14] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][13] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][12] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][11] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][10] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][9] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][8] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][7] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][6] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][5] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][4] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][3] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][2] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][1] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[9][0] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][31] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][30] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][29] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][28] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][27] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][26] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][25] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][24] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][23] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][22] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][21] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][20] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][19] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][18] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][17] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][16] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][15] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][14] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][13] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][12] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][11] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][10] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][9] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][8] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][7] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][6] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][5] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][4] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][3] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][2] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][1] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[17][0] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[19][31] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[19][30] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[19][29] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] WARNING: [Synth 8-3295] tying undriven pin ipb_sys_regs:regs_i[19][28] to constant 0 [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/patch/system_core.vhd:447] INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 780.688 ; gain = 406.770 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 780.688 ; gain = 406.770 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 578 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Device 21-403] Loading part xc7k420tffg1156-2 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt/ngFEC_mgt_in_context.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_in_context.xdc] for cell 'sys/eth/phy' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_in_context.xdc] for cell 'sys/eth/phy' Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fc7_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fc7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fc7_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fc7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc] INFO: [Timing 38-2] Deriving generated clocks [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc:67] get_clocks: Time (s): cpu = 00:00:25 ; elapsed = 00:00:15 . Memory (MB): peak = 2450.391 ; gain = 57.414 Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fc7_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fc7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fc7_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fc7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fc7_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fc7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.167 . Memory (MB): peak = 2450.391 ; gain = 0.000 Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[0].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[0].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[10].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[10].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[11].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[11].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[1].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[1].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[2].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[2].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[3].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[3].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[4].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[4].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[5].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[5].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[6].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[6].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[7].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[7].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[8].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[8].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[9].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[9].tx_ready_Sync_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fc7_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fc7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.201 . Memory (MB): peak = 2450.391 ; gain = 0.000 Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 2450.391 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 32 instances were transformed. BUFGMUX => BUFGCTRL (inverted pins: CE0): 1 instances IBUFGDS => IBUFDS: 1 instances IOBUF => IOBUF (IBUF, OBUFT): 26 instances OBUFDS => OBUFDS: 1 instances PLLE2_BASE => PLLE2_ADV: 1 instances SRL16 => SRL16E: 2 instances Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 2450.391 ; gain = 0.000 Constraint Validation Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.830 . Memory (MB): peak = 2450.391 ; gain = 0.000 WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst' at clock pin 'SYSCLK_IN' is different from the actual clock period '24.951', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '16.000' specified during out-of-context synthesis of instance 'sys/eth/phy' at clock pin 'rxuserclk2' is different from the actual clock period '8.000', this can lead to different synthesis results. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:02:29 ; elapsed = 00:02:10 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 2 processes. --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k420tffg1156-2 INFO: [Synth 8-5545] ROM "rst" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "timer" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "bad_crc" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5544] ROM "invert" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "byte_cnt" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5546] ROM "tick_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "set_addr_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "send_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "buf_to_load_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "set_addr_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "send_buf_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "do_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "clr_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "int_valid_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "int_data_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "set_addr_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "send_buf_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "do_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "clr_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "int_valid_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "int_data_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "send_pending_i" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "addr_to_set_int" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "addr_to_set_int" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "shift_buf" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5546] ROM "set_addr_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "send_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_pending" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_data_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "set_addr_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "send_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "next_load" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "request_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "header" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5546] ROM "short_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "send_special_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "flip_cksum" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "counting" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "low_addr_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ipbus_hdr_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "byteswap_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "byteswap_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ipbus_out_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "next_state" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "rxram_active_int0" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "pkt_id_buf_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) WARNING: [Synth 8-3936] Found unconnected internal register 'pkt_rdy_buf_reg' and it is trimmed from '3' to '2' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:154] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-5544] ROM "wctr" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "trans_out[pkt_done]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-5546] ROM "last_wd" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "tx_hdr" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "rmw_write" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "err_d" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "buf_req" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "buf_we" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "SerialInValid" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "SerialOutValid" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "we_pipe" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "r_addr_pipe" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ipbus_out[ipb_rdata]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "reset_ipbus_to_pipe" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sel" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'w_state_reg' in module 'icap_interface' INFO: [Synth 8-802] inferred FSM for state register 'r_state_reg' in module 'icap_interface' INFO: [Synth 8-5544] ROM "r_state" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "read_delay" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "r_state" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'icap_interface_fsm' INFO: [Synth 8-5544] ROM "FMS_SELECT_O" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'datafsm_reg' in module 'i2c_bitwise' INFO: [Synth 8-5544] ROM "datafsm" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "completed" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "datafsm" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "completed" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'chopexecfsm_reg' in module 'i2c_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'ctrlfsm_reg' in module 'i2c_ctrl' INFO: [Synth 8-5546] ROM "error_rdack1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "ctrlfsmprev" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "p_2_in" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "p_0_in" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "p_7_in" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5546] ROM "error_rdack1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "ctrlfsmprev" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "p_2_in" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "p_0_in" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "p_7_in" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ctrlfsm" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'fsm_reg' in module 'i2c_eep_autoread' INFO: [Synth 8-5546] ROM "player_rxdata_reg[1]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[3]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[5]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[7]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[9]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[11]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[13]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[15]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[17]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[19]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[21]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[23]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[25]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[27]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[29]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[31]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[33]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[35]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[37]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[39]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[41]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "player_rxdata_reg[43]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "addrcnt" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "fsm" won't be mapped to RAM because it is too sparse INFO: [Synth 8-4471] merging register 'data_o_reg[31:0]' into 'rxdata_reg[31:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:240] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'spi_master' INFO: [Synth 8-5546] ROM "busy" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "pos_cnt" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'dmtd_with_deglitcher' INFO: [Synth 8-5546] ROM "resync_p_o" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'pd_state_reg' in module 'dmtd_phase_meas' INFO: [Synth 8-5544] ROM "phase_raw_b" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "start" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'cdce_synchronizer' INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "timer" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "fsm_pwrdown" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sync_busy_o" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5546] ROM "regs_reg[0]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[1]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[2]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[3]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[4]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[5]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[6]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[7]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[8]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[9]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "regs_reg[10]" won't be mapped to RAM because it is too sparse INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mgt_bitslipctrl' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mgt_framealigner_pattsearch' INFO: [Synth 8-5544] ROM "headerFlag_s" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' in module 'mgt__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' in module 'mgt__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[3].rstBitSlip_FSM_reg[3]' in module 'mgt__xdcDup__1' INFO: [Synth 8-5544] ROM "reg1" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "DET_IS_ZERO_O" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ZERO_O" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' in module 'mgt__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' in module 'mgt__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' in module 'mgt' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' in module 'mgt' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[3].rstBitSlip_FSM_reg[3]' in module 'mgt' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' in module 'mgt__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' in module 'mgt__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[3].rstBitSlip_FSM_reg[3]' in module 'mgt__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'gtxLatOpt_gen[4].rstBitSlip_FSM_reg[4]' in module 'mgt__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'fe_status_reg' in module 'buffer_ngccm_jtag_com' INFO: [Synth 8-4471] merging register 'output_size_reg[31:0]' into 'response_length_reg[31:0]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngFEC_module/buffer_ngccm_com.vhd:93] INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized3' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized5' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized7' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized9' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized11' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized13' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized15' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized17' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized19' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized21' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized23' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized25' INFO: [Synth 8-802] inferred FSM for state register 'server_ack_reg' in module 'buffer_server_com__parameterized27' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__1' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_bit_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'statemachine.c_state_reg' in module 'i2c_master_byte_ctrl' INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__2' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__3' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__4' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__5' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__5' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__5' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__6' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__6' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__6' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__7' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__7' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__7' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__8' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__8' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__8' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__9' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__9' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__9' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__10' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__10' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__10' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster__xdcDup__11' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster__xdcDup__11' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster__xdcDup__11' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGCtrl_reg' in module 'JTAGMaster' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGIO_reg' in module 'JTAGMaster' INFO: [Synth 8-802] inferred FSM for state register 'StateJTAGTDO_reg' in module 'JTAGMaster' INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "DoSleep" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- w_s0 | 000 | 000 w_s1 | 001 | 001 w_s2 | 010 | 010 w_s3 | 011 | 011 w_s4 | 100 | 100 w_s5 | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'w_state_reg' using encoding 'sequential' in module 'icap_interface' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- r_s0 | 00 | 00 r_s1 | 01 | 01 r_s2 | 10 | 10 r_s3 | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'r_state_reg' using encoding 'sequential' in module 'icap_interface' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s0 | 00001 | 000 s1 | 00010 | 001 s2 | 00100 | 010 s3 | 01000 | 011 s4 | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'icap_interface_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start | 001 | 001 stop | 010 | 010 writebyte | 011 | 011 readbyte | 100 | 101 getack | 101 | 100 sendack | 110 | 110 sendnak | 111 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'datafsm_reg' using encoding 'sequential' in module 'i2c_bitwise' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 a | 01 | 01 b | 10 | 10 iSTATE | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'chopexecfsm_reg' using encoding 'sequential' in module 'i2c_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000 | 00000 req_startclk | 00001 | 00001 req_start_1 | 00010 | 00010 req_chipaddr_1 | 00011 | 00011 req_getack_1 | 00100 | 00100 req_regaddr | 00101 | 00101 req_getack_2 | 00110 | 00110 req_start_2 | 00111 | 01010 req_chipaddr_2 | 01000 | 01011 req_getack_4 | 01001 | 01100 req_wrdata | 01010 | 00111 req_getack_3 | 01011 | 01000 req_rddata | 01100 | 01101 req_sendack | 01101 | 01110 req_rddata_2 | 01110 | 01111 req_sendnak | 01111 | 10000 req_stop_2 | 10000 | 10001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'ctrlfsm_reg' using encoding 'sequential' in module 'i2c_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 00001 | 000 iSTATE | 00010 | 001 iSTATE0 | 00100 | 010 iSTATE1 | 01000 | 011 iSTATE3 | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_reg' using encoding 'one-hot' in module 'i2c_eep_autoread' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE1 | 00 | 00 iSTATE | 01 | 01 iSTATE0 | 10 | 10 iSTATE2 | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'spi_master' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- wait_stable_0 | 001 | 00 wait_edge | 010 | 01 got_edge | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'dmtd_with_deglitcher' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- pd_wait_tag | 00 | 00 pd_wait_b | 01 | 10 pd_wait_a | 10 | 01 pd_get_phase | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'pd_state_reg' using encoding 'sequential' in module 'dmtd_phase_meas' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'cdce_synchronizer' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- e0_idle | 001 | 00 e4_dobitslip | 010 | 01 e5_waitncycles | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'mgt_bitslipctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- unlocked | 00 | 00 going_lock | 01 | 01 locked | 10 | 10 going_unlock | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mgt_framealigner_pattsearch' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' using encoding 'one-hot' in module 'mgt__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' using encoding 'one-hot' in module 'mgt__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[3].rstBitSlip_FSM_reg[3]' using encoding 'one-hot' in module 'mgt__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' using encoding 'one-hot' in module 'mgt__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' using encoding 'one-hot' in module 'mgt__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' using encoding 'one-hot' in module 'mgt' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' using encoding 'one-hot' in module 'mgt' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[3].rstBitSlip_FSM_reg[3]' using encoding 'one-hot' in module 'mgt' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[1].rstBitSlip_FSM_reg[1]' using encoding 'one-hot' in module 'mgt__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[2].rstBitSlip_FSM_reg[2]' using encoding 'one-hot' in module 'mgt__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[3].rstBitSlip_FSM_reg[3]' using encoding 'one-hot' in module 'mgt__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 reset_tx | 010 | 01 reset_rx | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gtxLatOpt_gen[4].rstBitSlip_FSM_reg[4]' using encoding 'one-hot' in module 'mgt__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle_s | 000 | 000 write_s | 001 | 011 wait_s | 010 | 100 precmd_s | 011 | 101 cmd_s | 100 | 110 busy_s | 101 | 001 response_s | 110 | 010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fe_status_reg' using encoding 'sequential' in module 'buffer_ngccm_jtag_com' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized13' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized15' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized17' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized19' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized21' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized23' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized25' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE0 | 00 | 00 iSTATE1 | 01 | 01 iSTATE2 | 10 | 10 iSTATE | 11 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'server_ack_reg' using encoding 'sequential' in module 'buffer_server_com__parameterized27' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle_b | 00000 | 00001 idle_c | 00001 | 00010 idle_d | 00010 | 00011 idle_e | 00011 | 00100 idle_f | 00100 | 00101 start_a | 00101 | 00110 start_b | 00110 | 00111 start_c | 00111 | 01000 start_d | 01000 | 01001 start_e | 01001 | 01010 stop_a | 01010 | 01011 stop_b | 01011 | 01100 stop_c | 01100 | 01101 stop_d | 01101 | 01110 stop_e | 01110 | 01111 wr_a | 01111 | 10101 wr_b | 10000 | 10110 wr_c | 10001 | 10111 wr_d | 10010 | 11000 wr_e | 10011 | 11001 rd_a | 10100 | 10000 rd_b | 10101 | 10001 rd_c | 10110 | 10010 rd_d | 10111 | 10011 rd_e | 11000 | 10100 idle_a | 11001 | 00000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_bit_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 000 | 000 st_start | 001 | 001 st_read | 010 | 010 st_write | 011 | 011 st_ack | 100 | 100 st_stop | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'statemachine.c_state_reg' using encoding 'sequential' in module 'i2c_master_byte_ctrl' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__2' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__3' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__4' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__5' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__6' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__6' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__6' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__7' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__7' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__8' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__8' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__8' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__9' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__9' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__10' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__10' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__10' WARNING: [Synth 8-327] inferring latch for variable 'jtag_tck_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:553] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:554] WARNING: [Synth 8-327] inferring latch for variable 'jtag_tms_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:555] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_reset]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'ngccmPinsOutReg_reg[sec_sel_addr]' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:468] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tdo_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:970] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tck_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:971] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_tms_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:973] WARNING: [Synth 8-327] inferring latch for variable 'jtag_bridge_trst_i_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:974] WARNING: [Synth 8-327] inferring latch for variable 'sec_jtag_tdi_o_reg' [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/ngCCM.vhd:559] INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster__xdcDup__11' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 capture | 01 | 01 next_bit | 10 | 10 wait_tck | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGTDO_reg' using encoding 'sequential' in module 'JTAGMaster' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- jtag_idle | 00 | 00 jtag_go | 01 | 01 jtag_wait | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGCtrl_reg' using encoding 'sequential' in module 'JTAGMaster' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 next_word_ld | 001 | 110 fall | 010 | 001 prerise | 011 | 010 rise | 100 | 011 prefall | 101 | 100 next_word_rd | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'StateJTAGIO_reg' using encoding 'sequential' in module 'JTAGMaster' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:03:13 ; elapsed = 00:02:56 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------------------+------------+----------+ |1 |i2c_master_core | 1| 1974| |2 |system_core__GC0 | 1| 32499| |3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| |4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| |5 |TTC_decoder__GC0 | 1| 366| |6 |gbt_rx | 12| 10684| |7 |gbt_bank__xdcDup__1__GC0 | 1| 22419| |8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 516| |9 |gbt_bank__parameterized0__GC0 | 1| 14932| |10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 344| |11 |gbt_bank__GC0 | 1| 22419| |12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 516| |13 |gbt_bank__parameterized1__GC0 | 1| 29920| |14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 688| |15 |ngFEC_module__GBM0 | 1| 34676| |16 |ngFEC_module__GBM1 | 1| 12685| |17 |ngFEC_module__GBM2 | 1| 16886| |18 |ngFEC_logic__GCB0 | 1| 27110| |19 |ngFEC_logic__GCB1 | 1| 22694| |20 |ngFEC_logic__GCB2 | 1| 22692| |21 |ngFEC_logic__GCB3 | 1| 22692| |22 |ngFEC_logic__GCB4 | 1| 25447| |23 |ngFEC_logic__GCB5 | 1| 22692| |24 |ngFEC_logic__GCB6 | 1| 22692| |25 |ngFEC_logic__GCB7 | 1| 22692| |26 |ngFEC_logic__GCB8 | 1| 22692| |27 |ngCCM | 1| 22608| |28 |ngCCM__xdcDup__11 | 1| 22608| |29 |ngCCM__xdcDup__10 | 1| 22608| |30 |ngFEC_logic__GCB12 | 1| 22692| |31 |ngFEC_logic__GCB13 | 1| 170| |32 |fc7_top__GC0 | 1| 3| +------+-----------------------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 723 2 Input 26 Bit Adders := 12 2 Input 24 Bit Adders := 1 2 Input 20 Bit Adders := 13 2 Input 19 Bit Adders := 12 2 Input 18 Bit Adders := 24 2 Input 17 Bit Adders := 24 2 Input 16 Bit Adders := 186 2 Input 15 Bit Adders := 24 2 Input 14 Bit Adders := 14 3 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 15 2 Input 12 Bit Adders := 218 2 Input 11 Bit Adders := 26 2 Input 10 Bit Adders := 21 2 Input 9 Bit Adders := 18 2 Input 8 Bit Adders := 28 2 Input 7 Bit Adders := 25 2 Input 6 Bit Adders := 30 2 Input 5 Bit Adders := 50 2 Input 4 Bit Adders := 224 2 Input 3 Bit Adders := 233 2 Input 2 Bit Adders := 17 +---XORs : 2 Input 44 Bit XORs := 12 2 Input 40 Bit XORs := 12 2 Input 20 Bit XORs := 12 2 Input 16 Bit XORs := 1 4 Input 16 Bit XORs := 1 2 Input 1 Bit XORs := 26841 5 Input 1 Bit XORs := 5676 7 Input 1 Bit XORs := 394 10 Input 1 Bit XORs := 2 3 Input 1 Bit XORs := 4740 4 Input 1 Bit XORs := 2779 6 Input 1 Bit XORs := 1068 12 Input 1 Bit XORs := 2 9 Input 1 Bit XORs := 4 8 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 2 17 Input 1 Bit XORs := 1 11 Input 1 Bit XORs := 2 +---XORs : 39 Bit Wide XORs := 1 13 Bit Wide XORs := 1 7 Bit Wide XORs := 1 +---Registers : 336 Bit Registers := 1 128 Bit Registers := 8 120 Bit Registers := 12 112 Bit Registers := 1 100 Bit Registers := 12 84 Bit Registers := 72 48 Bit Registers := 5 45 Bit Registers := 2 42 Bit Registers := 3 39 Bit Registers := 1 38 Bit Registers := 2 36 Bit Registers := 1 34 Bit Registers := 1 32 Bit Registers := 3076 31 Bit Registers := 2 30 Bit Registers := 2 26 Bit Registers := 12 24 Bit Registers := 4 21 Bit Registers := 144 20 Bit Registers := 49 18 Bit Registers := 12 16 Bit Registers := 95 15 Bit Registers := 12 14 Bit Registers := 7 13 Bit Registers := 24 12 Bit Registers := 1108 11 Bit Registers := 14 10 Bit Registers := 36 9 Bit Registers := 11 8 Bit Registers := 1077 7 Bit Registers := 330 6 Bit Registers := 40 5 Bit Registers := 66 4 Bit Registers := 726 3 Bit Registers := 597 2 Bit Registers := 204 1 Bit Registers := 9948 +---RAMs : 256K Bit RAMs := 1 64K Bit RAMs := 4 32K Bit RAMs := 13 +---Muxes : 2 Input 336 Bit Muxes := 2 2 Input 128 Bit Muxes := 9 4 Input 128 Bit Muxes := 1 2 Input 112 Bit Muxes := 1 2 Input 100 Bit Muxes := 12 2 Input 84 Bit Muxes := 24 2 Input 60 Bit Muxes := 24 2 Input 48 Bit Muxes := 7 4 Input 48 Bit Muxes := 1 2 Input 44 Bit Muxes := 24 2 Input 42 Bit Muxes := 1 2 Input 32 Bit Muxes := 4540 3 Input 32 Bit Muxes := 38 6 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 193 19 Input 32 Bit Muxes := 1 11 Input 32 Bit Muxes := 1 5 Input 32 Bit Muxes := 829 44 Input 32 Bit Muxes := 1 7 Input 32 Bit Muxes := 252 2 Input 31 Bit Muxes := 14 2 Input 26 Bit Muxes := 12 2 Input 24 Bit Muxes := 5 4 Input 24 Bit Muxes := 2 19 Input 24 Bit Muxes := 1 2 Input 21 Bit Muxes := 96 2 Input 20 Bit Muxes := 13 4 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 24 15 Input 18 Bit Muxes := 1 2 Input 18 Bit Muxes := 24 3 Input 18 Bit Muxes := 12 14 Input 18 Bit Muxes := 12 2 Input 17 Bit Muxes := 12 2 Input 16 Bit Muxes := 343 4 Input 16 Bit Muxes := 14 14 Input 16 Bit Muxes := 3 11 Input 16 Bit Muxes := 1 8 Input 16 Bit Muxes := 1 5 Input 16 Bit Muxes := 2 18 Input 16 Bit Muxes := 4 7 Input 16 Bit Muxes := 12 3 Input 16 Bit Muxes := 2 2 Input 15 Bit Muxes := 12 4 Input 15 Bit Muxes := 12 2 Input 14 Bit Muxes := 12 3 Input 14 Bit Muxes := 2 2 Input 13 Bit Muxes := 48 4 Input 13 Bit Muxes := 2 8 Input 13 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 666 7 Input 12 Bit Muxes := 24 2 Input 11 Bit Muxes := 24 7 Input 11 Bit Muxes := 12 2 Input 10 Bit Muxes := 44 4 Input 10 Bit Muxes := 2 3 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 41 8 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 3675 17 Input 8 Bit Muxes := 2 3 Input 8 Bit Muxes := 14 4 Input 8 Bit Muxes := 21 13 Input 8 Bit Muxes := 1 5 Input 8 Bit Muxes := 170 9 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 27 4 Input 7 Bit Muxes := 13 7 Input 7 Bit Muxes := 1 8 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 58 3 Input 6 Bit Muxes := 15 6 Input 6 Bit Muxes := 2 5 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 1 7 Input 6 Bit Muxes := 2 4 Input 6 Bit Muxes := 1 17 Input 5 Bit Muxes := 1 36 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 42 5 Input 5 Bit Muxes := 3 4 Input 5 Bit Muxes := 12 32 Input 5 Bit Muxes := 156 8 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 161 2 Input 4 Bit Muxes := 776 5 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 17 16 Input 4 Bit Muxes := 48 7 Input 4 Bit Muxes := 12 6 Input 4 Bit Muxes := 156 15 Input 3 Bit Muxes := 157 2 Input 3 Bit Muxes := 5106 17 Input 3 Bit Muxes := 1 8 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 182 6 Input 3 Bit Muxes := 1 7 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 360 12 Input 3 Bit Muxes := 24 5 Input 3 Bit Muxes := 168 3 Input 2 Bit Muxes := 357 2 Input 2 Bit Muxes := 647 4 Input 2 Bit Muxes := 208 17 Input 2 Bit Muxes := 2 6 Input 2 Bit Muxes := 1 5 Input 2 Bit Muxes := 348 2 Input 1 Bit Muxes := 10926 7 Input 1 Bit Muxes := 309 8 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 2286 5 Input 1 Bit Muxes := 1224 4 Input 1 Bit Muxes := 869 6 Input 1 Bit Muxes := 961 17 Input 1 Bit Muxes := 26 9 Input 1 Bit Muxes := 4 11 Input 1 Bit Muxes := 2 12 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 9 16 Input 1 Bit Muxes := 9 19 Input 1 Bit Muxes := 16 26 Input 1 Bit Muxes := 1092 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module i2c_bitwise Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 2 2 Input 4 Bit Adders := 1 +---Registers : 10 Bit Registers := 2 9 Bit Registers := 1 8 Bit Registers := 4 4 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 2 Input 10 Bit Muxes := 4 8 Input 8 Bit Muxes := 2 8 Input 4 Bit Muxes := 1 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 1 8 Input 1 Bit Muxes := 13 Module i2c_ctrl Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 2 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 3 8 Bit Registers := 9 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 39 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 4 Input 10 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 17 Input 8 Bit Muxes := 1 17 Input 5 Bit Muxes := 1 36 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 17 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 24 3 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 2 4 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 1 17 Input 1 Bit Muxes := 25 Module i2c_master_core Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 Module clocks_7s_serdes Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 2 6 Input 1 Bit Muxes := 1 Module EthernetCRC__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 22 5 Input 1 Bit XORs := 5 7 Input 1 Bit XORs := 5 10 Input 1 Bit XORs := 1 3 Input 1 Bit XORs := 5 4 Input 1 Bit XORs := 9 6 Input 1 Bit XORs := 5 12 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 2 8 Input 1 Bit XORs := 1 +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 3 Module EthernetCRC Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 22 5 Input 1 Bit XORs := 5 7 Input 1 Bit XORs := 5 10 Input 1 Bit XORs := 1 3 Input 1 Bit XORs := 5 4 Input 1 Bit XORs := 9 6 Input 1 Bit XORs := 5 12 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 2 8 Input 1 Bit XORs := 1 +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 3 Module soft_emac Detailed RTL Component Info : +---Adders : 2 Input 11 Bit Adders := 2 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 2 2 Input 2 Bit Adders := 1 +---Registers : 11 Bit Registers := 2 8 Bit Registers := 6 5 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 2 1 Bit Registers := 19 +---Muxes : 3 Input 8 Bit Muxes := 1 4 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module eth_7s_1000basex Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module udp_ipaddr_block Detailed RTL Component Info : +---Registers : 42 Bit Registers := 1 32 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module udp_rarp_block Detailed RTL Component Info : +---Adders : 2 Input 24 Bit Adders := 1 2 Input 6 Bit Adders := 2 +---XORs : 2 Input 16 Bit XORs := 1 4 Input 16 Bit XORs := 1 +---Registers : 336 Bit Registers := 1 42 Bit Registers := 1 24 Bit Registers := 1 16 Bit Registers := 2 13 Bit Registers := 1 8 Bit Registers := 1 6 Bit Registers := 4 5 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 336 Bit Muxes := 2 2 Input 42 Bit Muxes := 1 2 Input 24 Bit Muxes := 1 2 Input 16 Bit Muxes := 4 2 Input 6 Bit Muxes := 3 2 Input 1 Bit Muxes := 4 Module udp_build_arp Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 48 Bit Registers := 2 13 Bit Registers := 1 8 Bit Registers := 1 6 Bit Registers := 4 1 Bit Registers := 7 +---Muxes : 2 Input 48 Bit Muxes := 3 2 Input 8 Bit Muxes := 2 3 Input 6 Bit Muxes := 1 6 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 8 2 Input 3 Bit Muxes := 1 6 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 5 Module udp_build_payload Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 4 13 Bit Registers := 6 8 Bit Registers := 2 1 Bit Registers := 20 +---Muxes : 2 Input 16 Bit Muxes := 6 4 Input 16 Bit Muxes := 2 14 Input 16 Bit Muxes := 3 11 Input 16 Bit Muxes := 1 2 Input 13 Bit Muxes := 12 2 Input 8 Bit Muxes := 2 13 Input 8 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 23 9 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 2 11 Input 1 Bit Muxes := 2 12 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 9 Module udp_build_ping Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 +---Registers : 16 Bit Registers := 2 13 Bit Registers := 4 8 Bit Registers := 2 6 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 14 +---Muxes : 2 Input 16 Bit Muxes := 2 8 Input 16 Bit Muxes := 1 5 Input 16 Bit Muxes := 1 2 Input 13 Bit Muxes := 8 4 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 7 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 3 2 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 11 4 Input 1 Bit Muxes := 8 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 Module udp_build_resend Detailed RTL Component Info : +---Registers : 45 Bit Registers := 1 16 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module udp_build_status Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 13 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 4 1 Bit Registers := 9 +---Muxes : 2 Input 128 Bit Muxes := 2 2 Input 8 Bit Muxes := 2 2 Input 7 Bit Muxes := 9 2 Input 6 Bit Muxes := 2 7 Input 6 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 6 8 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 3 Module udp_status_buffer Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 128 Bit Registers := 4 16 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 12 +---Muxes : 2 Input 128 Bit Muxes := 4 4 Input 128 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 5 Bit Muxes := 3 5 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 4 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 25 4 Input 1 Bit Muxes := 2 Module udp_byte_sum__1 Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 2 +---Registers : 9 Bit Registers := 4 8 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 9 Bit Muxes := 6 2 Input 8 Bit Muxes := 7 2 Input 1 Bit Muxes := 9 Module udp_do_rx_reset Detailed RTL Component Info : +---Registers : 12 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 12 Bit Muxes := 1 Module udp_packet_parser Detailed RTL Component Info : +---Registers : 128 Bit Registers := 2 112 Bit Registers := 1 48 Bit Registers := 1 45 Bit Registers := 1 42 Bit Registers := 1 38 Bit Registers := 2 36 Bit Registers := 1 34 Bit Registers := 1 32 Bit Registers := 4 24 Bit Registers := 2 16 Bit Registers := 1 10 Bit Registers := 1 8 Bit Registers := 1 6 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 17 +---Muxes : 2 Input 128 Bit Muxes := 2 2 Input 112 Bit Muxes := 1 2 Input 48 Bit Muxes := 1 4 Input 48 Bit Muxes := 1 2 Input 32 Bit Muxes := 4 3 Input 32 Bit Muxes := 1 2 Input 24 Bit Muxes := 2 4 Input 24 Bit Muxes := 2 2 Input 16 Bit Muxes := 1 5 Input 16 Bit Muxes := 1 3 Input 10 Bit Muxes := 1 4 Input 8 Bit Muxes := 6 5 Input 8 Bit Muxes := 1 4 Input 7 Bit Muxes := 1 4 Input 6 Bit Muxes := 1 4 Input 4 Bit Muxes := 3 5 Input 4 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 32 4 Input 1 Bit Muxes := 1 Module udp_rxram_mux Detailed RTL Component Info : +---Registers : 13 Bit Registers := 2 8 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 13 Bit Muxes := 5 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 6 Module udp_DualPortRAM Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module udp_buffer_selector Detailed RTL Component Info : +---Registers : 2 Bit Registers := 3 1 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 8 2 Input 1 Bit Muxes := 2 Module udp_rxram_shim Detailed RTL Component Info : +---Registers : 13 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 2 Input 13 Bit Muxes := 1 Module udp_DualPortRAM_rx Detailed RTL Component Info : +---Registers : 8 Bit Registers := 4 +---RAMs : 64K Bit RAMs := 4 +---Muxes : 4 Input 1 Bit Muxes := 4 Module udp_buffer_selector__parameterized0__1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---Registers : 16 Bit Registers := 3 4 Bit Registers := 2 1 Bit Registers := 3 +---Muxes : 2 Input 16 Bit Muxes := 8 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module udp_DualPortRAM_tx Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 +---Muxes : 4 Input 8 Bit Muxes := 1 Module udp_buffer_selector__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---Registers : 16 Bit Registers := 3 4 Bit Registers := 2 1 Bit Registers := 3 +---Muxes : 2 Input 16 Bit Muxes := 8 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module udp_byte_sum Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 2 +---Registers : 9 Bit Registers := 4 8 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 9 Bit Muxes := 6 2 Input 8 Bit Muxes := 7 2 Input 1 Bit Muxes := 9 Module udp_rxtransactor_if Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 2 Module udp_tx_mux Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 2 Input 5 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 4 13 Bit Registers := 6 8 Bit Registers := 4 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 24 +---Muxes : 6 Input 32 Bit Muxes := 1 18 Input 16 Bit Muxes := 4 2 Input 13 Bit Muxes := 10 8 Input 13 Bit Muxes := 1 4 Input 13 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 13 9 Input 8 Bit Muxes := 1 17 Input 8 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 17 Input 2 Bit Muxes := 2 2 Input 2 Bit Muxes := 1 8 Input 1 Bit Muxes := 8 7 Input 1 Bit Muxes := 7 2 Input 1 Bit Muxes := 27 5 Input 1 Bit Muxes := 2 9 Input 1 Bit Muxes := 3 16 Input 1 Bit Muxes := 8 17 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 2 Module udp_txtransactor_if Detailed RTL Component Info : +---Registers : 16 Bit Registers := 16 4 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 16 16 Input 1 Bit Muxes := 1 Module udp_clock_crossing_if Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 10 +---Registers : 4 Bit Registers := 5 3 Bit Registers := 7 2 Bit Registers := 5 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 3 Bit Muxes := 2 Module UDP_if Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 1 Module transactor_if Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 12 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 7 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 3 7 Input 1 Bit Muxes := 1 Module transactor_sm Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 8 Bit Adders := 3 +---Registers : 32 Bit Registers := 5 8 Bit Registers := 3 4 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 5 3 Input 8 Bit Muxes := 1 6 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 6 2 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 2 6 Input 1 Bit Muxes := 1 Module transactor_cfg Detailed RTL Component Info : +---Registers : 128 Bit Registers := 1 +---Muxes : 2 Input 128 Bit Muxes := 1 4 Input 32 Bit Muxes := 1 Module trans_arb Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 8 Module trans_buffer Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 1 Bit Registers := 9 Module spi_interface Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---Registers : 30 Bit Registers := 2 16 Bit Registers := 3 4 Bit Registers := 2 3 Bit Registers := 3 2 Bit Registers := 1 1 Bit Registers := 10 +---Muxes : 2 Input 16 Bit Muxes := 6 2 Input 4 Bit Muxes := 4 6 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 28 4 Input 1 Bit Muxes := 1 Module uc_pipe_interface Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 2 2 Input 9 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 1 10 Bit Registers := 2 9 Bit Registers := 2 2 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 2 Input 32 Bit Muxes := 3 2 Input 9 Bit Muxes := 4 2 Input 1 Bit Muxes := 15 Module ip_mac_select Detailed RTL Component Info : +---Registers : 48 Bit Registers := 2 32 Bit Registers := 2 1 Bit Registers := 21 +---Muxes : 2 Input 48 Bit Muxes := 3 2 Input 32 Bit Muxes := 3 2 Input 1 Bit Muxes := 4 Module ipbus_sys_fabric Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Muxes : 2 Input 32 Bit Muxes := 19 15 Input 18 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 18 Module system_regs Detailed RTL Component Info : +---Registers : 32 Bit Registers := 19 1 Bit Registers := 1 +---Muxes : 19 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 24 Bit Muxes := 1 19 Input 24 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 19 Input 1 Bit Muxes := 16 Module flashIcap_ioControl Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module icap_interface Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 6 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 12 6 Input 1 Bit Muxes := 11 4 Input 1 Bit Muxes := 11 Module icap_interface_fsm Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 11 Input 32 Bit Muxes := 1 5 Input 32 Bit Muxes := 1 5 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 5 Input 1 Bit Muxes := 5 Module i2c_eep_autoread Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 31 Bit Registers := 2 24 Bit Registers := 1 8 Bit Registers := 22 6 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 44 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 2 2 Input 24 Bit Muxes := 1 5 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 23 5 Input 1 Bit Muxes := 24 Module spi_master Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 2 2 Input 10 Bit Adders := 1 2 Input 6 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 2 10 Bit Registers := 2 7 Bit Registers := 1 6 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 2 Input 32 Bit Muxes := 6 2 Input 12 Bit Muxes := 2 4 Input 10 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 8 Input 7 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 20 4 Input 1 Bit Muxes := 6 Module system_core Detailed RTL Component Info : +---Muxes : 7 Input 3 Bit Muxes := 1 Module TTC_decoder Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 2 3 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 2 17 Input 1 Bit XORs := 1 11 Input 1 Bit XORs := 2 6 Input 1 Bit XORs := 2 5 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 1 +---XORs : 39 Bit Wide XORs := 1 13 Bit Wide XORs := 1 7 Bit Wide XORs := 1 +---Registers : 39 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 1 6 Bit Registers := 2 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 2 Input 7 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 12 Module gbt_rx_decoder_gbtframe_syndrom__2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 385 4 Input 1 Bit XORs := 9 5 Input 1 Bit XORs := 3 3 Input 1 Bit XORs := 7 Module gbt_rx_decoder_gbtframe_lmbddet__2 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 6 Input 1 Bit XORs := 2 5 Input 1 Bit XORs := 3 3 Input 1 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_errlcpoly__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 10 2 Input 1 Bit XORs := 32 4 Input 1 Bit XORs := 6 5 Input 1 Bit XORs := 22 6 Input 1 Bit XORs := 3 +---Muxes : 2 Input 4 Bit Muxes := 4 Module gbt_rx_decoder_gbtframe_elpeval__30 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__29 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__28 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__27 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__26 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__25 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__24 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__23 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__22 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__21 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__20 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__19 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__18 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__17 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__16 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_chnsrch__2 Detailed RTL Component Info : +---Muxes : 2 Input 12 Bit Muxes := 1 16 Input 4 Bit Muxes := 2 Module gbt_rx_decoder_gbtframe_rs2errcor__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 6 2 Input 1 Bit XORs := 204 4 Input 1 Bit XORs := 5 5 Input 1 Bit XORs := 11 6 Input 1 Bit XORs := 3 +---Muxes : 2 Input 60 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_rsdec__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 44 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_syndrom Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 385 4 Input 1 Bit XORs := 9 5 Input 1 Bit XORs := 3 3 Input 1 Bit XORs := 7 Module gbt_rx_decoder_gbtframe_lmbddet Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 6 Input 1 Bit XORs := 2 5 Input 1 Bit XORs := 3 3 Input 1 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_errlcpoly Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 10 2 Input 1 Bit XORs := 32 4 Input 1 Bit XORs := 6 5 Input 1 Bit XORs := 22 6 Input 1 Bit XORs := 3 +---Muxes : 2 Input 4 Bit Muxes := 4 Module gbt_rx_decoder_gbtframe_elpeval__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__3 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__4 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__5 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__6 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__7 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__8 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__9 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__10 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__11 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__12 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__13 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__14 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval__15 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_elpeval Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 2 Input 1 Bit XORs := 15 4 Input 1 Bit XORs := 4 5 Input 1 Bit XORs := 7 6 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_chnsrch Detailed RTL Component Info : +---Muxes : 2 Input 12 Bit Muxes := 1 16 Input 4 Bit Muxes := 2 Module gbt_rx_decoder_gbtframe_rs2errcor Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 6 2 Input 1 Bit XORs := 204 4 Input 1 Bit XORs := 5 5 Input 1 Bit XORs := 11 6 Input 1 Bit XORs := 3 +---Muxes : 2 Input 60 Bit Muxes := 1 Module gbt_rx_decoder_gbtframe_rsdec Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 44 Bit Muxes := 1 Module gbt_rx_decoder Detailed RTL Component Info : +---XORs : 2 Input 44 Bit XORs := 1 2 Input 40 Bit XORs := 1 +---Registers : 84 Bit Registers := 1 Module gbt_rx_descrambler_21bit__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 2 Module gbt_rx_descrambler_21bit__3 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 2 Module gbt_rx_descrambler_21bit__4 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 2 Module gbt_rx_descrambler_21bit Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 2 Module gbt_rx_descrambler Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module mgt_bitslipctrl__2 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__2 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl__3 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__3 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl__4 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__4 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 18 Bit Adders := 3 2 Input 8 Bit Adders := 3 +---Registers : 18 Bit Registers := 3 8 Bit Registers := 6 1 Bit Registers := 15 +---Muxes : 2 Input 18 Bit Muxes := 3 3 Input 18 Bit Muxes := 3 3 Input 8 Bit Muxes := 3 3 Input 3 Bit Muxes := 12 2 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 6 Module gbt_tx_scrambler_21bit__8 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__7 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__6 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__5 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__2 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__4 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__3 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__12 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__11 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__10 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__9 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__3 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__6 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__5 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__3 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__4 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__13 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__4 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__7 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module xpm_cdc_single__38 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__37 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__2 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__36 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__3 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__2 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__3 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__4 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_bank_reset__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module xlx_k7v7_gbt_ngFEC_design__xdcDup__1 Detailed RTL Component Info : +---Registers : 6 Bit Registers := 3 +---Muxes : 2 Input 6 Bit Muxes := 3 Module mgt_bitslipctrl__5 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__5 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl__6 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__6 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 18 Bit Adders := 2 2 Input 8 Bit Adders := 2 +---Registers : 18 Bit Registers := 2 8 Bit Registers := 4 1 Bit Registers := 10 +---Muxes : 2 Input 18 Bit Muxes := 2 3 Input 18 Bit Muxes := 2 3 Input 8 Bit Muxes := 2 3 Input 2 Bit Muxes := 8 2 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 4 Module gbt_tx_scrambler_21bit__20 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__19 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__18 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__17 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__5 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__10 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__9 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__14 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__15 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__16 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__21 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__6 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__8 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__11 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module xpm_cdc_single__40 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__4 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__39 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__5 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__5 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__6 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_bank_reset__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module xlx_k7v7_gbt_ngFEC_design__parameterized1 Detailed RTL Component Info : +---Registers : 6 Bit Registers := 2 +---Muxes : 2 Input 6 Bit Muxes := 2 Module mgt_bitslipctrl__7 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__7 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl__8 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__8 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl__9 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__9 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt Detailed RTL Component Info : +---Adders : 2 Input 18 Bit Adders := 3 2 Input 8 Bit Adders := 3 +---Registers : 18 Bit Registers := 3 8 Bit Registers := 6 1 Bit Registers := 15 +---Muxes : 2 Input 18 Bit Muxes := 3 3 Input 18 Bit Muxes := 3 3 Input 8 Bit Muxes := 3 3 Input 3 Bit Muxes := 12 2 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 6 Module gbt_tx_scrambler_21bit__28 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__27 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__26 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__25 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__7 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__14 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__13 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__32 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__31 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__30 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__29 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__8 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__16 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__15 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__22 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__23 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__24 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__33 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__9 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__12 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__17 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module xpm_cdc_single__43 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__6 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__42 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__7 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__41 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__8 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__7 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__8 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__9 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_bank_reset__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module xlx_k7v7_gbt_ngFEC_design Detailed RTL Component Info : +---Registers : 6 Bit Registers := 3 +---Muxes : 2 Input 6 Bit Muxes := 3 Module mgt_bitslipctrl__10 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__10 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl__11 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__11 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl__12 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch__12 Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt_bitslipctrl Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module mgt_framealigner_pattsearch Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 4 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 12 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 Module mgt__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 18 Bit Adders := 4 2 Input 8 Bit Adders := 4 +---Registers : 18 Bit Registers := 4 8 Bit Registers := 8 1 Bit Registers := 20 +---Muxes : 2 Input 18 Bit Muxes := 4 3 Input 18 Bit Muxes := 4 3 Input 8 Bit Muxes := 4 3 Input 4 Bit Muxes := 16 2 Input 1 Bit Muxes := 4 3 Input 1 Bit Muxes := 8 Module gbt_tx_scrambler_21bit__40 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__39 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__38 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__37 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__10 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__20 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__19 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__44 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__43 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__42 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__41 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__11 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__22 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__21 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__48 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__47 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__46 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__45 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler__12 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__24 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv__23 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_scrambler_21bit__34 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__35 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit__36 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler_21bit Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 21 +---Registers : 21 Bit Registers := 1 +---Muxes : 2 Input 21 Bit Muxes := 2 Module gbt_tx_scrambler Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 Module gbt_tx_encoder_gbtframe_polydiv__18 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module gbt_tx_encoder_gbtframe_polydiv Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 44 2 Input 1 Bit XORs := 260 4 Input 1 Bit XORs := 34 5 Input 1 Bit XORs := 92 6 Input 1 Bit XORs := 6 Module xpm_cdc_single__47 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__9 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__46 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__10 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__45 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox__xdcDup__11 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__44 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module gbt_tx_gearbox Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 120 Bit Registers := 1 20 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__10 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__11 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox__12 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_rx_gearbox Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 100 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 100 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module gbt_bank_reset__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module gbt_bank_reset Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 Module xlx_k7v7_gbt_ngFEC_design__parameterized4 Detailed RTL Component Info : +---Registers : 6 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 4 Module buffer_ngccm_jtag_com Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 3 2 Input 17 Bit Adders := 1 2 Input 12 Bit Adders := 2 2 Input 11 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 3 11 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 20 3 Input 32 Bit Muxes := 3 4 Input 32 Bit Muxes := 1 7 Input 32 Bit Muxes := 6 2 Input 31 Bit Muxes := 1 2 Input 12 Bit Muxes := 9 7 Input 12 Bit Muxes := 2 2 Input 11 Bit Muxes := 1 7 Input 11 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 12 7 Input 1 Bit Muxes := 13 Module buffer_ngccm_com__1 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__2 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__3 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__4 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__5 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__6 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__7 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module Module_RAM__1 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__2 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__3 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__4 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__5 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__6 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized23 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__7 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized25 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__8 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized27 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module buffer_server_com__parameterized21 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__9 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized19 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__10 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__11 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_ngccm_com__8 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__9 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__10 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_server_com__parameterized17 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__12 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized15 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__13 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized13 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM__14 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_server_com__parameterized11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module Module_RAM Detailed RTL Component Info : +---Registers : 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 2 Module buffer_ngccm_com__11 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__12 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com__13 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module buffer_ngccm_com Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 12 Bit Adders := 1 +---Registers : 32 Bit Registers := 8 12 Bit Registers := 2 8 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 5 Input 32 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 7 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 15 2 Input 3 Bit Muxes := 28 5 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 11 2 Input 1 Bit Muxes := 26 5 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 4 Module ngFEC_module Detailed RTL Component Info : +---Registers : 32 Bit Registers := 30 1 Bit Registers := 15 +---Muxes : 2 Input 32 Bit Muxes := 60 2 Input 19 Bit Muxes := 1 14 Input 18 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 4 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 30 Module Sync__42 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__43 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__44 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__22 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__22 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__22 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__22 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__22 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__415 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__10 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__10 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__274 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__273 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__142 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__142 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__142 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__142 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__276 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__275 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__143 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__143 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__143 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__143 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__278 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__277 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__144 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__144 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__144 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__144 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__280 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__279 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__145 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__145 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__145 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__145 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__282 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__281 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__146 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__146 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__146 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__146 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__284 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__283 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__147 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__147 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__147 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__147 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__286 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__285 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__148 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__148 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__148 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__148 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__288 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__287 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__149 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__149 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__149 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__149 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__290 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__289 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__150 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__150 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__150 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__150 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__292 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__291 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__151 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__151 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__151 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__151 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__294 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__293 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__152 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__152 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__152 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__152 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__296 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__295 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__153 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__153 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__153 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__153 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__272 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__297 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__154 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__154 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__154 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__154 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__414 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__136 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__413 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__137 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__412 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__138 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__411 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__139 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__410 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__140 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__409 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__141 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__408 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__142 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__407 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__143 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__406 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__144 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__405 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__145 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__404 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__146 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__403 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__147 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__402 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__148 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__401 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__149 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__400 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__150 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__10 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__39 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__40 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__41 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__21 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__21 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__21 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__21 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__21 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__399 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__11 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__11 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__248 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__247 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__129 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__129 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__129 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__129 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__250 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__249 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__130 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__130 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__130 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__130 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__252 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__251 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__131 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__131 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__131 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__131 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__254 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__253 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__132 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__132 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__132 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__132 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__256 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__255 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__133 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__133 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__133 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__133 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__258 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__257 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__134 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__134 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__134 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__134 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__260 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__259 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__135 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__135 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__135 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__135 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__262 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__261 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__136 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__136 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__136 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__136 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__264 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__263 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__137 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__137 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__137 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__137 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__266 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__265 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__138 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__138 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__138 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__138 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__268 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__267 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__139 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__139 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__139 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__139 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__270 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__269 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__140 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__140 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__140 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__140 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__246 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__271 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__141 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__141 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__141 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__141 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__398 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__151 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__397 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__152 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__396 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__153 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__395 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__154 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__394 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__155 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__393 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__156 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__392 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__157 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__391 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__158 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__390 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__159 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__389 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__160 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__388 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__161 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__387 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__162 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__386 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__163 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__385 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__164 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__384 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__165 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__11 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__36 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__37 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__38 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__20 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__20 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__20 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__20 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__20 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__383 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__222 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__221 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__116 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__116 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__116 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__116 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__224 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__223 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__117 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__117 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__117 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__117 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__226 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__225 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__118 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__118 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__118 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__118 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__228 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__227 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__119 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__119 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__119 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__119 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__230 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__229 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__120 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__120 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__120 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__120 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__232 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__231 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__121 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__121 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__121 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__121 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__234 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__233 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__122 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__122 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__122 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__122 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__236 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__235 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__123 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__123 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__123 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__123 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__238 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__237 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__124 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__124 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__124 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__124 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__240 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__239 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__125 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__125 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__125 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__125 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__242 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__241 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__126 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__126 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__126 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__126 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__244 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__243 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__127 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__127 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__127 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__127 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__220 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__245 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__128 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__128 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__128 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__128 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__382 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__166 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__381 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__167 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__380 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__168 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__379 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__169 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__378 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__170 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__377 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__171 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__376 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__172 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__375 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__173 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__374 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__174 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__373 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__175 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__372 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__176 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__371 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__177 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__370 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__178 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__369 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__179 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__368 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module cdce_synchronizer Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 +---Registers : 20 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 20 Bit Muxes := 1 4 Input 20 Bit Muxes := 1 2 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 5 Module ipb_user_status_regs Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipb_user_control_regs Detailed RTL Component Info : +---Registers : 32 Bit Registers := 33 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 32 Module ttc_counter Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 9 3 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module clkRateTool32__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__12 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__13 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32__14 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module clkRateTool32 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 12 Module global_mux__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__15 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__14 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__13 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__12 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__11 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__10 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__9 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__8 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module global_mux Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__3 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__4 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__5 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__6 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux__7 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module sfp_signal_mux Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module delay_counter__1 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__2 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__3 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__4 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__5 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__6 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__7 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__8 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__9 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__10 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter__11 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module delay_counter Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__70 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__68 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__69 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__2 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__66 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__67 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__3 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__64 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__65 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__4 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__62 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__63 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__5 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__60 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__61 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__6 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__58 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__59 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__7 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__56 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__57 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__8 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__54 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__55 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__9 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__52 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__53 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__10 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__50 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__51 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm__xdcDup__11 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__48 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module xpm_cdc_single__49 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module pm Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 10 Bit Registers := 2 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module xpm_cdc_single__parameterized1__216 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__217 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__218 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__219 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__220 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__221 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__222 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__223 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__224 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__225 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__226 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__227 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__228 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__229 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__230 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__231 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__232 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__233 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__234 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__235 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__236 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__237 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__238 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_single__parameterized1__239 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module Sync__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__14 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__12 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__12 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__12 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__12 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__12 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__255 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__8 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__8 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__14 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__13 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__12 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__12 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__12 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__16 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__15 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__13 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__13 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__13 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__18 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__17 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__14 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__14 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__14 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__14 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__20 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__19 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__15 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__15 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__15 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__15 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__22 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__21 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__16 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__16 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__16 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__16 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__24 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__23 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__17 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__17 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__17 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__17 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__26 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__25 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__18 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__18 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__18 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__18 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__28 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__27 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__19 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__19 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__19 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__19 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__30 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__29 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__20 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__20 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__20 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__20 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__32 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__31 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__21 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__21 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__21 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__21 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__34 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__33 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__22 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__22 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__22 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__22 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__36 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__35 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__23 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__23 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__23 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__23 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__12 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__37 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__24 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__24 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__24 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__24 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__254 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__106 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__253 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__107 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__252 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__108 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__251 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__109 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__250 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__110 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__249 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__111 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__248 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__112 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__247 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__113 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__246 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__114 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__245 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__115 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__244 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__116 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__243 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__117 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__242 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__118 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__241 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__119 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__240 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__120 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__8 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__15 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__16 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__17 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__13 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__13 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__13 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__13 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__13 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__271 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__7 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__7 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__40 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__39 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__25 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__25 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__25 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__25 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__42 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__41 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__26 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__26 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__26 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__26 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__44 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__43 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__27 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__27 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__27 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__27 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__46 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__45 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__28 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__28 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__28 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__28 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__48 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__47 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__29 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__29 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__29 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__29 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__50 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__49 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__30 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__30 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__30 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__30 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__52 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__51 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__31 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__31 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__31 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__31 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__54 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__53 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__32 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__32 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__32 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__32 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__56 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__55 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__33 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__33 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__33 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__33 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__58 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__57 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__34 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__34 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__34 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__34 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__60 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__59 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__35 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__35 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__35 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__35 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__62 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__61 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__36 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__36 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__36 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__36 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__38 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__63 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__37 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__37 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__37 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__37 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__270 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__91 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__269 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__92 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__268 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__93 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__267 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__94 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__266 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__95 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__265 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__96 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__264 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__97 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__263 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__98 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__262 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__99 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__261 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__100 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__260 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__101 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__259 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__102 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__258 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__103 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__257 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__104 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__256 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__105 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__7 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__18 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__19 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__20 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__14 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__14 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__14 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__14 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__14 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__287 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__6 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__6 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__66 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__65 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__38 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__38 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__38 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__38 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__68 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__67 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__39 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__39 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__39 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__39 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__70 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__69 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__40 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__40 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__40 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__40 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__72 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__71 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__41 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__41 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__41 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__41 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__74 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__73 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__42 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__42 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__42 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__42 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__76 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__75 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__43 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__43 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__43 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__43 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__78 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__77 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__44 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__44 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__44 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__44 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__80 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__79 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__45 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__45 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__45 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__45 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__82 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__81 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__46 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__46 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__46 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__46 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__84 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__83 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__47 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__47 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__47 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__47 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__86 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__85 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__48 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__48 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__48 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__48 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__88 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__87 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__49 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__49 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__49 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__49 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__64 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__89 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__50 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__50 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__50 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__50 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__286 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__76 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__285 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__77 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__284 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__78 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__283 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__79 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__282 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__80 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__281 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__81 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__280 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__82 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__279 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__83 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__278 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__84 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__277 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__85 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__276 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__86 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__275 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__87 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__274 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__88 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__273 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__89 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__272 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__90 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__6 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__21 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__22 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__23 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__15 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__15 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__15 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__15 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__15 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__303 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__5 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__5 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__92 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__91 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__51 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__51 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__51 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__51 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__94 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__93 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__52 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__52 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__52 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__52 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__96 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__95 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__53 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__53 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__53 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__53 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__98 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__97 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__54 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__54 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__54 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__54 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__100 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__99 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__55 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__55 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__55 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__55 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__102 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__101 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__56 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__56 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__56 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__56 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__104 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__103 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__57 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__57 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__57 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__57 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__106 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__105 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__58 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__58 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__58 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__58 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__108 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__107 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__59 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__59 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__59 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__59 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__110 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__109 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__60 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__60 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__60 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__60 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__112 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__111 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__61 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__61 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__61 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__61 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__114 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__113 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__62 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__62 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__62 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__62 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__90 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__115 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__63 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__63 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__63 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__63 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__302 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__61 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__301 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__62 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__300 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__63 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__299 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__64 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__298 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__65 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__297 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__66 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__296 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__67 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__295 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__68 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__294 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__69 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__293 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__70 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__292 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__71 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__291 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__72 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__290 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__73 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__289 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__74 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__288 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__75 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__5 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module gc_sync_ffs__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__40 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_pulse_synchronizer__1 Detailed RTL Component Info : +---Registers : 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 2 Input 1 Bit Muxes := 2 Module gc_sync_ffs__39 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__38 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_extend_pulse__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module dmtd_with_deglitcher__1 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 2 Input 14 Bit Adders := 1 +---Registers : 16 Bit Registers := 1 14 Bit Registers := 2 6 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 16 Bit Muxes := 3 3 Input 16 Bit Muxes := 1 3 Input 14 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 5 Module gc_sync_ffs__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_pulse_synchronizer Detailed RTL Component Info : +---Registers : 3 Bit Registers := 2 1 Bit Registers := 5 +---Muxes : 2 Input 1 Bit Muxes := 2 Module gc_sync_ffs__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_extend_pulse Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module dmtd_with_deglitcher Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 2 Input 14 Bit Adders := 1 +---Registers : 16 Bit Registers := 1 14 Bit Registers := 2 6 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 16 Bit Muxes := 3 3 Input 16 Bit Muxes := 1 3 Input 14 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 5 Module gc_sync_ffs__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__14 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__15 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__16 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__17 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__18 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__19 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__20 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__21 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__22 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__23 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__24 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__25 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__26 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__27 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__28 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__29 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__30 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__31 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__32 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__33 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__34 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__35 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__36 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs__37 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module gc_sync_ffs Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module dmtd_phase_meas Detailed RTL Component Info : +---Adders : 3 Input 14 Bit Adders := 1 +---Registers : 32 Bit Registers := 4 14 Bit Registers := 3 8 Bit Registers := 1 1 Bit Registers := 8 +---Muxes : 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 2 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 5 Module clk_divide3 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---Registers : 2 Bit Registers := 2 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 Module Sync__24 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__25 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__26 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__16 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__16 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__16 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__16 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__16 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__319 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__4 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__4 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__118 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__117 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__64 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__64 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__64 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__64 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__120 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__119 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__65 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__65 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__65 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__65 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__122 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__121 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__66 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__66 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__66 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__66 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__124 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__123 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__67 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__67 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__67 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__67 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__126 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__125 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__68 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__68 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__68 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__68 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__128 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__127 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__69 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__69 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__69 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__69 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__130 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__129 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__70 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__70 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__70 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__70 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__132 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__131 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__71 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__71 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__71 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__71 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__134 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__133 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__72 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__72 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__72 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__72 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__136 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__135 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__73 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__73 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__73 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__73 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__138 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__137 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__74 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__74 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__74 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__74 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__140 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__139 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__75 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__75 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__75 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__75 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__116 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__141 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__76 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__76 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__76 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__76 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__318 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__46 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__317 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__47 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__316 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__48 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__315 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__49 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__314 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__50 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__313 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__51 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__312 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__52 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__311 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__53 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__310 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__54 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__309 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__55 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__308 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__56 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__307 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__57 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__306 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__58 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__305 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__59 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__304 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__60 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__4 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__27 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__28 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__29 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__17 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__17 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__17 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__17 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__17 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__335 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__3 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__3 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__144 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__143 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__77 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__77 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__77 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__77 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__146 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__145 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__78 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__78 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__78 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__78 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__148 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__147 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__79 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__79 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__79 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__79 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__150 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__149 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__80 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__80 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__80 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__80 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__152 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__151 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__81 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__81 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__81 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__81 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__154 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__153 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__82 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__82 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__82 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__82 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__156 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__155 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__83 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__83 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__83 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__83 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__158 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__157 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__84 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__84 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__84 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__84 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__160 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__159 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__85 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__85 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__85 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__85 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__162 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__161 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__86 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__86 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__86 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__86 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__164 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__163 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__87 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__87 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__87 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__87 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__166 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__165 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__88 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__88 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__88 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__88 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__142 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__167 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__89 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__89 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__89 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__89 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__334 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__31 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__333 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__32 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__332 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__33 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__331 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__34 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__330 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__35 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__329 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__36 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__328 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__37 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__327 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__38 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__326 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__39 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__325 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__40 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__324 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__41 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__323 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__42 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__322 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__43 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__321 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__44 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__320 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__45 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__3 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__30 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__31 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__32 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__18 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__18 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__18 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__18 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__18 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__351 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__2 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__2 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__170 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__169 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__90 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__90 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__90 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__90 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__172 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__171 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__91 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__91 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__91 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__91 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__174 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__173 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__92 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__92 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__92 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__92 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__176 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__175 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__93 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__93 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__93 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__93 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__178 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__177 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__94 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__94 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__94 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__94 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__180 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__179 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__95 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__95 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__95 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__95 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__182 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__181 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__96 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__96 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__96 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__96 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__184 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__183 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__97 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__97 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__97 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__97 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__186 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__185 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__98 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__98 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__98 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__98 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__188 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__187 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__99 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__99 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__99 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__99 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__190 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__189 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__100 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__100 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__100 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__100 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__192 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__191 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__101 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__101 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__101 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__101 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__168 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__193 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__102 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__102 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__102 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__102 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__350 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__16 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__349 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__17 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__348 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__18 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__347 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__19 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__346 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__20 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__345 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__21 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__344 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__22 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__343 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__23 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__342 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__24 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__341 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__25 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__340 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__26 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__339 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__27 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__338 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__28 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__337 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__29 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__336 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__30 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__2 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__33 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__34 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__35 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs__19 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker__19 Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter__19 Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX__19 Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM__19 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1__367 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__196 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__195 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__103 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__103 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__103 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__103 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__198 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__197 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__104 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__104 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__104 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__104 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__200 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__199 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__105 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__105 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__105 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__105 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__202 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__201 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__106 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__106 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__106 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__106 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__204 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__203 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__107 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__107 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__107 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__107 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__206 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__205 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__108 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__108 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__108 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__108 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__208 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__207 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__109 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__109 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__109 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__109 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__210 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__209 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__110 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__110 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__110 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__110 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__212 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__211 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__111 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__111 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__111 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__111 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__214 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__213 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__112 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__112 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__112 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__112 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__216 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__215 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__113 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__113 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__113 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__113 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__218 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__217 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__114 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__114 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__114 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__114 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__194 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__219 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__115 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__115 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__115 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__115 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__366 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__365 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__2 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__364 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__3 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__363 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__4 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__362 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__5 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__361 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__6 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__360 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__7 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__359 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__8 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__358 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__9 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__357 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__10 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__356 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__11 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__355 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__12 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__354 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__13 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__353 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__14 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__352 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__15 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module Sync__45 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync__46 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module Sync Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module prbs Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 Module gbt_rx_checker Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 2 Input 19 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 1 2 Input 14 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 1 2 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 20 Bit Registers := 1 +---Muxes : 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module Agnostic_Counter Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 +---Muxes : 2 Input 26 Bit Muxes := 1 Module CrossClock_RX Detailed RTL Component Info : +---Registers : 84 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 Module RAM Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module xpm_cdc_single__parameterized1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module JTAGMaster__xdcDup__9 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 2 2 Input 15 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 2 15 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 14 +---Muxes : 2 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 4 Input 16 Bit Muxes := 1 7 Input 16 Bit Muxes := 1 4 Input 15 Bit Muxes := 1 2 Input 10 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 15 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 7 7 Input 1 Bit Muxes := 12 Module LocalJTAGBridge__xdcDup__9 Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module glitch_filter__300 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__299 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__155 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__155 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__155 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__155 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__302 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__301 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__156 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__156 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__156 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__156 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__304 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__303 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__157 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__157 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__157 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__157 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__306 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__305 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__158 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__158 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__158 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__158 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__308 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__307 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__159 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__159 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__159 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__159 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__310 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__309 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__160 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__160 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__160 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__160 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__312 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__311 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__161 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__161 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__161 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__161 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__314 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__313 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__162 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__162 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__162 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__162 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__316 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__315 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__163 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__163 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__163 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__163 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__318 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__317 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__164 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__164 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__164 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__164 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__320 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__319 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__165 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__165 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__165 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__165 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__322 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter__321 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl__166 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl__166 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr__166 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge__166 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module glitch_filter__298 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module glitch_filter Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 4 Module i2c_master_bit_ctrl Detailed RTL Component Info : +---Registers : 1 Bit Registers := 15 +---Muxes : 32 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 3 Input 1 Bit Muxes := 1 26 Input 1 Bit Muxes := 7 Module i2c_master_byte_ctrl Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 15 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 6 Module i2c_master_usr Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 6 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 2 Input 1 Bit Muxes := 2 Module LocalI2CBridge Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 2 Module xpm_cdc_single__parameterized1__430 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__121 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__429 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__122 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__428 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__123 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__427 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__124 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__426 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__125 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__425 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__126 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__424 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__127 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__423 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__128 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__422 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__129 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__421 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__130 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__420 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__131 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__419 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__132 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__418 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__133 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__417 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__134 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module xpm_cdc_single__parameterized1__416 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module IPbus_local__xdcDup__135 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module ngCCM__xdcDup__9 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 8 +---Registers : 84 Bit Registers := 3 32 Bit Registers := 15 20 Bit Registers := 1 12 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 2 Input 84 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 16 Bit Muxes := 21 2 Input 1 Bit Muxes := 25 Module ngFEC_logic Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 51 2 Input 10 Bit Adders := 1 2 Input 8 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 84 Bit Registers := 12 32 Bit Registers := 49 16 Bit Registers := 2 10 Bit Registers := 1 8 Bit Registers := 1 4 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 42 +---Muxes : 2 Input 16 Bit Muxes := 36 2 Input 10 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 1680 (col length:160) BRAMs: 1670 (col length: RAMB18 160 RAMB36 80) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[2] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[3] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[4] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_master_xpoint_ctrl[5] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port k7_pcie_clk_ctrl[2] driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port k7_pcie_clk_ctrl[3] driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_pwr_en driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_pwr_en driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_pg_c2m driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port sysled1_g driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_spare[6] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_spare[7] driven by constant 1 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_spare[8] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_la_p[15] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_la_p[8] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_la_n[11] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l8_la_n[4] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_p[31] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_p[24] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_p[15] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_p[8] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_n[27] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_n[20] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_n[11] driven by constant 0 WARNING: [Synth 8-3917] design fc7_top has port fmc_l12_la_n[4] driven by constant 0 INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_25_reg[0]' (FDE) to 'sys/i2c_m/core/u1/presc_50_reg[1]' INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_25_reg[1]' (FDE) to 'sys/i2c_m/core/u1/presc_50_reg[2]' INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_25_reg[2]' (FDE) to 'sys/i2c_m/core/u1/presc_50_reg[3]' INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_50_reg[4]' (FDE) to 'sys/i2c_m/core/u1/presc_25_reg[3]' INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_50_reg[5]' (FDE) to 'sys/i2c_m/core/u1/presc_25_reg[4]' INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_50_reg[6]' (FDE) to 'sys/i2c_m/core/u1/presc_25_reg[5]' INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_50_reg[7]' (FDE) to 'sys/i2c_m/core/u1/presc_25_reg[6]' INFO: [Synth 8-3886] merging instance 'sys/i2c_m/core/u1/presc_50_reg[8]' (FDE) to 'sys/i2c_m/core/u1/presc_25_reg[7]' INFO: [Synth 8-5545] ROM "mac/i_mac/i_rx_CRC32D8/bad_crc" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "send_special_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "send_special_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5545] ROM "clocks/timer" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "clocks/rst" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "p_0_out" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[0]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[1]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[2]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[3]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[4]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[5]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[6]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/data_buffer_reg[7]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/we_buffer_reg[0]' (FDR) to 'ipb/udp_if/RARP_block/rarp_end_addr_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__3' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__3' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__3' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__3' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__6' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__4' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__4' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__6' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__1' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__2' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[0]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__6' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__1' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__2' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[1]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__6' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__1' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[2]__2' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__6' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__0' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__1' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[3]__2' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__1' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__2' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__1' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__2' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]__1' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__1' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[4]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]__1' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[5]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]__1' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[6]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]__1' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]__0' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]__1' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[8]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[9]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[10]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_mask_reg[11]__3' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[0]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[1]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[1]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[2]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[2]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[3]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[3]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[24]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[4]' (FDSE) to 'ipb/udp_if/status_buffer/header_reg[5]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[5]' (FDSE) to 'ipb/udp_if/status_buffer/header_reg[6]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[6]' (FDSE) to 'ipb/udp_if/status_buffer/header_reg[7]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[7]' (FDSE) to 'ipb/udp_if/status_buffer/header_reg[29]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[8]' (FDSE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[0]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[9]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[1]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[10]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[2]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[11]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[3]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[12]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[4]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[13]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[5]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[14]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[6]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[15]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[7]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[16]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[8]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[17]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[9]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[18]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[10]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[19]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[11]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[20]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[12]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[21]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[13]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[22]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[14]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[23]' (FDRE) to 'ipb/udp_if/status_buffer/next_pkt_id_int_reg[15]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[24]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[25]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[25]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[26]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[26]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[27]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[27]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[28]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[28]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[30]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/status_buffer/header_reg[30]' (FDRE) to 'ipb/udp_if/status_buffer/header_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[32] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[33] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[34] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[35] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[36] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[37] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[38] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[39] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[40] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[41] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[42] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[43] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[44] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[45] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[46] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[47] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[48] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[49] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[50] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[51] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[52] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[53] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[54] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[55] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[56] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[57] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[58] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[59] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[60] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[61] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[62] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[63] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[64] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[65] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[66] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[67] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[68] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[69] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[70] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[71] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[72] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[73] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[74] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[75] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[76] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[77] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[78] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[79] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[80] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[81] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[82] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[83] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[84] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[85] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[86] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[87] ) INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[6]__5' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[0]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[7]__5' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[0]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[0]__5' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[4]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[1]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[2]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[2]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[3]__5' INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/rx_packet_parser/\pkt_data_reg[3]__5 ) INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[4]__5' (FDSE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[5]__5' INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[88] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[89] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[90] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[91] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[92] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[93] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[94] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[95] ) INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[14]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[8]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[15]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[8]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[8]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[12]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[9]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[10]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[10]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[11]__5' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/rx_packet_parser/pkt_data_reg[12]__5' (FDRE) to 'ipb/udp_if/rx_packet_parser/pkt_data_reg[13]__5' INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[96] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[97] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[98] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[99] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[100] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[101] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[102] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/status_buffer/\header_reg[103] ) INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/y_reg[0]' (FD) to 'ipb/udp_if/RARP_block/rndm_reg[0]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/y_reg[1]' (FD) to 'ipb/udp_if/RARP_block/rndm_reg[1]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/y_reg[2]' (FD) to 'ipb/udp_if/RARP_block/rndm_reg[2]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/y_reg[3]' (FD) to 'ipb/udp_if/RARP_block/rndm_reg[3]' INFO: [Synth 8-3886] merging instance 'ipb/udp_if/RARP_block/y_reg[4]' (FD) to 'ipb/udp_if/RARP_block/rndm_reg[4]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/rx_packet_parser/\pkt_data_reg[3]__4 ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[104] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[105] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[106] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[107] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[108] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[109] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[110] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[111] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[112] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[113] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[114] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[115] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[116] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[117] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[118] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[119] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (ipb/udp_if/RARP_block/\req_end_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/rx_packet_parser/\pkt_data_reg[5]__2 ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/ARP/\arp_end_addr_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/RARP_block/\rarp_end_addr_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[120] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[121] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[122] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[123] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (ipb/udp_if/status_buffer/\header_reg[124] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[3]) is unused and will be removed from module cdce_synchronizer. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__8. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__8. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__8. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__7. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__7. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__7. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__6. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__6. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__6. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__5. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__5. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__5. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__4. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__4. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__4. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__3. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__3. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__3. INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__2. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__2. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__2. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__1. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__1. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__1. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[31] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[30] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[29] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[28] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[27] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[10] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[9] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM has port ngccm_bkp_regs[8] driven by constant 0 INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[31] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[30] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[29] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[28] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[27] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[10] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[9] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__11 has port ngccm_bkp_regs[8] driven by constant 0 INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__11. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__11. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__11. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[31] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[30] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[29] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[28] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[27] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[10] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[9] driven by constant 0 WARNING: [Synth 8-3917] design ngCCM__xdcDup__10 has port ngccm_bkp_regs[8] driven by constant 0 INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__10. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__10. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__10. INFO: [Synth 8-5545] ROM "SleepCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) WARNING: [Synth 8-3936] Found unconnected internal register 'CrossClock_DV_cnt/DataAtoB_reg_reg' and it is trimmed from '84' to '77' bits. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/ngFEC/ngCCM_gbt_com/ngCCM/util/CrossClock_RX.v:102] INFO: [Synth 8-5545] ROM "jtag_trst_o" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM JTAGMaster_inst/JTAG_BRAM/memory_reg to conserve power WARNING: [Synth 8-3332] Sequential element (jtag_bridge_tms_i_reg) is unused and will be removed from module ngCCM__xdcDup__9. WARNING: [Synth 8-3332] Sequential element (jtag_bridge_trst_i_reg) is unused and will be removed from module ngCCM__xdcDup__9. WARNING: [Synth 8-3332] Sequential element (ngccmPinsOutReg_reg[sec_sel_addr][3]) is unused and will be removed from module ngCCM__xdcDup__9. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:05:28 ; elapsed = 00:05:32 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: +------------+---------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------+---------------+----------------+ |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | |JTAGMaster | stateTrans[0] | 32x4 | LUT | +------------+---------------+---------------+----------------+ Block RAM: Preliminary Mapping Report (see note below) +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |udp_DualPortRAM: | ram_reg | 4 K x 8(NO_CHANGE) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |udp_DualPortRAM_rx: | ram1_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_rx: | ram2_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_rx: | ram3_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_rx: | ram4_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_tx: | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/i_0/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_1/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_1/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_2/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_2/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_3/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_3/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_4/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_rx_rami_4/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/ipb/udp_if/ipbus_tx_ram/i_0/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_50/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_51/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_52/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_53/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_54/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_55/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_56/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_57/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_58/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/i_0/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. Report RTL Partitions: +------+-----------------------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------------------+------------+----------+ |1 |i2c_master_core | 1| 943| |2 |system_core__GC0 | 1| 18862| |3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| |4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| |5 |TTC_decoder__GC0 | 1| 342| |6 |gbt_rx | 12| 4084| |7 |gbt_bank__xdcDup__1__GC0 | 1| 8304| |8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 309| |9 |gbt_bank__parameterized0__GC0 | 1| 5536| |10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 206| |11 |gbt_bank__GC0 | 1| 8304| |12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 309| |13 |gbt_bank__parameterized1__GC0 | 1| 11072| |14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 412| |15 |ngFEC_module__GBM0 | 12| 17290| |16 |ngFEC_module__GBM1 | 12| 6039| |17 |ngFEC_module__GBM2 | 12| 8082| |18 |ngFEC_logic__GCB0 | 1| 18733| |19 |ngFEC_logic__GCB1 | 1| 14322| |20 |ngFEC_logic__GCB2 | 1| 14320| |21 |ngFEC_logic__GCB3 | 1| 14320| |22 |ngFEC_logic__GCB4 | 1| 15442| |23 |ngFEC_logic__GCB5 | 1| 14320| |24 |ngFEC_logic__GCB6 | 1| 14320| |25 |ngFEC_logic__GCB7 | 1| 14320| |26 |ngFEC_logic__GCB8 | 1| 14320| |27 |ngCCM | 1| 14578| |28 |ngCCM__xdcDup__11 | 1| 14578| |29 |ngCCM__xdcDup__10 | 1| 14578| |30 |ngFEC_logic__GCB12 | 1| 14320| |31 |ngFEC_logic__GCB13 | 1| 170| |32 |fc7_top__GC0 | 1| 3| +------+-----------------------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_rxoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_rxoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_txoutclk_out' to pin '{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclk_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/gt0_txoutclkfabric_out' to pin '{mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/bbstub_gt0_txoutclkfabric_out/O}' INFO: [Synth 8-5578] Moved timing constraint from pin 'eth/phy/rxoutclk' to pin 'eth/phy/bbstub_rxoutclk/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'eth/phy/txoutclk' to pin 'eth/phy/bbstub_txoutclk/O' INFO: [Synth 8-5819] Moved 18 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:05:46 ; elapsed = 00:05:51 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[31]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[31]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[30]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[30]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[23]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[23]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[21]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[21]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[19]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[19]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[6]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[6]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[4]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (ip_addr_reg[4]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[47]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[47]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[45]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[45]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[43]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[43]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[41]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[41]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[39]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[39]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[37]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[37]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[36]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[36]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[35]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[35]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[33]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[33]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[32]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[32]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[31]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[31]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[30]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[30]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[27]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[27]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[26]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[26]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[23]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[23]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[22]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[22]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[20]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[20]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[19]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[19]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[18]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[18]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[16]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[16]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[15]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[15]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[14]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[14]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[13]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[13]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[11]_LDC) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[11]_C) is unused and will be removed from module ip_mac_select. WARNING: [Synth 8-3332] Sequential element (mac_addr_reg[10]_LDC) is unused and will be removed from module ip_mac_select. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:06:40 ; elapsed = 00:06:46 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |udp_DualPortRAM: | ram_reg | 4 K x 8(NO_CHANGE) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |udp_DualPortRAM_rx: | ram1_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_rx: | ram2_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_rx: | ram3_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_rx: | ram4_reg | 8 K x 8(WRITE_FIRST) | | R | 8 K x 8(NO_CHANGE) | W | | Port A and B | 0 | 2 | |udp_DualPortRAM_tx: | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |RAM: | memory_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +--------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------------------+------------+----------+ |1 |i2c_master_core | 1| 943| |2 |system_core__GC0 | 1| 18301| |3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| |4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| |5 |TTC_decoder__GC0 | 1| 340| |6 |gbt_rx | 12| 3889| |7 |gbt_bank__xdcDup__1__GC0 | 1| 8025| |8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 309| |9 |gbt_bank__parameterized0__GC0 | 1| 5350| |10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 206| |11 |gbt_bank__GC0 | 1| 8025| |12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 309| |13 |gbt_bank__parameterized1__GC0 | 1| 10700| |14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 412| |15 |ngFEC_module__GBM0 | 12| 17274| |16 |ngFEC_module__GBM1 | 12| 6039| |17 |ngFEC_module__GBM2 | 12| 8082| |18 |ngFEC_logic__GCB0 | 1| 18175| |19 |ngFEC_logic__GCB1 | 1| 14323| |20 |ngFEC_logic__GCB2 | 1| 14321| |21 |ngFEC_logic__GCB3 | 1| 14321| |22 |ngFEC_logic__GCB4 | 1| 15443| |23 |ngFEC_logic__GCB5 | 1| 14321| |24 |ngFEC_logic__GCB6 | 1| 14321| |25 |ngFEC_logic__GCB7 | 1| 14321| |26 |ngFEC_logic__GCB8 | 1| 14321| |27 |ngCCM | 1| 14219| |28 |ngCCM__xdcDup__11 | 1| 14219| |29 |ngCCM__xdcDup__10 | 1| 14219| |30 |ngFEC_logic__GCB12 | 1| 14321| |31 |ngFEC_logic__GCB13 | 1| 170| |32 |fc7_top__GC0 | 1| 3| +------+-----------------------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sysi_1/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_50/ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_51/ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_52/ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_53/ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_54/ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_55/ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_56/ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_57/ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFECi_58/ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:07:47 ; elapsed = 00:07:53 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------------------+------------+----------+ |1 |i2c_master_core | 1| 517| |2 |system_core__GC0 | 1| 10041| |3 |phase_mon_mmcm_1_clk_wiz__GC0 | 1| 2| |4 |phase_mon_mmcm_2_clk_wiz__GC0 | 1| 3| |5 |TTC_decoder__GC0 | 1| 156| |6 |gbt_rx | 1| 1502| |7 |gbt_bank__xdcDup__1__GC0 | 1| 3912| |8 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1__GC0 | 1| 252| |9 |gbt_bank__parameterized0__GC0 | 1| 2608| |10 |xlx_k7v7_gbt_ngFEC_design__parameterized1__GC0 | 1| 168| |11 |gbt_bank__GC0 | 1| 3912| |12 |xlx_k7v7_gbt_ngFEC_design__GC0 | 1| 252| |13 |gbt_bank__parameterized1__GC0 | 1| 5216| |14 |xlx_k7v7_gbt_ngFEC_design__parameterized4__GC0 | 1| 336| |15 |ngFEC_module__GBM0 | 12| 9330| |16 |ngFEC_module__GBM1 | 1| 3413| |17 |ngFEC_module__GBM2 | 1| 4537| |18 |ngFEC_logic__GCB0 | 1| 10566| |19 |ngFEC_logic__GCB1 | 1| 7930| |20 |ngFEC_logic__GCB2 | 1| 7929| |21 |ngFEC_logic__GCB3 | 1| 7929| |22 |ngFEC_logic__GCB4 | 1| 8695| |23 |ngFEC_logic__GCB5 | 1| 7929| |24 |ngFEC_logic__GCB6 | 1| 7929| |25 |ngFEC_logic__GCB7 | 1| 7929| |26 |ngFEC_logic__GCB8 | 1| 7929| |27 |ngCCM | 1| 7846| |28 |ngCCM__xdcDup__11 | 1| 7846| |29 |ngCCM__xdcDup__10 | 1| 7846| |30 |ngFEC_logic__GCB12 | 1| 7929| |31 |ngFEC_logic__GCB13 | 1| 170| |32 |fc7_top__GC0 | 1| 3| |33 |gbt_rx__4 | 1| 1502| |34 |gbt_rx__5 | 1| 1502| |35 |gbt_rx__6 | 1| 1502| |36 |gbt_rx__7 | 1| 1502| |37 |gbt_rx__8 | 1| 1502| |38 |gbt_rx__9 | 1| 1502| |39 |gbt_rx__10 | 1| 1502| |40 |gbt_rx__11 | 1| 1502| |41 |gbt_rx__12 | 1| 1502| |42 |gbt_rx__13 | 1| 1502| |43 |gbt_rx__14 | 1| 1502| |44 |ngFEC_module__GBM1__1 | 1| 3413| |45 |ngFEC_module__GBM2__1 | 1| 4537| |46 |ngFEC_module__GBM1__2 | 1| 3413| |47 |ngFEC_module__GBM2__2 | 1| 4537| |48 |ngFEC_module__GBM1__3 | 1| 3413| |49 |ngFEC_module__GBM2__3 | 1| 4537| |50 |ngFEC_module__GBM1__4 | 1| 3413| |51 |ngFEC_module__GBM2__4 | 1| 4537| |52 |ngFEC_module__GBM1__5 | 1| 3413| |53 |ngFEC_module__GBM2__5 | 1| 4537| |54 |ngFEC_module__GBM1__6 | 1| 3413| |55 |ngFEC_module__GBM2__6 | 1| 4537| |56 |ngFEC_module__GBM1__7 | 1| 3413| |57 |ngFEC_module__GBM2__7 | 1| 4537| |58 |ngFEC_module__GBM1__8 | 1| 3413| |59 |ngFEC_module__GBM2__8 | 1| 4537| |60 |ngFEC_module__GBM1__9 | 1| 3413| |61 |ngFEC_module__GBM2__9 | 1| 4537| |62 |ngFEC_module__GBM1__10 | 1| 3413| |63 |ngFEC_module__GBM2__10 | 1| 4537| |64 |ngFEC_module__GBM1__11 | 1| 3413| |65 |ngFEC_module__GBM2__11 | 1| 4537| +------+-----------------------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance sys/ipb/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-6837] The timing for the instance ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[3].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[5].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[6].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[2].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[4].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[12].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[10].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[8].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[8].ngFEC_module/bkp_buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Synth 8-5365] Flop ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31] is being inverted and renamed to ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/sleep_cyc_reg[31]_inv. INFO: [Common 17-14] Message 'Synth 8-5365' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:83] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:83] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:83] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:83] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:83] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:83] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:173] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:168] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:180] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:122] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_if.vhd:77] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/transactor_sm.vhd:128] WARNING: [Synth 8-5396] Clock pin CLKBWRCLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:64] WARNING: [Synth 8-5396] Clock pin CLKBWRCLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:64] WARNING: [Synth 8-5396] Clock pin CLKBWRCLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:68] WARNING: [Synth 8-5396] Clock pin CLKBWRCLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/tmp/ipbus-firmware-master/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:68] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:55] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:135] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:135] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:135] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:56] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:133] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:147] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:136] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:69] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:67] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:254] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:259] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/cdce/spi/spi_master.vhd:269] INFO: [Common 17-14] Message 'Synth 8-5396' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-4560] design has 23 instantiated BUFGs while the limit set by the -bufg synthesis option is 12 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:08:42 ; elapsed = 00:08:52 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:08:45 ; elapsed = 00:08:55 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:52 ; elapsed = 00:10:02 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:09:55 ; elapsed = 00:10:04 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:10:02 ; elapsed = 00:10:12 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:10:04 ; elapsed = 00:10:13 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |fc7_top | ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 3 | NO | NO | YES | 3 | 0 | |fc7_top | ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 2 | NO | NO | YES | 2 | 0 | |fc7_top | ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 3 | NO | NO | YES | 3 | 0 | |fc7_top | ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4] | 4 | 4 | NO | NO | YES | 4 | 0 | |fc7_top | ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4] | 3 | 12 | NO | NO | YES | 12 | 0 | |fc7_top | ngFEC/clkRate0/counting_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |fc7_top | ngFEC/clkRate1/counting_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |fc7_top | ngFEC/clkRate2/counting_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |fc7_top | ngFEC/clk_rate_gen[1].clkRate3/counting_reg | 3 | 12 | NO | NO | YES | 12 | 0 | |fc7_top | ngFEC/update_toggle_Sync_Regs_reg[2] | 3 | 1 | NO | NO | YES | 1 | 0 | |fc7_top | sys/ipb/udp_if/IPADDR/pkt_mask_reg[41] | 22 | 1 | YES | NO | YES | 0 | 1 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[27] | 6 | 3 | YES | NO | YES | 3 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[17] | 4 | 2 | YES | NO | YES | 2 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[35] | 23 | 2 | YES | NO | YES | 0 | 2 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[41]__0 | 12 | 2 | YES | NO | YES | 2 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[15]__4 | 10 | 4 | YES | NO | YES | 4 | 0 | |fc7_top | sys/ipb/udp_if/resend/pkt_mask_reg[44] | 31 | 1 | YES | NO | YES | 0 | 1 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[19]__3 | 8 | 1 | YES | NO | YES | 1 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[79] | 6 | 6 | YES | NO | YES | 6 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[67] | 5 | 4 | YES | NO | YES | 4 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[111]__0 | 10 | 5 | YES | NO | YES | 5 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[90]__0 | 4 | 4 | YES | NO | YES | 4 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[119]__0 | 9 | 1 | YES | NO | YES | 1 | 0 | |fc7_top | sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[109]__1 | 8 | 2 | YES | NO | YES | 2 | 0 | +------------+------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------------------+----------+ | |BlackBox name |Instances | +------+--------------------------+----------+ |1 |ngFEC_mgt | 12| |2 |gig_ethernet_pcs_pma_16_1 | 1| |3 |sdpram_16x10_32x9 | 2| |4 |sdpram_32x9_16x10 | 2| +------+--------------------------+----------+ Report Cell Usage: +------+----------------------------------+------+ | |Cell |Count | +------+----------------------------------+------+ |1 |gig_ethernet_pcs_pma_16_1_bbox_10 | 1| |2 |ngFEC_mgt_bbox_15 | 1| |3 |ngFEC_mgt_bbox_15__2 | 1| |4 |ngFEC_mgt_bbox_16 | 1| |5 |ngFEC_mgt_bbox_16__2 | 1| |6 |ngFEC_mgt_bbox_17 | 1| |7 |ngFEC_mgt_bbox_17__2 | 1| |8 |ngFEC_mgt_bbox_18 | 1| |9 |ngFEC_mgt_bbox_19 | 1| |10 |ngFEC_mgt_bbox_20 | 1| |11 |ngFEC_mgt_bbox_21 | 1| |12 |ngFEC_mgt_bbox_22 | 1| |13 |ngFEC_mgt_bbox_23 | 1| |14 |sdpram_16x10_32x9_bbox_11 | 1| |15 |sdpram_16x10_32x9_bbox_13 | 1| |16 |sdpram_32x9_16x10_bbox_12 | 1| |17 |sdpram_32x9_16x10_bbox_14 | 1| |18 |BUFG | 22| |19 |BUFGMUX | 1| |20 |BUFH | 14| |21 |CARRY4 | 12978| |22 |IBUFDS_GTE2 | 4| |23 |ICAPE2 | 1| |24 |IDDR | 1| |25 |LUT1 | 9036| |26 |LUT2 | 28488| |27 |LUT3 | 40109| |28 |LUT4 | 25284| |29 |LUT5 | 33226| |30 |LUT6 | 60573| |31 |MMCME2_ADV | 3| |32 |MUXF7 | 1760| |33 |MUXF8 | 515| |34 |ODDR | 1| |35 |PLLE2_BASE | 1| |36 |RAMB36E1 | 1| |37 |RAMB36E1_1 | 16| |38 |RAMB36E1_2 | 180| |39 |RAMB36E1_3 | 360| |40 |RAMB36E1_4 | 12| |41 |SRL16 | 2| |42 |SRL16E | 85| |43 |SRLC32E | 7| |44 |FDCE | 54897| |45 |FDPE | 3990| |46 |FDRE | 85529| |47 |FDSE | 1230| |48 |LD | 72| |49 |LDC | 1| |50 |IBUF | 85| |51 |IBUFDS | 1| |52 |IBUFGDS | 1| |53 |IOBUF | 42| |54 |OBUF | 106| |55 |OBUFDS | 1| +------+----------------------------------+------+ Report Instance Areas: +------+-----------------------------------------------------------------+---------------------------------------------+-------+ | |Instance |Module |Cells | +------+-----------------------------------------------------------------+---------------------------------------------+-------+ |1 |top | | 359677| |2 | ngFEC |ngFEC_logic | 331395| |3 | \g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__216 | 4| |4 | \g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__217 | 4| |5 | \g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__218 | 4| |6 | \g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__219 | 4| |7 | \g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__220 | 4| |8 | \g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__221 | 4| |9 | \g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__222 | 4| |10 | \g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__223 | 4| |11 | \g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__224 | 4| |12 | \g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__225 | 4| |13 | \g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__226 | 4| |14 | \g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst |xpm_cdc_single__parameterized1__227 | 4| |15 | \g_tx_ready_cnt[0].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__228 | 4| |16 | \g_tx_ready_cnt[1].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__229 | 4| |17 | \g_tx_ready_cnt[2].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__230 | 4| |18 | \g_tx_ready_cnt[3].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__231 | 4| |19 | \g_tx_ready_cnt[4].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__232 | 4| |20 | \g_tx_ready_cnt[5].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__233 | 4| |21 | \g_tx_ready_cnt[6].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__234 | 4| |22 | \g_tx_ready_cnt[7].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__235 | 4| |23 | \g_tx_ready_cnt[8].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__236 | 4| |24 | \g_tx_ready_cnt[9].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__237 | 4| |25 | \g_tx_ready_cnt[10].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__238 | 4| |26 | \g_tx_ready_cnt[11].tx_ready_Sync_inst |xpm_cdc_single__parameterized1__239 | 4| |27 | DTC |DTC_top | 161| |28 | Inst_TTC_decoder |TTC_decoder | 161| |29 | DTC_Counter |ttc_counter | 814| |30 | \SFP_GEN[10].QIE_RESET_DELAY |delay_counter | 40| |31 | \SFP_GEN[10].ngCCM_gbt |ngCCM__xdcDup__10 | 8160| |32 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__136 | 104| |33 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__414 | 4| |34 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__137 | 104| |35 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__413 | 4| |36 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__138 | 104| |37 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__412 | 4| |38 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__139 | 104| |39 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__411 | 4| |40 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__140 | 104| |41 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__410 | 4| |42 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__141 | 104| |43 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__409 | 4| |44 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__142 | 104| |45 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__408 | 4| |46 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__143 | 104| |47 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__407 | 4| |48 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__144 | 104| |49 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__406 | 4| |50 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__145 | 104| |51 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__405 | 4| |52 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__146 | 104| |53 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__404 | 4| |54 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__147 | 104| |55 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__403 | 4| |56 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__148 | 104| |57 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__402 | 4| |58 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__149 | 104| |59 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__401 | 4| |60 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__150 | 104| |61 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__400 | 4| |62 | CrossClock_DV_cnt |CrossClock_RX_2247 | 41| |63 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__10 | 566| |64 | JTAGMaster_inst |JTAGMaster__xdcDup__10 | 417| |65 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__415 | 4| |66 | JTAG_BRAM |RAM_2331 | 85| |67 | Sync_RX_Reset |Sync_2248 | 2| |68 | Sync_TX_Reset |Sync_2249 | 45| |69 | Sync_error_counter_reset |Sync_2250 | 3| |70 | gbt_rx_checker |gbt_rx_checker_2251 | 104| |71 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_2252 | 309| |72 | i2c_master |i2c_master_usr_2326 | 309| |73 | byte_ctrl |i2c_master_byte_ctrl_2327 | 256| |74 | bit_ctrl |i2c_master_bit_ctrl_2328 | 207| |75 | \bus_status_ctrl.gf_scl |glitch_filter_2329 | 18| |76 | \bus_status_ctrl.gf_sda |glitch_filter_2330 | 20| |77 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_2253 | 309| |78 | i2c_master |i2c_master_usr_2321 | 309| |79 | byte_ctrl |i2c_master_byte_ctrl_2322 | 256| |80 | bit_ctrl |i2c_master_bit_ctrl_2323 | 207| |81 | \bus_status_ctrl.gf_scl |glitch_filter_2324 | 18| |82 | \bus_status_ctrl.gf_sda |glitch_filter_2325 | 20| |83 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_2254 | 309| |84 | i2c_master |i2c_master_usr_2316 | 309| |85 | byte_ctrl |i2c_master_byte_ctrl_2317 | 256| |86 | bit_ctrl |i2c_master_bit_ctrl_2318 | 207| |87 | \bus_status_ctrl.gf_scl |glitch_filter_2319 | 18| |88 | \bus_status_ctrl.gf_sda |glitch_filter_2320 | 20| |89 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_2255 | 309| |90 | i2c_master |i2c_master_usr_2311 | 309| |91 | byte_ctrl |i2c_master_byte_ctrl_2312 | 256| |92 | bit_ctrl |i2c_master_bit_ctrl_2313 | 207| |93 | \bus_status_ctrl.gf_scl |glitch_filter_2314 | 18| |94 | \bus_status_ctrl.gf_sda |glitch_filter_2315 | 20| |95 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_2256 | 309| |96 | i2c_master |i2c_master_usr_2306 | 309| |97 | byte_ctrl |i2c_master_byte_ctrl_2307 | 256| |98 | bit_ctrl |i2c_master_bit_ctrl_2308 | 207| |99 | \bus_status_ctrl.gf_scl |glitch_filter_2309 | 18| |100 | \bus_status_ctrl.gf_sda |glitch_filter_2310 | 20| |101 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_2257 | 309| |102 | i2c_master |i2c_master_usr_2301 | 309| |103 | byte_ctrl |i2c_master_byte_ctrl_2302 | 256| |104 | bit_ctrl |i2c_master_bit_ctrl_2303 | 207| |105 | \bus_status_ctrl.gf_scl |glitch_filter_2304 | 18| |106 | \bus_status_ctrl.gf_sda |glitch_filter_2305 | 20| |107 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_2258 | 309| |108 | i2c_master |i2c_master_usr_2296 | 309| |109 | byte_ctrl |i2c_master_byte_ctrl_2297 | 256| |110 | bit_ctrl |i2c_master_bit_ctrl_2298 | 207| |111 | \bus_status_ctrl.gf_scl |glitch_filter_2299 | 18| |112 | \bus_status_ctrl.gf_sda |glitch_filter_2300 | 20| |113 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_2259 | 309| |114 | i2c_master |i2c_master_usr_2291 | 309| |115 | byte_ctrl |i2c_master_byte_ctrl_2292 | 256| |116 | bit_ctrl |i2c_master_bit_ctrl_2293 | 207| |117 | \bus_status_ctrl.gf_scl |glitch_filter_2294 | 18| |118 | \bus_status_ctrl.gf_sda |glitch_filter_2295 | 20| |119 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_2260 | 309| |120 | i2c_master |i2c_master_usr_2286 | 309| |121 | byte_ctrl |i2c_master_byte_ctrl_2287 | 256| |122 | bit_ctrl |i2c_master_bit_ctrl_2288 | 207| |123 | \bus_status_ctrl.gf_scl |glitch_filter_2289 | 18| |124 | \bus_status_ctrl.gf_sda |glitch_filter_2290 | 20| |125 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_2261 | 309| |126 | i2c_master |i2c_master_usr_2281 | 309| |127 | byte_ctrl |i2c_master_byte_ctrl_2282 | 256| |128 | bit_ctrl |i2c_master_bit_ctrl_2283 | 207| |129 | \bus_status_ctrl.gf_scl |glitch_filter_2284 | 18| |130 | \bus_status_ctrl.gf_sda |glitch_filter_2285 | 20| |131 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_2262 | 309| |132 | i2c_master |i2c_master_usr_2276 | 309| |133 | byte_ctrl |i2c_master_byte_ctrl_2277 | 256| |134 | bit_ctrl |i2c_master_bit_ctrl_2278 | 207| |135 | \bus_status_ctrl.gf_scl |glitch_filter_2279 | 18| |136 | \bus_status_ctrl.gf_sda |glitch_filter_2280 | 20| |137 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_2263 | 309| |138 | i2c_master |i2c_master_usr_2271 | 309| |139 | byte_ctrl |i2c_master_byte_ctrl_2272 | 256| |140 | bit_ctrl |i2c_master_bit_ctrl_2273 | 207| |141 | \bus_status_ctrl.gf_scl |glitch_filter_2274 | 18| |142 | \bus_status_ctrl.gf_sda |glitch_filter_2275 | 20| |143 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_2264 | 307| |144 | i2c_master |i2c_master_usr_2266 | 307| |145 | byte_ctrl |i2c_master_byte_ctrl_2267 | 255| |146 | bit_ctrl |i2c_master_bit_ctrl_2268 | 206| |147 | \bus_status_ctrl.gf_scl |glitch_filter_2269 | 17| |148 | \bus_status_ctrl.gf_sda |glitch_filter_2270 | 19| |149 | prbs |prbs_2265 | 20| |150 | \SFP_GEN[10].ngFEC_module |ngFEC_module | 15549| |151 | bkp_buffer_ngccm |buffer_ngccm_com_2157 | 511| |152 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_2158 | 281| |153 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2244 | 194| |154 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2245 | 20| |155 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2246 | 24| |156 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_2159 | 168| |157 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_2160 | 257| |158 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2241 | 167| |159 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2242 | 18| |160 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2243 | 29| |161 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_2161 | 166| |162 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_2162 | 257| |163 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2238 | 167| |164 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2239 | 18| |165 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2240 | 29| |166 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_2163 | 166| |167 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_2164 | 280| |168 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2235 | 188| |169 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2236 | 20| |170 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2237 | 29| |171 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_2165 | 264| |172 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_2166 | 134| |173 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2232 | 69| |174 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2233 | 20| |175 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2234 | 18| |176 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_2167 | 133| |177 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_2168 | 280| |178 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2229 | 188| |179 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2230 | 20| |180 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2231 | 29| |181 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_2169 | 168| |182 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_2170 | 257| |183 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2226 | 167| |184 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2227 | 18| |185 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2228 | 29| |186 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_2171 | 198| |187 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_2172 | 280| |188 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2223 | 188| |189 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2224 | 20| |190 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2225 | 29| |191 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_2173 | 168| |192 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_2174 | 280| |193 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2220 | 188| |194 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2221 | 20| |195 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2222 | 29| |196 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_2175 | 167| |197 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_2176 | 280| |198 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2217 | 188| |199 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2218 | 20| |200 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2219 | 29| |201 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_2177 | 168| |202 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_2178 | 280| |203 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2214 | 188| |204 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2215 | 20| |205 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2216 | 29| |206 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_2179 | 234| |207 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_2180 | 257| |208 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2211 | 167| |209 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2212 | 18| |210 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2213 | 29| |211 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_2181 | 166| |212 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_2182 | 257| |213 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2208 | 167| |214 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2209 | 18| |215 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2210 | 29| |216 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_2183 | 166| |217 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_2184 | 257| |218 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2205 | 167| |219 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2206 | 18| |220 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2207 | 29| |221 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_2185 | 165| |222 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_2186 | 257| |223 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2202 | 167| |224 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2203 | 18| |225 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2204 | 29| |226 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_2187 | 198| |227 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_2188 | 662| |228 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_2189 | 510| |229 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_2190 | 535| |230 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_2191 | 535| |231 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_2192 | 511| |232 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_2193 | 535| |233 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_2194 | 511| |234 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_2195 | 511| |235 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_2196 | 511| |236 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_2197 | 511| |237 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_2198 | 535| |238 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_2199 | 535| |239 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_2200 | 535| |240 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_2201 | 535| |241 | \SFP_GEN[11].QIE_RESET_DELAY |delay_counter_3 | 40| |242 | \SFP_GEN[11].ngCCM_gbt |ngCCM__xdcDup__11 | 8159| |243 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__151 | 104| |244 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__398 | 4| |245 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__152 | 104| |246 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__397 | 4| |247 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__153 | 104| |248 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__396 | 4| |249 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__154 | 104| |250 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__395 | 4| |251 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__155 | 104| |252 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__394 | 4| |253 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__156 | 104| |254 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__393 | 4| |255 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__157 | 104| |256 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__392 | 4| |257 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__158 | 104| |258 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__391 | 4| |259 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__159 | 104| |260 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__390 | 4| |261 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__160 | 104| |262 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__389 | 4| |263 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__161 | 104| |264 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__388 | 4| |265 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__162 | 104| |266 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__387 | 4| |267 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__163 | 104| |268 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__386 | 4| |269 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__164 | 104| |270 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__385 | 4| |271 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__165 | 104| |272 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__384 | 4| |273 | CrossClock_DV_cnt |CrossClock_RX_2072 | 41| |274 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__11 | 566| |275 | JTAGMaster_inst |JTAGMaster__xdcDup__11 | 417| |276 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__399 | 4| |277 | JTAG_BRAM |RAM_2156 | 85| |278 | Sync_RX_Reset |Sync_2073 | 2| |279 | Sync_TX_Reset |Sync_2074 | 45| |280 | Sync_error_counter_reset |Sync_2075 | 3| |281 | gbt_rx_checker |gbt_rx_checker_2076 | 104| |282 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_2077 | 309| |283 | i2c_master |i2c_master_usr_2151 | 309| |284 | byte_ctrl |i2c_master_byte_ctrl_2152 | 256| |285 | bit_ctrl |i2c_master_bit_ctrl_2153 | 207| |286 | \bus_status_ctrl.gf_scl |glitch_filter_2154 | 18| |287 | \bus_status_ctrl.gf_sda |glitch_filter_2155 | 20| |288 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_2078 | 309| |289 | i2c_master |i2c_master_usr_2146 | 309| |290 | byte_ctrl |i2c_master_byte_ctrl_2147 | 256| |291 | bit_ctrl |i2c_master_bit_ctrl_2148 | 207| |292 | \bus_status_ctrl.gf_scl |glitch_filter_2149 | 18| |293 | \bus_status_ctrl.gf_sda |glitch_filter_2150 | 20| |294 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_2079 | 309| |295 | i2c_master |i2c_master_usr_2141 | 309| |296 | byte_ctrl |i2c_master_byte_ctrl_2142 | 256| |297 | bit_ctrl |i2c_master_bit_ctrl_2143 | 207| |298 | \bus_status_ctrl.gf_scl |glitch_filter_2144 | 18| |299 | \bus_status_ctrl.gf_sda |glitch_filter_2145 | 20| |300 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_2080 | 309| |301 | i2c_master |i2c_master_usr_2136 | 309| |302 | byte_ctrl |i2c_master_byte_ctrl_2137 | 256| |303 | bit_ctrl |i2c_master_bit_ctrl_2138 | 207| |304 | \bus_status_ctrl.gf_scl |glitch_filter_2139 | 18| |305 | \bus_status_ctrl.gf_sda |glitch_filter_2140 | 20| |306 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_2081 | 309| |307 | i2c_master |i2c_master_usr_2131 | 309| |308 | byte_ctrl |i2c_master_byte_ctrl_2132 | 256| |309 | bit_ctrl |i2c_master_bit_ctrl_2133 | 207| |310 | \bus_status_ctrl.gf_scl |glitch_filter_2134 | 18| |311 | \bus_status_ctrl.gf_sda |glitch_filter_2135 | 20| |312 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_2082 | 309| |313 | i2c_master |i2c_master_usr_2126 | 309| |314 | byte_ctrl |i2c_master_byte_ctrl_2127 | 256| |315 | bit_ctrl |i2c_master_bit_ctrl_2128 | 207| |316 | \bus_status_ctrl.gf_scl |glitch_filter_2129 | 18| |317 | \bus_status_ctrl.gf_sda |glitch_filter_2130 | 20| |318 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_2083 | 309| |319 | i2c_master |i2c_master_usr_2121 | 309| |320 | byte_ctrl |i2c_master_byte_ctrl_2122 | 256| |321 | bit_ctrl |i2c_master_bit_ctrl_2123 | 207| |322 | \bus_status_ctrl.gf_scl |glitch_filter_2124 | 18| |323 | \bus_status_ctrl.gf_sda |glitch_filter_2125 | 20| |324 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_2084 | 309| |325 | i2c_master |i2c_master_usr_2116 | 309| |326 | byte_ctrl |i2c_master_byte_ctrl_2117 | 256| |327 | bit_ctrl |i2c_master_bit_ctrl_2118 | 207| |328 | \bus_status_ctrl.gf_scl |glitch_filter_2119 | 18| |329 | \bus_status_ctrl.gf_sda |glitch_filter_2120 | 20| |330 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_2085 | 309| |331 | i2c_master |i2c_master_usr_2111 | 309| |332 | byte_ctrl |i2c_master_byte_ctrl_2112 | 256| |333 | bit_ctrl |i2c_master_bit_ctrl_2113 | 207| |334 | \bus_status_ctrl.gf_scl |glitch_filter_2114 | 18| |335 | \bus_status_ctrl.gf_sda |glitch_filter_2115 | 20| |336 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_2086 | 309| |337 | i2c_master |i2c_master_usr_2106 | 309| |338 | byte_ctrl |i2c_master_byte_ctrl_2107 | 256| |339 | bit_ctrl |i2c_master_bit_ctrl_2108 | 207| |340 | \bus_status_ctrl.gf_scl |glitch_filter_2109 | 18| |341 | \bus_status_ctrl.gf_sda |glitch_filter_2110 | 20| |342 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_2087 | 309| |343 | i2c_master |i2c_master_usr_2101 | 309| |344 | byte_ctrl |i2c_master_byte_ctrl_2102 | 256| |345 | bit_ctrl |i2c_master_bit_ctrl_2103 | 207| |346 | \bus_status_ctrl.gf_scl |glitch_filter_2104 | 18| |347 | \bus_status_ctrl.gf_sda |glitch_filter_2105 | 20| |348 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_2088 | 309| |349 | i2c_master |i2c_master_usr_2096 | 309| |350 | byte_ctrl |i2c_master_byte_ctrl_2097 | 256| |351 | bit_ctrl |i2c_master_bit_ctrl_2098 | 207| |352 | \bus_status_ctrl.gf_scl |glitch_filter_2099 | 18| |353 | \bus_status_ctrl.gf_sda |glitch_filter_2100 | 20| |354 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_2089 | 307| |355 | i2c_master |i2c_master_usr_2091 | 307| |356 | byte_ctrl |i2c_master_byte_ctrl_2092 | 255| |357 | bit_ctrl |i2c_master_bit_ctrl_2093 | 206| |358 | \bus_status_ctrl.gf_scl |glitch_filter_2094 | 17| |359 | \bus_status_ctrl.gf_sda |glitch_filter_2095 | 19| |360 | prbs |prbs_2090 | 20| |361 | \SFP_GEN[11].ngFEC_module |ngFEC_module_4 | 15549| |362 | bkp_buffer_ngccm |buffer_ngccm_com_1982 | 511| |363 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1983 | 281| |364 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2069 | 194| |365 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2070 | 20| |366 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2071 | 24| |367 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1984 | 168| |368 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1985 | 257| |369 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2066 | 167| |370 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2067 | 18| |371 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2068 | 29| |372 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1986 | 166| |373 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1987 | 257| |374 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2063 | 167| |375 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2064 | 18| |376 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2065 | 29| |377 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1988 | 166| |378 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1989 | 280| |379 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2060 | 188| |380 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2061 | 20| |381 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2062 | 29| |382 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1990 | 264| |383 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1991 | 134| |384 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2057 | 69| |385 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2058 | 20| |386 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2059 | 18| |387 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1992 | 133| |388 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1993 | 280| |389 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2054 | 188| |390 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2055 | 20| |391 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2056 | 29| |392 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1994 | 168| |393 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1995 | 257| |394 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2051 | 167| |395 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2052 | 18| |396 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2053 | 29| |397 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1996 | 198| |398 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1997 | 280| |399 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2048 | 188| |400 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2049 | 20| |401 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2050 | 29| |402 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1998 | 168| |403 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1999 | 280| |404 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2045 | 188| |405 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2046 | 20| |406 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2047 | 29| |407 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_2000 | 167| |408 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_2001 | 280| |409 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2042 | 188| |410 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2043 | 20| |411 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2044 | 29| |412 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_2002 | 168| |413 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_2003 | 280| |414 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2039 | 188| |415 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2040 | 20| |416 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2041 | 29| |417 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_2004 | 234| |418 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_2005 | 257| |419 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2036 | 167| |420 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2037 | 18| |421 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2038 | 29| |422 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_2006 | 166| |423 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_2007 | 257| |424 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2033 | 167| |425 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2034 | 18| |426 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2035 | 29| |427 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_2008 | 166| |428 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_2009 | 257| |429 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2030 | 167| |430 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2031 | 18| |431 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2032 | 29| |432 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_2010 | 165| |433 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_2011 | 257| |434 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_2027 | 167| |435 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_2028 | 18| |436 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_2029 | 29| |437 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_2012 | 198| |438 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_2013 | 662| |439 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_2014 | 510| |440 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_2015 | 535| |441 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_2016 | 535| |442 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_2017 | 511| |443 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_2018 | 535| |444 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_2019 | 511| |445 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_2020 | 511| |446 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_2021 | 511| |447 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_2022 | 511| |448 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_2023 | 535| |449 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_2024 | 535| |450 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_2025 | 535| |451 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_2026 | 535| |452 | \SFP_GEN[12].QIE_RESET_DELAY |delay_counter_5 | 40| |453 | \SFP_GEN[12].ngCCM_gbt |ngCCM | 8157| |454 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__166 | 104| |455 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__382 | 4| |456 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__167 | 104| |457 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__381 | 4| |458 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__168 | 104| |459 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__380 | 4| |460 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__169 | 104| |461 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__379 | 4| |462 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__170 | 104| |463 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__378 | 4| |464 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__171 | 104| |465 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__377 | 4| |466 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__172 | 104| |467 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__376 | 4| |468 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__173 | 104| |469 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__375 | 4| |470 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__174 | 104| |471 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__374 | 4| |472 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__175 | 104| |473 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__373 | 4| |474 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__176 | 104| |475 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__372 | 4| |476 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__177 | 104| |477 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__371 | 4| |478 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__178 | 104| |479 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__370 | 4| |480 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__179 | 104| |481 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__369 | 4| |482 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local | 104| |483 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__368 | 4| |484 | CrossClock_DV_cnt |CrossClock_RX_1897 | 41| |485 | LocalJTAGBridge_inst |LocalJTAGBridge | 566| |486 | JTAGMaster_inst |JTAGMaster | 417| |487 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__383 | 4| |488 | JTAG_BRAM |RAM_1981 | 85| |489 | Sync_RX_Reset |Sync_1898 | 2| |490 | Sync_TX_Reset |Sync_1899 | 45| |491 | Sync_error_counter_reset |Sync_1900 | 3| |492 | gbt_rx_checker |gbt_rx_checker_1901 | 104| |493 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1902 | 309| |494 | i2c_master |i2c_master_usr_1976 | 309| |495 | byte_ctrl |i2c_master_byte_ctrl_1977 | 256| |496 | bit_ctrl |i2c_master_bit_ctrl_1978 | 207| |497 | \bus_status_ctrl.gf_scl |glitch_filter_1979 | 18| |498 | \bus_status_ctrl.gf_sda |glitch_filter_1980 | 20| |499 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1903 | 309| |500 | i2c_master |i2c_master_usr_1971 | 309| |501 | byte_ctrl |i2c_master_byte_ctrl_1972 | 256| |502 | bit_ctrl |i2c_master_bit_ctrl_1973 | 207| |503 | \bus_status_ctrl.gf_scl |glitch_filter_1974 | 18| |504 | \bus_status_ctrl.gf_sda |glitch_filter_1975 | 20| |505 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1904 | 309| |506 | i2c_master |i2c_master_usr_1966 | 309| |507 | byte_ctrl |i2c_master_byte_ctrl_1967 | 256| |508 | bit_ctrl |i2c_master_bit_ctrl_1968 | 207| |509 | \bus_status_ctrl.gf_scl |glitch_filter_1969 | 18| |510 | \bus_status_ctrl.gf_sda |glitch_filter_1970 | 20| |511 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1905 | 309| |512 | i2c_master |i2c_master_usr_1961 | 309| |513 | byte_ctrl |i2c_master_byte_ctrl_1962 | 256| |514 | bit_ctrl |i2c_master_bit_ctrl_1963 | 207| |515 | \bus_status_ctrl.gf_scl |glitch_filter_1964 | 18| |516 | \bus_status_ctrl.gf_sda |glitch_filter_1965 | 20| |517 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1906 | 309| |518 | i2c_master |i2c_master_usr_1956 | 309| |519 | byte_ctrl |i2c_master_byte_ctrl_1957 | 256| |520 | bit_ctrl |i2c_master_bit_ctrl_1958 | 207| |521 | \bus_status_ctrl.gf_scl |glitch_filter_1959 | 18| |522 | \bus_status_ctrl.gf_sda |glitch_filter_1960 | 20| |523 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1907 | 309| |524 | i2c_master |i2c_master_usr_1951 | 309| |525 | byte_ctrl |i2c_master_byte_ctrl_1952 | 256| |526 | bit_ctrl |i2c_master_bit_ctrl_1953 | 207| |527 | \bus_status_ctrl.gf_scl |glitch_filter_1954 | 18| |528 | \bus_status_ctrl.gf_sda |glitch_filter_1955 | 20| |529 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1908 | 309| |530 | i2c_master |i2c_master_usr_1946 | 309| |531 | byte_ctrl |i2c_master_byte_ctrl_1947 | 256| |532 | bit_ctrl |i2c_master_bit_ctrl_1948 | 207| |533 | \bus_status_ctrl.gf_scl |glitch_filter_1949 | 18| |534 | \bus_status_ctrl.gf_sda |glitch_filter_1950 | 20| |535 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1909 | 309| |536 | i2c_master |i2c_master_usr_1941 | 309| |537 | byte_ctrl |i2c_master_byte_ctrl_1942 | 256| |538 | bit_ctrl |i2c_master_bit_ctrl_1943 | 207| |539 | \bus_status_ctrl.gf_scl |glitch_filter_1944 | 18| |540 | \bus_status_ctrl.gf_sda |glitch_filter_1945 | 20| |541 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1910 | 309| |542 | i2c_master |i2c_master_usr_1936 | 309| |543 | byte_ctrl |i2c_master_byte_ctrl_1937 | 256| |544 | bit_ctrl |i2c_master_bit_ctrl_1938 | 207| |545 | \bus_status_ctrl.gf_scl |glitch_filter_1939 | 18| |546 | \bus_status_ctrl.gf_sda |glitch_filter_1940 | 20| |547 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1911 | 309| |548 | i2c_master |i2c_master_usr_1931 | 309| |549 | byte_ctrl |i2c_master_byte_ctrl_1932 | 256| |550 | bit_ctrl |i2c_master_bit_ctrl_1933 | 207| |551 | \bus_status_ctrl.gf_scl |glitch_filter_1934 | 18| |552 | \bus_status_ctrl.gf_sda |glitch_filter_1935 | 20| |553 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1912 | 309| |554 | i2c_master |i2c_master_usr_1926 | 309| |555 | byte_ctrl |i2c_master_byte_ctrl_1927 | 256| |556 | bit_ctrl |i2c_master_bit_ctrl_1928 | 207| |557 | \bus_status_ctrl.gf_scl |glitch_filter_1929 | 18| |558 | \bus_status_ctrl.gf_sda |glitch_filter_1930 | 20| |559 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1913 | 309| |560 | i2c_master |i2c_master_usr_1921 | 309| |561 | byte_ctrl |i2c_master_byte_ctrl_1922 | 256| |562 | bit_ctrl |i2c_master_bit_ctrl_1923 | 207| |563 | \bus_status_ctrl.gf_scl |glitch_filter_1924 | 18| |564 | \bus_status_ctrl.gf_sda |glitch_filter_1925 | 20| |565 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1914 | 307| |566 | i2c_master |i2c_master_usr_1916 | 307| |567 | byte_ctrl |i2c_master_byte_ctrl_1917 | 255| |568 | bit_ctrl |i2c_master_bit_ctrl_1918 | 206| |569 | \bus_status_ctrl.gf_scl |glitch_filter_1919 | 17| |570 | \bus_status_ctrl.gf_sda |glitch_filter_1920 | 19| |571 | prbs |prbs_1915 | 20| |572 | \SFP_GEN[12].ngFEC_module |ngFEC_module_6 | 15549| |573 | bkp_buffer_ngccm |buffer_ngccm_com_1807 | 511| |574 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1808 | 281| |575 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1894 | 194| |576 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1895 | 20| |577 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1896 | 24| |578 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1809 | 168| |579 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1810 | 257| |580 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1891 | 167| |581 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1892 | 18| |582 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1893 | 29| |583 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1811 | 166| |584 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1812 | 257| |585 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1888 | 167| |586 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1889 | 18| |587 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1890 | 29| |588 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1813 | 166| |589 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1814 | 280| |590 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1885 | 188| |591 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1886 | 20| |592 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1887 | 29| |593 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1815 | 264| |594 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1816 | 134| |595 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1882 | 69| |596 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1883 | 20| |597 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1884 | 18| |598 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1817 | 133| |599 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1818 | 280| |600 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1879 | 188| |601 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1880 | 20| |602 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1881 | 29| |603 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1819 | 168| |604 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1820 | 257| |605 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1876 | 167| |606 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1877 | 18| |607 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1878 | 29| |608 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1821 | 198| |609 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1822 | 280| |610 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1873 | 188| |611 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1874 | 20| |612 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1875 | 29| |613 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1823 | 168| |614 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1824 | 280| |615 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1870 | 188| |616 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1871 | 20| |617 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1872 | 29| |618 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1825 | 167| |619 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1826 | 280| |620 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1867 | 188| |621 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1868 | 20| |622 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1869 | 29| |623 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1827 | 168| |624 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1828 | 280| |625 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1864 | 188| |626 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1865 | 20| |627 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1866 | 29| |628 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1829 | 234| |629 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1830 | 257| |630 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1861 | 167| |631 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1862 | 18| |632 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1863 | 29| |633 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1831 | 166| |634 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1832 | 257| |635 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1858 | 167| |636 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1859 | 18| |637 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1860 | 29| |638 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1833 | 166| |639 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1834 | 257| |640 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1855 | 167| |641 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1856 | 18| |642 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1857 | 29| |643 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1835 | 165| |644 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1836 | 257| |645 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1852 | 167| |646 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1853 | 18| |647 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1854 | 29| |648 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1837 | 198| |649 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1838 | 662| |650 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1839 | 510| |651 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1840 | 535| |652 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1841 | 535| |653 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1842 | 511| |654 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1843 | 535| |655 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1844 | 511| |656 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1845 | 511| |657 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1846 | 511| |658 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1847 | 511| |659 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1848 | 535| |660 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1849 | 535| |661 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1850 | 535| |662 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1851 | 535| |663 | \SFP_GEN[1].QIE_RESET_DELAY |delay_counter_7 | 40| |664 | \SFP_GEN[1].ngCCM_gbt |ngCCM__xdcDup__1 | 8153| |665 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__1 | 104| |666 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__366 | 4| |667 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__2 | 104| |668 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__365 | 4| |669 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__3 | 104| |670 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__364 | 4| |671 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__4 | 104| |672 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__363 | 4| |673 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__5 | 104| |674 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__362 | 4| |675 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__6 | 104| |676 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__361 | 4| |677 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__7 | 104| |678 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__360 | 4| |679 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__8 | 104| |680 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__359 | 4| |681 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__9 | 104| |682 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__358 | 4| |683 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__10 | 104| |684 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__357 | 4| |685 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__11 | 104| |686 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__356 | 4| |687 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__12 | 104| |688 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__355 | 4| |689 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__13 | 104| |690 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__354 | 4| |691 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__14 | 104| |692 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__353 | 4| |693 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__15 | 104| |694 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__352 | 4| |695 | CrossClock_DV_cnt |CrossClock_RX_1722 | 70| |696 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__1 | 629| |697 | JTAGMaster_inst |JTAGMaster__xdcDup__1 | 462| |698 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__367 | 4| |699 | JTAG_BRAM |RAM_1806 | 117| |700 | Sync_RX_Reset |Sync_1723 | 2| |701 | Sync_TX_Reset |Sync_1724 | 114| |702 | Sync_error_counter_reset |Sync_1725 | 2| |703 | gbt_rx_checker |gbt_rx_checker_1726 | 106| |704 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1727 | 332| |705 | i2c_master |i2c_master_usr_1801 | 332| |706 | byte_ctrl |i2c_master_byte_ctrl_1802 | 279| |707 | bit_ctrl |i2c_master_bit_ctrl_1803 | 224| |708 | \bus_status_ctrl.gf_scl |glitch_filter_1804 | 18| |709 | \bus_status_ctrl.gf_sda |glitch_filter_1805 | 20| |710 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1728 | 332| |711 | i2c_master |i2c_master_usr_1796 | 332| |712 | byte_ctrl |i2c_master_byte_ctrl_1797 | 279| |713 | bit_ctrl |i2c_master_bit_ctrl_1798 | 224| |714 | \bus_status_ctrl.gf_scl |glitch_filter_1799 | 18| |715 | \bus_status_ctrl.gf_sda |glitch_filter_1800 | 20| |716 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1729 | 332| |717 | i2c_master |i2c_master_usr_1791 | 332| |718 | byte_ctrl |i2c_master_byte_ctrl_1792 | 279| |719 | bit_ctrl |i2c_master_bit_ctrl_1793 | 224| |720 | \bus_status_ctrl.gf_scl |glitch_filter_1794 | 18| |721 | \bus_status_ctrl.gf_sda |glitch_filter_1795 | 20| |722 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1730 | 332| |723 | i2c_master |i2c_master_usr_1786 | 332| |724 | byte_ctrl |i2c_master_byte_ctrl_1787 | 279| |725 | bit_ctrl |i2c_master_bit_ctrl_1788 | 224| |726 | \bus_status_ctrl.gf_scl |glitch_filter_1789 | 18| |727 | \bus_status_ctrl.gf_sda |glitch_filter_1790 | 20| |728 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1731 | 332| |729 | i2c_master |i2c_master_usr_1781 | 332| |730 | byte_ctrl |i2c_master_byte_ctrl_1782 | 279| |731 | bit_ctrl |i2c_master_bit_ctrl_1783 | 224| |732 | \bus_status_ctrl.gf_scl |glitch_filter_1784 | 18| |733 | \bus_status_ctrl.gf_sda |glitch_filter_1785 | 20| |734 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1732 | 332| |735 | i2c_master |i2c_master_usr_1776 | 332| |736 | byte_ctrl |i2c_master_byte_ctrl_1777 | 279| |737 | bit_ctrl |i2c_master_bit_ctrl_1778 | 224| |738 | \bus_status_ctrl.gf_scl |glitch_filter_1779 | 18| |739 | \bus_status_ctrl.gf_sda |glitch_filter_1780 | 20| |740 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1733 | 332| |741 | i2c_master |i2c_master_usr_1771 | 332| |742 | byte_ctrl |i2c_master_byte_ctrl_1772 | 279| |743 | bit_ctrl |i2c_master_bit_ctrl_1773 | 224| |744 | \bus_status_ctrl.gf_scl |glitch_filter_1774 | 18| |745 | \bus_status_ctrl.gf_sda |glitch_filter_1775 | 20| |746 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1734 | 332| |747 | i2c_master |i2c_master_usr_1766 | 332| |748 | byte_ctrl |i2c_master_byte_ctrl_1767 | 279| |749 | bit_ctrl |i2c_master_bit_ctrl_1768 | 224| |750 | \bus_status_ctrl.gf_scl |glitch_filter_1769 | 18| |751 | \bus_status_ctrl.gf_sda |glitch_filter_1770 | 20| |752 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1735 | 332| |753 | i2c_master |i2c_master_usr_1761 | 332| |754 | byte_ctrl |i2c_master_byte_ctrl_1762 | 279| |755 | bit_ctrl |i2c_master_bit_ctrl_1763 | 224| |756 | \bus_status_ctrl.gf_scl |glitch_filter_1764 | 18| |757 | \bus_status_ctrl.gf_sda |glitch_filter_1765 | 20| |758 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1736 | 332| |759 | i2c_master |i2c_master_usr_1756 | 332| |760 | byte_ctrl |i2c_master_byte_ctrl_1757 | 279| |761 | bit_ctrl |i2c_master_bit_ctrl_1758 | 224| |762 | \bus_status_ctrl.gf_scl |glitch_filter_1759 | 18| |763 | \bus_status_ctrl.gf_sda |glitch_filter_1760 | 20| |764 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1737 | 332| |765 | i2c_master |i2c_master_usr_1751 | 332| |766 | byte_ctrl |i2c_master_byte_ctrl_1752 | 279| |767 | bit_ctrl |i2c_master_bit_ctrl_1753 | 224| |768 | \bus_status_ctrl.gf_scl |glitch_filter_1754 | 18| |769 | \bus_status_ctrl.gf_sda |glitch_filter_1755 | 20| |770 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1738 | 332| |771 | i2c_master |i2c_master_usr_1746 | 332| |772 | byte_ctrl |i2c_master_byte_ctrl_1747 | 279| |773 | bit_ctrl |i2c_master_bit_ctrl_1748 | 224| |774 | \bus_status_ctrl.gf_scl |glitch_filter_1749 | 18| |775 | \bus_status_ctrl.gf_sda |glitch_filter_1750 | 20| |776 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1739 | 331| |777 | i2c_master |i2c_master_usr_1741 | 331| |778 | byte_ctrl |i2c_master_byte_ctrl_1742 | 279| |779 | bit_ctrl |i2c_master_bit_ctrl_1743 | 224| |780 | \bus_status_ctrl.gf_scl |glitch_filter_1744 | 18| |781 | \bus_status_ctrl.gf_sda |glitch_filter_1745 | 20| |782 | prbs |prbs_1740 | 25| |783 | \SFP_GEN[1].ngFEC_module |ngFEC_module_8 | 15549| |784 | bkp_buffer_ngccm |buffer_ngccm_com_1632 | 511| |785 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1633 | 281| |786 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1719 | 194| |787 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1720 | 20| |788 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1721 | 24| |789 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1634 | 168| |790 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1635 | 257| |791 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1716 | 167| |792 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1717 | 18| |793 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1718 | 29| |794 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1636 | 166| |795 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1637 | 257| |796 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1713 | 167| |797 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1714 | 18| |798 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1715 | 29| |799 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1638 | 166| |800 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1639 | 280| |801 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1710 | 188| |802 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1711 | 20| |803 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1712 | 29| |804 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1640 | 264| |805 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1641 | 134| |806 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1707 | 69| |807 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1708 | 20| |808 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1709 | 18| |809 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1642 | 133| |810 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1643 | 280| |811 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1704 | 188| |812 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1705 | 20| |813 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1706 | 29| |814 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1644 | 168| |815 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1645 | 257| |816 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1701 | 167| |817 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1702 | 18| |818 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1703 | 29| |819 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1646 | 198| |820 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1647 | 280| |821 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1698 | 188| |822 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1699 | 20| |823 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1700 | 29| |824 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1648 | 168| |825 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1649 | 280| |826 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1695 | 188| |827 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1696 | 20| |828 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1697 | 29| |829 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1650 | 167| |830 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1651 | 280| |831 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1692 | 188| |832 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1693 | 20| |833 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1694 | 29| |834 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1652 | 168| |835 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1653 | 280| |836 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1689 | 188| |837 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1690 | 20| |838 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1691 | 29| |839 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1654 | 234| |840 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1655 | 257| |841 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1686 | 167| |842 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1687 | 18| |843 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1688 | 29| |844 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1656 | 166| |845 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1657 | 257| |846 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1683 | 167| |847 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1684 | 18| |848 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1685 | 29| |849 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1658 | 166| |850 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1659 | 257| |851 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1680 | 167| |852 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1681 | 18| |853 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1682 | 29| |854 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1660 | 165| |855 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1661 | 257| |856 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1677 | 167| |857 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1678 | 18| |858 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1679 | 29| |859 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1662 | 198| |860 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1663 | 662| |861 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1664 | 510| |862 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1665 | 535| |863 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1666 | 535| |864 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1667 | 511| |865 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1668 | 535| |866 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1669 | 511| |867 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1670 | 511| |868 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1671 | 511| |869 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1672 | 511| |870 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1673 | 535| |871 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1674 | 535| |872 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1675 | 535| |873 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1676 | 535| |874 | \SFP_GEN[2].QIE_RESET_DELAY |delay_counter_9 | 40| |875 | \SFP_GEN[2].ngCCM_gbt |ngCCM__xdcDup__2 | 8153| |876 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__16 | 104| |877 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__350 | 4| |878 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__17 | 104| |879 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__349 | 4| |880 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__18 | 104| |881 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__348 | 4| |882 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__19 | 104| |883 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__347 | 4| |884 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__20 | 104| |885 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__346 | 4| |886 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__21 | 104| |887 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__345 | 4| |888 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__22 | 104| |889 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__344 | 4| |890 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__23 | 104| |891 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__343 | 4| |892 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__24 | 104| |893 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__342 | 4| |894 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__25 | 104| |895 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__341 | 4| |896 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__26 | 104| |897 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__340 | 4| |898 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__27 | 104| |899 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__339 | 4| |900 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__28 | 104| |901 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__338 | 4| |902 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__29 | 104| |903 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__337 | 4| |904 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__30 | 104| |905 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__336 | 4| |906 | CrossClock_DV_cnt |CrossClock_RX_1547 | 70| |907 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__2 | 629| |908 | JTAGMaster_inst |JTAGMaster__xdcDup__2 | 462| |909 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__351 | 4| |910 | JTAG_BRAM |RAM_1631 | 117| |911 | Sync_RX_Reset |Sync_1548 | 2| |912 | Sync_TX_Reset |Sync_1549 | 114| |913 | Sync_error_counter_reset |Sync_1550 | 2| |914 | gbt_rx_checker |gbt_rx_checker_1551 | 106| |915 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1552 | 332| |916 | i2c_master |i2c_master_usr_1626 | 332| |917 | byte_ctrl |i2c_master_byte_ctrl_1627 | 279| |918 | bit_ctrl |i2c_master_bit_ctrl_1628 | 224| |919 | \bus_status_ctrl.gf_scl |glitch_filter_1629 | 18| |920 | \bus_status_ctrl.gf_sda |glitch_filter_1630 | 20| |921 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1553 | 332| |922 | i2c_master |i2c_master_usr_1621 | 332| |923 | byte_ctrl |i2c_master_byte_ctrl_1622 | 279| |924 | bit_ctrl |i2c_master_bit_ctrl_1623 | 224| |925 | \bus_status_ctrl.gf_scl |glitch_filter_1624 | 18| |926 | \bus_status_ctrl.gf_sda |glitch_filter_1625 | 20| |927 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1554 | 332| |928 | i2c_master |i2c_master_usr_1616 | 332| |929 | byte_ctrl |i2c_master_byte_ctrl_1617 | 279| |930 | bit_ctrl |i2c_master_bit_ctrl_1618 | 224| |931 | \bus_status_ctrl.gf_scl |glitch_filter_1619 | 18| |932 | \bus_status_ctrl.gf_sda |glitch_filter_1620 | 20| |933 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1555 | 332| |934 | i2c_master |i2c_master_usr_1611 | 332| |935 | byte_ctrl |i2c_master_byte_ctrl_1612 | 279| |936 | bit_ctrl |i2c_master_bit_ctrl_1613 | 224| |937 | \bus_status_ctrl.gf_scl |glitch_filter_1614 | 18| |938 | \bus_status_ctrl.gf_sda |glitch_filter_1615 | 20| |939 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1556 | 332| |940 | i2c_master |i2c_master_usr_1606 | 332| |941 | byte_ctrl |i2c_master_byte_ctrl_1607 | 279| |942 | bit_ctrl |i2c_master_bit_ctrl_1608 | 224| |943 | \bus_status_ctrl.gf_scl |glitch_filter_1609 | 18| |944 | \bus_status_ctrl.gf_sda |glitch_filter_1610 | 20| |945 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1557 | 332| |946 | i2c_master |i2c_master_usr_1601 | 332| |947 | byte_ctrl |i2c_master_byte_ctrl_1602 | 279| |948 | bit_ctrl |i2c_master_bit_ctrl_1603 | 224| |949 | \bus_status_ctrl.gf_scl |glitch_filter_1604 | 18| |950 | \bus_status_ctrl.gf_sda |glitch_filter_1605 | 20| |951 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1558 | 332| |952 | i2c_master |i2c_master_usr_1596 | 332| |953 | byte_ctrl |i2c_master_byte_ctrl_1597 | 279| |954 | bit_ctrl |i2c_master_bit_ctrl_1598 | 224| |955 | \bus_status_ctrl.gf_scl |glitch_filter_1599 | 18| |956 | \bus_status_ctrl.gf_sda |glitch_filter_1600 | 20| |957 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1559 | 332| |958 | i2c_master |i2c_master_usr_1591 | 332| |959 | byte_ctrl |i2c_master_byte_ctrl_1592 | 279| |960 | bit_ctrl |i2c_master_bit_ctrl_1593 | 224| |961 | \bus_status_ctrl.gf_scl |glitch_filter_1594 | 18| |962 | \bus_status_ctrl.gf_sda |glitch_filter_1595 | 20| |963 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1560 | 332| |964 | i2c_master |i2c_master_usr_1586 | 332| |965 | byte_ctrl |i2c_master_byte_ctrl_1587 | 279| |966 | bit_ctrl |i2c_master_bit_ctrl_1588 | 224| |967 | \bus_status_ctrl.gf_scl |glitch_filter_1589 | 18| |968 | \bus_status_ctrl.gf_sda |glitch_filter_1590 | 20| |969 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1561 | 332| |970 | i2c_master |i2c_master_usr_1581 | 332| |971 | byte_ctrl |i2c_master_byte_ctrl_1582 | 279| |972 | bit_ctrl |i2c_master_bit_ctrl_1583 | 224| |973 | \bus_status_ctrl.gf_scl |glitch_filter_1584 | 18| |974 | \bus_status_ctrl.gf_sda |glitch_filter_1585 | 20| |975 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1562 | 332| |976 | i2c_master |i2c_master_usr_1576 | 332| |977 | byte_ctrl |i2c_master_byte_ctrl_1577 | 279| |978 | bit_ctrl |i2c_master_bit_ctrl_1578 | 224| |979 | \bus_status_ctrl.gf_scl |glitch_filter_1579 | 18| |980 | \bus_status_ctrl.gf_sda |glitch_filter_1580 | 20| |981 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1563 | 332| |982 | i2c_master |i2c_master_usr_1571 | 332| |983 | byte_ctrl |i2c_master_byte_ctrl_1572 | 279| |984 | bit_ctrl |i2c_master_bit_ctrl_1573 | 224| |985 | \bus_status_ctrl.gf_scl |glitch_filter_1574 | 18| |986 | \bus_status_ctrl.gf_sda |glitch_filter_1575 | 20| |987 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1564 | 331| |988 | i2c_master |i2c_master_usr_1566 | 331| |989 | byte_ctrl |i2c_master_byte_ctrl_1567 | 279| |990 | bit_ctrl |i2c_master_bit_ctrl_1568 | 224| |991 | \bus_status_ctrl.gf_scl |glitch_filter_1569 | 18| |992 | \bus_status_ctrl.gf_sda |glitch_filter_1570 | 20| |993 | prbs |prbs_1565 | 25| |994 | \SFP_GEN[2].ngFEC_module |ngFEC_module_10 | 15549| |995 | bkp_buffer_ngccm |buffer_ngccm_com_1457 | 511| |996 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1458 | 281| |997 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1544 | 194| |998 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1545 | 20| |999 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1546 | 24| |1000 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1459 | 168| |1001 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1460 | 257| |1002 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1541 | 167| |1003 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1542 | 18| |1004 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1543 | 29| |1005 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1461 | 166| |1006 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1462 | 257| |1007 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1538 | 167| |1008 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1539 | 18| |1009 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1540 | 29| |1010 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1463 | 166| |1011 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1464 | 280| |1012 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1535 | 188| |1013 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1536 | 20| |1014 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1537 | 29| |1015 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1465 | 264| |1016 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1466 | 134| |1017 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1532 | 69| |1018 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1533 | 20| |1019 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1534 | 18| |1020 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1467 | 133| |1021 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1468 | 280| |1022 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1529 | 188| |1023 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1530 | 20| |1024 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1531 | 29| |1025 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1469 | 168| |1026 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1470 | 257| |1027 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1526 | 167| |1028 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1527 | 18| |1029 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1528 | 29| |1030 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1471 | 198| |1031 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1472 | 280| |1032 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1523 | 188| |1033 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1524 | 20| |1034 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1525 | 29| |1035 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1473 | 168| |1036 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1474 | 280| |1037 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1520 | 188| |1038 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1521 | 20| |1039 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1522 | 29| |1040 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1475 | 167| |1041 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1476 | 280| |1042 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1517 | 188| |1043 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1518 | 20| |1044 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1519 | 29| |1045 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1477 | 168| |1046 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1478 | 280| |1047 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1514 | 188| |1048 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1515 | 20| |1049 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1516 | 29| |1050 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1479 | 234| |1051 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1480 | 257| |1052 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1511 | 167| |1053 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1512 | 18| |1054 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1513 | 29| |1055 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1481 | 166| |1056 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1482 | 257| |1057 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1508 | 167| |1058 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1509 | 18| |1059 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1510 | 29| |1060 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1483 | 166| |1061 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1484 | 257| |1062 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1505 | 167| |1063 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1506 | 18| |1064 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1507 | 29| |1065 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1485 | 165| |1066 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1486 | 257| |1067 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1502 | 167| |1068 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1503 | 18| |1069 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1504 | 29| |1070 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1487 | 198| |1071 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1488 | 662| |1072 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1489 | 510| |1073 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1490 | 535| |1074 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1491 | 535| |1075 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1492 | 511| |1076 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1493 | 535| |1077 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1494 | 511| |1078 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1495 | 511| |1079 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1496 | 511| |1080 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1497 | 511| |1081 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1498 | 535| |1082 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1499 | 535| |1083 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1500 | 535| |1084 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1501 | 535| |1085 | \SFP_GEN[3].QIE_RESET_DELAY |delay_counter_11 | 40| |1086 | \SFP_GEN[3].ngCCM_gbt |ngCCM__xdcDup__3 | 8153| |1087 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__31 | 104| |1088 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__334 | 4| |1089 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__32 | 104| |1090 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__333 | 4| |1091 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__33 | 104| |1092 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__332 | 4| |1093 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__34 | 104| |1094 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__331 | 4| |1095 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__35 | 104| |1096 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__330 | 4| |1097 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__36 | 104| |1098 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__329 | 4| |1099 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__37 | 104| |1100 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__328 | 4| |1101 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__38 | 104| |1102 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__327 | 4| |1103 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__39 | 104| |1104 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__326 | 4| |1105 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__40 | 104| |1106 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__325 | 4| |1107 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__41 | 104| |1108 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__324 | 4| |1109 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__42 | 104| |1110 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__323 | 4| |1111 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__43 | 104| |1112 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__322 | 4| |1113 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__44 | 104| |1114 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__321 | 4| |1115 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__45 | 104| |1116 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__320 | 4| |1117 | CrossClock_DV_cnt |CrossClock_RX_1372 | 70| |1118 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__3 | 629| |1119 | JTAGMaster_inst |JTAGMaster__xdcDup__3 | 462| |1120 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__335 | 4| |1121 | JTAG_BRAM |RAM_1456 | 117| |1122 | Sync_RX_Reset |Sync_1373 | 2| |1123 | Sync_TX_Reset |Sync_1374 | 114| |1124 | Sync_error_counter_reset |Sync_1375 | 2| |1125 | gbt_rx_checker |gbt_rx_checker_1376 | 106| |1126 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1377 | 332| |1127 | i2c_master |i2c_master_usr_1451 | 332| |1128 | byte_ctrl |i2c_master_byte_ctrl_1452 | 279| |1129 | bit_ctrl |i2c_master_bit_ctrl_1453 | 224| |1130 | \bus_status_ctrl.gf_scl |glitch_filter_1454 | 18| |1131 | \bus_status_ctrl.gf_sda |glitch_filter_1455 | 20| |1132 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1378 | 332| |1133 | i2c_master |i2c_master_usr_1446 | 332| |1134 | byte_ctrl |i2c_master_byte_ctrl_1447 | 279| |1135 | bit_ctrl |i2c_master_bit_ctrl_1448 | 224| |1136 | \bus_status_ctrl.gf_scl |glitch_filter_1449 | 18| |1137 | \bus_status_ctrl.gf_sda |glitch_filter_1450 | 20| |1138 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1379 | 332| |1139 | i2c_master |i2c_master_usr_1441 | 332| |1140 | byte_ctrl |i2c_master_byte_ctrl_1442 | 279| |1141 | bit_ctrl |i2c_master_bit_ctrl_1443 | 224| |1142 | \bus_status_ctrl.gf_scl |glitch_filter_1444 | 18| |1143 | \bus_status_ctrl.gf_sda |glitch_filter_1445 | 20| |1144 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1380 | 332| |1145 | i2c_master |i2c_master_usr_1436 | 332| |1146 | byte_ctrl |i2c_master_byte_ctrl_1437 | 279| |1147 | bit_ctrl |i2c_master_bit_ctrl_1438 | 224| |1148 | \bus_status_ctrl.gf_scl |glitch_filter_1439 | 18| |1149 | \bus_status_ctrl.gf_sda |glitch_filter_1440 | 20| |1150 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1381 | 332| |1151 | i2c_master |i2c_master_usr_1431 | 332| |1152 | byte_ctrl |i2c_master_byte_ctrl_1432 | 279| |1153 | bit_ctrl |i2c_master_bit_ctrl_1433 | 224| |1154 | \bus_status_ctrl.gf_scl |glitch_filter_1434 | 18| |1155 | \bus_status_ctrl.gf_sda |glitch_filter_1435 | 20| |1156 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1382 | 332| |1157 | i2c_master |i2c_master_usr_1426 | 332| |1158 | byte_ctrl |i2c_master_byte_ctrl_1427 | 279| |1159 | bit_ctrl |i2c_master_bit_ctrl_1428 | 224| |1160 | \bus_status_ctrl.gf_scl |glitch_filter_1429 | 18| |1161 | \bus_status_ctrl.gf_sda |glitch_filter_1430 | 20| |1162 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1383 | 332| |1163 | i2c_master |i2c_master_usr_1421 | 332| |1164 | byte_ctrl |i2c_master_byte_ctrl_1422 | 279| |1165 | bit_ctrl |i2c_master_bit_ctrl_1423 | 224| |1166 | \bus_status_ctrl.gf_scl |glitch_filter_1424 | 18| |1167 | \bus_status_ctrl.gf_sda |glitch_filter_1425 | 20| |1168 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1384 | 332| |1169 | i2c_master |i2c_master_usr_1416 | 332| |1170 | byte_ctrl |i2c_master_byte_ctrl_1417 | 279| |1171 | bit_ctrl |i2c_master_bit_ctrl_1418 | 224| |1172 | \bus_status_ctrl.gf_scl |glitch_filter_1419 | 18| |1173 | \bus_status_ctrl.gf_sda |glitch_filter_1420 | 20| |1174 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1385 | 332| |1175 | i2c_master |i2c_master_usr_1411 | 332| |1176 | byte_ctrl |i2c_master_byte_ctrl_1412 | 279| |1177 | bit_ctrl |i2c_master_bit_ctrl_1413 | 224| |1178 | \bus_status_ctrl.gf_scl |glitch_filter_1414 | 18| |1179 | \bus_status_ctrl.gf_sda |glitch_filter_1415 | 20| |1180 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1386 | 332| |1181 | i2c_master |i2c_master_usr_1406 | 332| |1182 | byte_ctrl |i2c_master_byte_ctrl_1407 | 279| |1183 | bit_ctrl |i2c_master_bit_ctrl_1408 | 224| |1184 | \bus_status_ctrl.gf_scl |glitch_filter_1409 | 18| |1185 | \bus_status_ctrl.gf_sda |glitch_filter_1410 | 20| |1186 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1387 | 332| |1187 | i2c_master |i2c_master_usr_1401 | 332| |1188 | byte_ctrl |i2c_master_byte_ctrl_1402 | 279| |1189 | bit_ctrl |i2c_master_bit_ctrl_1403 | 224| |1190 | \bus_status_ctrl.gf_scl |glitch_filter_1404 | 18| |1191 | \bus_status_ctrl.gf_sda |glitch_filter_1405 | 20| |1192 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1388 | 332| |1193 | i2c_master |i2c_master_usr_1396 | 332| |1194 | byte_ctrl |i2c_master_byte_ctrl_1397 | 279| |1195 | bit_ctrl |i2c_master_bit_ctrl_1398 | 224| |1196 | \bus_status_ctrl.gf_scl |glitch_filter_1399 | 18| |1197 | \bus_status_ctrl.gf_sda |glitch_filter_1400 | 20| |1198 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1389 | 331| |1199 | i2c_master |i2c_master_usr_1391 | 331| |1200 | byte_ctrl |i2c_master_byte_ctrl_1392 | 279| |1201 | bit_ctrl |i2c_master_bit_ctrl_1393 | 224| |1202 | \bus_status_ctrl.gf_scl |glitch_filter_1394 | 18| |1203 | \bus_status_ctrl.gf_sda |glitch_filter_1395 | 20| |1204 | prbs |prbs_1390 | 25| |1205 | \SFP_GEN[3].ngFEC_module |ngFEC_module_12 | 15549| |1206 | bkp_buffer_ngccm |buffer_ngccm_com_1282 | 511| |1207 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1283 | 281| |1208 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1369 | 194| |1209 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1370 | 20| |1210 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1371 | 24| |1211 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1284 | 168| |1212 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1285 | 257| |1213 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1366 | 167| |1214 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1367 | 18| |1215 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1368 | 29| |1216 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1286 | 166| |1217 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1287 | 257| |1218 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1363 | 167| |1219 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1364 | 18| |1220 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1365 | 29| |1221 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1288 | 166| |1222 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1289 | 280| |1223 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1360 | 188| |1224 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1361 | 20| |1225 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1362 | 29| |1226 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1290 | 264| |1227 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1291 | 134| |1228 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1357 | 69| |1229 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1358 | 20| |1230 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1359 | 18| |1231 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1292 | 133| |1232 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1293 | 280| |1233 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1354 | 188| |1234 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1355 | 20| |1235 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1356 | 29| |1236 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1294 | 168| |1237 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1295 | 257| |1238 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1351 | 167| |1239 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1352 | 18| |1240 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1353 | 29| |1241 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1296 | 198| |1242 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1297 | 280| |1243 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1348 | 188| |1244 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1349 | 20| |1245 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1350 | 29| |1246 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1298 | 168| |1247 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1299 | 280| |1248 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1345 | 188| |1249 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1346 | 20| |1250 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1347 | 29| |1251 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1300 | 167| |1252 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1301 | 280| |1253 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1342 | 188| |1254 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1343 | 20| |1255 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1344 | 29| |1256 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1302 | 168| |1257 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1303 | 280| |1258 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1339 | 188| |1259 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1340 | 20| |1260 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1341 | 29| |1261 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1304 | 234| |1262 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1305 | 257| |1263 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1336 | 167| |1264 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1337 | 18| |1265 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1338 | 29| |1266 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1306 | 166| |1267 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1307 | 257| |1268 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1333 | 167| |1269 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1334 | 18| |1270 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1335 | 29| |1271 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1308 | 166| |1272 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1309 | 257| |1273 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1330 | 167| |1274 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1331 | 18| |1275 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1332 | 29| |1276 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1310 | 165| |1277 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1311 | 257| |1278 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1327 | 167| |1279 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1328 | 18| |1280 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1329 | 29| |1281 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1312 | 198| |1282 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1313 | 662| |1283 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1314 | 510| |1284 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1315 | 535| |1285 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1316 | 535| |1286 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1317 | 511| |1287 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1318 | 535| |1288 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1319 | 511| |1289 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1320 | 511| |1290 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1321 | 511| |1291 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1322 | 511| |1292 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1323 | 535| |1293 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1324 | 535| |1294 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1325 | 535| |1295 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1326 | 535| |1296 | \SFP_GEN[4].QIE_RESET_DELAY |delay_counter_13 | 40| |1297 | \SFP_GEN[4].ngCCM_gbt |ngCCM__xdcDup__4 | 8153| |1298 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__46 | 104| |1299 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__318 | 4| |1300 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__47 | 104| |1301 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__317 | 4| |1302 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__48 | 104| |1303 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__316 | 4| |1304 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__49 | 104| |1305 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__315 | 4| |1306 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__50 | 104| |1307 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__314 | 4| |1308 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__51 | 104| |1309 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__313 | 4| |1310 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__52 | 104| |1311 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__312 | 4| |1312 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__53 | 104| |1313 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__311 | 4| |1314 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__54 | 104| |1315 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__310 | 4| |1316 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__55 | 104| |1317 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__309 | 4| |1318 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__56 | 104| |1319 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__308 | 4| |1320 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__57 | 104| |1321 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__307 | 4| |1322 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__58 | 104| |1323 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__306 | 4| |1324 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__59 | 104| |1325 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__305 | 4| |1326 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__60 | 104| |1327 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__304 | 4| |1328 | CrossClock_DV_cnt |CrossClock_RX_1197 | 70| |1329 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__4 | 629| |1330 | JTAGMaster_inst |JTAGMaster__xdcDup__4 | 462| |1331 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__319 | 4| |1332 | JTAG_BRAM |RAM_1281 | 117| |1333 | Sync_RX_Reset |Sync_1198 | 2| |1334 | Sync_TX_Reset |Sync_1199 | 114| |1335 | Sync_error_counter_reset |Sync_1200 | 2| |1336 | gbt_rx_checker |gbt_rx_checker_1201 | 106| |1337 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1202 | 332| |1338 | i2c_master |i2c_master_usr_1276 | 332| |1339 | byte_ctrl |i2c_master_byte_ctrl_1277 | 279| |1340 | bit_ctrl |i2c_master_bit_ctrl_1278 | 224| |1341 | \bus_status_ctrl.gf_scl |glitch_filter_1279 | 18| |1342 | \bus_status_ctrl.gf_sda |glitch_filter_1280 | 20| |1343 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1203 | 332| |1344 | i2c_master |i2c_master_usr_1271 | 332| |1345 | byte_ctrl |i2c_master_byte_ctrl_1272 | 279| |1346 | bit_ctrl |i2c_master_bit_ctrl_1273 | 224| |1347 | \bus_status_ctrl.gf_scl |glitch_filter_1274 | 18| |1348 | \bus_status_ctrl.gf_sda |glitch_filter_1275 | 20| |1349 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1204 | 332| |1350 | i2c_master |i2c_master_usr_1266 | 332| |1351 | byte_ctrl |i2c_master_byte_ctrl_1267 | 279| |1352 | bit_ctrl |i2c_master_bit_ctrl_1268 | 224| |1353 | \bus_status_ctrl.gf_scl |glitch_filter_1269 | 18| |1354 | \bus_status_ctrl.gf_sda |glitch_filter_1270 | 20| |1355 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1205 | 332| |1356 | i2c_master |i2c_master_usr_1261 | 332| |1357 | byte_ctrl |i2c_master_byte_ctrl_1262 | 279| |1358 | bit_ctrl |i2c_master_bit_ctrl_1263 | 224| |1359 | \bus_status_ctrl.gf_scl |glitch_filter_1264 | 18| |1360 | \bus_status_ctrl.gf_sda |glitch_filter_1265 | 20| |1361 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1206 | 332| |1362 | i2c_master |i2c_master_usr_1256 | 332| |1363 | byte_ctrl |i2c_master_byte_ctrl_1257 | 279| |1364 | bit_ctrl |i2c_master_bit_ctrl_1258 | 224| |1365 | \bus_status_ctrl.gf_scl |glitch_filter_1259 | 18| |1366 | \bus_status_ctrl.gf_sda |glitch_filter_1260 | 20| |1367 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1207 | 332| |1368 | i2c_master |i2c_master_usr_1251 | 332| |1369 | byte_ctrl |i2c_master_byte_ctrl_1252 | 279| |1370 | bit_ctrl |i2c_master_bit_ctrl_1253 | 224| |1371 | \bus_status_ctrl.gf_scl |glitch_filter_1254 | 18| |1372 | \bus_status_ctrl.gf_sda |glitch_filter_1255 | 20| |1373 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1208 | 332| |1374 | i2c_master |i2c_master_usr_1246 | 332| |1375 | byte_ctrl |i2c_master_byte_ctrl_1247 | 279| |1376 | bit_ctrl |i2c_master_bit_ctrl_1248 | 224| |1377 | \bus_status_ctrl.gf_scl |glitch_filter_1249 | 18| |1378 | \bus_status_ctrl.gf_sda |glitch_filter_1250 | 20| |1379 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1209 | 332| |1380 | i2c_master |i2c_master_usr_1241 | 332| |1381 | byte_ctrl |i2c_master_byte_ctrl_1242 | 279| |1382 | bit_ctrl |i2c_master_bit_ctrl_1243 | 224| |1383 | \bus_status_ctrl.gf_scl |glitch_filter_1244 | 18| |1384 | \bus_status_ctrl.gf_sda |glitch_filter_1245 | 20| |1385 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1210 | 332| |1386 | i2c_master |i2c_master_usr_1236 | 332| |1387 | byte_ctrl |i2c_master_byte_ctrl_1237 | 279| |1388 | bit_ctrl |i2c_master_bit_ctrl_1238 | 224| |1389 | \bus_status_ctrl.gf_scl |glitch_filter_1239 | 18| |1390 | \bus_status_ctrl.gf_sda |glitch_filter_1240 | 20| |1391 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1211 | 332| |1392 | i2c_master |i2c_master_usr_1231 | 332| |1393 | byte_ctrl |i2c_master_byte_ctrl_1232 | 279| |1394 | bit_ctrl |i2c_master_bit_ctrl_1233 | 224| |1395 | \bus_status_ctrl.gf_scl |glitch_filter_1234 | 18| |1396 | \bus_status_ctrl.gf_sda |glitch_filter_1235 | 20| |1397 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1212 | 332| |1398 | i2c_master |i2c_master_usr_1226 | 332| |1399 | byte_ctrl |i2c_master_byte_ctrl_1227 | 279| |1400 | bit_ctrl |i2c_master_bit_ctrl_1228 | 224| |1401 | \bus_status_ctrl.gf_scl |glitch_filter_1229 | 18| |1402 | \bus_status_ctrl.gf_sda |glitch_filter_1230 | 20| |1403 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1213 | 332| |1404 | i2c_master |i2c_master_usr_1221 | 332| |1405 | byte_ctrl |i2c_master_byte_ctrl_1222 | 279| |1406 | bit_ctrl |i2c_master_bit_ctrl_1223 | 224| |1407 | \bus_status_ctrl.gf_scl |glitch_filter_1224 | 18| |1408 | \bus_status_ctrl.gf_sda |glitch_filter_1225 | 20| |1409 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1214 | 331| |1410 | i2c_master |i2c_master_usr_1216 | 331| |1411 | byte_ctrl |i2c_master_byte_ctrl_1217 | 279| |1412 | bit_ctrl |i2c_master_bit_ctrl_1218 | 224| |1413 | \bus_status_ctrl.gf_scl |glitch_filter_1219 | 18| |1414 | \bus_status_ctrl.gf_sda |glitch_filter_1220 | 20| |1415 | prbs |prbs_1215 | 25| |1416 | \SFP_GEN[4].ngFEC_module |ngFEC_module_14 | 15549| |1417 | bkp_buffer_ngccm |buffer_ngccm_com_1107 | 511| |1418 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_1108 | 281| |1419 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1194 | 194| |1420 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1195 | 20| |1421 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1196 | 24| |1422 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_1109 | 168| |1423 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_1110 | 257| |1424 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1191 | 167| |1425 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1192 | 18| |1426 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1193 | 29| |1427 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_1111 | 166| |1428 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_1112 | 257| |1429 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1188 | 167| |1430 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1189 | 18| |1431 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1190 | 29| |1432 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_1113 | 166| |1433 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_1114 | 280| |1434 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1185 | 188| |1435 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1186 | 20| |1436 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1187 | 29| |1437 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_1115 | 264| |1438 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_1116 | 134| |1439 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1182 | 69| |1440 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1183 | 20| |1441 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1184 | 18| |1442 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_1117 | 133| |1443 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_1118 | 280| |1444 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1179 | 188| |1445 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1180 | 20| |1446 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1181 | 29| |1447 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_1119 | 168| |1448 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_1120 | 257| |1449 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1176 | 167| |1450 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1177 | 18| |1451 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1178 | 29| |1452 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_1121 | 198| |1453 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_1122 | 280| |1454 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1173 | 188| |1455 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1174 | 20| |1456 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1175 | 29| |1457 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_1123 | 168| |1458 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_1124 | 280| |1459 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1170 | 188| |1460 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1171 | 20| |1461 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1172 | 29| |1462 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_1125 | 167| |1463 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_1126 | 280| |1464 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1167 | 188| |1465 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1168 | 20| |1466 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1169 | 29| |1467 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_1127 | 168| |1468 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_1128 | 280| |1469 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1164 | 188| |1470 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1165 | 20| |1471 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1166 | 29| |1472 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_1129 | 234| |1473 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_1130 | 257| |1474 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1161 | 167| |1475 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1162 | 18| |1476 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1163 | 29| |1477 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_1131 | 166| |1478 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_1132 | 257| |1479 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1158 | 167| |1480 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1159 | 18| |1481 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1160 | 29| |1482 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_1133 | 166| |1483 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_1134 | 257| |1484 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1155 | 167| |1485 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1156 | 18| |1486 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1157 | 29| |1487 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_1135 | 165| |1488 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_1136 | 257| |1489 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1152 | 167| |1490 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1153 | 18| |1491 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1154 | 29| |1492 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_1137 | 198| |1493 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_1138 | 662| |1494 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_1139 | 510| |1495 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_1140 | 535| |1496 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_1141 | 535| |1497 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_1142 | 511| |1498 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_1143 | 535| |1499 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_1144 | 511| |1500 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_1145 | 511| |1501 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_1146 | 511| |1502 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_1147 | 511| |1503 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_1148 | 535| |1504 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_1149 | 535| |1505 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_1150 | 535| |1506 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_1151 | 535| |1507 | \SFP_GEN[5].QIE_RESET_DELAY |delay_counter_15 | 40| |1508 | \SFP_GEN[5].ngCCM_gbt |ngCCM__xdcDup__5 | 8153| |1509 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__61 | 104| |1510 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__302 | 4| |1511 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__62 | 104| |1512 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__301 | 4| |1513 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__63 | 104| |1514 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__300 | 4| |1515 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__64 | 104| |1516 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__299 | 4| |1517 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__65 | 104| |1518 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__298 | 4| |1519 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__66 | 104| |1520 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__297 | 4| |1521 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__67 | 104| |1522 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__296 | 4| |1523 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__68 | 104| |1524 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__295 | 4| |1525 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__69 | 104| |1526 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__294 | 4| |1527 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__70 | 104| |1528 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__293 | 4| |1529 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__71 | 104| |1530 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__292 | 4| |1531 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__72 | 104| |1532 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__291 | 4| |1533 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__73 | 104| |1534 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__290 | 4| |1535 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__74 | 104| |1536 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__289 | 4| |1537 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__75 | 104| |1538 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__288 | 4| |1539 | CrossClock_DV_cnt |CrossClock_RX_1022 | 70| |1540 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__5 | 629| |1541 | JTAGMaster_inst |JTAGMaster__xdcDup__5 | 462| |1542 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__303 | 4| |1543 | JTAG_BRAM |RAM_1106 | 117| |1544 | Sync_RX_Reset |Sync_1023 | 2| |1545 | Sync_TX_Reset |Sync_1024 | 114| |1546 | Sync_error_counter_reset |Sync_1025 | 2| |1547 | gbt_rx_checker |gbt_rx_checker_1026 | 106| |1548 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_1027 | 332| |1549 | i2c_master |i2c_master_usr_1101 | 332| |1550 | byte_ctrl |i2c_master_byte_ctrl_1102 | 279| |1551 | bit_ctrl |i2c_master_bit_ctrl_1103 | 224| |1552 | \bus_status_ctrl.gf_scl |glitch_filter_1104 | 18| |1553 | \bus_status_ctrl.gf_sda |glitch_filter_1105 | 20| |1554 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_1028 | 332| |1555 | i2c_master |i2c_master_usr_1096 | 332| |1556 | byte_ctrl |i2c_master_byte_ctrl_1097 | 279| |1557 | bit_ctrl |i2c_master_bit_ctrl_1098 | 224| |1558 | \bus_status_ctrl.gf_scl |glitch_filter_1099 | 18| |1559 | \bus_status_ctrl.gf_sda |glitch_filter_1100 | 20| |1560 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_1029 | 332| |1561 | i2c_master |i2c_master_usr_1091 | 332| |1562 | byte_ctrl |i2c_master_byte_ctrl_1092 | 279| |1563 | bit_ctrl |i2c_master_bit_ctrl_1093 | 224| |1564 | \bus_status_ctrl.gf_scl |glitch_filter_1094 | 18| |1565 | \bus_status_ctrl.gf_sda |glitch_filter_1095 | 20| |1566 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_1030 | 332| |1567 | i2c_master |i2c_master_usr_1086 | 332| |1568 | byte_ctrl |i2c_master_byte_ctrl_1087 | 279| |1569 | bit_ctrl |i2c_master_bit_ctrl_1088 | 224| |1570 | \bus_status_ctrl.gf_scl |glitch_filter_1089 | 18| |1571 | \bus_status_ctrl.gf_sda |glitch_filter_1090 | 20| |1572 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_1031 | 332| |1573 | i2c_master |i2c_master_usr_1081 | 332| |1574 | byte_ctrl |i2c_master_byte_ctrl_1082 | 279| |1575 | bit_ctrl |i2c_master_bit_ctrl_1083 | 224| |1576 | \bus_status_ctrl.gf_scl |glitch_filter_1084 | 18| |1577 | \bus_status_ctrl.gf_sda |glitch_filter_1085 | 20| |1578 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_1032 | 332| |1579 | i2c_master |i2c_master_usr_1076 | 332| |1580 | byte_ctrl |i2c_master_byte_ctrl_1077 | 279| |1581 | bit_ctrl |i2c_master_bit_ctrl_1078 | 224| |1582 | \bus_status_ctrl.gf_scl |glitch_filter_1079 | 18| |1583 | \bus_status_ctrl.gf_sda |glitch_filter_1080 | 20| |1584 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_1033 | 332| |1585 | i2c_master |i2c_master_usr_1071 | 332| |1586 | byte_ctrl |i2c_master_byte_ctrl_1072 | 279| |1587 | bit_ctrl |i2c_master_bit_ctrl_1073 | 224| |1588 | \bus_status_ctrl.gf_scl |glitch_filter_1074 | 18| |1589 | \bus_status_ctrl.gf_sda |glitch_filter_1075 | 20| |1590 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_1034 | 332| |1591 | i2c_master |i2c_master_usr_1066 | 332| |1592 | byte_ctrl |i2c_master_byte_ctrl_1067 | 279| |1593 | bit_ctrl |i2c_master_bit_ctrl_1068 | 224| |1594 | \bus_status_ctrl.gf_scl |glitch_filter_1069 | 18| |1595 | \bus_status_ctrl.gf_sda |glitch_filter_1070 | 20| |1596 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_1035 | 332| |1597 | i2c_master |i2c_master_usr_1061 | 332| |1598 | byte_ctrl |i2c_master_byte_ctrl_1062 | 279| |1599 | bit_ctrl |i2c_master_bit_ctrl_1063 | 224| |1600 | \bus_status_ctrl.gf_scl |glitch_filter_1064 | 18| |1601 | \bus_status_ctrl.gf_sda |glitch_filter_1065 | 20| |1602 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_1036 | 332| |1603 | i2c_master |i2c_master_usr_1056 | 332| |1604 | byte_ctrl |i2c_master_byte_ctrl_1057 | 279| |1605 | bit_ctrl |i2c_master_bit_ctrl_1058 | 224| |1606 | \bus_status_ctrl.gf_scl |glitch_filter_1059 | 18| |1607 | \bus_status_ctrl.gf_sda |glitch_filter_1060 | 20| |1608 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_1037 | 332| |1609 | i2c_master |i2c_master_usr_1051 | 332| |1610 | byte_ctrl |i2c_master_byte_ctrl_1052 | 279| |1611 | bit_ctrl |i2c_master_bit_ctrl_1053 | 224| |1612 | \bus_status_ctrl.gf_scl |glitch_filter_1054 | 18| |1613 | \bus_status_ctrl.gf_sda |glitch_filter_1055 | 20| |1614 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_1038 | 332| |1615 | i2c_master |i2c_master_usr_1046 | 332| |1616 | byte_ctrl |i2c_master_byte_ctrl_1047 | 279| |1617 | bit_ctrl |i2c_master_bit_ctrl_1048 | 224| |1618 | \bus_status_ctrl.gf_scl |glitch_filter_1049 | 18| |1619 | \bus_status_ctrl.gf_sda |glitch_filter_1050 | 20| |1620 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_1039 | 331| |1621 | i2c_master |i2c_master_usr_1041 | 331| |1622 | byte_ctrl |i2c_master_byte_ctrl_1042 | 279| |1623 | bit_ctrl |i2c_master_bit_ctrl_1043 | 224| |1624 | \bus_status_ctrl.gf_scl |glitch_filter_1044 | 18| |1625 | \bus_status_ctrl.gf_sda |glitch_filter_1045 | 20| |1626 | prbs |prbs_1040 | 25| |1627 | \SFP_GEN[5].ngFEC_module |ngFEC_module_16 | 15549| |1628 | bkp_buffer_ngccm |buffer_ngccm_com_932 | 511| |1629 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_933 | 281| |1630 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1019 | 194| |1631 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1020 | 20| |1632 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1021 | 24| |1633 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_934 | 168| |1634 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_935 | 257| |1635 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1016 | 167| |1636 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1017 | 18| |1637 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1018 | 29| |1638 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_936 | 166| |1639 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_937 | 257| |1640 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1013 | 167| |1641 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1014 | 18| |1642 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1015 | 29| |1643 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_938 | 166| |1644 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_939 | 280| |1645 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1010 | 188| |1646 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1011 | 20| |1647 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1012 | 29| |1648 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_940 | 264| |1649 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_941 | 134| |1650 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1007 | 69| |1651 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1008 | 20| |1652 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1009 | 18| |1653 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_942 | 133| |1654 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_943 | 280| |1655 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1004 | 188| |1656 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1005 | 20| |1657 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1006 | 29| |1658 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_944 | 168| |1659 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_945 | 257| |1660 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_1001 | 167| |1661 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_1002 | 18| |1662 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1003 | 29| |1663 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_946 | 198| |1664 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_947 | 280| |1665 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_998 | 188| |1666 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_999 | 20| |1667 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_1000 | 29| |1668 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_948 | 168| |1669 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_949 | 280| |1670 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_995 | 188| |1671 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_996 | 20| |1672 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_997 | 29| |1673 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_950 | 167| |1674 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_951 | 280| |1675 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_992 | 188| |1676 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_993 | 20| |1677 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_994 | 29| |1678 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_952 | 168| |1679 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_953 | 280| |1680 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_989 | 188| |1681 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_990 | 20| |1682 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_991 | 29| |1683 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_954 | 234| |1684 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_955 | 257| |1685 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_986 | 167| |1686 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_987 | 18| |1687 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_988 | 29| |1688 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_956 | 166| |1689 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_957 | 257| |1690 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_983 | 167| |1691 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_984 | 18| |1692 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_985 | 29| |1693 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_958 | 166| |1694 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_959 | 257| |1695 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_980 | 167| |1696 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_981 | 18| |1697 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_982 | 29| |1698 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_960 | 165| |1699 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_961 | 257| |1700 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_977 | 167| |1701 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_978 | 18| |1702 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_979 | 29| |1703 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_962 | 198| |1704 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_963 | 662| |1705 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_964 | 510| |1706 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_965 | 535| |1707 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_966 | 535| |1708 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_967 | 511| |1709 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_968 | 535| |1710 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_969 | 511| |1711 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_970 | 511| |1712 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_971 | 511| |1713 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_972 | 511| |1714 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_973 | 535| |1715 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_974 | 535| |1716 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_975 | 535| |1717 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_976 | 535| |1718 | \SFP_GEN[6].QIE_RESET_DELAY |delay_counter_17 | 40| |1719 | \SFP_GEN[6].ngCCM_gbt |ngCCM__xdcDup__6 | 8153| |1720 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__76 | 104| |1721 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__286 | 4| |1722 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__77 | 104| |1723 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__285 | 4| |1724 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__78 | 104| |1725 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__284 | 4| |1726 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__79 | 104| |1727 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__283 | 4| |1728 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__80 | 104| |1729 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__282 | 4| |1730 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__81 | 104| |1731 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__281 | 4| |1732 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__82 | 104| |1733 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__280 | 4| |1734 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__83 | 104| |1735 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__279 | 4| |1736 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__84 | 104| |1737 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__278 | 4| |1738 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__85 | 104| |1739 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__277 | 4| |1740 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__86 | 104| |1741 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__276 | 4| |1742 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__87 | 104| |1743 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__275 | 4| |1744 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__88 | 104| |1745 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__274 | 4| |1746 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__89 | 104| |1747 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__273 | 4| |1748 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__90 | 104| |1749 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__272 | 4| |1750 | CrossClock_DV_cnt |CrossClock_RX_847 | 70| |1751 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__6 | 629| |1752 | JTAGMaster_inst |JTAGMaster__xdcDup__6 | 462| |1753 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__287 | 4| |1754 | JTAG_BRAM |RAM_931 | 117| |1755 | Sync_RX_Reset |Sync_848 | 2| |1756 | Sync_TX_Reset |Sync_849 | 114| |1757 | Sync_error_counter_reset |Sync_850 | 2| |1758 | gbt_rx_checker |gbt_rx_checker_851 | 106| |1759 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_852 | 332| |1760 | i2c_master |i2c_master_usr_926 | 332| |1761 | byte_ctrl |i2c_master_byte_ctrl_927 | 279| |1762 | bit_ctrl |i2c_master_bit_ctrl_928 | 224| |1763 | \bus_status_ctrl.gf_scl |glitch_filter_929 | 18| |1764 | \bus_status_ctrl.gf_sda |glitch_filter_930 | 20| |1765 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_853 | 332| |1766 | i2c_master |i2c_master_usr_921 | 332| |1767 | byte_ctrl |i2c_master_byte_ctrl_922 | 279| |1768 | bit_ctrl |i2c_master_bit_ctrl_923 | 224| |1769 | \bus_status_ctrl.gf_scl |glitch_filter_924 | 18| |1770 | \bus_status_ctrl.gf_sda |glitch_filter_925 | 20| |1771 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_854 | 332| |1772 | i2c_master |i2c_master_usr_916 | 332| |1773 | byte_ctrl |i2c_master_byte_ctrl_917 | 279| |1774 | bit_ctrl |i2c_master_bit_ctrl_918 | 224| |1775 | \bus_status_ctrl.gf_scl |glitch_filter_919 | 18| |1776 | \bus_status_ctrl.gf_sda |glitch_filter_920 | 20| |1777 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_855 | 332| |1778 | i2c_master |i2c_master_usr_911 | 332| |1779 | byte_ctrl |i2c_master_byte_ctrl_912 | 279| |1780 | bit_ctrl |i2c_master_bit_ctrl_913 | 224| |1781 | \bus_status_ctrl.gf_scl |glitch_filter_914 | 18| |1782 | \bus_status_ctrl.gf_sda |glitch_filter_915 | 20| |1783 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_856 | 332| |1784 | i2c_master |i2c_master_usr_906 | 332| |1785 | byte_ctrl |i2c_master_byte_ctrl_907 | 279| |1786 | bit_ctrl |i2c_master_bit_ctrl_908 | 224| |1787 | \bus_status_ctrl.gf_scl |glitch_filter_909 | 18| |1788 | \bus_status_ctrl.gf_sda |glitch_filter_910 | 20| |1789 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_857 | 332| |1790 | i2c_master |i2c_master_usr_901 | 332| |1791 | byte_ctrl |i2c_master_byte_ctrl_902 | 279| |1792 | bit_ctrl |i2c_master_bit_ctrl_903 | 224| |1793 | \bus_status_ctrl.gf_scl |glitch_filter_904 | 18| |1794 | \bus_status_ctrl.gf_sda |glitch_filter_905 | 20| |1795 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_858 | 332| |1796 | i2c_master |i2c_master_usr_896 | 332| |1797 | byte_ctrl |i2c_master_byte_ctrl_897 | 279| |1798 | bit_ctrl |i2c_master_bit_ctrl_898 | 224| |1799 | \bus_status_ctrl.gf_scl |glitch_filter_899 | 18| |1800 | \bus_status_ctrl.gf_sda |glitch_filter_900 | 20| |1801 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_859 | 332| |1802 | i2c_master |i2c_master_usr_891 | 332| |1803 | byte_ctrl |i2c_master_byte_ctrl_892 | 279| |1804 | bit_ctrl |i2c_master_bit_ctrl_893 | 224| |1805 | \bus_status_ctrl.gf_scl |glitch_filter_894 | 18| |1806 | \bus_status_ctrl.gf_sda |glitch_filter_895 | 20| |1807 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_860 | 332| |1808 | i2c_master |i2c_master_usr_886 | 332| |1809 | byte_ctrl |i2c_master_byte_ctrl_887 | 279| |1810 | bit_ctrl |i2c_master_bit_ctrl_888 | 224| |1811 | \bus_status_ctrl.gf_scl |glitch_filter_889 | 18| |1812 | \bus_status_ctrl.gf_sda |glitch_filter_890 | 20| |1813 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_861 | 332| |1814 | i2c_master |i2c_master_usr_881 | 332| |1815 | byte_ctrl |i2c_master_byte_ctrl_882 | 279| |1816 | bit_ctrl |i2c_master_bit_ctrl_883 | 224| |1817 | \bus_status_ctrl.gf_scl |glitch_filter_884 | 18| |1818 | \bus_status_ctrl.gf_sda |glitch_filter_885 | 20| |1819 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_862 | 332| |1820 | i2c_master |i2c_master_usr_876 | 332| |1821 | byte_ctrl |i2c_master_byte_ctrl_877 | 279| |1822 | bit_ctrl |i2c_master_bit_ctrl_878 | 224| |1823 | \bus_status_ctrl.gf_scl |glitch_filter_879 | 18| |1824 | \bus_status_ctrl.gf_sda |glitch_filter_880 | 20| |1825 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_863 | 332| |1826 | i2c_master |i2c_master_usr_871 | 332| |1827 | byte_ctrl |i2c_master_byte_ctrl_872 | 279| |1828 | bit_ctrl |i2c_master_bit_ctrl_873 | 224| |1829 | \bus_status_ctrl.gf_scl |glitch_filter_874 | 18| |1830 | \bus_status_ctrl.gf_sda |glitch_filter_875 | 20| |1831 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_864 | 331| |1832 | i2c_master |i2c_master_usr_866 | 331| |1833 | byte_ctrl |i2c_master_byte_ctrl_867 | 279| |1834 | bit_ctrl |i2c_master_bit_ctrl_868 | 224| |1835 | \bus_status_ctrl.gf_scl |glitch_filter_869 | 18| |1836 | \bus_status_ctrl.gf_sda |glitch_filter_870 | 20| |1837 | prbs |prbs_865 | 25| |1838 | \SFP_GEN[6].ngFEC_module |ngFEC_module_18 | 15549| |1839 | bkp_buffer_ngccm |buffer_ngccm_com_757 | 511| |1840 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_758 | 281| |1841 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_844 | 194| |1842 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_845 | 20| |1843 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_846 | 24| |1844 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_759 | 168| |1845 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_760 | 257| |1846 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_841 | 167| |1847 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_842 | 18| |1848 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_843 | 29| |1849 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_761 | 166| |1850 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_762 | 257| |1851 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_838 | 167| |1852 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_839 | 18| |1853 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_840 | 29| |1854 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_763 | 166| |1855 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_764 | 280| |1856 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_835 | 188| |1857 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_836 | 20| |1858 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_837 | 29| |1859 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_765 | 264| |1860 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_766 | 134| |1861 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_832 | 69| |1862 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_833 | 20| |1863 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_834 | 18| |1864 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_767 | 133| |1865 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_768 | 280| |1866 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_829 | 188| |1867 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_830 | 20| |1868 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_831 | 29| |1869 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_769 | 168| |1870 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_770 | 257| |1871 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_826 | 167| |1872 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_827 | 18| |1873 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_828 | 29| |1874 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_771 | 198| |1875 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_772 | 280| |1876 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_823 | 188| |1877 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_824 | 20| |1878 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_825 | 29| |1879 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_773 | 168| |1880 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_774 | 280| |1881 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_820 | 188| |1882 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_821 | 20| |1883 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_822 | 29| |1884 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_775 | 167| |1885 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_776 | 280| |1886 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_817 | 188| |1887 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_818 | 20| |1888 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_819 | 29| |1889 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_777 | 168| |1890 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_778 | 280| |1891 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_814 | 188| |1892 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_815 | 20| |1893 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_816 | 29| |1894 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_779 | 234| |1895 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_780 | 257| |1896 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_811 | 167| |1897 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_812 | 18| |1898 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_813 | 29| |1899 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_781 | 166| |1900 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_782 | 257| |1901 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_808 | 167| |1902 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_809 | 18| |1903 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_810 | 29| |1904 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_783 | 166| |1905 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_784 | 257| |1906 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_805 | 167| |1907 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_806 | 18| |1908 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_807 | 29| |1909 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_785 | 165| |1910 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_786 | 257| |1911 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_802 | 167| |1912 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_803 | 18| |1913 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_804 | 29| |1914 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_787 | 198| |1915 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_788 | 662| |1916 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_789 | 510| |1917 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_790 | 535| |1918 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_791 | 535| |1919 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_792 | 511| |1920 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_793 | 535| |1921 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_794 | 511| |1922 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_795 | 511| |1923 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_796 | 511| |1924 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_797 | 511| |1925 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_798 | 535| |1926 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_799 | 535| |1927 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_800 | 535| |1928 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_801 | 535| |1929 | \SFP_GEN[7].QIE_RESET_DELAY |delay_counter_19 | 40| |1930 | \SFP_GEN[7].ngCCM_gbt |ngCCM__xdcDup__7 | 8153| |1931 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__91 | 104| |1932 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__270 | 4| |1933 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__92 | 104| |1934 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__269 | 4| |1935 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__93 | 104| |1936 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__268 | 4| |1937 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__94 | 104| |1938 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__267 | 4| |1939 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__95 | 104| |1940 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__266 | 4| |1941 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__96 | 104| |1942 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__265 | 4| |1943 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__97 | 104| |1944 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__264 | 4| |1945 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__98 | 104| |1946 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__263 | 4| |1947 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__99 | 104| |1948 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__262 | 4| |1949 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__100 | 104| |1950 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__261 | 4| |1951 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__101 | 104| |1952 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__260 | 4| |1953 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__102 | 104| |1954 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__259 | 4| |1955 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__103 | 104| |1956 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__258 | 4| |1957 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__104 | 104| |1958 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__257 | 4| |1959 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__105 | 104| |1960 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__256 | 4| |1961 | CrossClock_DV_cnt |CrossClock_RX_672 | 70| |1962 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__7 | 629| |1963 | JTAGMaster_inst |JTAGMaster__xdcDup__7 | 462| |1964 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__271 | 4| |1965 | JTAG_BRAM |RAM_756 | 117| |1966 | Sync_RX_Reset |Sync_673 | 2| |1967 | Sync_TX_Reset |Sync_674 | 114| |1968 | Sync_error_counter_reset |Sync_675 | 2| |1969 | gbt_rx_checker |gbt_rx_checker_676 | 106| |1970 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_677 | 332| |1971 | i2c_master |i2c_master_usr_751 | 332| |1972 | byte_ctrl |i2c_master_byte_ctrl_752 | 279| |1973 | bit_ctrl |i2c_master_bit_ctrl_753 | 224| |1974 | \bus_status_ctrl.gf_scl |glitch_filter_754 | 18| |1975 | \bus_status_ctrl.gf_sda |glitch_filter_755 | 20| |1976 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_678 | 332| |1977 | i2c_master |i2c_master_usr_746 | 332| |1978 | byte_ctrl |i2c_master_byte_ctrl_747 | 279| |1979 | bit_ctrl |i2c_master_bit_ctrl_748 | 224| |1980 | \bus_status_ctrl.gf_scl |glitch_filter_749 | 18| |1981 | \bus_status_ctrl.gf_sda |glitch_filter_750 | 20| |1982 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_679 | 332| |1983 | i2c_master |i2c_master_usr_741 | 332| |1984 | byte_ctrl |i2c_master_byte_ctrl_742 | 279| |1985 | bit_ctrl |i2c_master_bit_ctrl_743 | 224| |1986 | \bus_status_ctrl.gf_scl |glitch_filter_744 | 18| |1987 | \bus_status_ctrl.gf_sda |glitch_filter_745 | 20| |1988 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_680 | 332| |1989 | i2c_master |i2c_master_usr_736 | 332| |1990 | byte_ctrl |i2c_master_byte_ctrl_737 | 279| |1991 | bit_ctrl |i2c_master_bit_ctrl_738 | 224| |1992 | \bus_status_ctrl.gf_scl |glitch_filter_739 | 18| |1993 | \bus_status_ctrl.gf_sda |glitch_filter_740 | 20| |1994 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_681 | 332| |1995 | i2c_master |i2c_master_usr_731 | 332| |1996 | byte_ctrl |i2c_master_byte_ctrl_732 | 279| |1997 | bit_ctrl |i2c_master_bit_ctrl_733 | 224| |1998 | \bus_status_ctrl.gf_scl |glitch_filter_734 | 18| |1999 | \bus_status_ctrl.gf_sda |glitch_filter_735 | 20| |2000 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_682 | 332| |2001 | i2c_master |i2c_master_usr_726 | 332| |2002 | byte_ctrl |i2c_master_byte_ctrl_727 | 279| |2003 | bit_ctrl |i2c_master_bit_ctrl_728 | 224| |2004 | \bus_status_ctrl.gf_scl |glitch_filter_729 | 18| |2005 | \bus_status_ctrl.gf_sda |glitch_filter_730 | 20| |2006 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_683 | 332| |2007 | i2c_master |i2c_master_usr_721 | 332| |2008 | byte_ctrl |i2c_master_byte_ctrl_722 | 279| |2009 | bit_ctrl |i2c_master_bit_ctrl_723 | 224| |2010 | \bus_status_ctrl.gf_scl |glitch_filter_724 | 18| |2011 | \bus_status_ctrl.gf_sda |glitch_filter_725 | 20| |2012 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_684 | 332| |2013 | i2c_master |i2c_master_usr_716 | 332| |2014 | byte_ctrl |i2c_master_byte_ctrl_717 | 279| |2015 | bit_ctrl |i2c_master_bit_ctrl_718 | 224| |2016 | \bus_status_ctrl.gf_scl |glitch_filter_719 | 18| |2017 | \bus_status_ctrl.gf_sda |glitch_filter_720 | 20| |2018 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_685 | 332| |2019 | i2c_master |i2c_master_usr_711 | 332| |2020 | byte_ctrl |i2c_master_byte_ctrl_712 | 279| |2021 | bit_ctrl |i2c_master_bit_ctrl_713 | 224| |2022 | \bus_status_ctrl.gf_scl |glitch_filter_714 | 18| |2023 | \bus_status_ctrl.gf_sda |glitch_filter_715 | 20| |2024 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_686 | 332| |2025 | i2c_master |i2c_master_usr_706 | 332| |2026 | byte_ctrl |i2c_master_byte_ctrl_707 | 279| |2027 | bit_ctrl |i2c_master_bit_ctrl_708 | 224| |2028 | \bus_status_ctrl.gf_scl |glitch_filter_709 | 18| |2029 | \bus_status_ctrl.gf_sda |glitch_filter_710 | 20| |2030 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_687 | 332| |2031 | i2c_master |i2c_master_usr_701 | 332| |2032 | byte_ctrl |i2c_master_byte_ctrl_702 | 279| |2033 | bit_ctrl |i2c_master_bit_ctrl_703 | 224| |2034 | \bus_status_ctrl.gf_scl |glitch_filter_704 | 18| |2035 | \bus_status_ctrl.gf_sda |glitch_filter_705 | 20| |2036 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_688 | 332| |2037 | i2c_master |i2c_master_usr_696 | 332| |2038 | byte_ctrl |i2c_master_byte_ctrl_697 | 279| |2039 | bit_ctrl |i2c_master_bit_ctrl_698 | 224| |2040 | \bus_status_ctrl.gf_scl |glitch_filter_699 | 18| |2041 | \bus_status_ctrl.gf_sda |glitch_filter_700 | 20| |2042 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_689 | 331| |2043 | i2c_master |i2c_master_usr_691 | 331| |2044 | byte_ctrl |i2c_master_byte_ctrl_692 | 279| |2045 | bit_ctrl |i2c_master_bit_ctrl_693 | 224| |2046 | \bus_status_ctrl.gf_scl |glitch_filter_694 | 18| |2047 | \bus_status_ctrl.gf_sda |glitch_filter_695 | 20| |2048 | prbs |prbs_690 | 25| |2049 | \SFP_GEN[7].ngFEC_module |ngFEC_module_20 | 15549| |2050 | bkp_buffer_ngccm |buffer_ngccm_com_582 | 511| |2051 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_583 | 281| |2052 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_669 | 194| |2053 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_670 | 20| |2054 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_671 | 24| |2055 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_584 | 168| |2056 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_585 | 257| |2057 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_666 | 167| |2058 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_667 | 18| |2059 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_668 | 29| |2060 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_586 | 166| |2061 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_587 | 257| |2062 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_663 | 167| |2063 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_664 | 18| |2064 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_665 | 29| |2065 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_588 | 166| |2066 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_589 | 280| |2067 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_660 | 188| |2068 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_661 | 20| |2069 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_662 | 29| |2070 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_590 | 264| |2071 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_591 | 134| |2072 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_657 | 69| |2073 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_658 | 20| |2074 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_659 | 18| |2075 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_592 | 133| |2076 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_593 | 280| |2077 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_654 | 188| |2078 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_655 | 20| |2079 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_656 | 29| |2080 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_594 | 168| |2081 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_595 | 257| |2082 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_651 | 167| |2083 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_652 | 18| |2084 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_653 | 29| |2085 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_596 | 198| |2086 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_597 | 280| |2087 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_648 | 188| |2088 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_649 | 20| |2089 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_650 | 29| |2090 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_598 | 168| |2091 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_599 | 280| |2092 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_645 | 188| |2093 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_646 | 20| |2094 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_647 | 29| |2095 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_600 | 167| |2096 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_601 | 280| |2097 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_642 | 188| |2098 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_643 | 20| |2099 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_644 | 29| |2100 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_602 | 168| |2101 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_603 | 280| |2102 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_639 | 188| |2103 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_640 | 20| |2104 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_641 | 29| |2105 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_604 | 234| |2106 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_605 | 257| |2107 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_636 | 167| |2108 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_637 | 18| |2109 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_638 | 29| |2110 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_606 | 166| |2111 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_607 | 257| |2112 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_633 | 167| |2113 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_634 | 18| |2114 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_635 | 29| |2115 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_608 | 166| |2116 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_609 | 257| |2117 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_630 | 167| |2118 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_631 | 18| |2119 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_632 | 29| |2120 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_610 | 165| |2121 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_611 | 257| |2122 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_627 | 167| |2123 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_628 | 18| |2124 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_629 | 29| |2125 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_612 | 198| |2126 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_613 | 662| |2127 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_614 | 510| |2128 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_615 | 535| |2129 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_616 | 535| |2130 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_617 | 511| |2131 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_618 | 535| |2132 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_619 | 511| |2133 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_620 | 511| |2134 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_621 | 511| |2135 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_622 | 511| |2136 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_623 | 535| |2137 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_624 | 535| |2138 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_625 | 535| |2139 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_626 | 535| |2140 | \SFP_GEN[8].QIE_RESET_DELAY |delay_counter_21 | 40| |2141 | \SFP_GEN[8].ngCCM_gbt |ngCCM__xdcDup__8 | 8153| |2142 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__106 | 104| |2143 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__254 | 4| |2144 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__107 | 104| |2145 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__253 | 4| |2146 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__108 | 104| |2147 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__252 | 4| |2148 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__109 | 104| |2149 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__251 | 4| |2150 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__110 | 104| |2151 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__250 | 4| |2152 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__111 | 104| |2153 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__249 | 4| |2154 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__112 | 104| |2155 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__248 | 4| |2156 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__113 | 104| |2157 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__247 | 4| |2158 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__114 | 104| |2159 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__246 | 4| |2160 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__115 | 104| |2161 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__245 | 4| |2162 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__116 | 104| |2163 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__244 | 4| |2164 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__117 | 104| |2165 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__243 | 4| |2166 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__118 | 104| |2167 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__242 | 4| |2168 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__119 | 104| |2169 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__241 | 4| |2170 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__120 | 104| |2171 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__240 | 4| |2172 | CrossClock_DV_cnt |CrossClock_RX_497 | 70| |2173 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__8 | 629| |2174 | JTAGMaster_inst |JTAGMaster__xdcDup__8 | 462| |2175 | tck_in_Sync_inst |xpm_cdc_single__parameterized1__255 | 4| |2176 | JTAG_BRAM |RAM_581 | 117| |2177 | Sync_RX_Reset |Sync_498 | 2| |2178 | Sync_TX_Reset |Sync_499 | 114| |2179 | Sync_error_counter_reset |Sync_500 | 2| |2180 | gbt_rx_checker |gbt_rx_checker_501 | 106| |2181 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge_502 | 332| |2182 | i2c_master |i2c_master_usr_576 | 332| |2183 | byte_ctrl |i2c_master_byte_ctrl_577 | 279| |2184 | bit_ctrl |i2c_master_bit_ctrl_578 | 224| |2185 | \bus_status_ctrl.gf_scl |glitch_filter_579 | 18| |2186 | \bus_status_ctrl.gf_sda |glitch_filter_580 | 20| |2187 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_503 | 332| |2188 | i2c_master |i2c_master_usr_571 | 332| |2189 | byte_ctrl |i2c_master_byte_ctrl_572 | 279| |2190 | bit_ctrl |i2c_master_bit_ctrl_573 | 224| |2191 | \bus_status_ctrl.gf_scl |glitch_filter_574 | 18| |2192 | \bus_status_ctrl.gf_sda |glitch_filter_575 | 20| |2193 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_504 | 332| |2194 | i2c_master |i2c_master_usr_566 | 332| |2195 | byte_ctrl |i2c_master_byte_ctrl_567 | 279| |2196 | bit_ctrl |i2c_master_bit_ctrl_568 | 224| |2197 | \bus_status_ctrl.gf_scl |glitch_filter_569 | 18| |2198 | \bus_status_ctrl.gf_sda |glitch_filter_570 | 20| |2199 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_505 | 332| |2200 | i2c_master |i2c_master_usr_561 | 332| |2201 | byte_ctrl |i2c_master_byte_ctrl_562 | 279| |2202 | bit_ctrl |i2c_master_bit_ctrl_563 | 224| |2203 | \bus_status_ctrl.gf_scl |glitch_filter_564 | 18| |2204 | \bus_status_ctrl.gf_sda |glitch_filter_565 | 20| |2205 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_506 | 332| |2206 | i2c_master |i2c_master_usr_556 | 332| |2207 | byte_ctrl |i2c_master_byte_ctrl_557 | 279| |2208 | bit_ctrl |i2c_master_bit_ctrl_558 | 224| |2209 | \bus_status_ctrl.gf_scl |glitch_filter_559 | 18| |2210 | \bus_status_ctrl.gf_sda |glitch_filter_560 | 20| |2211 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_507 | 332| |2212 | i2c_master |i2c_master_usr_551 | 332| |2213 | byte_ctrl |i2c_master_byte_ctrl_552 | 279| |2214 | bit_ctrl |i2c_master_bit_ctrl_553 | 224| |2215 | \bus_status_ctrl.gf_scl |glitch_filter_554 | 18| |2216 | \bus_status_ctrl.gf_sda |glitch_filter_555 | 20| |2217 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_508 | 332| |2218 | i2c_master |i2c_master_usr_546 | 332| |2219 | byte_ctrl |i2c_master_byte_ctrl_547 | 279| |2220 | bit_ctrl |i2c_master_bit_ctrl_548 | 224| |2221 | \bus_status_ctrl.gf_scl |glitch_filter_549 | 18| |2222 | \bus_status_ctrl.gf_sda |glitch_filter_550 | 20| |2223 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_509 | 332| |2224 | i2c_master |i2c_master_usr_541 | 332| |2225 | byte_ctrl |i2c_master_byte_ctrl_542 | 279| |2226 | bit_ctrl |i2c_master_bit_ctrl_543 | 224| |2227 | \bus_status_ctrl.gf_scl |glitch_filter_544 | 18| |2228 | \bus_status_ctrl.gf_sda |glitch_filter_545 | 20| |2229 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_510 | 332| |2230 | i2c_master |i2c_master_usr_536 | 332| |2231 | byte_ctrl |i2c_master_byte_ctrl_537 | 279| |2232 | bit_ctrl |i2c_master_bit_ctrl_538 | 224| |2233 | \bus_status_ctrl.gf_scl |glitch_filter_539 | 18| |2234 | \bus_status_ctrl.gf_sda |glitch_filter_540 | 20| |2235 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_511 | 332| |2236 | i2c_master |i2c_master_usr_531 | 332| |2237 | byte_ctrl |i2c_master_byte_ctrl_532 | 279| |2238 | bit_ctrl |i2c_master_bit_ctrl_533 | 224| |2239 | \bus_status_ctrl.gf_scl |glitch_filter_534 | 18| |2240 | \bus_status_ctrl.gf_sda |glitch_filter_535 | 20| |2241 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_512 | 332| |2242 | i2c_master |i2c_master_usr_526 | 332| |2243 | byte_ctrl |i2c_master_byte_ctrl_527 | 279| |2244 | bit_ctrl |i2c_master_bit_ctrl_528 | 224| |2245 | \bus_status_ctrl.gf_scl |glitch_filter_529 | 18| |2246 | \bus_status_ctrl.gf_sda |glitch_filter_530 | 20| |2247 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_513 | 332| |2248 | i2c_master |i2c_master_usr_521 | 332| |2249 | byte_ctrl |i2c_master_byte_ctrl_522 | 279| |2250 | bit_ctrl |i2c_master_bit_ctrl_523 | 224| |2251 | \bus_status_ctrl.gf_scl |glitch_filter_524 | 18| |2252 | \bus_status_ctrl.gf_sda |glitch_filter_525 | 20| |2253 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_514 | 331| |2254 | i2c_master |i2c_master_usr_516 | 331| |2255 | byte_ctrl |i2c_master_byte_ctrl_517 | 279| |2256 | bit_ctrl |i2c_master_bit_ctrl_518 | 224| |2257 | \bus_status_ctrl.gf_scl |glitch_filter_519 | 18| |2258 | \bus_status_ctrl.gf_sda |glitch_filter_520 | 20| |2259 | prbs |prbs_515 | 25| |2260 | \SFP_GEN[8].ngFEC_module |ngFEC_module_22 | 15549| |2261 | bkp_buffer_ngccm |buffer_ngccm_com_407 | 511| |2262 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM_408 | 281| |2263 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_494 | 194| |2264 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_495 | 20| |2265 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_496 | 24| |2266 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com_409 | 168| |2267 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_410 | 257| |2268 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_491 | 167| |2269 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_492 | 18| |2270 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_493 | 29| |2271 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19_411 | 166| |2272 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_412 | 257| |2273 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_488 | 167| |2274 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_489 | 18| |2275 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_490 | 29| |2276 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21_413 | 166| |2277 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_414 | 280| |2278 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_485 | 188| |2279 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_486 | 20| |2280 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_487 | 29| |2281 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23_415 | 264| |2282 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_416 | 134| |2283 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_482 | 69| |2284 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_483 | 20| |2285 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_484 | 18| |2286 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25_417 | 133| |2287 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_418 | 280| |2288 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_479 | 188| |2289 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_480 | 20| |2290 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_481 | 29| |2291 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27_419 | 168| |2292 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_420 | 257| |2293 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_476 | 167| |2294 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_477 | 18| |2295 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_478 | 29| |2296 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1_421 | 198| |2297 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_422 | 280| |2298 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_473 | 188| |2299 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_474 | 20| |2300 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_475 | 29| |2301 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3_423 | 168| |2302 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_424 | 280| |2303 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_470 | 188| |2304 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_471 | 20| |2305 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_472 | 29| |2306 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5_425 | 167| |2307 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_426 | 280| |2308 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_467 | 188| |2309 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_468 | 20| |2310 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_469 | 29| |2311 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7_427 | 168| |2312 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_428 | 280| |2313 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_464 | 188| |2314 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_465 | 20| |2315 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_466 | 29| |2316 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9_429 | 234| |2317 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_430 | 257| |2318 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_461 | 167| |2319 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_462 | 18| |2320 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_463 | 29| |2321 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11_431 | 166| |2322 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_432 | 257| |2323 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_458 | 167| |2324 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_459 | 18| |2325 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_460 | 29| |2326 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13_433 | 166| |2327 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_434 | 257| |2328 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_455 | 167| |2329 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_456 | 18| |2330 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_457 | 29| |2331 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15_435 | 165| |2332 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_436 | 257| |2333 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_452 | 167| |2334 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_453 | 18| |2335 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_454 | 29| |2336 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17_437 | 198| |2337 | buffer_ngccm_jtag |buffer_ngccm_jtag_com_438 | 662| |2338 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_439 | 510| |2339 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_440 | 535| |2340 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_441 | 535| |2341 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_442 | 511| |2342 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_443 | 535| |2343 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_444 | 511| |2344 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_445 | 511| |2345 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_446 | 511| |2346 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_447 | 511| |2347 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_448 | 535| |2348 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_449 | 535| |2349 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_450 | 535| |2350 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_451 | 535| |2351 | \SFP_GEN[9].QIE_RESET_DELAY |delay_counter_23 | 40| |2352 | \SFP_GEN[9].ngCCM_gbt |ngCCM__xdcDup__9 | 8153| |2353 | \IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__121 | 104| |2354 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__430 | 4| |2355 | \IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__122 | 104| |2356 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__429 | 4| |2357 | \IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__123 | 104| |2358 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__428 | 4| |2359 | \IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__124 | 104| |2360 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__427 | 4| |2361 | \IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__125 | 104| |2362 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__426 | 4| |2363 | \IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__126 | 104| |2364 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__425 | 4| |2365 | \IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__127 | 104| |2366 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__424 | 4| |2367 | \IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__128 | 104| |2368 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__423 | 4| |2369 | \IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__129 | 104| |2370 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__422 | 4| |2371 | \IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__130 | 104| |2372 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__421 | 4| |2373 | \IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__131 | 104| |2374 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__420 | 4| |2375 | \IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__132 | 104| |2376 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__419 | 4| |2377 | \IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__133 | 104| |2378 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__418 | 4| |2379 | \IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__134 | 104| |2380 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__417 | 4| |2381 | \IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst |IPbus_local__xdcDup__135 | 104| |2382 | IPbus_strobe_Sync_inst |xpm_cdc_single__parameterized1__416 | 4| |2383 | CrossClock_DV_cnt |CrossClock_RX | 70| |2384 | LocalJTAGBridge_inst |LocalJTAGBridge__xdcDup__9 | 629| |2385 | JTAGMaster_inst |JTAGMaster__xdcDup__9 | 462| |2386 | tck_in_Sync_inst |xpm_cdc_single__parameterized1 | 4| |2387 | JTAG_BRAM |RAM | 117| |2388 | Sync_RX_Reset |Sync | 2| |2389 | Sync_TX_Reset |Sync_332 | 114| |2390 | Sync_error_counter_reset |Sync_333 | 2| |2391 | gbt_rx_checker |gbt_rx_checker | 106| |2392 | \i2c_gen[0].LocalI2CBridge_fe |LocalI2CBridge | 332| |2393 | i2c_master |i2c_master_usr_402 | 332| |2394 | byte_ctrl |i2c_master_byte_ctrl_403 | 279| |2395 | bit_ctrl |i2c_master_bit_ctrl_404 | 224| |2396 | \bus_status_ctrl.gf_scl |glitch_filter_405 | 18| |2397 | \bus_status_ctrl.gf_sda |glitch_filter_406 | 20| |2398 | \i2c_gen[10].LocalI2CBridge_fe |LocalI2CBridge_334 | 332| |2399 | i2c_master |i2c_master_usr_397 | 332| |2400 | byte_ctrl |i2c_master_byte_ctrl_398 | 279| |2401 | bit_ctrl |i2c_master_bit_ctrl_399 | 224| |2402 | \bus_status_ctrl.gf_scl |glitch_filter_400 | 18| |2403 | \bus_status_ctrl.gf_sda |glitch_filter_401 | 20| |2404 | \i2c_gen[11].LocalI2CBridge_fe |LocalI2CBridge_335 | 332| |2405 | i2c_master |i2c_master_usr_392 | 332| |2406 | byte_ctrl |i2c_master_byte_ctrl_393 | 279| |2407 | bit_ctrl |i2c_master_bit_ctrl_394 | 224| |2408 | \bus_status_ctrl.gf_scl |glitch_filter_395 | 18| |2409 | \bus_status_ctrl.gf_sda |glitch_filter_396 | 20| |2410 | \i2c_gen[1].LocalI2CBridge_fe |LocalI2CBridge_336 | 332| |2411 | i2c_master |i2c_master_usr_387 | 332| |2412 | byte_ctrl |i2c_master_byte_ctrl_388 | 279| |2413 | bit_ctrl |i2c_master_bit_ctrl_389 | 224| |2414 | \bus_status_ctrl.gf_scl |glitch_filter_390 | 18| |2415 | \bus_status_ctrl.gf_sda |glitch_filter_391 | 20| |2416 | \i2c_gen[2].LocalI2CBridge_fe |LocalI2CBridge_337 | 332| |2417 | i2c_master |i2c_master_usr_382 | 332| |2418 | byte_ctrl |i2c_master_byte_ctrl_383 | 279| |2419 | bit_ctrl |i2c_master_bit_ctrl_384 | 224| |2420 | \bus_status_ctrl.gf_scl |glitch_filter_385 | 18| |2421 | \bus_status_ctrl.gf_sda |glitch_filter_386 | 20| |2422 | \i2c_gen[3].LocalI2CBridge_fe |LocalI2CBridge_338 | 332| |2423 | i2c_master |i2c_master_usr_377 | 332| |2424 | byte_ctrl |i2c_master_byte_ctrl_378 | 279| |2425 | bit_ctrl |i2c_master_bit_ctrl_379 | 224| |2426 | \bus_status_ctrl.gf_scl |glitch_filter_380 | 18| |2427 | \bus_status_ctrl.gf_sda |glitch_filter_381 | 20| |2428 | \i2c_gen[4].LocalI2CBridge_fe |LocalI2CBridge_339 | 332| |2429 | i2c_master |i2c_master_usr_372 | 332| |2430 | byte_ctrl |i2c_master_byte_ctrl_373 | 279| |2431 | bit_ctrl |i2c_master_bit_ctrl_374 | 224| |2432 | \bus_status_ctrl.gf_scl |glitch_filter_375 | 18| |2433 | \bus_status_ctrl.gf_sda |glitch_filter_376 | 20| |2434 | \i2c_gen[5].LocalI2CBridge_fe |LocalI2CBridge_340 | 332| |2435 | i2c_master |i2c_master_usr_367 | 332| |2436 | byte_ctrl |i2c_master_byte_ctrl_368 | 279| |2437 | bit_ctrl |i2c_master_bit_ctrl_369 | 224| |2438 | \bus_status_ctrl.gf_scl |glitch_filter_370 | 18| |2439 | \bus_status_ctrl.gf_sda |glitch_filter_371 | 20| |2440 | \i2c_gen[6].LocalI2CBridge_fe |LocalI2CBridge_341 | 332| |2441 | i2c_master |i2c_master_usr_362 | 332| |2442 | byte_ctrl |i2c_master_byte_ctrl_363 | 279| |2443 | bit_ctrl |i2c_master_bit_ctrl_364 | 224| |2444 | \bus_status_ctrl.gf_scl |glitch_filter_365 | 18| |2445 | \bus_status_ctrl.gf_sda |glitch_filter_366 | 20| |2446 | \i2c_gen[7].LocalI2CBridge_fe |LocalI2CBridge_342 | 332| |2447 | i2c_master |i2c_master_usr_357 | 332| |2448 | byte_ctrl |i2c_master_byte_ctrl_358 | 279| |2449 | bit_ctrl |i2c_master_bit_ctrl_359 | 224| |2450 | \bus_status_ctrl.gf_scl |glitch_filter_360 | 18| |2451 | \bus_status_ctrl.gf_sda |glitch_filter_361 | 20| |2452 | \i2c_gen[8].LocalI2CBridge_fe |LocalI2CBridge_343 | 332| |2453 | i2c_master |i2c_master_usr_352 | 332| |2454 | byte_ctrl |i2c_master_byte_ctrl_353 | 279| |2455 | bit_ctrl |i2c_master_bit_ctrl_354 | 224| |2456 | \bus_status_ctrl.gf_scl |glitch_filter_355 | 18| |2457 | \bus_status_ctrl.gf_sda |glitch_filter_356 | 20| |2458 | \i2c_gen[9].LocalI2CBridge_fe |LocalI2CBridge_344 | 332| |2459 | i2c_master |i2c_master_usr_347 | 332| |2460 | byte_ctrl |i2c_master_byte_ctrl_348 | 279| |2461 | bit_ctrl |i2c_master_bit_ctrl_349 | 224| |2462 | \bus_status_ctrl.gf_scl |glitch_filter_350 | 18| |2463 | \bus_status_ctrl.gf_sda |glitch_filter_351 | 20| |2464 | \i2c_sfp_gen[12].LocalI2CBridge_sfp |LocalI2CBridge_345 | 331| |2465 | i2c_master |i2c_master_usr | 331| |2466 | byte_ctrl |i2c_master_byte_ctrl | 279| |2467 | bit_ctrl |i2c_master_bit_ctrl | 224| |2468 | \bus_status_ctrl.gf_scl |glitch_filter | 18| |2469 | \bus_status_ctrl.gf_sda |glitch_filter_346 | 20| |2470 | prbs |prbs | 25| |2471 | \SFP_GEN[9].ngFEC_module |ngFEC_module_24 | 15549| |2472 | bkp_buffer_ngccm |buffer_ngccm_com | 511| |2473 | \bram_array[0].skip_SFP_SEC.RAM |Module_RAM | 281| |2474 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_329 | 194| |2475 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_330 | 20| |2476 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_331 | 24| |2477 | \bram_array[0].skip_SFP_SEC.buffer_server |buffer_server_com | 168| |2478 | \bram_array[10].skip_SFP_SEC.RAM |Module_RAM_262 | 257| |2479 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_326 | 167| |2480 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_327 | 18| |2481 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_328 | 29| |2482 | \bram_array[10].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized19 | 166| |2483 | \bram_array[11].skip_SFP_SEC.RAM |Module_RAM_263 | 257| |2484 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_323 | 167| |2485 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_324 | 18| |2486 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_325 | 29| |2487 | \bram_array[11].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized21 | 166| |2488 | \bram_array[12].skip_SFP_SEC.RAM |Module_RAM_264 | 280| |2489 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_320 | 188| |2490 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_321 | 20| |2491 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_322 | 29| |2492 | \bram_array[12].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized23 | 264| |2493 | \bram_array[14].skip_SFP_SEC.RAM |Module_RAM_265 | 134| |2494 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_317 | 69| |2495 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_318 | 20| |2496 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_319 | 18| |2497 | \bram_array[14].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized25 | 133| |2498 | \bram_array[15].skip_SFP_SEC.RAM |Module_RAM_266 | 280| |2499 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_314 | 188| |2500 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_315 | 20| |2501 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_316 | 29| |2502 | \bram_array[15].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized27 | 168| |2503 | \bram_array[1].skip_SFP_SEC.RAM |Module_RAM_267 | 257| |2504 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_311 | 167| |2505 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_312 | 18| |2506 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_313 | 29| |2507 | \bram_array[1].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized1 | 198| |2508 | \bram_array[2].skip_SFP_SEC.RAM |Module_RAM_268 | 280| |2509 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_308 | 188| |2510 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_309 | 20| |2511 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_310 | 29| |2512 | \bram_array[2].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized3 | 168| |2513 | \bram_array[3].skip_SFP_SEC.RAM |Module_RAM_269 | 280| |2514 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_305 | 188| |2515 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_306 | 20| |2516 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_307 | 29| |2517 | \bram_array[3].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized5 | 167| |2518 | \bram_array[4].skip_SFP_SEC.RAM |Module_RAM_270 | 280| |2519 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_302 | 188| |2520 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_303 | 20| |2521 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_304 | 29| |2522 | \bram_array[4].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized7 | 168| |2523 | \bram_array[5].skip_SFP_SEC.RAM |Module_RAM_271 | 280| |2524 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_299 | 188| |2525 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_300 | 20| |2526 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_301 | 29| |2527 | \bram_array[5].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized9 | 234| |2528 | \bram_array[6].skip_SFP_SEC.RAM |Module_RAM_272 | 257| |2529 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_296 | 167| |2530 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_297 | 18| |2531 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_298 | 29| |2532 | \bram_array[6].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized11 | 166| |2533 | \bram_array[7].skip_SFP_SEC.RAM |Module_RAM_273 | 257| |2534 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_293 | 167| |2535 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_294 | 18| |2536 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_295 | 29| |2537 | \bram_array[7].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized13 | 166| |2538 | \bram_array[8].skip_SFP_SEC.RAM |Module_RAM_274 | 257| |2539 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0_290 | 167| |2540 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO_291 | 18| |2541 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_292 | 29| |2542 | \bram_array[8].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized15 | 165| |2543 | \bram_array[9].skip_SFP_SEC.RAM |Module_RAM_275 | 257| |2544 | BRAM_h |unimacro_BRAM_TDP_MACRO__parameterized0 | 167| |2545 | \bram_gen[0].BRAM_l |unimacro_BRAM_TDP_MACRO | 18| |2546 | \bram_gen[1].BRAM_l |unimacro_BRAM_TDP_MACRO_289 | 29| |2547 | \bram_array[9].skip_SFP_SEC.buffer_server |buffer_server_com__parameterized17 | 198| |2548 | buffer_ngccm_jtag |buffer_ngccm_jtag_com | 662| |2549 | \i2c_comm_gen[0].buffer_ngccm |buffer_ngccm_com_276 | 510| |2550 | \i2c_comm_gen[10].buffer_ngccm |buffer_ngccm_com_277 | 535| |2551 | \i2c_comm_gen[11].buffer_ngccm |buffer_ngccm_com_278 | 535| |2552 | \i2c_comm_gen[12].buffer_ngccm |buffer_ngccm_com_279 | 511| |2553 | \i2c_comm_gen[1].buffer_ngccm |buffer_ngccm_com_280 | 535| |2554 | \i2c_comm_gen[2].buffer_ngccm |buffer_ngccm_com_281 | 511| |2555 | \i2c_comm_gen[3].buffer_ngccm |buffer_ngccm_com_282 | 511| |2556 | \i2c_comm_gen[4].buffer_ngccm |buffer_ngccm_com_283 | 511| |2557 | \i2c_comm_gen[5].buffer_ngccm |buffer_ngccm_com_284 | 511| |2558 | \i2c_comm_gen[6].buffer_ngccm |buffer_ngccm_com_285 | 535| |2559 | \i2c_comm_gen[7].buffer_ngccm |buffer_ngccm_com_286 | 535| |2560 | \i2c_comm_gen[8].buffer_ngccm |buffer_ngccm_com_287 | 535| |2561 | \i2c_comm_gen[9].buffer_ngccm |buffer_ngccm_com_288 | 535| |2562 | cdce_synch |cdce_synchronizer | 82| |2563 | clkRate0 |clkRateTool32 | 110| |2564 | clkRate1 |clkRateTool32_25 | 110| |2565 | clkRate2 |clkRateTool32_26 | 110| |2566 | \clk_rate_gen[10].clkRate3 |clkRateTool32_27 | 109| |2567 | \clk_rate_gen[11].clkRate3 |clkRateTool32_28 | 109| |2568 | \clk_rate_gen[12].clkRate3 |clkRateTool32_29 | 109| |2569 | \clk_rate_gen[1].clkRate3 |clkRateTool32_30 | 109| |2570 | \clk_rate_gen[2].clkRate3 |clkRateTool32_31 | 109| |2571 | \clk_rate_gen[3].clkRate3 |clkRateTool32_32 | 109| |2572 | \clk_rate_gen[4].clkRate3 |clkRateTool32_33 | 109| |2573 | \clk_rate_gen[5].clkRate3 |clkRateTool32_34 | 109| |2574 | \clk_rate_gen[6].clkRate3 |clkRateTool32_35 | 109| |2575 | \clk_rate_gen[7].clkRate3 |clkRateTool32_36 | 109| |2576 | \clk_rate_gen[8].clkRate3 |clkRateTool32_37 | 109| |2577 | \clk_rate_gen[9].clkRate3 |clkRateTool32_38 | 109| |2578 | ctrl_regs_inst |ipb_user_control_regs | 1980| |2579 | dmdt_clk |dmdt_clock_gen | 7| |2580 | mmcm1 |phase_mon_mmcm_1 | 3| |2581 | U0 |phase_mon_mmcm_1_clk_wiz | 3| |2582 | mmcm2 |phase_mon_mmcm_2 | 4| |2583 | U0 |phase_mon_mmcm_2_clk_wiz | 4| |2584 | dmdt_meas |dmtd_phase_meas | 784| |2585 | DMTD_A |dmtd_with_deglitcher | 146| |2586 | U_Sync_Resync_Done |gc_sync_ffs_259 | 2| |2587 | U_Sync_Resync_Pulse |gc_sync_ffs_260 | 2| |2588 | U_sync_tag_strobe |gc_sync_ffs_261 | 10| |2589 | DMTD_B |dmtd_with_deglitcher_221 | 141| |2590 | U_Sync_Resync_Done |gc_sync_ffs_256 | 2| |2591 | U_Sync_Resync_Pulse |gc_sync_ffs_257 | 2| |2592 | U_sync_tag_strobe |gc_sync_ffs_258 | 5| |2593 | sync_busy_clka |gc_sync_ffs | 3| |2594 | sync_done_clka |gc_sync_ffs_222 | 6| |2595 | sync_reset_dmtdclk |gc_sync_ffs_223 | 4| |2596 | \t[0].o |gc_sync_ffs_224 | 3| |2597 | \t[10].o |gc_sync_ffs_225 | 3| |2598 | \t[11].o |gc_sync_ffs_226 | 3| |2599 | \t[12].o |gc_sync_ffs_227 | 3| |2600 | \t[13].o |gc_sync_ffs_228 | 3| |2601 | \t[14].o |gc_sync_ffs_229 | 3| |2602 | \t[15].o |gc_sync_ffs_230 | 3| |2603 | \t[16].o |gc_sync_ffs_231 | 3| |2604 | \t[17].o |gc_sync_ffs_232 | 3| |2605 | \t[18].o |gc_sync_ffs_233 | 3| |2606 | \t[19].o |gc_sync_ffs_234 | 3| |2607 | \t[1].o |gc_sync_ffs_235 | 3| |2608 | \t[20].o |gc_sync_ffs_236 | 3| |2609 | \t[21].o |gc_sync_ffs_237 | 3| |2610 | \t[22].o |gc_sync_ffs_238 | 3| |2611 | \t[23].o |gc_sync_ffs_239 | 3| |2612 | \t[24].o |gc_sync_ffs_240 | 3| |2613 | \t[25].o |gc_sync_ffs_241 | 3| |2614 | \t[26].o |gc_sync_ffs_242 | 3| |2615 | \t[27].o |gc_sync_ffs_243 | 3| |2616 | \t[28].o |gc_sync_ffs_244 | 3| |2617 | \t[29].o |gc_sync_ffs_245 | 3| |2618 | \t[2].o |gc_sync_ffs_246 | 3| |2619 | \t[30].o |gc_sync_ffs_247 | 3| |2620 | \t[31].o |gc_sync_ffs_248 | 3| |2621 | \t[3].o |gc_sync_ffs_249 | 3| |2622 | \t[4].o |gc_sync_ffs_250 | 3| |2623 | \t[5].o |gc_sync_ffs_251 | 3| |2624 | \t[6].o |gc_sync_ffs_252 | 3| |2625 | \t[7].o |gc_sync_ffs_253 | 3| |2626 | \t[8].o |gc_sync_ffs_254 | 3| |2627 | \t[9].o |gc_sync_ffs_255 | 3| |2628 | \g_pm[10].phase_mon |pm__xdcDup__10 | 97| |2629 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__52 | 5| |2630 | sample_PS_Sync_inst |xpm_cdc_single__53 | 5| |2631 | \g_pm[11].phase_mon |pm__xdcDup__11 | 97| |2632 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__50 | 5| |2633 | sample_PS_Sync_inst |xpm_cdc_single__51 | 5| |2634 | \g_pm[12].phase_mon |pm | 97| |2635 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__48 | 5| |2636 | sample_PS_Sync_inst |xpm_cdc_single__49 | 5| |2637 | \g_pm[1].phase_mon |pm__xdcDup__1 | 97| |2638 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__70 | 5| |2639 | sample_PS_Sync_inst |xpm_cdc_single | 5| |2640 | \g_pm[2].phase_mon |pm__xdcDup__2 | 97| |2641 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__68 | 5| |2642 | sample_PS_Sync_inst |xpm_cdc_single__69 | 5| |2643 | \g_pm[3].phase_mon |pm__xdcDup__3 | 97| |2644 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__66 | 5| |2645 | sample_PS_Sync_inst |xpm_cdc_single__67 | 5| |2646 | \g_pm[4].phase_mon |pm__xdcDup__4 | 97| |2647 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__64 | 5| |2648 | sample_PS_Sync_inst |xpm_cdc_single__65 | 5| |2649 | \g_pm[5].phase_mon |pm__xdcDup__5 | 97| |2650 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__62 | 5| |2651 | sample_PS_Sync_inst |xpm_cdc_single__63 | 5| |2652 | \g_pm[6].phase_mon |pm__xdcDup__6 | 97| |2653 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__60 | 5| |2654 | sample_PS_Sync_inst |xpm_cdc_single__61 | 5| |2655 | \g_pm[7].phase_mon |pm__xdcDup__7 | 97| |2656 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__58 | 5| |2657 | sample_PS_Sync_inst |xpm_cdc_single__59 | 5| |2658 | \g_pm[8].phase_mon |pm__xdcDup__8 | 97| |2659 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__56 | 5| |2660 | sample_PS_Sync_inst |xpm_cdc_single__57 | 5| |2661 | \g_pm[9].phase_mon |pm__xdcDup__9 | 97| |2662 | fabric_clk_PS_toggle_Sync_inst |xpm_cdc_single__54 | 5| |2663 | sample_PS_Sync_inst |xpm_cdc_single__55 | 5| |2664 | gbtbank1_l12_118 |xlx_k7v7_gbt_ngFEC_design__xdcDup__1 | 8778| |2665 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset_173 | 68| |2666 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_174 | 68| |2667 | \gbtBank_rst_gen[3].gbtBank_gbtBankRst |gbt_bank_reset_175 | 68| |2668 | gbt_inst |gbt_bank__xdcDup__1 | 8454| |2669 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx_176 | 546| |2670 | decoder |gbt_rx_decoder_215 | 1| |2671 | descrambler |gbt_rx_descrambler_216 | 247| |2672 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_217 | 61| |2673 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_218 | 61| |2674 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_219 | 60| |2675 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_220 | 61| |2676 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_177 | 546| |2677 | decoder |gbt_rx_decoder_209 | 1| |2678 | descrambler |gbt_rx_descrambler_210 | 247| |2679 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_211 | 61| |2680 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_212 | 61| |2681 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_213 | 60| |2682 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_214 | 61| |2683 | \gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst |gbt_rx_178 | 546| |2684 | decoder |gbt_rx_decoder_203 | 1| |2685 | descrambler |gbt_rx_descrambler_204 | 247| |2686 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_205 | 61| |2687 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_206 | 61| |2688 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_207 | 60| |2689 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_208 | 61| |2690 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox_179 | 1316| |2691 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_180 | 1316| |2692 | \gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst |gbt_rx_gearbox_181 | 1316| |2693 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx_182 | 328| |2694 | scrambler |gbt_tx_scrambler_198 | 328| |2695 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_199 | 83| |2696 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_200 | 82| |2697 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_201 | 80| |2698 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_202 | 82| |2699 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_183 | 328| |2700 | scrambler |gbt_tx_scrambler_193 | 328| |2701 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_194 | 83| |2702 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_195 | 82| |2703 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_196 | 80| |2704 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_197 | 82| |2705 | \gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst |gbt_tx_184 | 328| |2706 | scrambler |gbt_tx_scrambler_188 | 328| |2707 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_189 | 83| |2708 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_190 | 82| |2709 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_191 | 80| |2710 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_192 | 82| |2711 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__1 | 195| |2712 | xpm_cdc_single_inst |xpm_cdc_single__38 | 5| |2713 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__2 | 195| |2714 | xpm_cdc_single_inst |xpm_cdc_single__37 | 5| |2715 | \gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__3 | 195| |2716 | xpm_cdc_single_inst |xpm_cdc_single__36 | 5| |2717 | mgt_inst |mgt__xdcDup__1 | 1299| |2718 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__2 | 29| |2719 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__3 | 29| |2720 | \gtxLatOpt_gen[3].rxBitSlipControl |mgt_bitslipctrl__4 | 29| |2721 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch_185 | 122| |2722 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_186 | 122| |2723 | \gtxLatOpt_gen[3].patternSearch |mgt_framealigner_pattsearch_187 | 122| |2724 | gbtbank2_l12_117 |xlx_k7v7_gbt_ngFEC_design__parameterized1 | 5852| |2725 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset_141 | 68| |2726 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_142 | 68| |2727 | gbt_inst |gbt_bank__parameterized0 | 5636| |2728 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx_143 | 546| |2729 | decoder |gbt_rx_decoder_167 | 1| |2730 | descrambler |gbt_rx_descrambler_168 | 247| |2731 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_169 | 61| |2732 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_170 | 61| |2733 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_171 | 60| |2734 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_172 | 61| |2735 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_144 | 546| |2736 | decoder |gbt_rx_decoder_161 | 1| |2737 | descrambler |gbt_rx_descrambler_162 | 247| |2738 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_163 | 61| |2739 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_164 | 61| |2740 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_165 | 60| |2741 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_166 | 61| |2742 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox_145 | 1316| |2743 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_146 | 1316| |2744 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx_147 | 328| |2745 | scrambler |gbt_tx_scrambler_156 | 328| |2746 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_157 | 83| |2747 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_158 | 82| |2748 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_159 | 80| |2749 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_160 | 82| |2750 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_148 | 328| |2751 | scrambler |gbt_tx_scrambler_151 | 328| |2752 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_152 | 83| |2753 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_153 | 82| |2754 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_154 | 80| |2755 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_155 | 82| |2756 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__4 | 195| |2757 | xpm_cdc_single_inst |xpm_cdc_single__40 | 5| |2758 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__5 | 195| |2759 | xpm_cdc_single_inst |xpm_cdc_single__39 | 5| |2760 | mgt_inst |mgt__parameterized0 | 866| |2761 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__5 | 29| |2762 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__6 | 29| |2763 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch_149 | 122| |2764 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_150 | 122| |2765 | gbtbank3_l12_116 |xlx_k7v7_gbt_ngFEC_design | 8778| |2766 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset_93 | 68| |2767 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_94 | 68| |2768 | \gbtBank_rst_gen[3].gbtBank_gbtBankRst |gbt_bank_reset_95 | 68| |2769 | gbt_inst |gbt_bank | 8454| |2770 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx_96 | 546| |2771 | decoder |gbt_rx_decoder_135 | 1| |2772 | descrambler |gbt_rx_descrambler_136 | 247| |2773 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_137 | 61| |2774 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_138 | 61| |2775 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_139 | 60| |2776 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_140 | 61| |2777 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_97 | 546| |2778 | decoder |gbt_rx_decoder_129 | 1| |2779 | descrambler |gbt_rx_descrambler_130 | 247| |2780 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_131 | 61| |2781 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_132 | 61| |2782 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_133 | 60| |2783 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_134 | 61| |2784 | \gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst |gbt_rx_98 | 546| |2785 | decoder |gbt_rx_decoder_123 | 1| |2786 | descrambler |gbt_rx_descrambler_124 | 247| |2787 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_125 | 61| |2788 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_126 | 61| |2789 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_127 | 60| |2790 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_128 | 61| |2791 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox_99 | 1316| |2792 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_100 | 1316| |2793 | \gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst |gbt_rx_gearbox_101 | 1316| |2794 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx_102 | 328| |2795 | scrambler |gbt_tx_scrambler_118 | 328| |2796 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_119 | 83| |2797 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_120 | 82| |2798 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_121 | 80| |2799 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_122 | 82| |2800 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_103 | 328| |2801 | scrambler |gbt_tx_scrambler_113 | 328| |2802 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_114 | 83| |2803 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_115 | 82| |2804 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_116 | 80| |2805 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_117 | 82| |2806 | \gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst |gbt_tx_104 | 328| |2807 | scrambler |gbt_tx_scrambler_108 | 328| |2808 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_109 | 83| |2809 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_110 | 82| |2810 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_111 | 80| |2811 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_112 | 82| |2812 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__6 | 195| |2813 | xpm_cdc_single_inst |xpm_cdc_single__43 | 5| |2814 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__7 | 195| |2815 | xpm_cdc_single_inst |xpm_cdc_single__42 | 5| |2816 | \gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__8 | 195| |2817 | xpm_cdc_single_inst |xpm_cdc_single__41 | 5| |2818 | mgt_inst |mgt | 1299| |2819 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__7 | 29| |2820 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__8 | 29| |2821 | \gtxLatOpt_gen[3].rxBitSlipControl |mgt_bitslipctrl__9 | 29| |2822 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch_105 | 122| |2823 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_106 | 122| |2824 | \gtxLatOpt_gen[3].patternSearch |mgt_framealigner_pattsearch_107 | 122| |2825 | gbtbank4_l8_112 |xlx_k7v7_gbt_ngFEC_design__parameterized4 | 11704| |2826 | \gbtBank_rst_gen[1].gbtBank_gbtBankRst |gbt_bank_reset | 68| |2827 | \gbtBank_rst_gen[2].gbtBank_gbtBankRst |gbt_bank_reset_39 | 68| |2828 | \gbtBank_rst_gen[3].gbtBank_gbtBankRst |gbt_bank_reset_40 | 68| |2829 | \gbtBank_rst_gen[4].gbtBank_gbtBankRst |gbt_bank_reset_41 | 68| |2830 | gbt_inst |gbt_bank__parameterized1 | 11272| |2831 | \gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst |gbt_rx | 472| |2832 | decoder |gbt_rx_decoder_87 | 1| |2833 | descrambler |gbt_rx_descrambler_88 | 247| |2834 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_89 | 61| |2835 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_90 | 61| |2836 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_91 | 60| |2837 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_92 | 61| |2838 | \gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst |gbt_rx_42 | 472| |2839 | decoder |gbt_rx_decoder_81 | 1| |2840 | descrambler |gbt_rx_descrambler_82 | 247| |2841 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_83 | 61| |2842 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_84 | 61| |2843 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_85 | 60| |2844 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_86 | 61| |2845 | \gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst |gbt_rx_43 | 472| |2846 | decoder |gbt_rx_decoder_75 | 1| |2847 | descrambler |gbt_rx_descrambler_76 | 247| |2848 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_77 | 61| |2849 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_78 | 61| |2850 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_79 | 60| |2851 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_80 | 61| |2852 | \gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst |gbt_rx_44 | 472| |2853 | decoder |gbt_rx_decoder | 1| |2854 | descrambler |gbt_rx_descrambler | 247| |2855 | \gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit | 61| |2856 | \gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_72 | 61| |2857 | \gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_73 | 60| |2858 | \gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit |gbt_rx_descrambler_21bit_74 | 61| |2859 | \gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst |gbt_rx_gearbox | 1390| |2860 | \gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst |gbt_rx_gearbox_45 | 1390| |2861 | \gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst |gbt_rx_gearbox_46 | 1390| |2862 | \gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst |gbt_rx_gearbox_47 | 1390| |2863 | \gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst |gbt_tx | 328| |2864 | scrambler |gbt_tx_scrambler_67 | 328| |2865 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_68 | 83| |2866 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_69 | 82| |2867 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_70 | 80| |2868 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_71 | 82| |2869 | \gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst |gbt_tx_48 | 328| |2870 | scrambler |gbt_tx_scrambler_62 | 328| |2871 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_63 | 83| |2872 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_64 | 82| |2873 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_65 | 80| |2874 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_66 | 82| |2875 | \gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst |gbt_tx_49 | 328| |2876 | scrambler |gbt_tx_scrambler_57 | 328| |2877 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_58 | 83| |2878 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_59 | 82| |2879 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_60 | 80| |2880 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_61 | 82| |2881 | \gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst |gbt_tx_50 | 328| |2882 | scrambler |gbt_tx_scrambler | 328| |2883 | \gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit |gbt_tx_scrambler_21bit | 83| |2884 | \gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_54 | 82| |2885 | \gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_55 | 80| |2886 | \gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit |gbt_tx_scrambler_21bit_56 | 82| |2887 | \gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__9 | 195| |2888 | xpm_cdc_single_inst |xpm_cdc_single__47 | 5| |2889 | \gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__10 | 195| |2890 | xpm_cdc_single_inst |xpm_cdc_single__46 | 5| |2891 | \gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst |gbt_tx_gearbox__xdcDup__11 | 195| |2892 | xpm_cdc_single_inst |xpm_cdc_single__45 | 5| |2893 | \gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst |gbt_tx_gearbox | 195| |2894 | xpm_cdc_single_inst |xpm_cdc_single__44 | 5| |2895 | mgt_inst |mgt__parameterized1 | 1732| |2896 | \gtxLatOpt_gen[1].rxBitSlipControl |mgt_bitslipctrl__10 | 29| |2897 | \gtxLatOpt_gen[2].rxBitSlipControl |mgt_bitslipctrl__11 | 29| |2898 | \gtxLatOpt_gen[3].rxBitSlipControl |mgt_bitslipctrl__12 | 29| |2899 | \gtxLatOpt_gen[4].rxBitSlipControl |mgt_bitslipctrl | 29| |2900 | \gtxLatOpt_gen[1].patternSearch |mgt_framealigner_pattsearch | 122| |2901 | \gtxLatOpt_gen[2].patternSearch |mgt_framealigner_pattsearch_51 | 122| |2902 | \gtxLatOpt_gen[3].patternSearch |mgt_framealigner_pattsearch_52 | 122| |2903 | \gtxLatOpt_gen[4].patternSearch |mgt_framealigner_pattsearch_53 | 122| |2904 | phmon |clk_divide3 | 10| |2905 | stat_regs_inst |ipb_user_status_regs | 2117| |2906 | sys |system_core | 28063| |2907 | clocks |clocks_7s_serdes | 148| |2908 | clkdiv |ipbus_clock_div | 38| |2909 | eth |eth_7s_1000basex | 461| |2910 | mac |tri_mode_eth_mac_v5_5 | 426| |2911 | i_mac |soft_emac | 426| |2912 | i_rx_CRC32D8 |EthernetCRC | 103| |2913 | i_tx_CRC32D8 |EthernetCRC_2 | 107| |2914 | i2c_eep |i2c_eep_autoread | 320| |2915 | i2c_m |i2c_master_top | 511| |2916 | core |i2c_master_core | 509| |2917 | u1 |i2c_bitwise | 144| |2918 | u2 |i2c_ctrl | 330| |2919 | icap_if |icap_interface_wrapper | 192| |2920 | confFsm |icap_interface_fsm | 83| |2921 | icapInterface |icap_interface | 109| |2922 | ip_mac |ip_mac_select | 197| |2923 | ipb |ipbus_ctrl | 6789| |2924 | \arb_gen.arb |trans_arb | 38| |2925 | trans |transactor | 1097| |2926 | cfg__0 |transactor_cfg | 1| |2927 | iface |transactor_if | 317| |2928 | sm |transactor_sm | 779| |2929 | udp_if |UDP_if | 5654| |2930 | ipbus_rx_ram |udp_DualPortRAM_rx | 8| |2931 | ARP |udp_build_arp | 275| |2932 | IPADDR |udp_ipaddr_block | 185| |2933 | RARP_block |udp_rarp_block | 885| |2934 | clock_crossing_if |udp_clock_crossing_if | 89| |2935 | internal_ram |udp_DualPortRAM | 1| |2936 | internal_ram_selector |udp_buffer_selector | 19| |2937 | internal_ram_shim |udp_rxram_shim | 69| |2938 | ipbus_tx_ram |udp_DualPortRAM_tx | 18| |2939 | payload |udp_build_payload | 413| |2940 | ping |udp_build_ping | 241| |2941 | resend |udp_build_resend | 39| |2942 | rx_byte_sum |udp_byte_sum | 89| |2943 | rx_packet_parser |udp_packet_parser | 680| |2944 | rx_ram_mux |udp_rxram_mux | 40| |2945 | rx_ram_selector |udp_buffer_selector__parameterized0 | 125| |2946 | rx_reset_block |udp_do_rx_reset | 116| |2947 | rx_transactor |udp_rxtransactor_if | 7| |2948 | status |udp_build_status | 325| |2949 | status_buffer |udp_status_buffer | 818| |2950 | tx_byte_sum |udp_byte_sum_0 | 76| |2951 | tx_main |udp_tx_mux | 488| |2952 | tx_ram_selector |udp_buffer_selector__parameterized0_1 | 201| |2953 | tx_transactor |udp_txtransactor_if | 446| |2954 | ipb_fabric |ipbus_sys_fabric | 6| |2955 | ipb_sys_regs |system_regs | 945| |2956 | spi |spi_master | 310| |2957 | uc_if |uc_if | 454| |2958 | spi |spi_interface | 118| |2959 | uc_pipe_if |uc_pipe_interface | 256| |2960 | uc_trans |trans_buffer | 80| +------+-----------------------------------------------------------------+---------------------------------------------+-------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:10:04 ; elapsed = 00:10:14 . Memory (MB): peak = 2456.355 ; gain = 2082.438 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3566 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:07:38 ; elapsed = 00:08:26 . Memory (MB): peak = 2456.355 ; gain = 406.770 Synthesis Optimization Complete : Time (s): cpu = 00:10:04 ; elapsed = 00:10:15 . Memory (MB): peak = 2456.355 ; gain = 2082.438 INFO: [Project 1-571] Translating synthesized netlist Release 14.7 - ngc2edif P_INT.20180726 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Reading design sdpram_16x10_32x9.ngc ... WARNING:NetListWriters:298 - No output is written to sdpram_16x10_32x9.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file sdpram_16x10_32x9.edif ... ngc2edif: Total memory usage is 4321768 kilobytes Reading core file 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ipcore_dir/sdpram_16x10_32x9.ngc' for (cell view 'sdpram_16x10_32x9', library 'work') Parsing EDIF File [./.ngc2edfcache/sdpram_16x10_32x9_ngc_79b4cb59.edif] Finished Parsing EDIF File [./.ngc2edfcache/sdpram_16x10_32x9_ngc_79b4cb59.edif] Release 14.7 - ngc2edif P_INT.20180726 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Reading design sdpram_32x9_16x10.ngc ... WARNING:NetListWriters:298 - No output is written to sdpram_32x9_16x10.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file sdpram_32x9_16x10.edif ... ngc2edif: Total memory usage is 4321768 kilobytes Reading core file 'D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/imports/fc7half/sys/ipb_fc7/ipcore_dir/sdpram_32x9_16x10.ngc' for (cell view 'sdpram_32x9_16x10', library 'work') Parsing EDIF File [./.ngc2edfcache/sdpram_32x9_16x10_ngc_79b4cb59.edif] Finished Parsing EDIF File [./.ngc2edfcache/sdpram_32x9_16x10_ngc_79b4cb59.edif] INFO: [Netlist 29-17] Analyzing 15953 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Project 1-479] Netlist was created with Xilinx ngc2edif P_INT.20180726 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. ngFEC/dmdt_clk/mmcm1/U0/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. ngFEC/dmdt_clk/mmcm2/U0/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.148 . Memory (MB): peak = 3048.039 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 121 instances were transformed. BUFGMUX => BUFGCTRL (inverted pins: CE0): 1 instances IBUFGDS => IBUFDS: 1 instances IOBUF => IOBUF (IBUF, OBUFT): 42 instances LD => LDCE: 72 instances LDC => LDCE: 1 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances PLLE2_BASE => PLLE2_ADV: 1 instances SRL16 => SRL16E: 2 instances INFO: [Common 17-83] Releasing license: Synthesis 1580 Infos, 859 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:11:39 ; elapsed = 00:11:51 . Memory (MB): peak = 3048.039 ; gain = 2684.563 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.143 . Memory (MB): peak = 3048.039 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/synth_1/fc7_top.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:04 ; elapsed = 00:00:46 . Memory (MB): peak = 3048.039 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file fc7_top_utilization_synth.rpt -pb fc7_top_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Mon May 18 09:12:41 2020...