
g
Command: %s
53*	vivadotcl26
"write_bitstream -force fc7_top.bit2default:defaultZ4-113h px 
¤
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xc7k420t2default:defaultZ17-347h px 
”
0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xc7k420t2default:defaultZ17-349h px 
Ñ
The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
719*common2
2020.012default:defaultZ17-1540h px 
x
,Running DRC as a precondition to command %s
1349*	planAhead2#
write_bitstream2default:defaultZ12-1349h px 
>
IP Catalog is up to date.1232*coregenZ19-1839h px 
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px 
Ç
{Input Buffer Connections: Input buffer %s has no loads. It is recommended to have an input buffer drive an internal load.%s*DRC2n
 "X
 sys/i2c_m/bufgen[0].scl_buf/IBUF	 sys/i2c_m/bufgen[0].scl_buf/IBUF2default:default2default:default2>
 &DRC|Netlist|Instance|Required Pin|IBUF2default:default8ZBUFC-1h px 
±
YReport rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.%s*DRC29
 !DRC|DRC System|Rule limit reached2default:default8ZCHECK-3h px 
‚
•Bidirection LVDS IOs: The following port(s) use the LVDS_25 I/O standard and have bi-directional differential usage. Please note that LVDS_25 is a fixed impedance structure optimized to 100ohm differential. This is only intended to be used in point-to-point transmissions that do not have turn around timing requirements. If the intended usage is a bus structure, please use BLVDS/BLVDS_25, instead. %s.%s*DRC2˜
 "@
k7_fabric_amc_rx_n03k7_fabric_amc_rx_n032default:default"@
k7_fabric_amc_rx_p03k7_fabric_amc_rx_p032default:default2default:default23
 DRC|Pin Planning|Chip Level2default:default8ZLVDS-1h px 
õ
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2„
 "n
+ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o3_out+ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1/O0ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1/O2default:default2default:default2Š
 "t
.ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1	.ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
Œ
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2~
 "h
(ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_trst_o1(ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_trst_o12default:default2default:default2
 "†
7ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O7ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O2default:default2default:default2™
 "‚
5ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1	5ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 

òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2›
 "„
6ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_06ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_02default:default2default:default2—
 "€
4ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O4ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1	2ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
õ
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2„
 "n
+ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o3_out+ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1/O0ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1/O2default:default2default:default2Š
 "t
.ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1	.ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
Œ
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2~
 "h
(ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_trst_o1(ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_trst_o12default:default2default:default2
 "†
7ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O7ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O2default:default2default:default2™
 "‚
5ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1	5ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 

òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2›
 "„
6ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_06ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_02default:default2default:default2—
 "€
4ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O4ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1	2ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
õ
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2„
 "n
+ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o3_out+ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1/O0ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1/O2default:default2default:default2Š
 "t
.ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1	.ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
Œ
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2~
 "h
(ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_trst_o1(ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_trst_o12default:default2default:default2
 "†
7ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O7ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O2default:default2default:default2™
 "‚
5ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1	5ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 

òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2›
 "„
6ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_06ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_02default:default2default:default2—
 "€
4ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O4ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1	2ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6/O2ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6	0ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__62default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6/O9ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6	7ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__62default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6_n_08ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6/O6ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6	4ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__62default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5/O2ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5	0ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__52default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5/O9ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5	7ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__52default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5_n_08ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5/O6ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5	4ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__52default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4/O2ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4	0ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__42default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4/O9ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4	7ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__42default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4_n_08ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4/O6ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4	4ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__42default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3/O2ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3	0ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__32default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3/O9ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3	7ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__32default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3_n_08ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3/O6ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3	4ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__32default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2/O2ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2	0ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__22default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2/O9ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2	7ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__22default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2_n_08ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2/O6ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2	4ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__22default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1/O2ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1	0ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1/O9ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1	7ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1_n_08ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1/O6ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1	4ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0/O2ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0	0ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__02default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0/O9ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0	7ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__02default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0_n_08ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0/O6ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0	4ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__02default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ï
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2Œ
 "v
/ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1/O/ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1/O2default:default2default:default2ˆ
 "r
-ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1	-ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
†
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_trst_o12default:default2default:default2›
 "„
6ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2/O6ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2	4ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_22default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
–
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2™
 "‚
5ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_05ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_02default:default2default:default2”
 "~
3ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O3ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O2default:default2default:default2
 "z
1ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1	1ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
û
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2‚
 "l
*ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o3_out*ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o3_out2default:default2default:default2’
 "|
2ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7/O2ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7/O2default:default2default:default2Ž
 "x
0ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7	0ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__72default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
’
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2|
 "f
'ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_trst_o1'ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_trst_o12default:default2default:default2¡
 "Š
9ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7/O9ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7/O2default:default2default:default2
 "†
7ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7	7ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__72default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2Ÿ
 "ˆ
8ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7_n_08ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7_n_02default:default2default:default2›
 "„
6ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7/O6ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7/O2default:default2default:default2—
 "€
4ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7	4ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__72default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
ª
òGated clock check: Net %s is a gated clock net sourced by a combinational pin %s, cell %s. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.%s*DRC2t
 "^
#sys/ipb_sys_regs/regs_reg[11][12]_0#sys/ipb_sys_regs/regs_reg[11][12]_02default:default2default:default2r
 "\
"sys/ipb_sys_regs/sck_reg_LDC_i_1/O"sys/ipb_sys_regs/sck_reg_LDC_i_1/O2default:default2default:default2n
 "X
 sys/ipb_sys_regs/sck_reg_LDC_i_1	 sys/ipb_sys_regs/sck_reg_LDC_i_12default:default2default:default2=
 %DRC|Physical Configuration|Chip Level2default:default8ZPDRC-153h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‹
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2ù
 "â
engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
‰
ñRAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2Ù
 "Â
UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg	UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]2default:default2default:default2á
 "Ê
YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]2default:default2default:default2÷
 "à
dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]	dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z	REQP-1839h px 
g
DRC finished with %s
1905*	planAhead2)
0 Errors, 60 Warnings2default:defaultZ12-3199h px 
i
BPlease refer to the DRC report (report_drc) for more information.
1906*	planAheadZ12-3200h px 
i
)Running write_bitstream with %s threads.
1750*designutils2
22default:defaultZ20-2272h px 
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Loading data files...
1271*designutilsZ12-1165h px 
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Loading site data...
1273*designutilsZ12-1167h px 
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Loading route data...
1272*designutilsZ12-1166h px 
?
Processing options...
1362*designutilsZ12-1514h px 
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Creating bitmap...
1249*designutilsZ12-1141h px 
7
Creating bitstream...
7*	bitstreamZ40-7h px 
^
Writing bitstream %s...
11*	bitstream2!
./fc7_top.bit2default:defaultZ40-11h px 
F
Bitgen Completed Successfully.
1606*	planAheadZ12-1842h px 
s
QWebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
118*projectZ1-118h px 
Z
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83h px 
É
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
1272default:default2
2822default:default2
02default:default2
02default:defaultZ4-41h px 
a
%s completed successfully
29*	vivadotcl2#
write_bitstream2default:defaultZ4-42h px 
Š
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2%
write_bitstream: 2default:default2
00:04:152default:default2
00:02:352default:default2
7873.4572default:default2
1058.7702default:defaultZ17-268h px 


End Record