Q Command: %s 53* vivadotcl2 route_design2default:defaultZ4-113hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2" Implementation2default:default2 xc7k420t2default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2" Implementation2default:default2 xc7k420t2default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2020.012default:defaultZ17-1540hpx p ,Running DRC as a precondition to command %s 22* vivadotcl2 route_design2default:defaultZ4-22hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s %s %s %s %s %s %s %s %s %s and 1 more (total of 12.)%s*DRC2D ". amc_tx_n[15:1]amc_tx_n2default:default2default:default2F "0 amc_tx_n[11] amc_tx_n[11]2default:default2default:default2F "0 amc_tx_n[10] amc_tx_n[10]2default:default2default:default2D ". amc_tx_n[9] amc_tx_n[9]2default:default2default:default2D ". amc_tx_n[8] amc_tx_n[8]2default:default2default:default2D ". amc_tx_n[7] amc_tx_n[7]2default:default2default:default2D ". amc_tx_n[6] amc_tx_n[6]2default:default2default:default2D ". amc_tx_n[5] amc_tx_n[5]2default:default2default:default2D ". amc_tx_n[4] amc_tx_n[4]2default:default2default:default2D ". amc_tx_n[3] amc_tx_n[3]2default:default2default:default2D ". amc_tx_n[2] amc_tx_n[2]2default:default2default:default28  DRC|Implementation|Placement|IOs2default:default8ZPLIO-3hpx  Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s %s %s %s %s %s %s %s %s %s and 1 more (total of 12.)%s*DRC2D ". amc_tx_p[15:1]amc_tx_p2default:default2default:default2F "0 amc_tx_p[11] amc_tx_p[11]2default:default2default:default2F "0 amc_tx_p[10] amc_tx_p[10]2default:default2default:default2D ". amc_tx_p[9] amc_tx_p[9]2default:default2default:default2D ". amc_tx_p[8] amc_tx_p[8]2default:default2default:default2D ". amc_tx_p[7] amc_tx_p[7]2default:default2default:default2D ". amc_tx_p[6] amc_tx_p[6]2default:default2default:default2D ". amc_tx_p[5] amc_tx_p[5]2default:default2default:default2D ". amc_tx_p[4] amc_tx_p[4]2default:default2default:default2D ". amc_tx_p[3] amc_tx_p[3]2default:default2default:default2D ". amc_tx_p[2] amc_tx_p[2]2default:default2default:default28  DRC|Implementation|Placement|IOs2default:default8ZPLIO-3hpx  Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s %s %s %s %s %s %s %s %s %s and 1 more (total of 12.)%s*DRC2J "4 k7_amc_rx_n[15:1] k7_amc_rx_n2default:default2default:default2L "6 k7_amc_rx_n[11]k7_amc_rx_n[11]2default:default2default:default2L "6 k7_amc_rx_n[10]k7_amc_rx_n[10]2default:default2default:default2J "4 k7_amc_rx_n[9]k7_amc_rx_n[9]2default:default2default:default2J "4 k7_amc_rx_n[8]k7_amc_rx_n[8]2default:default2default:default2J "4 k7_amc_rx_n[7]k7_amc_rx_n[7]2default:default2default:default2J "4 k7_amc_rx_n[6]k7_amc_rx_n[6]2default:default2default:default2J "4 k7_amc_rx_n[5]k7_amc_rx_n[5]2default:default2default:default2J "4 k7_amc_rx_n[4]k7_amc_rx_n[4]2default:default2default:default2J "4 k7_amc_rx_n[3]k7_amc_rx_n[3]2default:default2default:default2J "4 k7_amc_rx_n[2]k7_amc_rx_n[2]2default:default2default:default28  DRC|Implementation|Placement|IOs2default:default8ZPLIO-3hpx  Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s %s %s %s %s %s %s %s %s %s and 1 more (total of 12.)%s*DRC2J "4 k7_amc_rx_p[15:1] k7_amc_rx_p2default:default2default:default2L "6 k7_amc_rx_p[11]k7_amc_rx_p[11]2default:default2default:default2L "6 k7_amc_rx_p[10]k7_amc_rx_p[10]2default:default2default:default2J "4 k7_amc_rx_p[9]k7_amc_rx_p[9]2default:default2default:default2J "4 k7_amc_rx_p[8]k7_amc_rx_p[8]2default:default2default:default2J "4 k7_amc_rx_p[7]k7_amc_rx_p[7]2default:default2default:default2J "4 k7_amc_rx_p[6]k7_amc_rx_p[6]2default:default2default:default2J "4 k7_amc_rx_p[5]k7_amc_rx_p[5]2default:default2default:default2J "4 k7_amc_rx_p[4]k7_amc_rx_p[4]2default:default2default:default2J "4 k7_amc_rx_p[3]k7_amc_rx_p[3]2default:default2default:default2J "4 k7_amc_rx_p[2]k7_amc_rx_p[2]2default:default2default:default28  DRC|Implementation|Placement|IOs2default:default8ZPLIO-3hpx b DRC finished with %s 79* vivadotcl2( 0 Errors, 4 Warnings2default:defaultZ4-198hpx e BPlease refer to the DRC report (report_drc) for more information. 80* vivadotclZ4-199hpx V  Starting %s Task 103* constraints2 Routing2default:defaultZ18-103hpx } BMultithreading enabled for route_design using a maximum of %s CPUs17* routeflow2 22default:defaultZ35-254hpx p Phase %s%s 101* constraints2 1 2default:default2# Build RT Design2default:defaultZ18-101hpx B -Phase 1 Build RT Design | Checksum: e08d330d *commonhpx   %s * constraints2o [Time (s): cpu = 00:02:08 ; elapsed = 00:01:23 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx v Phase %s%s 101* constraints2 2 2default:default2) Router Initialization2default:defaultZ18-101hpx o Phase %s%s 101* constraints2 2.1 2default:default2 Create Timer2default:defaultZ18-101hpx A ,Phase 2.1 Create Timer | Checksum: e08d330d *commonhpx   %s * constraints2o [Time (s): cpu = 00:02:11 ; elapsed = 00:01:26 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx { Phase %s%s 101* constraints2 2.2 2default:default2, Fix Topology Constraints2default:defaultZ18-101hpx M 8Phase 2.2 Fix Topology Constraints | Checksum: e08d330d *commonhpx   %s * constraints2o [Time (s): cpu = 00:02:14 ; elapsed = 00:01:28 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx t Phase %s%s 101* constraints2 2.3 2default:default2% Pre Route Cleanup2default:defaultZ18-101hpx F 1Phase 2.3 Pre Route Cleanup | Checksum: e08d330d *commonhpx   %s * constraints2o [Time (s): cpu = 00:02:15 ; elapsed = 00:01:29 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx p Phase %s%s 101* constraints2 2.4 2default:default2! Update Timing2default:defaultZ18-101hpx C .Phase 2.4 Update Timing | Checksum: 1a0c8b2a6 *commonhpx   %s * constraints2o [Time (s): cpu = 00:04:37 ; elapsed = 00:03:09 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx  Intermediate Timing Summary %s164*route2M 9| WNS=1.037 | TNS=0.000 | WHS=-0.440 | THS=-12621.345| 2default:defaultZ35-416hpx I 4Phase 2 Router Initialization | Checksum: 1b27738ea *commonhpx   %s * constraints2o [Time (s): cpu = 00:05:43 ; elapsed = 00:03:49 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx p Phase %s%s 101* constraints2 3 2default:default2# Initial Routing2default:defaultZ18-101hpx C .Phase 3 Initial Routing | Checksum: 1d359dd7a *commonhpx   %s * constraints2o [Time (s): cpu = 00:09:02 ; elapsed = 00:05:39 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx s Phase %s%s 101* constraints2 4 2default:default2& Rip-up And Reroute2default:defaultZ18-101hpx u Phase %s%s 101* constraints2 4.1 2default:default2& Global Iteration 02default:defaultZ18-101hpx  Intermediate Timing Summary %s164*route2J 6| WNS=0.607 | TNS=0.000 | WHS=N/A | THS=N/A | 2default:defaultZ35-416hpx H 3Phase 4.1 Global Iteration 0 | Checksum: 146df2eb0 *commonhpx   %s * constraints2o [Time (s): cpu = 00:17:27 ; elapsed = 00:11:19 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx F 1Phase 4 Rip-up And Reroute | Checksum: 146df2eb0 *commonhpx   %s * constraints2o [Time (s): cpu = 00:17:28 ; elapsed = 00:11:20 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx | Phase %s%s 101* constraints2 5 2default:default2/ Delay and Skew Optimization2default:defaultZ18-101hpx p Phase %s%s 101* constraints2 5.1 2default:default2! Delay CleanUp2default:defaultZ18-101hpx C .Phase 5.1 Delay CleanUp | Checksum: 146df2eb0 *commonhpx   %s * constraints2o [Time (s): cpu = 00:17:30 ; elapsed = 00:11:21 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx z Phase %s%s 101* constraints2 5.2 2default:default2+ Clock Skew Optimization2default:defaultZ18-101hpx M 8Phase 5.2 Clock Skew Optimization | Checksum: 146df2eb0 *commonhpx   %s * constraints2o [Time (s): cpu = 00:17:30 ; elapsed = 00:11:22 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx O :Phase 5 Delay and Skew Optimization | Checksum: 146df2eb0 *commonhpx   %s * constraints2o [Time (s): cpu = 00:17:31 ; elapsed = 00:11:23 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx n Phase %s%s 101* constraints2 6 2default:default2! Post Hold Fix2default:defaultZ18-101hpx p Phase %s%s 101* constraints2 6.1 2default:default2! Hold Fix Iter2default:defaultZ18-101hpx r Phase %s%s 101* constraints2 6.1.1 2default:default2! Update Timing2default:defaultZ18-101hpx E 0Phase 6.1.1 Update Timing | Checksum: 151d68afb *commonhpx   %s * constraints2o [Time (s): cpu = 00:17:53 ; elapsed = 00:11:36 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx  Intermediate Timing Summary %s164*route2J 6| WNS=0.607 | TNS=0.000 | WHS=-0.012 | THS=-0.177 | 2default:defaultZ35-416hpx B -Phase 6.1 Hold Fix Iter | Checksum: f9f3b382 *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:01 ; elapsed = 00:11:41 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx A ,Phase 6 Post Hold Fix | Checksum: 17672ccdf *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:02 ; elapsed = 00:11:43 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx o Phase %s%s 101* constraints2 7 2default:default2" Route finalize2default:defaultZ18-101hpx A ,Phase 7 Route finalize | Checksum: ca853298 *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:05 ; elapsed = 00:11:45 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx v Phase %s%s 101* constraints2 8 2default:default2) Verifying routed nets2default:defaultZ18-101hpx H 3Phase 8 Verifying routed nets | Checksum: ca853298 *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:06 ; elapsed = 00:11:46 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx r Phase %s%s 101* constraints2 9 2default:default2% Depositing Routes2default:defaultZ18-101hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 \sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/GTREFCLK0\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/GTREFCLK02default:default2P GTXE2_CHANNEL_X0Y8/GTREFCLK1GTXE2_CHANNEL_X0Y8/GTREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK12default:default2\ "GTXE2_CHANNEL_X0Y28/GTNORTHREFCLK1"GTXE2_CHANNEL_X0Y28/GTNORTHREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK12default:default2\ "GTXE2_CHANNEL_X0Y31/GTNORTHREFCLK1"GTXE2_CHANNEL_X0Y31/GTNORTHREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK12default:default2\ "GTXE2_CHANNEL_X0Y30/GTNORTHREFCLK1"GTXE2_CHANNEL_X0Y30/GTNORTHREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK12default:default2\ "GTXE2_CHANNEL_X0Y21/GTSOUTHREFCLK1"GTXE2_CHANNEL_X0Y21/GTSOUTHREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK12default:default2\ "GTXE2_CHANNEL_X0Y20/GTSOUTHREFCLK1"GTXE2_CHANNEL_X0Y20/GTSOUTHREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK12default:default2\ "GTXE2_CHANNEL_X0Y23/GTSOUTHREFCLK1"GTXE2_CHANNEL_X0Y23/GTSOUTHREFCLK12default:default8Z35-467hpx D /Phase 9 Depositing Routes | Checksum: 71f20b3b *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:33 ; elapsed = 00:12:17 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx t Phase %s%s 101* constraints2 10 2default:default2& Post Router Timing2default:defaultZ18-101hpx q Phase %s%s 101* constraints2 10.1 2default:default2! Update Timing2default:defaultZ18-101hpx C .Phase 10.1 Update Timing | Checksum: f13b0a68 *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:55 ; elapsed = 00:12:32 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx  Estimated Timing Summary %s 57*route2J 6| WNS=0.607 | TNS=0.000 | WHS=0.050 | THS=0.000 | 2default:defaultZ35-57hpx  The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. 127*routeZ35-327hpx F 1Phase 10 Post Router Timing | Checksum: f13b0a68 *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:56 ; elapsed = 00:12:33 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx @ Router Completed Successfully 2* routeflowZ35-16hpx   %s * constraints2o [Time (s): cpu = 00:18:57 ; elapsed = 00:12:34 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx Z Releasing license: %s 83*common2" Implementation2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 982default:default2 2212default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 route_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" route_design: 2default:default2 00:19:342default:default2 00:12:542default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1392default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  H &Writing timing data to binary archive.266*timingZ38-480hpx D Writing placer database... 1603* designutilsZ20-1893hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:012default:default2 00:00:00.1372default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  = Writing XDEF routing. 211* designutilsZ20-211hpx J #Writing XDEF routing logical nets. 209* designutilsZ20-209hpx J #Writing XDEF routing special nets. 210* designutilsZ20-210hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2) Write XDEF Complete: 2default:default2 00:01:262default:default2 00:00:312default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   The %s '%s' has been generated. 621*common2 checkpoint2default:default2] ID:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_routed.dcp2default:defaultZ17-1381hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2& write_checkpoint: 2default:default2 00:01:452default:default2 00:00:522default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2~ jExecuting : report_drc -file fc7_top_drc_routed.rpt -pb fc7_top_drc_routed.pb -rpx fc7_top_drc_routed.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2q ]report_drc -file fc7_top_drc_routed.rpt -pb fc7_top_drc_routed.pb -rpx fc7_top_drc_routed.rpx2default:defaultZ4-113hpx > IP Catalog is up to date.1232*coregenZ19-1839hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  #The results of DRC are in file %s. 168*coretcl2 MD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_drc_routed.rptMD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_drc_routed.rpt2default:default8Z2-168hpx \ %s completed successfully 29* vivadotcl2 report_drc2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 report_drc: 2default:default2 00:01:152default:default2 00:00:412default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2 Executing : report_methodology -file fc7_top_methodology_drc_routed.rpt -pb fc7_top_methodology_drc_routed.pb -rpx fc7_top_methodology_drc_routed.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2 report_methodology -file fc7_top_methodology_drc_routed.rpt -pb fc7_top_methodology_drc_routed.pb -rpx fc7_top_methodology_drc_routed.rpx2default:defaultZ4-113hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx Y $Running Methodology with %s threads 74*drc2 22default:defaultZ23-133hpx  2The results of Report Methodology are in file %s. 450*coretcl2 YD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_methodology_drc_routed.rptYD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_methodology_drc_routed.rpt2default:default8Z2-1520hpx d %s completed successfully 29* vivadotcl2& report_methodology2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2( report_methodology: 2default:default2 00:02:542default:default2 00:01:422default:default2 6359.1252default:default2 449.3362default:defaultZ17-268hp x   %s4*runtcl2 zExecuting : report_power -file fc7_top_power_routed.rpt -pb fc7_top_power_summary_routed.pb -rpx fc7_top_power_routed.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2 mreport_power -file fc7_top_power_routed.rpt -pb fc7_top_power_summary_routed.pb -rpx fc7_top_power_routed.rpx2default:defaultZ4-113hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx K ,Running Vector-less Activity Propagation... 51*powerZ33-51hpx P 3 Finished Running Vector-less Activity Propagation 1*powerZ33-1hpx  Detected over-assertion of set/reset/preset/clear net with high fanouts, power estimation might not be accurate. Please run Tool - Power Constraint Wizard to set proper switching activities for control signals.282*powerZ33-332hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 1102default:default2 2222default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 report_power2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" report_power: 2default:default2 00:02:492default:default2 00:01:382default:default2 6634.6682default:default2 275.5432default:defaultZ17-268hp x   %s4*runtcl2o [Executing : report_route_status -file fc7_top_route_status.rpt -pb fc7_top_route_status.pb 2default:defaulthpx  %s4*runtcl2 Executing : report_timing_summary -max_paths 10 -file fc7_top_timing_summary_routed.rpt -pb fc7_top_timing_summary_routed.pb -rpx fc7_top_timing_summary_routed.rpx -warn_on_violation 2default:defaulthpx r UpdateTimingParams:%s. 91*timing29 % Speed grade: -2, Delay Type: min_max2default:defaultZ38-91hpx | CMultithreading enabled for timing update using a maximum of %s CPUs155*timing2 22default:defaultZ38-191hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2+ report_timing_summary: 2default:default2 00:00:172default:default2 00:00:122default:default2 6803.0632default:default2 144.6912default:defaultZ17-268hp x   %s4*runtcl2d PExecuting : report_incremental_reuse -file fc7_top_incremental_reuse_routed.rpt 2default:defaulthpx g BIncremental flow is disabled. No incremental reuse Info to report.423* vivadotclZ4-1062hpx  %s4*runtcl2d PExecuting : report_clock_utilization -file fc7_top_clock_utilization_routed.rpt 2default:defaulthpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. report_clock_utilization: 2default:default2 00:00:152default:default2 00:00:152default:default2 6814.6882default:default2 11.6252default:defaultZ17-268hp x   End Record