Q Command: %s 53* vivadotcl2 place_design2default:defaultZ4-113hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2" Implementation2default:default2 xc7k420t2default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2" Implementation2default:default2 xc7k420t2default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2020.012default:defaultZ17-1540hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx V DRC finished with %s 79* vivadotcl2 0 Errors2default:defaultZ4-198hpx e BPlease refer to the DRC report (report_drc) for more information. 80* vivadotclZ4-199hpx p ,Running DRC as a precondition to command %s 22* vivadotcl2 place_design2default:defaultZ4-22hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  YReport rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.%s*DRC29 !DRC|DRC System|Rule limit reached2default:default8ZCHECK-3hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]engFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx RAMB36 async control check: The RAMB36E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2 " UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg UngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9]2default:default2default:default2 " YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]YngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]2default:default2default:default2 " dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1] dngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]2default:default2default:default2B *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8Z REQP-1839hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[0]cpld2fpga_gpio[0]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[1]cpld2fpga_gpio[1]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[2]cpld2fpga_gpio[2]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[3]cpld2fpga_gpio[3]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[10]fmc_l12_la_n[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[11]fmc_l12_la_n[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[13]fmc_l12_la_n[13]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[14]fmc_l12_la_n[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[15]fmc_l12_la_n[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[17]fmc_l12_la_n[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[18]fmc_l12_la_n[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[19]fmc_l12_la_n[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[20]fmc_l12_la_n[20]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[22]fmc_l12_la_n[22]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[23]fmc_l12_la_n[23]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[24]fmc_l12_la_n[24]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[26]fmc_l12_la_n[26]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[27]fmc_l12_la_n[27]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[29]fmc_l12_la_n[29]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[30]fmc_l12_la_n[30]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[31]fmc_l12_la_n[31]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[33]fmc_l12_la_n[33]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[4]fmc_l12_la_n[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[6]fmc_l12_la_n[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[7]fmc_l12_la_n[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[8]fmc_l12_la_n[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[10]fmc_l12_la_p[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[11]fmc_l12_la_p[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[12]fmc_l12_la_p[12]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[14]fmc_l12_la_p[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[15]fmc_l12_la_p[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[17]fmc_l12_la_p[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[18]fmc_l12_la_p[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[19]fmc_l12_la_p[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[20]fmc_l12_la_p[20]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[21]fmc_l12_la_p[21]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[23]fmc_l12_la_p[23]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[24]fmc_l12_la_p[24]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[26]fmc_l12_la_p[26]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[27]fmc_l12_la_p[27]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[28]fmc_l12_la_p[28]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[30]fmc_l12_la_p[30]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[31]fmc_l12_la_p[31]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[33]fmc_l12_la_p[33]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[4]fmc_l12_la_p[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[5]fmc_l12_la_p[5]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[7]fmc_l12_la_p[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[8]fmc_l12_la_p[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_spare[6]fmc_l12_spare[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_spare[7]fmc_l12_spare[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[10]fmc_l8_la_n[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[11]fmc_l8_la_n[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[13]fmc_l8_la_n[13]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[14]fmc_l8_la_n[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[15]fmc_l8_la_n[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[17]fmc_l8_la_n[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[18]fmc_l8_la_n[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[19]fmc_l8_la_n[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[4]fmc_l8_la_n[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[6]fmc_l8_la_n[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[7]fmc_l8_la_n[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[8]fmc_l8_la_n[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[10]fmc_l8_la_p[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[11]fmc_l8_la_p[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[12]fmc_l8_la_p[12]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[14]fmc_l8_la_p[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[15]fmc_l8_la_p[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[17]fmc_l8_la_p[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[18]fmc_l8_la_p[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[19]fmc_l8_la_p[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[4]fmc_l8_la_p[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[5]fmc_l8_la_p[5]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[7]fmc_l8_la_p[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[8]fmc_l8_la_p[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[0]fmc_l8_spare[0]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[10]fmc_l8_spare[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[11]fmc_l8_spare[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[12]fmc_l8_spare[12]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[13]fmc_l8_spare[13]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[14]fmc_l8_spare[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[15]fmc_l8_spare[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[16]fmc_l8_spare[16]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[17]fmc_l8_spare[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[18]fmc_l8_spare[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[19]fmc_l8_spare[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[1]fmc_l8_spare[1]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[2]fmc_l8_spare[2]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[3]fmc_l8_spare[3]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[4]fmc_l8_spare[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[5]fmc_l8_spare[5]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[6]fmc_l8_spare[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[7]fmc_l8_spare[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[8]fmc_l8_spare[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[9]fmc_l8_spare[9]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2V "@ k7_fabric_amc_rx_n03k7_fabric_amc_rx_n032default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2V "@ k7_fabric_amc_rx_p03k7_fabric_amc_rx_p032default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx d DRC finished with %s 79* vivadotcl2* 0 Errors, 117 Warnings2default:defaultZ4-198hpx e BPlease refer to the DRC report (report_drc) for more information. 80* vivadotclZ4-199hpx U  Starting %s Task 103* constraints2 Placer2default:defaultZ18-103hpx } BMultithreading enabled for place_design using a maximum of %s CPUs12* placeflow2 22default:defaultZ30-611hpx v Phase %s%s 101* constraints2 1 2default:default2) Placer Initialization2default:defaultZ18-101hpx  Phase %s%s 101* constraints2 1.1 2default:default29 %Placer Initialization Netlist Sorting2default:defaultZ18-101hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1442default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  [ FPhase 1.1 Placer Initialization Netlist Sorting | Checksum: 11553df4f *commonhpx   %s * constraints2s _Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.197 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1972default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   Phase %s%s 101* constraints2 1.2 2default:default2F 2IO Placement/ Clock Placement/ Build Placer Device2default:defaultZ18-101hpx  [Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s 87*place2 amc_tx_n2default:default2  'amc_tx_n[11]' 'amc_tx_n[10]' 'amc_tx_n[9]' 'amc_tx_n[8]' 'amc_tx_n[7]' 'amc_tx_n[6]' 'amc_tx_n[5]' 'amc_tx_n[4]' 'amc_tx_n[3]' 'amc_tx_n[2]' 'amc_tx_n[1]' " amc_tx_n[11]2 ':' '" amc_tx_n[10]:' '" amc_tx_n[9]:' '" amc_tx_n[8]:' '" amc_tx_n[7]:' '" amc_tx_n[6]:' '" amc_tx_n[5]:' '" amc_tx_n[4]:' '" amc_tx_n[3]:' '" amc_tx_n[2]:' '" amc_tx_n[1]:' 2default:default8Z30-87hpx  [Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s 87*place2 amc_tx_p2default:default2  'amc_tx_p[11]' 'amc_tx_p[10]' 'amc_tx_p[9]' 'amc_tx_p[8]' 'amc_tx_p[7]' 'amc_tx_p[6]' 'amc_tx_p[5]' 'amc_tx_p[4]' 'amc_tx_p[3]' 'amc_tx_p[2]' 'amc_tx_p[1]' " amc_tx_p[11]2 ':' '" amc_tx_p[10]:' '" amc_tx_p[9]:' '" amc_tx_p[8]:' '" amc_tx_p[7]:' '" amc_tx_p[6]:' '" amc_tx_p[5]:' '" amc_tx_p[4]:' '" amc_tx_p[3]:' '" amc_tx_p[2]:' '" amc_tx_p[1]:' 2default:default8Z30-87hpx  [Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s 87*place2 k7_amc_rx_n2default:default2  'k7_amc_rx_n[11]' 'k7_amc_rx_n[10]' 'k7_amc_rx_n[9]' 'k7_amc_rx_n[8]' 'k7_amc_rx_n[7]' 'k7_amc_rx_n[6]' 'k7_amc_rx_n[5]' 'k7_amc_rx_n[4]' 'k7_amc_rx_n[3]' 'k7_amc_rx_n[2]' 'k7_amc_rx_n[1]' " k7_amc_rx_n[11]2 ':' '" k7_amc_rx_n[10]:' '" k7_amc_rx_n[9]:' '" k7_amc_rx_n[8]:' '" k7_amc_rx_n[7]:' '" k7_amc_rx_n[6]:' '" k7_amc_rx_n[5]:' '" k7_amc_rx_n[4]:' '" k7_amc_rx_n[3]:' '" k7_amc_rx_n[2]:' '" k7_amc_rx_n[1]:' 2default:default8Z30-87hpx  [Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s 87*place2 k7_amc_rx_p2default:default2  'k7_amc_rx_p[11]' 'k7_amc_rx_p[10]' 'k7_amc_rx_p[9]' 'k7_amc_rx_p[8]' 'k7_amc_rx_p[7]' 'k7_amc_rx_p[6]' 'k7_amc_rx_p[5]' 'k7_amc_rx_p[4]' 'k7_amc_rx_p[3]' 'k7_amc_rx_p[2]' 'k7_amc_rx_p[1]' " k7_amc_rx_p[11]2 ':' '" k7_amc_rx_p[10]:' '" k7_amc_rx_p[9]:' '" k7_amc_rx_p[8]:' '" k7_amc_rx_p[7]:' '" k7_amc_rx_p[6]:' '" k7_amc_rx_p[5]:' '" k7_amc_rx_p[4]:' '" k7_amc_rx_p[3]:' '" k7_amc_rx_p[2]:' '" k7_amc_rx_p[1]:' 2default:default8Z30-87hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx h SPhase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1881b8ff6 *commonhpx   %s * constraints2o [Time (s): cpu = 00:01:07 ; elapsed = 00:00:48 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx } Phase %s%s 101* constraints2 1.3 2default:default2. Build Placer Netlist Model2default:defaultZ18-101hpx P ;Phase 1.3 Build Placer Netlist Model | Checksum: 14d15e4a4 *commonhpx   %s * constraints2o [Time (s): cpu = 00:02:58 ; elapsed = 00:02:09 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx z Phase %s%s 101* constraints2 1.4 2default:default2+ Constrain Clocks/Macros2default:defaultZ18-101hpx M 8Phase 1.4 Constrain Clocks/Macros | Checksum: 14d15e4a4 *commonhpx   %s * constraints2o [Time (s): cpu = 00:02:59 ; elapsed = 00:02:11 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx I 4Phase 1 Placer Initialization | Checksum: 14d15e4a4 *commonhpx   %s * constraints2o [Time (s): cpu = 00:03:00 ; elapsed = 00:02:11 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx q Phase %s%s 101* constraints2 2 2default:default2$ Global Placement2default:defaultZ18-101hpx p Phase %s%s 101* constraints2 2.1 2default:default2! Floorplanning2default:defaultZ18-101hpx C .Phase 2.1 Floorplanning | Checksum: 140c33cb7 *commonhpx   %s * constraints2o [Time (s): cpu = 00:03:36 ; elapsed = 00:02:33 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx  Phase %s%s 101* constraints2 2.2 2default:default20 Physical Synthesis In Placer2default:defaultZ18-101hpx  =Pass %s. Identified %s candidate %s for fanout optimization. 76*physynth2 12default:default2 22default:default2 nets2default:defaultZ32-76hpx  'Processed net %s. Replicated %s times. 81*physynth2^ #sys/ipb/trans/sm/addr_reg[31]_0[16]#sys/ipb/trans/sm/addr_reg[31]_0[16]2default:default2 282default:default8Z32-81hpx  'Processed net %s. Replicated %s times. 81*physynth2^ #sys/ipb/trans/sm/addr_reg[31]_0[17]#sys/ipb/trans/sm/addr_reg[31]_0[17]2default:default2 172default:default8Z32-81hpx  $Optimized %s %s. Created %s new %s. 216*physynth2 22default:default2 nets2default:default2 452default:default2 instances2default:defaultZ32-232hpx  aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s 415*physynth2 12default:default2 22default:default2! nets or cells2default:default2 452default:default2 cells2default:default2 02default:default2 cell2default:default2 02default:default2 cell2default:defaultZ32-775hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:012default:default2 00:00:00.2672default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   0No setup violation found. %s was not performed.344*physynth2. Critical Cell Optimization2default:defaultZ32-670hpx  0No setup violation found. %s was not performed.344*physynth2- DSP Register Optimization2default:defaultZ32-670hpx  0No setup violation found. %s was not performed.344*physynth2/ Shift Register Optimization2default:defaultZ32-670hpx  0No setup violation found. %s was not performed.344*physynth2. BRAM Register Optimization2default:defaultZ32-670hpx R .No candidate nets found for HD net replication521*physynthZ32-949hpx  aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s 415*physynth2 12default:default2 02default:default2 net or cell2default:default2 02default:default2 cell2default:default2 02default:default2 cell2default:default2 02default:default2 cell2default:defaultZ32-775hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1332default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  B - Summary of Physical Synthesis Optimizations *commonhpx B -============================================ *commonhpx   *commonhpx   *commonhpx  ---------------------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ---------------------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Very High Fanout | 45 | 0 | 2 | 0 | 1 | 00:00:58 | | Critical Cell | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 45 | 0 | 2 | 0 | 2 | 00:00:58 | ---------------------------------------------------------------------------------------------------------------------------------------- *commonhpx   *commonhpx   *commonhpx R =Phase 2.2 Physical Synthesis In Placer | Checksum: 2165492ca *commonhpx   %s * constraints2o [Time (s): cpu = 00:11:48 ; elapsed = 00:09:09 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx C .Phase 2 Global Placement | Checksum: bea216e9 *commonhpx   %s * constraints2o [Time (s): cpu = 00:12:05 ; elapsed = 00:09:22 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx q Phase %s%s 101* constraints2 3 2default:default2$ Detail Placement2default:defaultZ18-101hpx } Phase %s%s 101* constraints2 3.1 2default:default2. Commit Multi Column Macros2default:defaultZ18-101hpx O :Phase 3.1 Commit Multi Column Macros | Checksum: bea216e9 *commonhpx   %s * constraints2o [Time (s): cpu = 00:12:07 ; elapsed = 00:09:23 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx  Phase %s%s 101* constraints2 3.2 2default:default20 Commit Most Macros & LUTRAMs2default:defaultZ18-101hpx Q Phase 4.1.1 Post Placement Optimization | Checksum: 15cfd72dd *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:48 ; elapsed = 00:15:07 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx N 9Phase 4.1 Post Commit Optimization | Checksum: 15cfd72dd *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:50 ; elapsed = 00:15:09 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx y Phase %s%s 101* constraints2 4.2 2default:default2* Post Placement Cleanup2default:defaultZ18-101hpx L 7Phase 4.2 Post Placement Cleanup | Checksum: 15cfd72dd *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:53 ; elapsed = 00:15:12 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx s Phase %s%s 101* constraints2 4.3 2default:default2$ Placer Reporting2default:defaultZ18-101hpx F 1Phase 4.3 Placer Reporting | Checksum: 15cfd72dd *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:56 ; elapsed = 00:15:14 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx z Phase %s%s 101* constraints2 4.4 2default:default2+ Final Placement Cleanup2default:defaultZ18-101hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1502default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  M 8Phase 4.4 Final Placement Cleanup | Checksum: 12a4bf385 *commonhpx   %s * constraints2o [Time (s): cpu = 00:18:58 ; elapsed = 00:15:16 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx \ GPhase 4 Post Placement Optimization and Clean-Up | Checksum: 12a4bf385 *commonhpx   %s * constraints2o [Time (s): cpu = 00:19:00 ; elapsed = 00:15:18 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx = (Ending Placer Task | Checksum: feab5849 *commonhpx   %s * constraints2o [Time (s): cpu = 00:19:01 ; elapsed = 00:15:19 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx Z Releasing license: %s 83*common2" Implementation2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 732default:default2 2172default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 place_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" place_design: 2default:default2 00:19:202default:default2 00:15:362default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1352default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  H &Writing timing data to binary archive.266*timingZ38-480hpx D Writing placer database... 1603* designutilsZ20-1893hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1392default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  = Writing XDEF routing. 211* designutilsZ20-211hpx J #Writing XDEF routing logical nets. 209* designutilsZ20-209hpx J #Writing XDEF routing special nets. 210* designutilsZ20-210hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2) Write XDEF Complete: 2default:default2 00:01:082default:default2 00:00:232default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   The %s '%s' has been generated. 621*common2 checkpoint2default:default2] ID:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_placed.dcp2default:defaultZ17-1381hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2& write_checkpoint: 2default:default2 00:01:342default:default2 00:00:512default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  b %s4*runtcl2F 2Executing : report_io -file fc7_top_io_placed.rpt 2default:defaulthpx  kreport_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.274 . Memory (MB): peak = 5909.789 ; gain = 0.000 *commonhpx  %s4*runtcl2z fExecuting : report_utilization -file fc7_top_utilization_placed.rpt -pb fc7_top_utilization_placed.pb 2default:defaulthpx  %s4*runtcl2c OExecuting : report_control_sets -verbose -file fc7_top_control_sets_placed.rpt 2default:defaulthpx  qreport_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 5909.789 ; gain = 0.000 *commonhpx  End Record