O Command: %s 53* vivadotcl2 opt_design2default:defaultZ4-113hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2" Implementation2default:default2 xc7k420t2default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2" Implementation2default:default2 xc7k420t2default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2020.012default:defaultZ17-1540hpx  !Parsing TCL File [%s] from IP %s 328*project2g Sd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/tcl/v7ht.tcl2default:default2h TD:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xci2default:defaultZ1-541hpx  Sourcing Tcl File [%s] 1447* designutils2i Sd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/tcl/v7ht.tcl2default:default8Z20-1688hpx  Finished Sourcing Tcl File [%s] 1445* designutils2i Sd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/tcl/v7ht.tcl2default:default8Z20-1686hpx n ,Running DRC as a precondition to command %s 22* vivadotcl2 opt_design2default:defaultZ4-22hpx R  Starting %s Task 103* constraints2 DRC2default:defaultZ18-103hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[0]cpld2fpga_gpio[0]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[1]cpld2fpga_gpio[1]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[2]cpld2fpga_gpio[2]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2P ": cpld2fpga_gpio[3]cpld2fpga_gpio[3]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[10]fmc_l12_la_n[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[11]fmc_l12_la_n[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[13]fmc_l12_la_n[13]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[14]fmc_l12_la_n[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[15]fmc_l12_la_n[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[17]fmc_l12_la_n[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[18]fmc_l12_la_n[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[19]fmc_l12_la_n[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[20]fmc_l12_la_n[20]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[22]fmc_l12_la_n[22]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[23]fmc_l12_la_n[23]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[24]fmc_l12_la_n[24]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[26]fmc_l12_la_n[26]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[27]fmc_l12_la_n[27]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[29]fmc_l12_la_n[29]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[30]fmc_l12_la_n[30]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[31]fmc_l12_la_n[31]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_n[33]fmc_l12_la_n[33]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[4]fmc_l12_la_n[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[6]fmc_l12_la_n[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[7]fmc_l12_la_n[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_n[8]fmc_l12_la_n[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[10]fmc_l12_la_p[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[11]fmc_l12_la_p[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[12]fmc_l12_la_p[12]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[14]fmc_l12_la_p[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[15]fmc_l12_la_p[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[17]fmc_l12_la_p[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[18]fmc_l12_la_p[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[19]fmc_l12_la_p[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[20]fmc_l12_la_p[20]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[21]fmc_l12_la_p[21]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[23]fmc_l12_la_p[23]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[24]fmc_l12_la_p[24]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[26]fmc_l12_la_p[26]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[27]fmc_l12_la_p[27]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[28]fmc_l12_la_p[28]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[30]fmc_l12_la_p[30]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[31]fmc_l12_la_p[31]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_la_p[33]fmc_l12_la_p[33]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[4]fmc_l12_la_p[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[5]fmc_l12_la_p[5]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[7]fmc_l12_la_p[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l12_la_p[8]fmc_l12_la_p[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_spare[6]fmc_l12_spare[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l12_spare[7]fmc_l12_spare[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[10]fmc_l8_la_n[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[11]fmc_l8_la_n[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[13]fmc_l8_la_n[13]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[14]fmc_l8_la_n[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[15]fmc_l8_la_n[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[17]fmc_l8_la_n[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[18]fmc_l8_la_n[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_n[19]fmc_l8_la_n[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[4]fmc_l8_la_n[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[6]fmc_l8_la_n[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[7]fmc_l8_la_n[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_n[8]fmc_l8_la_n[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[10]fmc_l8_la_p[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[11]fmc_l8_la_p[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[12]fmc_l8_la_p[12]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[14]fmc_l8_la_p[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[15]fmc_l8_la_p[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[17]fmc_l8_la_p[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[18]fmc_l8_la_p[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_la_p[19]fmc_l8_la_p[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[4]fmc_l8_la_p[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[5]fmc_l8_la_p[5]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[7]fmc_l8_la_p[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2J "4 fmc_l8_la_p[8]fmc_l8_la_p[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[0]fmc_l8_spare[0]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[10]fmc_l8_spare[10]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[11]fmc_l8_spare[11]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[12]fmc_l8_spare[12]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[13]fmc_l8_spare[13]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[14]fmc_l8_spare[14]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[15]fmc_l8_spare[15]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[16]fmc_l8_spare[16]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[17]fmc_l8_spare[17]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[18]fmc_l8_spare[18]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2N "8 fmc_l8_spare[19]fmc_l8_spare[19]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[1]fmc_l8_spare[1]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[2]fmc_l8_spare[2]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[3]fmc_l8_spare[3]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[4]fmc_l8_spare[4]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[5]fmc_l8_spare[5]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[6]fmc_l8_spare[6]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[7]fmc_l8_spare[7]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[8]fmc_l8_spare[8]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2L "6 fmc_l8_spare[9]fmc_l8_spare[9]2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2V "@ k7_fabric_amc_rx_n03k7_fabric_amc_rx_n032default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2V "@ k7_fabric_amc_rx_p03k7_fabric_amc_rx_p032default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx b DRC finished with %s 272*project2) 0 Errors, 96 Warnings2default:defaultZ1-461hpx d BPlease refer to the DRC report (report_drc) for more information. 274*projectZ1-462hpx   %s * constraints2o [Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx g  Starting %s Task 103* constraints2, Cache Timing Information2default:defaultZ18-103hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx P ;Ending Cache Timing Information Task | Checksum: 10c9ab98d *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx a  Starting %s Task 103* constraints2& Logic Optimization2default:defaultZ18-103hpx i Phase %s%s 101* constraints2 1 2default:default2 Retarget2default:defaultZ18-101hpx y )Pushed %s inverter(s) to %s load pin(s). 98*opt2 3732default:default2 7342default:defaultZ31-138hpx K Retargeted %s cell(s). 49*opt2 02default:defaultZ31-49hpx < 'Phase 1 Retarget | Checksum: 204094707 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2 Retarget2default:default2 2262default:default2 14822default:defaultZ31-389hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2 Retarget2default:default2 4352default:defaultZ31-1021hpx u Phase %s%s 101* constraints2 2 2default:default2( Constant propagation2default:defaultZ18-101hpx u )Pushed %s inverter(s) to %s load pin(s). 98*opt2 02default:default2 02default:defaultZ31-138hpx H 3Phase 2 Constant propagation | Checksum: 1ad3fc8ae *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2( Constant propagation2default:default2 32442default:default2 84822default:defaultZ31-389hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2( Constant propagation2default:default2 3962default:defaultZ31-1021hpx f Phase %s%s 101* constraints2 3 2default:default2 Sweep2default:defaultZ18-101hpx 9 $Phase 3 Sweep | Checksum: 16ed37936 *commonhpx   %s * constraints2o [Time (s): cpu = 00:01:02 ; elapsed = 00:00:56 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2 Sweep2default:default2 342default:default2 65952default:defaultZ31-389hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2 Sweep2default:default2 11672default:defaultZ31-1021hpx r Phase %s%s 101* constraints2 4 2default:default2% BUFG optimization2default:defaultZ18-101hpx E 0Phase 4 BUFG optimization | Checksum: 16ed37936 *commonhpx   %s * constraints2o [Time (s): cpu = 00:01:09 ; elapsed = 00:01:03 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx  EPhase %s created %s cells of which %s are BUFGs and removed %s cells.395*opt2% BUFG optimization2default:default2 02default:default2 02default:default2 02default:defaultZ31-662hpx | Phase %s%s 101* constraints2 5 2default:default2/ Shift Register Optimization2default:defaultZ18-101hpx N 9Phase 5 Shift Register Optimization | Checksum: d4bf9cd9 *commonhpx   %s * constraints2o [Time (s): cpu = 00:01:37 ; elapsed = 00:01:30 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2/ Shift Register Optimization2default:default2 02default:default2 02default:defaultZ31-389hpx x Phase %s%s 101* constraints2 6 2default:default2+ Post Processing Netlist2default:defaultZ18-101hpx J 5Phase 6 Post Processing Netlist | Checksum: f853391a *commonhpx   %s * constraints2o [Time (s): cpu = 00:01:40 ; elapsed = 00:01:34 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2+ Post Processing Netlist2default:default2 02default:default2 02default:defaultZ31-389hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2+ Post Processing Netlist2default:default2 2042default:defaultZ31-1021hpx / Opt_design Change Summary *commonhpx / ========================= *commonhpx   *commonhpx   *commonhpx  z------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Retarget | 226 | 1482 | 435 | | Constant propagation | 3244 | 8482 | 396 | | Sweep | 34 | 6595 | 1167 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 204 | ------------------------------------------------------------------------------------------------------------------------- *commonhpx   *commonhpx   *commonhpx a  Starting %s Task 103* constraints2& Connectivity Check2default:defaultZ18-103hpx   %s * constraints2o [Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx J 5Ending Logic Optimization Task | Checksum: 1674494c4 *commonhpx   %s * constraints2o [Time (s): cpu = 00:01:43 ; elapsed = 00:01:36 . Memory (MB): peak = 3352.520 ; gain = 0.0002default:defaulthpx a  Starting %s Task 103* constraints2& Power Optimization2default:defaultZ18-103hpx s 7Will skip clock gating for clocks with period < %s ns. 114*pwropt2 2.002default:defaultZ34-132hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx = Applying IDT optimizations ... 9*pwroptZ34-9hpx ? Applying ODC optimizations ... 10*pwroptZ34-10hpx  (%s %s Timing Summary | WNS=%s | TNS=%s |333*physynth2 Estimated2default:default2 2default:default2 2.0162default:default2 0.0002default:defaultZ32-619hpx K ,Running Vector-less Activity Propagation... 51*powerZ33-51hpx P 3 Finished Running Vector-less Activity Propagation 1*powerZ33-1hpx   *pwropthpx e  Starting %s Task 103* constraints2* PowerOpt Patch Enables2default:defaultZ18-103hpx  WRITE_MODE attribute of %s BRAM(s) out of a total of %s has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. 129*pwropt2 42default:default2 5732default:defaultZ34-162hpx d +Structural ODC has moved %s WE to EN ports 155*pwropt2 42default:defaultZ34-201hpx  CNumber of BRAM Ports augmented: %s newly gated: %s Total Ports: %s 65*pwropt2 82default:default2 212default:default2 11462default:defaultZ34-65hpx N 9Ending PowerOpt Patch Enables Task | Checksum: 15c277682 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx J 5Ending Power Optimization Task | Checksum: 15c277682 *commonhpx   %s * constraints2r ^Time (s): cpu = 00:05:46 ; elapsed = 00:03:20 . Memory (MB): peak = 5909.789 ; gain = 2557.2702default:defaulthpx \  Starting %s Task 103* constraints2! Final Cleanup2default:defaultZ18-103hpx a  Starting %s Task 103* constraints2& Logic Optimization2default:defaultZ18-103hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx J 5Ending Logic Optimization Task | Checksum: 15e501d5e *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:46 ; elapsed = 00:00:34 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx E 0Ending Final Cleanup Task | Checksum: 15e501d5e *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:50 ; elapsed = 00:00:38 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx b  Starting %s Task 103* constraints2' Netlist Obfuscation2default:defaultZ18-103hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:012default:default2 00:00:00.1352default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  K 6Ending Netlist Obfuscation Task | Checksum: 15e501d5e *commonhpx   %s * constraints2s _Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.136 . Memory (MB): peak = 5909.789 ; gain = 0.0002default:defaulthpx Z Releasing license: %s 83*common2" Implementation2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 392default:default2 962default:default2 02default:default2 02default:defaultZ4-41hpx \ %s completed successfully 29* vivadotcl2 opt_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 opt_design: 2default:default2 00:08:572default:default2 00:06:052default:default2 5909.7892default:default2 2557.2702default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1362default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x  H &Writing timing data to binary archive.266*timingZ38-480hpx D Writing placer database... 1603* designutilsZ20-1893hpx = Writing XDEF routing. 211* designutilsZ20-211hpx J #Writing XDEF routing logical nets. 209* designutilsZ20-209hpx J #Writing XDEF routing special nets. 210* designutilsZ20-210hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2) Write XDEF Complete: 2default:default2 00:00:002default:default2 00:00:00.1342default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.1372default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   The %s '%s' has been generated. 621*common2 checkpoint2default:default2Z FD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_opt.dcp2default:defaultZ17-1381hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2& write_checkpoint: 2default:default2 00:01:072default:default2 00:00:452default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2{ gExecuting : report_drc -file fc7_top_drc_opted.rpt -pb fc7_top_drc_opted.pb -rpx fc7_top_drc_opted.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2n Zreport_drc -file fc7_top_drc_opted.rpt -pb fc7_top_drc_opted.pb -rpx fc7_top_drc_opted.rpx2default:defaultZ4-113hpx > IP Catalog is up to date.1232*coregenZ19-1839hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  #The results of DRC are in file %s. 168*coretcl2 LD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_drc_opted.rptLD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_drc_opted.rpt2default:default8Z2-168hpx \ %s completed successfully 29* vivadotcl2 report_drc2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 report_drc: 2default:default2 00:00:282default:default2 00:00:152default:default2 5909.7892default:default2 0.0002default:defaultZ17-268hp x   End Record