,2014.3" TimingSummary"PB_RTimingSummaryp 2012.4)Timing analysis from Implemented netlist. j? ,4Q=%?&+,] 2014.3Zmin_maxbslackh p}IIqreport_timing_summary -max_paths 10 -file fc7_top_timing_summary_routed.rpt -pb fc7_top_timing_summary_routed.pb -rpx fc7_top_timing_summary_routed.rpx -warn_on_violationP -2min_max (08@HX`hpx"  ReportTiming Summary Report  Designfc7_top M PartEDevice=7k420t Package=ffg1156 Speed=-2 (PRODUCTION 1.12 2017-02-17) T VersionIVivado v2018.3 (64-bit) SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 DateMon May 18 09:56:07 2020  Commandreport_timing_summary -max_paths 10 -file fc7_top_timing_summary_routed.rpt -pb fc7_top_timing_summary_routed.pb -rpx fc7_top_timing_summary_routed.rpx -warn_on_violation*] ? clk_o_39_997@8@Gߤ D@!(0:@(@ = fabric_clkֳt8@s} D@!(0:ֳt(@ C fabric_clk_FBOUTֳt8@s} D@!(0:ֳt(@ O clk_o_40_08_phase_mon_mmcm_18@˽PD@!(0:(@ P clk_o_39_997_phase_mon_mmcm_2ޖ8@OT6 D@!(0:ޖ(@ L clkfbout_phase_mon_mmcm_2,rR@'*@!(0:,rB@ L clkfbout_phase_mon_mmcm_1ֳtH@s} 4@!(0:ֳt8@ C fabric_clk_PSOUTֳt8@s} D@!(0:ֳt(@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!( 0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!( 0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!( 0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!( 0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!( 0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!( 0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(!0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!("0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(#0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!($0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(%0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(&0:!~@  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!('0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!((0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!()0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(*0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(+0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(,0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(-0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(.0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(/0:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(00:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(10:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(20:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(30:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!~ @UN^@!(40:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC!~ @UN^@!(50:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!~ @UN^@!(60:!~@  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC!~ @UN^@!(70:!~@ ; osc125_a@@_@!(80:@ < clk125_ub@@_@!(90:@ = clk62_5_ub/@@O@!(:0:@ = clk_ipb_ub?@@?@!(;0:/@ ; osc125_b@@_@!(<0:@ A rxWordclkl12_1]_ff @ʠ|^@!(=0:]_ff@ A rxWordclkl12_2]_ff @ʠ|^@!(>0:]_ff@ A rxWordclkl12_3]_ff @ʠ|^@!(?0:]_ff@ A rxWordclkl12_4]_ff @ʠ|^@!(@0:]_ff@ A rxWordclkl12_5]_ff @ʠ|^@!(A0:]_ff@ A rxWordclkl12_6]_ff @ʠ|^@!(B0:]_ff@ A rxWordclkl12_7]_ff @ʠ|^@!(C0:]_ff@ A rxWordclkl12_8]_ff @ʠ|^@!(D0:]_ff@ @ rxWordclkl8_1]_ff @ʠ|^@!(E0:]_ff@ @ rxWordclkl8_2]_ff @ʠ|^@!(F0:]_ff@ @ rxWordclkl8_3]_ff @ʠ|^@!(G0:]_ff@ @ rxWordclkl8_4]_ff @ʠ|^@!(H0:]_ff@  [sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/RXOUTCLK/@@O@!(I0:@  [sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXOUTCLK/@@O@!(J0:@ C ttc_mgt_xpoint_a!~ @UN^@!(K0:!~@ C ttc_mgt_xpoint_bֳt8@s} D@!(L0:ֳt(@ C ttc_mgt_xpoint_c!~ @UN^@!(M0:!~@ A txWordclkl12_1]_ff @ʠ|^@!(N0:]_ff@ A txWordclkl12_2]_ff @ʠ|^@!(O0:]_ff@ A txWordclkl12_3]_ff @ʠ|^@!(P0:]_ff@ A txWordclkl12_4]_ff @ʠ|^@!(Q0:]_ff@ A txWordclkl12_5]_ff @ʠ|^@!(R0:]_ff@ A txWordclkl12_6]_ff @ʠ|^@!(S0:]_ff@ A txWordclkl12_7]_ff @ʠ|^@!(T0:]_ff@ A txWordclkl12_8]_ff @ʠ|^@!(U0:]_ff@ @ txWordclkl8_1]_ff @ʠ|^@!(V0:]_ff@ @ txWordclkl8_2]_ff @ʠ|^@!(W0:]_ff@ @ txWordclkl8_3]_ff @ʠ|^@!(X0:]_ff@ @ txWordclkl8_4]_ff @ʠ|^@!(Y0:]_ff@2> checkTimingRpx"; no_clockzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QjRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/sel_sec_jtag_reg/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QjRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/sel_sec_jtag_reg/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QzRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QjRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/sel_sec_jtag_reg/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/QyRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/QiRegister/Latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/sel_sec_jtag_reg/QWRegister/Latch pins with no clock driven by root clock pin: ngFEC/fabric_clk_div2_reg/QTRegister/Latch pins with no clock driven by root clock pin: sys/clocks/rst_ipb_reg/Q_Register/Latch pins with no clock driven by root clock pin: sys/ipb_sys_regs/regs_reg[11][12]/Q(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((H?" constant_clockH" pulse_width_clockH" unconstrained_internal_endpoints$Unconstrained Pins for maximum delay:Unconstrained Pins for maximum delay due to constant clock((H"/ no_input_delayPorts with no input delay(H"1 no_output_delayPorts with no output delay(H" multiple_clockH" generated_clocksH" loopsH" partial_input_delayH" partial_output_delayH" latch_loopsH0 :U checking no_clock checking constant_clock checking pulse_width_clock )checking unconstrained_internal_endpoints checking no_input_delay checking no_output_delay checking multiple_clock checking generated_clocks checking loops checking partial_input_delay checking partial_output_delay checking latch_loopsG checking no_clock  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) ~ There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)~  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) ~ There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)~  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) ~ There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)~  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH)  There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) } There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH)}o k There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/fabric_clk_div2_reg/Q (HIGH)kj f There is 1 register/latch pin with no clock driven by root clock pin: sys/clocks/rst_ipb_reg/Q (HIGH)fu q There is 1 register/latch pin with no clock driven by root clock pin: sys/ipb_sys_regs/regs_reg[11][12]/Q (HIGH)qT checking constant_clock9 5 There are 0 register/latch pins with constant_clock.5_ checking pulse_width_clockA = There are 0 register/latch pins which need pulse_width check= )checking unconstrained_internal_endpointsI E There are 77 pins that are not constrained for maximum delay. (HIGH)E] Y There is 1 pin that is not constrained for maximum delay due to constant clock. (MEDIUM)Y checking no_input_delayC ? There are 91 input ports with no input delay specified. (HIGH)?V R There are 0 input ports with no input delay but user has a false path constraint.R checking no_output_delay> : There are 87 ports with no output delay specified. (HIGH):P L There are 0 ports with no output delay but user has a false path constraintLk g There are 0 ports with no output delay but with a timing clock defined on it or propagating through itgU checking multiple_clock: 6 There are 0 register/latch pins with multiple clocks.6h checking generated_clocksK G There are 0 generated clocks that are not connected to a clock source.GE checking loops3 / There are 0 combinational loops in the design./` checking partial_input_delay@ < There are 0 input ports with partial input delay specified.<\ checking partial_output_delay; 7 There are 0 ports with partial output delay specified.7d checking latch_loopsL H There are 0 combinational latch loops in the design through latch inputH& ns"MHz(0Bcheck_timing reportB SlowYesYes FastYesYes# Enable Multi Corner AnalysisYes Enable Pessimism RemovalYes3 Pessimism Removal ResolutionNearest Common Node& Enable Input Delay Default ClockNo Enable Preset / Clear ArcsNo Disable Flight DelaysNo Ignore I/O PathsNo1 (Timing Early Launch at Borrowing Latchesfalse"B Timing Configuration Reportns"MHz(0Bconfig timing reportR  !)19AIej?hq},4Q=?8@>HPX`Z $ osc125_a Min Period 1_p 2T1"]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/DRPCLK*n/a2) osc125_aA@" osc125_a_p Min Period Z1_p 2a0"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/GTREFCLK0*n/a2) osc125_aA@" osc125_a_pg Min PeriodY r{1_p 200"sys/osc125a_clkbuf/I*n/a2) osc125_aA@" osc125_a_pg Min PeriodY 1_p 20"sys/osc125a_gtebuf/I*n/a2) osc125_aA@" osc125_a_pt Min Periodf 1_p 2m+0"%!sys/clocks/PLLE2_BASE_inst/CLKIN1*n/a2) osc125_aA@" osc125_a_p Min Period z1_p 2j@0"easys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/C*n/a2) osc125_aA@" osc125_a_p Min Period z1_p 2j@0"iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/C*n/a2) osc125_aA@" osc125_a_pt Max Periodf ?3_p 2b3"%!sys/clocks/PLLE2_BASE_inst/CLKIN1*n/a2) osc125_aA@" osc125_a_p"n Lowg ]p 1^p1_p 1"%!sys/clocks/PLLE2_BASE_inst/CLKIN1*Slow2) osc125_aA@" osc125_a_p"n Lowg ap 1`p1_p 1"%!sys/clocks/PLLE2_BASE_inst/CLKIN1*Fast2) osc125_aA@" osc125_a_p" Low f1]p1x00"misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Slow2) osc125_aA@" osc125_a_p" Low f1]p1x00"misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Slow2) osc125_aA@" osc125_a_p" Low f1]p1x00"misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Slow2) osc125_aA@" osc125_a_p" Low f1_p1x00"qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Slow2) osc125_aA@" osc125_a_p" Low f1_p1x00"plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK*Slow2) osc125_aA@" osc125_a_p" Low f1_p1x00"plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK*Slow2) osc125_aA@" osc125_a_p" Low f1_p1x00"plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK*Slow2) osc125_aA@" osc125_a_p" Low f1`p1x00"misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Fast2) osc125_aA@" osc125_a_p*o Highg ]p 1^p1_p 1"%!sys/clocks/PLLE2_BASE_inst/CLKIN1*Fast2) osc125_aA@" osc125_a_p*o Highg ap 1`p1_p 1"%!sys/clocks/PLLE2_BASE_inst/CLKIN1*Slow2) osc125_aA@" osc125_a_p* High f1^p1x00"misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Fast2) osc125_aA@" osc125_a_p* High f1^p1x00"misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Fast2) osc125_aA@" osc125_a_p* High f1^p1x00"misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Fast2) osc125_aA@" osc125_a_p* High f1^p1x00"qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Fast2) osc125_aA@" osc125_a_p* High f1^p1x00"plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK*Fast2) osc125_aA@" osc125_a_p* High f1^p1x00"plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK*Fast2) osc125_aA@" osc125_a_p* High f1^p1x00"plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK*Fast2) osc125_aA@" osc125_a_p* High f1_p1x00"qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Slow2) osc125_aA@" osc125_a_p 9 txWordclkl12_6 Min Period ̣1 2S8P1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period ̣1 2S8P1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0",(ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0",(ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0",(ngFEC/g_pm[10].phase_mon/en_chk_reg[2]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0".*ngFEC/g_pm[10].phase_mon/inh_cntr_reg[2]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C*n/a2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low ǡm1ߌ1x00"qmngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Slow2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low ɡm1ߌ1x00"qmngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/",(ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C*Slow2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/",(ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/",(ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C*Slow2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/",(ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/".*ngFEC/g_pm[10].phase_mon/inh_cntr_reg[2]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High ǡm1ߌ1x00"qmngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Slow2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High ǡm1ߌ1x00"qmngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[119]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[92]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/C*Fast2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C*Slow2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C*Slow2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C*Slow2n txWordclkl12_633A33@"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O 1 rxWordclkl12_4 Min Period ̣1 2S8P1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period ̣1 2S8P1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"GCngFEC/SFP_GEN[1].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"GCngFEC/SFP_GEN[1].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"<8ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[30]/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[31]/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[38]/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O Min Period 1 2(N0"51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/C*n/a2n rxWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O" Low ǡm1ߌ1x00"@:ngFEC/clk_rate_gen[9].clkRate3/counting_sync2_reg_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2^p2x00"?;ngFEC/clk_rate_gen[10].clkRate3/counting_sync2_reg_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2^p2x00"?;ngFEC/clk_rate_gen[11].clkRate3/counting_sync2_reg_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2^p2x00"?;ngFEC/clk_rate_gen[12].clkRate3/counting_sync2_reg_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0"x Lowq 2^p2x00"sys/reset_gen/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2_p2x00">:ngFEC/clk_rate_gen[9].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2_p2x00".*ngFEC/clkRate2/counting_sync2_reg_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2`p2x00">:ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2`p2x00">:ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0" Low 2`p2x00"1-ngFEC/update_toggle_Sync_Regs_reg[1]_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00".*ngFEC/clkRate1/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[1].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[2].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[3].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[4].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[5].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[6].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2]p2x00">:ngFEC/clk_rate_gen[7].clkRate3/counting_sync2_reg_srl2/CLK*Fast2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0* High 2^p2x00">:ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK*Slow2C clk_ipb_ubBA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT0 5 txWordclkl12_4 Min Period ̣1 2S8P1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period ̣1 2S8P1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[7]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[8]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"+'ngFEC/g_pm[1].phase_mon/en_chk_reg[2]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"-)ngFEC/g_pm[1].phase_mon/inh_cntr_reg[2]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O Min Period 1 2(N0"FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C*n/a2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low šm1ߌ1x00"qmngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low ǡm1ߌ1x00"qmngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Fast2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[7]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[8]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"+'ngFEC/g_pm[1].phase_mon/en_chk_reg[2]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"-)ngFEC/g_pm[1].phase_mon/inh_cntr_reg[2]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O" Low C~1ߌ1/"FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High ǡm1ߌ1x00"qmngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Fast2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High ɡm1ߌ1x00"qmngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[19]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[48]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[8]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Xـ1ߌ1j/"ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[9]/C*Slow2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Yـ1ߌ1j/"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[0]/C*Fast2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Yـ1ߌ1j/"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[1]/C*Fast2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Yـ1ߌ1j/"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[2]/C*Fast2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O* High Yـ1ߌ1j/"+'ngFEC/g_pm[1].phase_mon/PS_max_reg[3]/C*Fast2n txWordclkl12_433A33@"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O 3 rxWordclkl12_2 Min Period ̣1 2S8P1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period ̣1 2S8P1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[1][14]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"A=ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[3][2]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"A=ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[3][3]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][12]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"A=ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][1]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"A=ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][3]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][11]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O Min Period 1 2(N0"B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/C*n/a2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O" Low šm1ߌ1x00"@ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[0][15]/C*Slow2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O* High Xـ1ߌ1j/"B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[3][15]/C*Slow2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O* High Xـ1ߌ1j/"A=ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][0]/C*Slow2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O* High Xـ1ߌ1j/"B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][11]/C*Slow2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O* High Xـ1ߌ1j/"B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][15]/C*Slow2n rxWordclkl12_233A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O* High Xـ1ߌ1j/"@ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][11]/C*Slow2n rxWordclkl12_333A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O* High Xـ1ߌ1j/"B>ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][12]/C*Slow2n rxWordclkl12_333A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O* High Xـ1ߌ1j/"A=ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][1]/C*Slow2n rxWordclkl12_333A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O* High Xـ1ߌ1j/"A=ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][2]/C*Slow2n rxWordclkl12_333A33@"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O 8 ttc_mgt_xpoint_c Min Period ty1(2a0"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period ty1(2a0"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period ty1(2a0"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period ty1(2a0"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period ty1(2a0"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period ty1(2a0"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period ty1(2a0"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period ty1(2a0"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period 1(200"0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/I*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p Min Period 1(200"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I*n/a29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p" Low 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Fast29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p* High 3r1(1x00"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK*Slow29 ttc_mgt_xpoint_cSAS@"ttc_mgt_xpoint_c_p  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 7 ttc_mgt_xpoint_a Min Period ty1(2a0"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period ty1(2a0"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period ty1(2a0"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period ty1(2a0"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period 1(200"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period 1(200"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period 1(200"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period 1(200"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Periodq 1(20" ngFEC/cdceOut1IbufdsAGtxe2/I*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p Min Period J"2(2j@0"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C*n/a29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p" Low 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Fast29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p* High 3r1(1x00"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK*Slow29 ttc_mgt_xpoint_aSAS@"ttc_mgt_xpoint_a_p  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/I*n/a2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/I*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/I*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  fabric_clku Min Periodg !2S2m+0""ngFEC/fabric_clk_MMCME2/CLKIN1*n/a2- fabric_clkAGA" fabric_clk_pu Max Periodg *3S23""ngFEC/fabric_clk_MMCME2/CLKIN1*n/a2- fabric_clkAGA" fabric_clk_p"o Lowh m2SV2w̫1""ngFEC/fabric_clk_MMCME2/CLKIN1*Slow2- fabric_clkAGA" fabric_clk_p"o Lowh m2SV2w̫1""ngFEC/fabric_clk_MMCME2/CLKIN1*Fast2- fabric_clkAGA" fabric_clk_p*p Highh m2SV2w̫1""ngFEC/fabric_clk_MMCME2/CLKIN1*Fast2- fabric_clkAGA" fabric_clk_p*p Highh m2SV2w̫1""ngFEC/fabric_clk_MMCME2/CLKIN1*Slow2- fabric_clkAGA" fabric_clk_p  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I*n/a2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period 1(200"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK $ clk_o_39_997 Min Period 2:X2(N0"1-ngFEC/dmdt_meas/DMTD_A/new_edge_sreg_reg[5]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[6]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[7]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[8]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[9]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0"1-ngFEC/dmdt_meas/DMTD_B/new_edge_sreg_reg[5]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0")%ngFEC/dmdt_meas/DMTD_B/tag_o_reg[5]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0")%ngFEC/dmdt_meas/DMTD_B/tag_o_reg[6]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period 2:X2(N0")%ngFEC/dmdt_meas/DMTD_B/tag_o_reg[9]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O Min Period T2:X2j@0"40ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[0]/C*n/a2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO29XV2/")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[6]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO29XV2/")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[7]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO29XV2/")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[8]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO29XV2/")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[9]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO29XV2/")%ngFEC/dmdt_meas/DMTD_B/tag_o_reg[5]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO29XV2/")%ngFEC/dmdt_meas/DMTD_B/tag_o_reg[6]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO29XV2/")%ngFEC/dmdt_meas/DMTD_B/tag_o_reg[9]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO2:XV2/"1-ngFEC/dmdt_meas/DMTD_A/new_edge_sreg_reg[5]/C*Slow2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO2:XV2/"1-ngFEC/dmdt_meas/DMTD_A/new_edge_sreg_reg[5]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O" Low yO2:XV2/")%ngFEC/dmdt_meas/DMTD_A/tag_o_reg[6]/C*Slow2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"40ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[0]/C*Slow2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"40ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[0]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"40ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[1]/C*Slow2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"40ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[1]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"40ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[2]/C*Slow2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"40ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[2]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"-)ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[0]/C*Slow2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/"-)ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[0]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/".*ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[10]/C*Slow2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O* High TP2:XV2j/".*ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[10]/C*Fast2H clk_o_39_997AGA")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/I*n/a2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(2u&1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period 1(200"MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/I*n/a2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKSAS@"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK ( clk125_ub Min Period 1_p 20"1-sys/ipb/udp_if/internal_ram/ram_reg/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"1-sys/ipb/udp_if/internal_ram/ram_reg/CLKBWRCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_1/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_0/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_1/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_0/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Min Period 1_p 20"40sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_1/CLKARDCLK*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Max Period ?3_p 2b3"&"sys/clocks/PLLE2_BASE_inst/CLKFBIN*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT Max Period q5#4_p 2w+4"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT*n/a2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[0].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[1].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[2].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[3].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[4].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[5].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[6].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[7].SRL16E_inst/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"}sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[0]_srl5/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT" Low f1]p1x00"}sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[1]_srl5/CLK*Slow2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"#sys/clocks/clkdiv/reset_gen/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[0].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[1].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[2].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[3].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[4].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[5].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[6].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"95sys/eth/mac/i_mac/g_emacclientrxdp[7].SRL16E_inst/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT* High f1^p1x00"($sys/eth/mac/i_mac/i_ce_rx_crc_dl/CLK*Fast2C clk125_ubA@"'#sys/clocks/PLLE2_BASE_inst/CLKFBOUT / clk62_5_ub Min Period ^2_p2S8P1"_[sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/RXUSRCLK*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period ^2_p2S8P1"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/RXUSRCLK2*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period ^2_p2S8P1"_[sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXUSRCLK*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period ^2_p2S8P1"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXUSRCLK2*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Periodw z2_p200"sys/clocks/clk62_5_buf/I*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period =2_p2m+0"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period 2_p2(N0"fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period 2_p2(N0"sosys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period 2_p2(N0"sosys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period 2_p2(N0"sosys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg5/C*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 Max Period k4_p2w+4"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1*n/a2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"sosys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"sosys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"sosys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg5/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg3/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg5/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1" Low $2\p 2/"73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2_p 2j/"<8sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C*Fast2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1* High m2`p 2j/"fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C*Slow2C clk62_5_ubAA"&"sys/clocks/PLLE2_BASE_inst/CLKOUT1 . fabric_clk_FBOUT Min Period >2S2T1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Min Period >2S2T1"ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Max Period *3S23"0,ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Max Period *3S23"#ngFEC/fabric_clk_MMCME2/CLKFBIN*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT Max Period xMJ4S2e4"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT*n/a2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low m2SV2w̫1"0,ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low m2SV2w̫1"0,ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low 'E2SV2^0"!ngFEC/fabric_clk_MMCME2/PSCLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low 'E2SV2^0"!ngFEC/fabric_clk_MMCME2/PSCLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low{ GLK2SV2x00"ngFEC/i_PSDONE_dl32/CLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low HLK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low HLK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low ILK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low ILK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT" Low{ JLK2SV2x00"ngFEC/i_PSDONE_dl32/CLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High m2SV2w̫1"0,ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High m2SV2w̫1"0,ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High 'E2SV2^0"!ngFEC/fabric_clk_MMCME2/PSCLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High 'E2SV2^0"!ngFEC/fabric_clk_MMCME2/PSCLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High{ GLK2SV2x00"ngFEC/i_PSDONE_dl32/CLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High HLK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High HLK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High HLK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK*Slow2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High HLK2SV2x00"/+ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT* High{ HLK2SV2x00"ngFEC/i_PSDONE_dl32/CLK*Fast2G fabric_clk_FBOUTAGA"$ ngFEC/fabric_clk_MMCME2/CLKFBOUT  clk_o_39_997_phase_mon_mmcm_2 Min Period >2W200")%ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/I*n/a2a clk_o_39_997_phase_mon_mmcm_2uAuGA"1-ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0 Min Period 4%2W2m+0"1-ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0*n/a2a clk_o_39_997_phase_mon_mmcm_2uAuGA"1-ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0 Max Period LJ4W2e4"1-ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0*n/a2a clk_o_39_997_phase_mon_mmcm_2uAuGA"1-ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0  clkfbout_phase_mon_mmcm_2 Min Period gf3l300"&"ngFEC/dmdt_clk/mmcm2/U0/clkf_buf/I*n/a2^ clkfbout_phase_mon_mmcm_2>hB>hB"2.ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT Min Period  3l3m+0"2.ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT*n/a2^ clkfbout_phase_mon_mmcm_2>hB>hB"2.ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT Min Period  3l3m+0"1-ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBIN*n/a2^ clkfbout_phase_mon_mmcm_2>hB>hB"2.ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT Max Period dK2l33"1-ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBIN*n/a2^ clkfbout_phase_mon_mmcm_2>hB>hB"2.ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT Max Period 4l3e4"2.ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT*n/a2^ clkfbout_phase_mon_mmcm_2>hB>hB"2.ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT  clkfbout_phase_mon_mmcm_1 Min Period yQ3SV3m+0"2.ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT*n/a2^ clkfbout_phase_mon_mmcm_1GBA"2.ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT Min Period yQ3SV3m+0"1-ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBIN*n/a2^ clkfbout_phase_mon_mmcm_1GBA"2.ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT Max Period V+W3SV33"1-ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBIN*n/a2^ clkfbout_phase_mon_mmcm_1GBA"2.ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT Max Period /4SV3e4"2.ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT*n/a2^ clkfbout_phase_mon_mmcm_1GBA"2.ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT8 Iq (08@HPX`hp Pulse Width Reportns"MHz(0:  ReportPulse Width Report  Designfc7_top M PartEDevice=7k420t Package=ffg1156 Speed=-2 (PRODUCTION 1.12 2017-02-17) T VersionIVivado v2018.3 (64-bit) SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 DateMon May 18 09:56:09 2020Bmin pulse width reporthpx  clk_o_39_997 clk_o_39_997!)@(@1@8@9A@(@I@8@hq}W9AA5  fabric_clk fabric_clk!)ֳt(@1ֳt8@9Aֳt(@Iֳt8@hq}K7@1  fabric_clk_FBOUTfabric_clk_FBOUT!)ֳt(@1ֳt8@9Aֳt(@Iֳt8@e5j@hq}T=K7@: rise - rise rise - rise  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg6/C~ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg/D*:BJZ(LUT6=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsuryn>}awJQ=V?JQ?T=9)>o>=k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDSE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg6/Q Prop_fdre_C_Q JFDREXhzf= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/cplllock_sync Jnet (fo=2, routed)Xh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/adapt_count_reset_i_1/I0 JXhzf ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/adapt_count_reset_i_1/OProp_lut6_I0_O JLUT6XhzrA`< |xngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK_n_2 Jnet (fo=1, routed)Xh ~ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg/D JFDSEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< ~ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/SYSCLK_IN Jnet (fo=39427, routed)Xhz4? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg6/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< tpngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/SYSCLK_IN Jnet (fo=39427, routed)XhU? ~ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg/C JFDSEXhzr; Jclock pessimismXh9)> |ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg Hold_fdse_C_D JFDSEXhu=, JXh9 J required timeXhaw8 J arrival timeXh?, JXh1 JslackXhT=,`\ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[14]/CRNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]/D*:BJZ(LUT5=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsuSV>}||ML>+9?M?!]=\=>+->k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) `\ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[14]/Q Prop_fdre_C_Q JFDREXhzr=| <8ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr_reg[7]_14[2] Jnet (fo=1, routed)Xh+->h =9ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr[6]_i_1__69/I4 JXhzr <8ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr[6]_i_1__69/OProp_lut5_I4_O JLUT5XhzrA`< RNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]_0 Jnet (fo=1, routed)Xh RNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< SOngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/clk_local Jnet (fo=39427, routed)XhP? `\ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[14]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/CLKFBIN Jnet (fo=39427, routed)XhQ? RNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]/C JFDREXhzr; Jclock pessimismXh\= PLngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6] Hold_fdre_C_D JFDREXh$y=, JXh9 J required timeXh||8 J arrival timeXh*+?, JXh1 JslackXh!]=gcngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10]/CgcngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]/D*:BJZ(CARRY4=2 LUT3=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu>}ZUv>`,?U?D`=9)>|>J>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) gcngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10]/Q Prop_fdre_C_Q JFDREXhzr= eangFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10] Jnet (fo=3, routed)XhI> lhngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt[8]_i_3__122/I2 JXhzr kgngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt[8]_i_3__122/OProp_lut3_I2_O JLUT3Xhzr< mingFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt[8]_i_3__122_n_0 Jnet (fo=1, routed)Xh songFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[8]_i_1__124/DI[2] JXhzr songFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[8]_i_1__124/CO[3]Prop_carry4_DI[2]_CO[3] JCARRY4Xhzr}= qmngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[8]_i_1__124_n_0 Jnet (fo=1, routed)Xh|5: qmngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]_i_1__111/CI JXhzr songFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]_i_1__111/O[0]Prop_carry4_CI_O[0] JCARRY4Xhzr'= rnngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]_i_1__111_n_7 Jnet (fo=1, routed)Xh gcngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< a]ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN Jnet (fo=39427, routed)Xh ? gcngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< a]ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN Jnet (fo=39427, routed)XhY? gcngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]/C JFDREXhzr; Jclock pessimismXh9)> eangFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12] Hold_fdre_C_D JFDREXhj=, JXh9 J required timeXhZ8 J arrival timeXh\?, JXh1 JslackXhD`=`\ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[11]/CRNngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D*:BJZ(LUT6=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsuR>}Uu,^J>E?,^?;c=f=o>Y>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) `\ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[11]/Q Prop_fdre_C_Q JFDREXhzr= WSngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/DataIn_local[11] Jnet (fo=1, routed)XhY> WSngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__56/I0 JXhzr VRngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__56/OProp_lut6_I0_O JLUT6XhzrA`< XTngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__56_n_0 Jnet (fo=1, routed)Xh RNngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< SOngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/clk_local Jnet (fo=39427, routed)Xh #? `\ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[11]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/CLKFBIN Jnet (fo=39427, routed)Xhb? RNngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3]/C JFDREXhzr; Jclock pessimismXhf= PLngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhUu8 J arrival timeXh1?, JXh1 JslackXh;c=W|ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[3]/C|ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4]/D*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu'z>}lwLR@5^>.@?LR?Y-k=_Z>"=b)>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) |ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[3]/Q Prop_fdre_C_Q JFDREXhzr"= ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg_n_0_[3] Jnet (fo=3, routed)Xhb)> |ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< xtngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/CLKFBIN Jnet (fo=39427, routed)XhS? |ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[3]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< xtngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/CLKFBIN Jnet (fo=39427, routed)XhEV? |ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4]/C JFDREXhzr; Jclock pessimismXh_Z> ~zngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4] Hold_fdre_C_D JFDREXhc, JXh9 J required timeXhlw8 J arrival timeXhI?, JXh1 JslackXhY-k=,`\ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[12]/CRNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]/D*:BJZ(LUT5=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu>}~ML>+9?M?JIk=\=+>8>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) `\ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[12]/Q Prop_fdre_C_Q JFDREXhzr=| <8ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr_reg[7]_14[0] Jnet (fo=1, routed)Xh8>h =9ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr[4]_i_1__69/I4 JXhzr <8ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr[4]_i_1__69/OProp_lut5_I4_O JLUT5Xhzri< RNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]_0 Jnet (fo=1, routed)Xh RNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< SOngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/clk_local Jnet (fo=39427, routed)XhP? `\ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[12]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/CLKFBIN Jnet (fo=39427, routed)XhQ? RNngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]/C JFDREXhzr; Jclock pessimismXh\= PLngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4] Hold_fdre_C_D JFDREXh*\=, JXh9 J required timeXh~8 J arrival timeXh=?, JXh1 JslackXhJIk=TPngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/txr_reg[7]/C]YngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/D*:BJZ(LUT3=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsuΨ>}{5IYI>4W6?5I?XTl=\=>}L>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) TPngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/txr_reg[7]/Q Prop_fdre_C_Q JFDREXhzr= XTngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/txr[7] Jnet (fo=1, routed)Xh}L> b^ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[7]_i_2__19/I0 JXhzr a]ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[7]_i_2__19/OProp_lut3_I0_O JLUT3Xhzr< c_ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[7]_i_2__19_n_0 Jnet (fo=1, routed)Xh ]YngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< OKngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/CLKFBIN Jnet (fo=39427, routed)XhX9? TPngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/txr_reg[7]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< YUngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/CLKFBIN Jnet (fo=39427, routed)XhM? ]YngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/C JFDREXhzr; Jclock pessimismXh\= [WngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7] Hold_fdre_C_D JFDREXh=, JXh9 J required timeXh{8 J arrival timeXh!_?, JXh1 JslackXhXTl=_[ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[3]/CSOngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3]/D*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsuC>}ꊿQh>??Qh?gm=9)>=4ٍ>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) _[ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= VRngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/DataIn_local[3] Jnet (fo=1, routed)Xh4ٍ> SOngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< SOngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/clk_local Jnet (fo=39427, routed)Xhp? _[ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[3]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/CLKFBIN Jnet (fo=39427, routed)XhIl? SOngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3]/C JFDREXhzr; Jclock pessimismXh9)> QMngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3] Hold_fdre_C_D JFDREXhO=, JXh9 J required timeXhꊿ8 J arrival timeXh-X?, JXh1 JslackXhgm=SOngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/txr_reg[4]/C\XngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4]/D*:BJZ(LUT3=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsuB>}awqr)1>BH?qr?m=f=>偔>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/txr_reg[4]/Q Prop_fdre_C_Q JFDREXhzr= WSngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/txr[4] Jnet (fo=1, routed)Xh偔> a]ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[4]_i_1__64/I0 JXhzr `\ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[4]_i_1__64/OProp_lut3_I0_O JLUT3Xhzr< b^ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[4]_i_1__64_n_0 Jnet (fo=1, routed)Xh \XngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4]/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/CLKFBIN Jnet (fo=39427, routed)Xh$&? SOngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/txr_reg[4]/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< XTngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/CLKFBIN Jnet (fo=39427, routed)Xh-v? \XngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4]/C JFDREXhzr; Jclock pessimismXhf= ZVngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4] Hold_fdre_C_D JFDREXh=, JXh9 J required timeXhaw8 J arrival timeXh?, JXh1 JslackXhm=njngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_to_reg/CkgngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg/D*:BJZ(LUT5=1)j=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsuT>}ْnck:>K?nck?n=8)>o>>k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) njngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_to_reg/Q Prop_fdre_C_Q JFDREXhzf= ~ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/slave_wait_reg_0 Jnet (fo=2, routed)Xh> ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/slave_wait_i_1__2/I4 JXhzf ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/slave_wait_i_1__2/OProp_lut5_I4_O JLUT5XhzrA`< fbngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait0 Jnet (fo=1, routed)Xh kgngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg/D JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< b^ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN Jnet (fo=39427, routed)Xh(? njngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_to_reg/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< b^ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN Jnet (fo=39427, routed)Xh*\o? kgngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg/C JFDREXhzr; Jclock pessimismXh8)> iengFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhْ8 J arrival timeXhO?, JXh1 JslackXhn=ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsu8A}AFA0h;?0?Arӥ=А=.>5j@<>Ak(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)Xh%TAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xhh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXhFA8 J arrival timeXh, JXh1 JslackXh5j@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuA}AA',?'?Arӥ=А=.>2n@<>9%Ak(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)Xh:TAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXhA8 J arrival timeXh), JXh1 JslackXh2n@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuA}AA',?'?Arӥ=А=.>2n@<>9%Ak(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)Xh:TAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXhA8 J arrival timeXh), JXh1 JslackXh2n@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsu]KA}A}AB!/?B?Arӥ=А=.>mIn@<>Ak(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)Xh SAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xhz?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh}A8 J arrival timeXhδ, JXh1 JslackXhmIn@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsu7A}AqAXA?X?Arӥ=А=.>Qp@<>Ak(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)XhRAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)XhO?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhqA8 J arrival timeXhW, JXh1 JslackXhQp@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuA}AuA0h;?0?Arӥ=А=.>r@<>QAk(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)XhRAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xhh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhuA8 J arrival timeXh%, JXh1 JslackXhr@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuA}AuA0h;?0?Arӥ=А=.>r@<>QAk(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)XhRAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xhh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhuA8 J arrival timeXh%, JXh1 JslackXhr@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuA}AuA0h;?0?Arӥ=А=.>r@<>QAk(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)XhRAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xhh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhuA8 J arrival timeXh%, JXh1 JslackXhr@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuA}AuA0h;?0?Arӥ=А=.>r@<>QAk(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)XhRAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xhh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhuA8 J arrival timeXh%, JXh1 JslackXhr@ngFEC/fabric_clk_div2_reg/C51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43]/CE*:BJZ(LUT1=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuA}AFA0h;?0?Arӥ=А=.>$w@<>.Ak(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_FBOUTfabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)c ngFEC/fabric_clk_div2_reg/Q Prop_fdre_C_Q JFDREXhzf>r /+ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 Jnet (fo=2709, routed)Xhg@a 62ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/I0 JXhzfz 51ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=y 73ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] Jnet (fo=361, routed)Xh QAd 51ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43]/CE JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=U  ngFEC/CLKFBIN Jnet (fo=39427, routed)XhB`?N ngFEC/fabric_clk_div2_reg/C JFDREXhzrQ J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr=j &"ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN Jnet (fo=39427, routed)Xhh?c 40ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXhrӥu 2.ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXhFA8 J arrival timeXhb, JXh1 JslackXh$w@ clk_o_40_08_phase_mon_mmcm_1clk_o_40_08_phase_mon_mmcm_1!)(@18@9A(@I8@hq}Nk@ clk_o_39_997_phase_mon_mmcm_2clk_o_39_997_phase_mon_mmcm_2!)ޖ(@1ޖ8@9Aޖ(@Iޖ8@hq}ZA; clkfbout_phase_mon_mmcm_2clkfbout_phase_mon_mmcm_2!),rB@1,rR@9A,rB@I,rR@hq} _A< clkfbout_phase_mon_mmcm_1clkfbout_phase_mon_mmcm_1!)ֳt8@1ֳtH@9Aֳt8@IֳtH@hq}'SCB= fabric_clk_PSOUTfabric_clk_PSOUT!)ֳt(@1ֳt8@9Aֳt(@Iֳt8@e5Ahq} M> @5AA rise - rise rise - rise  $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsu*bB>}/Hv??M>k(=a=k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xha=v GCngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< B>ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?v GCngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhk( EAngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXhQ8=, JXh9 J required timeXh/8 J arrival timeXhh?, JXh1 JslackXhM> $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsu>}/Hv??*R>k(=:j>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh:j>v GCngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< B>ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?v GCngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhk( EAngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXhQ8=, JXh9 J required timeXh/8 J arrival timeXh u?, JXh1 JslackXh*R> $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsu>}SJHv??UY>k(=:j>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh:j>v GCngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< B>ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?v GCngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhk( EAngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXh=, JXh9 J required timeXhSJ8 J arrival timeXh u?, JXh1 JslackXhUY> $ ngFEC/fabric_clk_PS_toggle_reg/CHDngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsu>>}V_e<Hv??ؘ>h|׽=zI>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= B>ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)XhzI>w HDngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< C?ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?w HDngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhh|׽ FBngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXh #=, JXh9 J required timeXhV8 J arrival timeXhҼ?, JXh1 JslackXhؘ> $ ngFEC/fabric_clk_PS_toggle_reg/C$ ngFEC/fabric_clk_PS_toggle_reg/D*:BJZ(LUT1=1)j=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsu>}􏆿Hv??n>k(>WQ>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzf=_ ngFEC/fabric_clk_PS_toggle Jnet (fo=13, routed)XhWQ>P %!ngFEC/fabric_clk_PS_toggle_i_1/I0 JXhzfi $ ngFEC/fabric_clk_PS_toggle_i_1/OProp_lut1_I0_O JLUT1XhzrA`<f &"ngFEC/fabric_clk_PS_toggle_i_1_n_0 Jnet (fo=1, routed)XhS $ ngFEC/fabric_clk_PS_toggle_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr; Jclock pessimismXhk(c "ngFEC/fabric_clk_PS_toggle_reg Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh􏆿8 J arrival timeXhU?, JXh1 JslackXhn> $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsuC>}SJHv??w>k(=Y>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)XhY>v GCngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< B>ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?v GCngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhk( EAngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXh=, JXh9 J required timeXhSJ8 J arrival timeXh4?, JXh1 JslackXhw> $ ngFEC/fabric_clk_PS_toggle_reg/CHDngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsuC>}~Hv?? >k(=Y>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= B>ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)XhY>w HDngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< C?ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?w HDngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhk( FBngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXh<, JXh9 J required timeXh~8 J arrival timeXh4?, JXh1 JslackXh > $ ngFEC/fabric_clk_PS_toggle_reg/CHDngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsuJ>}Hv??>k(=>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= B>ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh>w HDngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< C?ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?w HDngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhk( FBngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXhL7=, JXh9 J required timeXh8 J arrival timeXh??, JXh1 JslackXh> $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsu7>}뉿g<Hv??)>^z=̔>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh̔>v GCngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< B>ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xhm?v GCngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXh^z EAngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXh=, JXh9 J required timeXh8 J arrival timeXh亯?, JXh1 JslackXh)> $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj=fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000nsuy>}Ӂ_e<Hv??>h|׽=>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fastfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT(DCD - SCD - CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh>v GCngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh$?I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr<X ngFEC/fabric_clk_PS Jnet (fo=13, routed)XhkT?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh?F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr< B>ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh?v GCngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhh|׽ EAngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg Hold_fdre_C_D JFDREXht=, JXh9 J required timeXhӁ8 J arrival timeXhK?, JXh1 JslackXh> $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsu?}AgATxi:?T?A>А={>5AD>>4yU?k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> A=ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh4yU?v GCngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= B>ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)XhK?v GCngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhD>= Jclock uncertaintyXh EAngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXhY9, JXh9 J required timeXhgA8 J arrival timeXh71, JXh1 JslackXh5A $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsuO{?}AmATxi:?T?A>А={>AD>>9?k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> A=ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh9?v GCngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= B>ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)XhK?v GCngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhD>= Jclock uncertaintyXh EAngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXh㥛, JXh9 J required timeXhmA8 J arrival timeXhnq*, JXh1 JslackXhA $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsu_?}AmATxi:?T?A>А={>AD>>?k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> A=ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh?v GCngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= B>ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)XhK?v GCngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhD>= Jclock uncertaintyXh EAngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXh㥛, JXh9 J required timeXhmA8 J arrival timeXh_a#, JXh1 JslackXhA $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsuAY?}AA9̼:?9?A>А={>}A:n^>>?k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> A=ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh?v GCngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= B>ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh'1?v GCngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXh:n^>= Jclock uncertaintyXh EAngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXhT, JXh9 J required timeXhA8 J arrival timeXh!, JXh1 JslackXh}A $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsu@?}A-UATxi:?T?A>А={>ܿAD>>#>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> A=ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh#>v GCngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= B>ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)XhK?v GCngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhD>= Jclock uncertaintyXh EAngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXh, JXh9 J required timeXh-UA8 J arrival timeXhn, JXh1 JslackXhܿA $ ngFEC/fabric_clk_PS_toggle_reg/CHDngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsu="C?}A>A9:?9?A>А={>Ax>>j?k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> B>ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xhj?w HDngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= C?ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh'1?w HDngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhx>= Jclock uncertaintyXh FBngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXh<, JXh9 J required timeXh>A8 J arrival timeXhf, JXh1 JslackXhA $ ngFEC/fabric_clk_PS_toggle_reg/CHDngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsu'?}AA9:?9?A>А={>;Ax>>:>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> B>ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh:>w HDngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= C?ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh'1?w HDngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhx>= Jclock uncertaintyXh FBngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXhT, JXh9 J required timeXhA8 J arrival timeXh,, JXh1 JslackXh;A $ ngFEC/fabric_clk_PS_toggle_reg/CHDngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsutx?}AA9̼:?9?A>А={>^VA:n^>>CU>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> B>ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)XhCU>w HDngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= C?ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh'1?w HDngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXh:n^>= Jclock uncertaintyXh FBngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXhr, JXh9 J required timeXhA8 J arrival timeXh{, JXh1 JslackXh^VA $ ngFEC/fabric_clk_PS_toggle_reg/CGCngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D*:BJZj>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsu'?}AA9:?9?A>А={>^Ax>>:>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzr> A=ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in Jnet (fo=13, routed)Xh:>v GCngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr Q J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr= B>ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk Jnet (fo=13, routed)Xh'1?v GCngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C JFDREXhzr; Jclock pessimismXhx>= Jclock uncertaintyXh EAngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_regSetup_fdre_C_D JFDREXhz;, JXh9 J required timeXhA8 J arrival timeXh,, JXh1 JslackXh^A D$ ngFEC/fabric_clk_PS_toggle_reg/C$ ngFEC/fabric_clk_PS_toggle_reg/D*:BJZ(LUT1=1)j>fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000nsu,?}AA9:?9?A>А={>׶Ax>>D>k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})k(rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slowfabric_clk_PSOUTfabric_clk_PSOUTfabric_clk_PSOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)h $ ngFEC/fabric_clk_PS_toggle_reg/Q Prop_fdre_C_Q JFDREXhzf>_ ngFEC/fabric_clk_PS_toggle Jnet (fo=13, routed)XhD>P %!ngFEC/fabric_clk_PS_toggle_i_1/I0 JXhzfi $ ngFEC/fabric_clk_PS_toggle_i_1/OProp_lut1_I0_O JLUT1Xhzr 0=f &"ngFEC/fabric_clk_PS_toggle_i_1_n_0 Jnet (fo=1, routed)XhS $ ngFEC/fabric_clk_PS_toggle_reg/D JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)Xh"@I ngFEC/fabric_clk_PS_bufg/I JXhzrb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzrv=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzrQ J"(clock fabric_clk_PSOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh~ #ngFEC/fabric_clk_MMCME2/CLKOUT0Prop_mmcme2_adv_CLKIN1_CLKOUT0 J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_PSOUT Jnet (fo=1, routed)XhM@F ngFEC/fabric_clk_PS_bufg/I JXhb ngFEC/fabric_clk_PS_bufg/O Prop_bufg_I_O JBUFGXhzr=X ngFEC/fabric_clk_PS Jnet (fo=13, routed)Xh'1?S $ ngFEC/fabric_clk_PS_toggle_reg/C JFDREXhzr; Jclock pessimismXhx>= Jclock uncertaintyXhd "ngFEC/fabric_clk_PS_toggle_regSetup_fdre_C_D JFDREXh+=, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh׶A  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!)!~@1!~ @9A!~@I!~ @hq}@* ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!)!~@1!~ @9A!~@I!~ @hq}@  - ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!)!~@1!~ @9A!~@I!~ @hq}@  0 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!)!~@1!~ @9A!~@I!~ @hq}@4 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK!)!~@1!~ @9A!~@I!~ @hq}@7 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK!)!~@1!~ @9A!~@I!~ @hq}@) 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JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhrh? plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXh lhsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXhP鿐8 J arrival timeXhg?, JXh1 JslackXh 0>misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKkgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj-osc125_a rise@0.000ns - osc125_a rise@0.000nsu>}`p꿍ԨY?Ԩ@ 0>>d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Fastosc125_aosc125_aosc125_a(DCD - SCD - CPR) misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh kgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhף0? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhi? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXh iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh`p꿐8 J arrival timeXh=:@, JXh1 JslackXh 0> plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLKoksys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D*:BJZj-osc125_a rise@0.000ns - osc125_a rise@0.000nsuO>}O꿍FFA?F@ -2>O>d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Fastosc125_aosc125_aosc125_a(DCD - SCD - CPR) plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzrO> plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32_n_1 Jnet (fo=1, routed)Xh oksys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xh/? plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhrh? qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr; Jclock pessimismXh misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31Hold_srlc32e_CLK_D JSRLC32EXha=, JXh9 J required timeXhO꿐8 J arrival timeXhJ@, JXh1 JslackXh -2>misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLKkgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D*:BJZj-osc125_a rise@0.000ns - osc125_a rise@0.000nsuO>}꿍ԨY?Ԩ@ -2>O>d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Fastosc125_aosc125_aosc125_a(DCD - SCD - CPR) misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzrO> misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh kgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhף0? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhi? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr; Jclock pessimismXh iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31Hold_srlc32e_CLK_D JSRLC32EXha=, JXh9 J required timeXh꿐8 J arrival timeXh)@, JXh1 JslackXh -2>plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLKnjsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D*:BJZj-osc125_a rise@0.000ns - osc125_a rise@0.000nsuO>}yI鿍FFA?F@,^:>O>d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Fastosc125_aosc125_aosc125_a(DCD - SCD - CPR) plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzrO> plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh njsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xh/? plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhrh? plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXh lhsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXhyI鿐8 J arrival timeXhJ@, JXh1 JslackXh,^:>qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKiesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj-osc125_a rise@0.000ns - osc125_a rise@0.000nsu>}d迍FFA?F@a;>>d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Fastosc125_aosc125_aosc125_a(DCD - SCD - CPR) oksys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr> qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xh/? qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhrh? iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXh gcsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhd运8 J arrival timeXhx@, JXh1 JslackXha;>misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKeasys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj-osc125_a rise@0.000ns - osc125_a rise@0.000nsu>})迍ԨY?Ԩ@l;>>d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Fastosc125_aosc125_aosc125_a(DCD - SCD - CPR) kgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr> misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh easys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhף0? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr< ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhi? easys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXh c_sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh)运8 J arrival timeXh[@, JXh1 JslackXhl;>;misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKeasys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj-osc125_a rise@8.000ns - osc125_a rise@0.000nsu?}AM@UA&Ʉ@&Ʉ@A=А=@.3??d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Slowosc125_aosc125_aosc125_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) kgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh easys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xh? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xh? easys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXh.3?= Jclock uncertaintyXh c_sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhM@UA8 J arrival timeXh, JXh1 JslackXh@[qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKiesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj-osc125_a rise@8.000ns - osc125_a rise@0.000nsu?}ApUA8L@@A=А=@В??d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Slowosc125_aosc125_aosc125_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) oksys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhˡ? qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)XhX9? iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXhВ?= Jclock uncertaintyXh gcsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhpUA8 J arrival timeXh9L, JXh1 JslackXh@plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLKnjsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D*:BJZj-osc125_a rise@8.000ns - osc125_a rise@0.000nsu 5>?}A SA&Ʉ@&Ʉ@A=А={c@.3??5>?d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Slowosc125_aosc125_aosc125_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr?5>? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh kgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xh? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xh? misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr; Jclock pessimismXh.3?= Jclock uncertaintyXh iesys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31Setup_srlc32e_CLK_D JSRLC32EXhX9, JXh9 J required timeXh SA8 J arrival timeXh\, JXh1 JslackXh{c@plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLKoksys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D*:BJZj-osc125_a rise@8.000ns - osc125_a rise@0.000nsu>5>?}A.SA8L@@A=А=}c@В??5>?d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns})Slowosc125_aosc125_aosc125_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr?5>? plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32_n_1 Jnet (fo=1, routed)Xh oksys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D JSRLC32EXhzr I J(clock osc125_a rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)Xhˡ? plsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr I J(clock osc125_a rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr= ]Ysys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg Jnet (fo=11, routed)XhX9? qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr; Jclock pessimismXhВ?= Jclock uncertaintyXh misys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31Setup_srlc32e_CLK_D JSRLC32EXhX9, JXh9 J required timeXh.SA8 J arrival timeXh, JXh1 JslackXh}c@jmisys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKkgsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj-osc125_a rise@8.000ns - osc125_a rise@0.000nsu(}鿍17bp2=z?17@ݎ= 5^=.c->b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})f(rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)q -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[7]/Q Prop_fdre_C_Q JFDREXhzr5^=s 3/sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/addrb[7] Jnet (fo=5, routed)Xh.c-> sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRBWRADDR[11] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<p -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 Jnet (fo=4650, routed)Xhc?\ -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[7]/C JFDREXhzrJ J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<r /+sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/clkb Jnet (fo=4650, routed)Xh]5X? sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK JRAMB36E1Xhzr; Jclock pessimismXh  sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram'Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[11] JRAMB36E1Xh+>, JXh9 J required timeXh鿐8 J arrival timeXh?, JXh1 JslackXhݎ=}2.sys/ipb/udp_if/status_buffer/history_reg[80]/C2.sys/ipb/udp_if/status_buffer/history_reg[88]/D*:BJZ(LUT5=1)j/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>}&O+>9?O@fk=۹o>G>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)v 2.sys/ipb/udp_if/status_buffer/history_reg[80]/Q Prop_fdre_C_Q JFDREXhzr=l ,(sys/ipb/udp_if/status_buffer/history[80] Jnet (fo=2, routed)XhG>^ 3/sys/ipb/udp_if/status_buffer/history[88]_i_1/I4 JXhzrw 2.sys/ipb/udp_if/status_buffer/history[88]_i_1/OProp_lut5_I4_O JLUT5XhzrA`<t 40sys/ipb/udp_if/status_buffer/history[88]_i_1_n_0 Jnet (fo=1, routed)Xha 2.sys/ipb/udp_if/status_buffer/history_reg[88]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhP?a 2.sys/ipb/udp_if/status_buffer/history_reg[80]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhMb?a 2.sys/ipb/udp_if/status_buffer/history_reg[88]/C JFDREXhzr; Jclock pessimismXh۹q 0,sys/ipb/udp_if/status_buffer/history_reg[88] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh&8 J arrival timeXh@, JXh1 JslackXhfk=I/+sys/ipb/udp_if/payload/addr_int_reg[8]__0/C95sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/ADDRARDADDR[8]*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsuD>}p K_>z? @=۹=>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})f(rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)s /+sys/ipb/udp_if/payload/addr_int_reg[8]__0/Q Prop_fdre_C_Q JFDREXhzr=p 0,sys/ipb/udp_if/ipbus_rx_ram/rx_full_addra[6] Jnet (fo=8, routed)Xh>l 95sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/ADDRARDADDR[8] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<q .*sys/ipb/udp_if/payload/int_valid_int_reg_0 Jnet (fo=4650, routed)Xhb?^ /+sys/ipb/udp_if/payload/addr_int_reg[8]__0/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_0 Jnet (fo=4650, routed)Xh8/W?g 40sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXh۹ *&sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0&Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8] JRAMB36E1XhZd;>, JXh9 J required timeXhp8 J arrival timeXhE@, JXh1 JslackXh=g95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1/Crnsys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61/D*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsuƗx>}ǫ鿍C c<\?C @h=  =]1>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRL16E clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)} 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1/Q Prop_fdre_C_Q JFDREXhzr={ ;7sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1_n_0 Jnet (fo=1, routed)Xh]1> rnsys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61/D JSRL16EXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xh?h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)XhEV? tpsys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61/CLK JSRL16EXhzr; Jclock pessimismXh   plsys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61Hold_srl16e_CLK_D JSRL16EXh.>, JXh9 J required timeXhǫ鿐8 J arrival timeXhT?, JXh1 JslackXhh=$ sys/uc_if/uc_trans/addr_reg[8]/Csys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRARDADDR[12]*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu?};Xh4Jt>?Xh@ x=۹=B>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})f(rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)h $ sys/uc_if/uc_trans/addr_reg[8]/Q Prop_fdre_C_Q JFDREXhzr=f &"sys/uc_if/uc_trans/ram_in/addra[8] Jnet (fo=4, routed)XhB> sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRARDADDR[12] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<g $ sys/uc_if/uc_trans/addr_reg[9]_0 Jnet (fo=4650, routed)Xhj?S $ sys/uc_if/uc_trans/addr_reg[8]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<e "sys/uc_if/uc_trans/ram_in/clka Jnet (fo=4650, routed)XhX? sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXh۹ sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram'Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12] JRAMB36E1XhZd;>, JXh9 J required timeXh;8 J arrival timeXh@, JXh1 JslackXh x='-)sys/ipb/udp_if/status/shift_buf_reg[50]/C-)sys/ipb/udp_if/status/shift_buf_reg[58]/D*:BJZ(LUT6=1)j/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu2>}QR zJ>?R @֧=۹o>t>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)q -)sys/ipb/udp_if/status/shift_buf_reg[50]/Q Prop_fdre_C_Q JFDREXhzr=g '#sys/ipb/udp_if/status/shift_buf[50] Jnet (fo=2, routed)Xht>Y .*sys/ipb/udp_if/status/shift_buf[58]_i_1/I2 JXhzrr -)sys/ipb/udp_if/status/shift_buf[58]_i_1/OProp_lut6_I2_O JLUT6XhzrA`<d $ sys/ipb/udp_if/status/p_1_in[58] Jnet (fo=1, routed)Xh\ -)sys/ipb/udp_if/status/shift_buf_reg[58]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<l )%sys/ipb/udp_if/status/status_we_reg_0 Jnet (fo=4650, routed)Xh?\ -)sys/ipb/udp_if/status/shift_buf_reg[50]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<l )%sys/ipb/udp_if/status/status_we_reg_0 Jnet (fo=4650, routed)XhףP?\ -)sys/ipb/udp_if/status/shift_buf_reg[58]/C JFDREXhzr; Jclock pessimismXh۹l +'sys/ipb/udp_if/status/shift_buf_reg[58] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhQ8 J arrival timeXh?, JXh1 JslackXh֧=sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/C{sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu+>}`e<Ђ?@V= =>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell SRL16E clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR) sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/Q Prop_fdre_C_Q JFDREXhzr= jfsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/Q[7] Jnet (fo=9, routed)Xh> {sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D JSRL16EXhzrJ J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr< HDsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/userclk2 Jnet (fo=4650, routed)Xh 0? sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/C JFDREXhzrJ J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr< njsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/userclk2 Jnet (fo=4650, routed)Xhxi? }sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/CLK JSRL16EXhzr; Jclock pessimismXh  }ysys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5Hold_srl16e_CLK_D JSRL16EXh.>, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXhV= ^-)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[4]/Csys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8]*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu,>}鿍17bp2=z?17@= 5^==8>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})f(rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)q -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[4]/Q Prop_fdre_C_Q JFDREXhzr5^=s 3/sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/addrb[4] Jnet (fo=5, routed)Xh=8> sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<p -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 Jnet (fo=4650, routed)Xhc?\ -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[4]/C JFDREXhzrJ J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<r /+sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/clkb Jnet (fo=4650, routed)Xh]5X? sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK JRAMB36E1Xhzr; Jclock pessimismXh  sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram&Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[8] JRAMB36E1Xhz>, JXh9 J required timeXh鿐8 J arrival timeXh5?, JXh1 JslackXh=d84sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2/Cqmsys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30/D*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsubG>}_⿍~ wD<*?~ @ī=  =K=b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell SRLC32E clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)| 84sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2/Q Prop_fdre_C_Q JFDREXhzr=z :6sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2_n_0 Jnet (fo=1, routed)XhK= qmsys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30/D JSRLC32EXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xhp?g 84sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)XhU? sosys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30/CLK JSRLC32EXhzr; Jclock pessimismXh   oksys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh_⿐8 J arrival timeXhK?, JXh1 JslackXhī=}2.sys/ipb/udp_if/status_buffer/history_reg[37]/C2.sys/ipb/udp_if/status_buffer/history_reg[45]/D*:BJZ(LUT5=1)j/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>}t(1>9?@fή=۹o>>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk125_ub clk125_ub(DCD - SCD - CPR)v 2.sys/ipb/udp_if/status_buffer/history_reg[37]/Q Prop_fdre_C_Q JFDREXhzr=l ,(sys/ipb/udp_if/status_buffer/history[37] Jnet (fo=2, routed)Xh>^ 3/sys/ipb/udp_if/status_buffer/history[45]_i_1/I4 JXhzrw 2.sys/ipb/udp_if/status_buffer/history[45]_i_1/OProp_lut5_I4_O JLUT5XhzrA`<t 40sys/ipb/udp_if/status_buffer/history[45]_i_1_n_0 Jnet (fo=1, routed)Xha 2.sys/ipb/udp_if/status_buffer/history_reg[45]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhP?a 2.sys/ipb/udp_if/status_buffer/history_reg[37]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)Xhb?a 2.sys/ipb/udp_if/status_buffer/history_reg[45]/C JFDREXhzr; Jclock pessimismXh۹q 0,sys/ipb/udp_if/status_buffer/history_reg[45] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXht8 J arrival timeXh-@, JXh1 JslackXhfή=sys/clocks/rst_125_reg/C40sys/ipb/udp_if/status_buffer/ipbus_in_reg[106]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu;g@}ALAA94a@@A9=А=h=@?'1>*@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh1@c 40sys/ipb/udp_if/status_buffer/ipbus_in_reg[106]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)Xh-?c 40sys/ipb/udp_if/status_buffer/ipbus_in_reg[106]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh9t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[106]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhLA8 J arrival timeXh', JXh1 JslackXh@ sys/clocks/rst_125_reg/C40sys/ipb/udp_if/status_buffer/ipbus_in_reg[122]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu;g@}ALAA94a@@A9=А=h=@?'1>*@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh1@c 40sys/ipb/udp_if/status_buffer/ipbus_in_reg[122]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)Xh-?c 40sys/ipb/udp_if/status_buffer/ipbus_in_reg[122]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh9t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[122]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhLA8 J arrival timeXh', JXh1 JslackXh@ sys/clocks/rst_125_reg/C3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[74]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu;g@}ALAA94a@@A9=А=h=@?'1>*@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh1@b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[74]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)Xh-?b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[74]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh9s 1-sys/ipb/udp_if/status_buffer/ipbus_in_reg[74]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhLA8 J arrival timeXh', JXh1 JslackXh@ sys/clocks/rst_125_reg/C3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[90]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu;g@}ALAA94a@@A9=А=h=@?'1>*@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh1@b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[90]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)Xh-?b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[90]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh9s 1-sys/ipb/udp_if/status_buffer/ipbus_in_reg[90]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhLA8 J arrival timeXh', JXh1 JslackXh@ sys/clocks/rst_125_reg/C3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[98]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu;g@}ALAA94a@@A9=А=h=@?'1>*@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh1@b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[98]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)Xh-?b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[98]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh9s 1-sys/ipb/udp_if/status_buffer/ipbus_in_reg[98]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhLA8 J arrival timeXh', JXh1 JslackXh@ sys/clocks/rst_125_reg/C3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[36]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu֢@}AJAura@u@A9=А=h=@S?'1> S@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh@b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[36]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhĠ?b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[36]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9s 1-sys/ipb/udp_if/status_buffer/ipbus_in_reg[36]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhJA8 J arrival timeXh?#, JXh1 JslackXh@ sys/clocks/rst_125_reg/C2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[4]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu֢@}AJAura@u@A9=А=h=@S?'1> S@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh@a 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[4]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhĠ?a 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[4]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9r 0,sys/ipb/udp_if/status_buffer/ipbus_in_reg[4]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhJA8 J arrival timeXh?#, JXh1 JslackXh@ sys/clocks/rst_125_reg/C3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[68]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu֢@}AJAura@u@A9=А=h=@S?'1> S@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh@b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[68]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhĠ?b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[68]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9s 1-sys/ipb/udp_if/status_buffer/ipbus_in_reg[68]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhJA8 J arrival timeXh?#, JXh1 JslackXh@ sys/clocks/rst_125_reg/C3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[92]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsu֢@}AJAura@u@A9=А=h=@S?'1> S@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xh@b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[92]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhĠ?b 3/sys/ipb/udp_if/status_buffer/ipbus_in_reg[92]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9s 1-sys/ipb/udp_if/status_buffer/ipbus_in_reg[92]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhJA8 J arrival timeXh?#, JXh1 JslackXh@ sys/clocks/rst_125_reg/C40sys/ipb/udp_if/status_buffer/ipbus_in_reg[116]/R*:BJZ(LUT2=1)j/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuĢ@}AJAura@u@A9=А=h=@S?'1>A@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzrZd>n +'sys/ipb/udp_if/rx_transactor/rst_125mhz Jnet (fo=1307, routed)Xh# /@` 51sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/I1 JXhzry 40sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/OProp_lut2_I1_O JLUT2Xhzr 0=t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 Jnet (fo=128, routed)Xhw@c 40sys/ipb/udp_if/status_buffer/ipbus_in_reg[116]/R JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/status_buffer/history_reg[127]_0 Jnet (fo=4650, routed)XhĠ?c 40sys/ipb/udp_if/status_buffer/ipbus_in_reg[116]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9t 2.sys/ipb/udp_if/status_buffer/ipbus_in_reg[116]Setup_fdre_C_R JFDREXh㥛, JXh9 J required timeXhJA8 J arrival timeXh#, JXh1 JslackXh@  clk62_5_ub clk62_5_ub!)@1/@9A@I/@eKsWAhq}L>.3@x::9 rise - rise rise - rise  fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D*:BJZ(LUT4=1)j1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsu{Y>}ӭ俍`?`@L>R>, k=d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/Q Prop_fdre_C_Q JFDREXhzr5^= `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3 Jnet (fo=2, routed)Xh, k= a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/I3 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/OProp_lut4_I3_O JLUT4Xhzro= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1_n_0 Jnet (fo=1, routed)Xh `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh.? fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhg? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C JFDREXhzr; Jclock pessimismXh ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg Hold_fdre_C_D JFDREXh$y=, JXh9 J required timeXhӭ俐8 J arrival timeXh\?, JXh1 JslackXhL>FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync1/CFBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/D*:BJZj1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsu*>}ܿrY?r@O>5^=c=d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync1/Q Prop_fdpe_C_Q JFDPEXhzr5^= HDsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg1 Jnet (fo=1, routed)Xhc=u FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/D JFDPEXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< @?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/Chdsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXCHARDISPMODE[0]*:BJZj1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsu5>}<=>?<@M >C =>d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})m(rising edge-triggered cell GTXE2_CHANNEL clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) ?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/data_sync_reg1[0] Jnet (fo=1, routed)Xh> hdsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXCHARDISPMODE[0] J GTXE2_CHANNELXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh`0?n ?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< VRsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/userclk Jnet (fo=118, routed)Xh? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhC  VRsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i.Hold_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0] J GTXE2_CHANNELXhw=, JXh9 J required timeXh8 J arrival timeXh0 @, JXh1 JslackXhM >=qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg6/Cd`sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/D*:BJZj1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsup>}mr忍94<[?@'> =~- >d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg6/Q Prop_fdre_C_Q JFDREXhzr= ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s2 Jnet (fo=1, routed)Xh~- > d`sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/D JFDREXhzrK J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< hdsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/userclk Jnet (fo=118, routed)Xh-? qmsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg6/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhf? d`sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C JFDREXhzr; Jclock pessimismXh  b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhmr忐8 J arrival timeXhdn?, JXh1 JslackXh'>FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync4/CFBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/D*:BJZj1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsu~{>}q㿍rY?r@]K>=%>d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync4/Q Prop_fdpe_C_Q JFDPEXhzr= HDsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg4 Jnet (fo=1, routed)Xh%>u FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/D JFDPEXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< @FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/CFBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D*:BJZj1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsu4j>}࿍r`e<Y?r@P>C 5^=n >d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/Q Prop_fdpe_C_Q JFDPEXhzr5^= HDsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg5 Jnet (fo=1, routed)Xhn >u FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D JFDPEXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< @`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/C`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/D*:BJZ(LUT4=1)j1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsu$>}q㿍^?@P>Vo>5 >d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/Q Prop_fdre_C_Q JFDREXhzr= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg_n_0 Jnet (fo=2, routed)Xh5 > d`sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_i_1__0/I0 JXhzr c_sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_i_1__0/OProp_lut4_I0_O JLUT4XhzrA`< easys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_i_1__0_n_0 Jnet (fo=1, routed)Xh `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/userclk Jnet (fo=118, routed)XhO-? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/userclk Jnet (fo=118, routed)XhUe? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/C JFDREXhzr; Jclock pessimismXhV ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhq㿐8 J arrival timeXha?, JXh1 JslackXhP>FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/CFBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync3/D*:BJZj1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsu9>}$f㿍rY?r@dS>= >d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/Q Prop_fdpe_C_Q JFDPEXhzr= HDsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg2 Jnet (fo=1, routed)Xh >u FBsys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync3/D JFDPEXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< @`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/D*:BJZ (CARRY4=1)j1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsuM>}鿍FGA?F@f\>ˡE>0=d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzr= ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh0= gcsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/S[2] JXhzr gcsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/O[2]Prop_carry4_S[2]_O[2] JCARRY4Xhzr= fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_5 Jnet (fo=1, routed)Xh `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh/? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhrh? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr; Jclock pessimismXh ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Hold_fdre_C_D JFDREXhj=, JXh9 J required timeXh鿐8 J arrival timeXhbJ@, JXh1 JslackXhf\>`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/D*:BJZ (CARRY4=1)j1clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000nsuu>}*迍$6 ?$6@\>ˡE>(=d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk62_5_ub clk62_5_ub(DCD - SCD - CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/Q Prop_fdre_C_Q JFDREXhzr= ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6] Jnet (fo=2, routed)Xh(= gcsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/S[2] JXhzr gcsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/O[2]Prop_carry4_S[2]_O[2] JCARRY4Xhzr= fbsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_5 Jnet (fo=1, routed)Xh `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh)\/? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr< MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh(1h? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C JFDREXhzr; Jclock pessimismXh ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6] Hold_fdre_C_D JFDREXhj=, JXh9 J required timeXh*运8 J arrival timeXh>@, JXh1 JslackXh\>`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsu@}ANfA8L@@A5=А= =KsWAВ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)Xha> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)XhX9? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C JFDREXhzr; Jclock pessimismXhВ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhNfA8 J arrival timeXh, JXh1 JslackXhKsWA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsu@}ANfA8L@@A5=А= =KsWAВ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)Xha> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)XhX9? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1]/C JFDREXhzr; Jclock pessimismXhВ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhNfA8 J arrival timeXh, JXh1 JslackXhKsWA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsu@}ANfA8L@@A5=А= =KsWAВ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)Xha> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)XhX9? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr; Jclock pessimismXhВ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhNfA8 J arrival timeXh, JXh1 JslackXhKsWA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsu@}ANfA8L@@A5=А= =KsWAВ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)Xha> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)XhX9? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3]/C JFDREXhzr; Jclock pessimismXhВ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhNfA8 J arrival timeXh, JXh1 JslackXhKsWA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsun @}A'5AϏļ8L@Ϗ@A5=А= =\XA7ߏ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)XhM> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/C JFDREXhzr; Jclock pessimismXh7ߏ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh'5A8 J arrival timeXho, JXh1 JslackXh\XA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsun @}A'5AϏļ8L@Ϗ@A5=А= =\XA7ߏ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)XhM> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/C JFDREXhzr; Jclock pessimismXh7ߏ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh'5A8 J arrival timeXho, JXh1 JslackXh\XA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsun @}A'5AϏļ8L@Ϗ@A5=А= =\XA7ߏ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)XhM> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C JFDREXhzr; Jclock pessimismXh7ߏ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh'5A8 J arrival timeXho, JXh1 JslackXh\XA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Ca]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsun @}A'5AϏļ8L@Ϗ@A5=А= =\XA7ߏ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)XhM> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C JFDREXhzr; Jclock pessimismXh7ߏ?= Jclock uncertaintyXh5 ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh'5A8 J arrival timeXho, JXh1 JslackXh\XA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Cb^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsuS@}A1Al`Լ8L@l@A5=А= = YA7ߏ?>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)XhJ> b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh ׳? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/C JFDREXhzr; Jclock pessimismXh7ߏ?= Jclock uncertaintyXh5 _[sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh1A8 J arrival timeXh&v, JXh1 JslackXh YA`\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Cb^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE*:BJZ(LUT2=1 LUT4=1 LUT6=1)j2clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000nsu-@}A3A ̼8L@@A5=А= =YA7ߏ?>J?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk62_5_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q Prop_fdre_C_Q JFDREXhzf> ^Zsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] Jnet (fo=2, routed)Xh> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/I0 JXhzf `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/OProp_lut4_I0_O JLUT4Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 Jnet (fo=1, routed)Xh-> a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I1 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut6_I1_O JLUT6Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh=? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=17, routed)Xh> b^sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xhˡ? `\sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr= MIsys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk Jnet (fo=118, routed)Xh? a]sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C JFDREXhzr; Jclock pessimismXh7ߏ?= Jclock uncertaintyXh5 _[sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh3A8 J arrival timeXhc, JXh1 JslackXhYA  clk_ipb_ub clk_ipb_ub!)/@1?@9A/@I?@e:/Ahq} ,4Q= ZuA;; rise - rise rise - rise  a]ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/server_din_o_reg[27]/C{wngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[11]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu ?}_gK=Rw@@,4Q=E6>7>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) a]ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/server_din_o_reg[27]/Q Prop_fdre_C_Q JFDREXhzrE6> ]YngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/DIADI[11] Jnet (fo=2, routed)Xh7> {wngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[11] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= ZVngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xh? a]ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/server_din_o_reg[27]/C JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= c_ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/clk_31_250_bufg Jnet (fo=82108, routed)Xh? {wngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXh qmngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl!Hold_ramb36e1_CLKARDCLK_DIADI[11] JRAMB36E1Xhy?, JXh9 J required timeXh_g8 J arrival timeXh @, JXh1 JslackXh,4Q=Ja]ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[28]/CokngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[28]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsul ?}{1F=@1@QMQ=ZR>a>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) a]ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[28]/Q Prop_fdre_C_Q JFDREXhzrR> QMngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/DIADI[28] Jnet (fo=2, routed)Xha> okngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[28] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= ZVngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xh? a]ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[28]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= WSngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/clk_31_250_bufg Jnet (fo=82108, routed)XhE? okngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXhZ eangFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl!Hold_ramb36e1_CLKARDCLK_DIADI[28] JRAMB36E1Xhy?, JXh9 J required timeXh{8 J arrival timeXht@, JXh1 JslackXhQMQ=$QMngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[4]/CnjngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[4]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu('?}<q=9L@q@R=팿R>>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) QMngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[4]/Q Prop_fdre_C_Q JFDREXhzrR> jfngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl_6[4] Jnet (fo=2, routed)Xh> njngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[4] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= NJngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)Xh> ? QMngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[4]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= WSngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/clk_31_250_bufg Jnet (fo=82108, routed)Xh? okngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK JRAMB36E1Xhzr; Jclock pessimismXh팿 eangFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl Hold_ramb36e1_CLKBWRCLK_DIBDI[4] JRAMB36E1Xhy?, JXh9 J required timeXh<8 J arrival timeXhP1@, JXh1 JslackXhR=b^ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[6]/C|xngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[6]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu!?} Hf[=@H@S=E6>~>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) b^ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[6]/Q Prop_fdre_C_Q JFDREXhzrE6> ^ZngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/DIADI[6] Jnet (fo=2, routed)Xh~> |xngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[6] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= \XngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xh? b^ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[6]/C JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= eangFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg Jnet (fo=82108, routed)Xh ? }yngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXh songFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl Hold_ramb36e1_CLKARDCLK_DIADI[6] JRAMB36E1Xhy?, JXh9 J required timeXh 8 J arrival timeXh**@, JXh1 JslackXhS=sRNngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[14]/C{wngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[14]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu7(?}!U=@U@S=/E6>ZL>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) RNngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[14]/Q Prop_fdre_C_Q JFDREXhzrE6> wsngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_1[14] Jnet (fo=2, routed)XhZL> {wngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[14] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= NJngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)Xh/? RNngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[14]/C JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= c_ngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg Jnet (fo=82108, routed)XhP>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) RNngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[24]/Q Prop_fdre_C_Q JFDREXhzrR> kgngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl_6[16] Jnet (fo=2, routed)XhP> okngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[24] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= NJngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)Xh? RNngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[24]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= WSngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/clk_31_250_bufg Jnet (fo=82108, routed)Xh? okngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK JRAMB36E1Xhzr; Jclock pessimismXh eangFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl!Hold_ramb36e1_CLKBWRCLK_DIBDI[24] JRAMB36E1Xhy?, JXh9 J required timeXhP:8 J arrival timeXh@, JXh1 JslackXhS=b^ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[25]/C{wngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[9]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu.!?}%aNW=@a@MS=E6>>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) b^ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[25]/Q Prop_fdre_C_Q JFDREXhzrE6> ]YngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/DIADI[9] Jnet (fo=2, routed)Xh> {wngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[9] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= [WngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xhʡ? b^ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[25]/C JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= d`ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/clk_31_250_bufg Jnet (fo=82108, routed)Xhl? |xngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXh rnngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl Hold_ramb36e1_CLKARDCLK_DIADI[9] JRAMB36E1Xhy?, JXh9 J required timeXh%8 J arrival timeXh.@, JXh1 JslackXhMS=lQMngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/ngccm_din_reg[8]/CzvngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[8]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu(?}ٞ=R|@@} T=&R>>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) QMngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/ngccm_din_reg[8]/Q Prop_fdre_C_Q JFDREXhzrR> vrngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_0[8] Jnet (fo=2, routed)Xh> zvngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[8] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= NJngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)Xh~? QMngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/ngccm_din_reg[8]/C JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= c_ngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg Jnet (fo=82108, routed)Xh+? {wngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK JRAMB36E1Xhzr; Jclock pessimismXh& qmngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl Hold_ramb36e1_CLKBWRCLK_DIBDI[8] JRAMB36E1Xhy?, JXh9 J required timeXh8 J arrival timeXhA*@, JXh1 JslackXh} T=rRNngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[31]/C{wngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[15]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsue'?}ǟ862=@86@@]V=/E6>>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) RNngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[31]/Q Prop_fdre_C_Q JFDREXhzrE6> vrngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_4[7] Jnet (fo=2, routed)Xh> {wngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[15] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= NJngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)Xh? RNngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[31]/C JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= c_ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/clk_31_250_bufg Jnet (fo=82108, routed)XhI? {wngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK JRAMB36E1Xhzr; Jclock pessimismXh/ qmngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl!Hold_ramb36e1_CLKBWRCLK_DIBDI[15] JRAMB36E1Xhy?, JXh9 J required timeXhǟ8 J arrival timeXh\t@, JXh1 JslackXh@]V=lQMngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[6]/CzvngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[6]*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu?}s=Wiu@s@7V=|j7A>b>e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) QMngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[6]/Q Prop_fdre_C_Q JFDREXhzr7A> vrngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_1[6] Jnet (fo=2, routed)Xhb> zvngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[6] JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= NJngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)Xh? QMngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[6]/C JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv= c_ngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg Jnet (fo=82108, routed)Xh?? {wngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK JRAMB36E1Xhzr; Jclock pessimismXh|j qmngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl Hold_ramb36e1_CLKBWRCLK_DIBDI[6] JRAMB36E1Xh2>, JXh9 J required timeXh8 J arrival timeXh"Ǎ@, JXh1 JslackXh7V=sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLKa]ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D*:BJZ(LUT5=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu`vA}BVBx]R>å@x@B3=А==:/AS?sh?_Ai(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23]!Prop_ramb36e1_CLKBWRCLK_DOBDO[23] JRAMB36E1Xhzrgf?a !sys/ipb/trans/iface/doutb[23] Jnet (fo=3, routed)Xh:?Q &"sys/ipb/trans/iface/hlen[7]_i_1/I0 JXhzrj %!sys/ipb/trans/iface/hlen[7]_i_1/OProp_lut5_I0_O JLUT5Xhzr 0=` sys/ipb/trans/sm/rx_data[23] Jnet (fo=8, routed)Xh?V +'sys/ipb/trans/sm/w_data_ipbus[7]_i_1/I4 JXhzro *&sys/ipb/trans/sm/w_data_ipbus[7]_i_1/OProp_lut5_I4_O JLUT5Xhzr 0= eangFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[23] Jnet (fo=594, routed)Xh@A a]ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=f "sys/uc_if/uc_trans/ram_in/clkb Jnet (fo=82108, routed)Xh ? sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= ZVngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xh:? a]ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh3 _[ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23]Setup_fdre_C_D JFDREXht<, JXh9 J required timeXhVB8 J arrival timeXhA, JXh1 JslackXh:/A}sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLKTPngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23]/D*:BJZ(LUT4=1 LUT5=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsuN1A}BWhBcS>å@@B3=А==\6AS?y?–Ai(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23]!Prop_ramb36e1_CLKBWRCLK_DOBDO[23] JRAMB36E1Xhzrgf?a !sys/ipb/trans/iface/doutb[23] Jnet (fo=3, routed)Xh:?Q &"sys/ipb/trans/iface/hlen[7]_i_1/I0 JXhzrj %!sys/ipb/trans/iface/hlen[7]_i_1/OProp_lut5_I0_O JLUT5Xhzr 0=` sys/ipb/trans/sm/rx_data[23] Jnet (fo=8, routed)Xh?V +'sys/ipb/trans/sm/w_data_ipbus[7]_i_1/I4 JXhzro *&sys/ipb/trans/sm/w_data_ipbus[7]_i_1/OProp_lut5_I4_O JLUT5Xhzr 0=c !sys/rmw_result_reg[31]_11[23] Jnet (fo=594, routed)XhRAi >:sys/bram_array[9].skip_SFP_SEC.input_size[9][23]_i_1__3/I3 JXhzr =9sys/bram_array[9].skip_SFP_SEC.input_size[9][23]_i_1__3/OProp_lut4_I3_O JLUT4Xhzr 0= XTngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][31]_0[23] Jnet (fo=1, routed)Xh TPngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23]/D JFDCEXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=f "sys/uc_if/uc_trans/ram_in/clkb Jnet (fo=82108, routed)Xh ? sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[5].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? TPngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh3 RNngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23]Setup_fdce_C_D JFDCEXhC =, JXh9 J required timeXhWhB8 J arrival timeXh0, JXh1 JslackXh\6A*40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLKTPngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21]/D*:BJZ(LUT3=1 LUT5=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsuOA}B BٌW>Y@ٌ@B3=А== 6AS?y?"Ai(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  3/sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/DOBDO[1] Prop_ramb36e1_CLKBWRCLK_DOBDO[1] JRAMB36E1Xhzrgf?o /+sys/ipb/trans/iface/trans_in_udp[rdata][21] Jnet (fo=3, routed)Xh?Q &"sys/ipb/trans/iface/hlen[5]_i_1/I2 JXhzrj %!sys/ipb/trans/iface/hlen[5]_i_1/OProp_lut5_I2_O JLUT5Xhzr 0=` sys/ipb/trans/sm/rx_data[21] Jnet (fo=8, routed)Xh@>V +'sys/ipb/trans/sm/w_data_ipbus[5]_i_1/I4 JXhzro *&sys/ipb/trans/sm/w_data_ipbus[5]_i_1/OProp_lut5_I4_O JLUT5Xhzr 0=c !sys/rmw_result_reg[31]_11[21] Jnet (fo=593, routed)XhZAi >:sys/bram_array[3].skip_SFP_SEC.input_size[3][21]_i_1__6/I2 JXhzr =9sys/bram_array[3].skip_SFP_SEC.input_size[3][21]_i_1__6/OProp_lut3_I2_O JLUT3Xhzr 0= XTngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][31]_0[21] Jnet (fo=1, routed)Xh TPngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21]/D JFDCEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=p ,(sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_1 Jnet (fo=82108, routed)Xh յ?g 40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh|?? TPngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh3 RNngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21]Setup_fdce_C_D JFDCEXho=, JXh9 J required timeXh B8 J arrival timeXh, JXh1 JslackXh 6Asys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLKb^ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D*:BJZ(LUT5=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsuA}BuB/u=j>å@/u@B3=А==j;AS?sh?0Ai(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23]!Prop_ramb36e1_CLKBWRCLK_DOBDO[23] JRAMB36E1Xhzrgf?a !sys/ipb/trans/iface/doutb[23] Jnet (fo=3, routed)Xh:?Q &"sys/ipb/trans/iface/hlen[7]_i_1/I0 JXhzrj %!sys/ipb/trans/iface/hlen[7]_i_1/OProp_lut5_I0_O JLUT5Xhzr 0=` sys/ipb/trans/sm/rx_data[23] Jnet (fo=8, routed)Xh?V +'sys/ipb/trans/sm/w_data_ipbus[7]_i_1/I4 JXhzro *&sys/ipb/trans/sm/w_data_ipbus[7]_i_1/OProp_lut5_I4_O JLUT5Xhzr 0= fbngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[23] Jnet (fo=594, routed)Xh"A b^ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D JFDREXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=f "sys/uc_if/uc_trans/ram_in/clkb Jnet (fo=82108, routed)Xh ? sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= [WngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xh? b^ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh3 `\ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]Setup_fdre_C_D JFDREXhT, JXh9 J required timeXhuB8 J arrival timeXh, JXh1 JslackXhj;A;40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLKa]ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21]/D*:BJZ(LUT5=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsui£A}B¤BqՎW>Y@qՎ@B3=А==aV +'sys/ipb/trans/sm/w_data_ipbus[5]_i_1/I4 JXhzro *&sys/ipb/trans/sm/w_data_ipbus[5]_i_1/OProp_lut5_I4_O JLUT5Xhzr 0= eangFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[21] Jnet (fo=593, routed)XhA a]ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=p ,(sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_1 Jnet (fo=82108, routed)Xh յ?g 40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= ZVngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xh/? a]ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh3 _[ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21]Setup_fdre_C_D JFDREXh #, JXh9 J required timeXh¤B8 J arrival timeXh, JXh1 JslackXhag %!sys/ipb_from_master[ipb_addr][19] Jnet (fo=746, routed)Xh[iA[ 0,sys/FSM_sequential_server_ack[1]_i_3__119/I1 JXhzrt /+sys/FSM_sequential_server_ack[1]_i_3__119/OProp_lut5_I1_O JLUT5Xhzr 0= @?Z /+sys/FSM_sequential_server_ack[1]_i_8__25/I3 JXhzrs .*sys/FSM_sequential_server_ack[1]_i_8__25/OProp_lut5_I3_O JLUT5Xhzf 0=p 0,sys/FSM_sequential_server_ack[1]_i_8__25_n_0 Jnet (fo=1, routed)XhW>Z /+sys/FSM_sequential_server_ack[1]_i_7__35/I0 JXhzfs .*sys/FSM_sequential_server_ack[1]_i_7__35/OProp_lut4_I0_O JLUT4Xhzf 0=p 0,sys/FSM_sequential_server_ack[1]_i_7__35_n_0 Jnet (fo=2, routed)Xh[>U *&sys/ram_miso[ipb_rdata][31]_i_6__21/I3 JXhzfn )%sys/ram_miso[ipb_rdata][31]_i_6__21/OProp_lut6_I3_O JLUT6Xhzf 0=X sys/addr_reg[13]_21 Jnet (fo=36, routed)Xh[ǵ?U *&sys/ram_miso[ipb_rdata][31]_i_7__21/I3 JXhzfn )%sys/ram_miso[ipb_rdata][31]_i_7__21/OProp_lut4_I3_O JLUT4Xhzr 0= fbngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso_reg[ipb_rdata][31]_5 Jnet (fo=30, routed)Xh$? kgngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_2__35/I5 JXhzr jfngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_2__35/OProp_lut6_I5_O JLUT6Xhzr 0= lhngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_2__35_n_0 Jnet (fo=1, routed)Xh=> kgngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_1__35/I0 JXhzr jfngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_1__35/OProp_lut5_I0_O JLUT5Xhzr 0= mingFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][31]_2[10] Jnet (fo=1, routed)Xh iengFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][10]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=\ sys/ipb/trans/sm/out Jnet (fo=82108, routed)Xhn?R #sys/ipb/trans/sm/addr_reg[19]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= [WngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xhl? iengFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][10]/C JFDREXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 gcngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][10]Setup_fdre_C_D JFDREXhC =, JXh9 J required timeXh7B8 J arrival timeXh, JXh1 JslackXh"=A;40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLKa]ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22]/D*:BJZ(LUT5=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu?Y@+@B3=А===AS?sh?%Ai(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3/sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/DOBDO[2] Prop_ramb36e1_CLKBWRCLK_DOBDO[2] JRAMB36E1Xhzrgf?o /+sys/ipb/trans/iface/trans_in_udp[rdata][22] Jnet (fo=3, routed)XhR?Q &"sys/ipb/trans/iface/hlen[6]_i_1/I2 JXhzrj %!sys/ipb/trans/iface/hlen[6]_i_1/OProp_lut5_I2_O JLUT5Xhzr 0=` sys/ipb/trans/sm/rx_data[22] Jnet (fo=8, routed)XhA@?V +'sys/ipb/trans/sm/w_data_ipbus[6]_i_1/I4 JXhzro *&sys/ipb/trans/sm/w_data_ipbus[6]_i_1/OProp_lut5_I4_O JLUT5Xhzr 0= eangFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[22] Jnet (fo=593, routed)XhA a]ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=p ,(sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_1 Jnet (fo=82108, routed)Xh յ?g 40sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= ZVngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)XhV? a]ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22]/C JFDREXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh3 _[ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22]Setup_fdre_C_D JFDREXh #, JXh9 J required timeXhB8 J arrival timeXh, JXh1 JslackXh=A#sys/ipb/trans/sm/addr_reg[19]/ChdngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4]/D*:BJZ(LUT4=2 LUT5=3 LUT6=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu{A}B=Bl}C33l@l}@B3=А===Aoh?(\?/Ae(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ipb/trans/sm/addr_reg[19]/Q Prop_fdre_C_Q JFDREXhzr>g %!sys/ipb_from_master[ipb_addr][19] Jnet (fo=746, routed)Xh[iA[ 0,sys/FSM_sequential_server_ack[1]_i_3__119/I1 JXhzrt /+sys/FSM_sequential_server_ack[1]_i_3__119/OProp_lut5_I1_O JLUT5Xhzr 0= @?Z /+sys/FSM_sequential_server_ack[1]_i_8__25/I3 JXhzrs .*sys/FSM_sequential_server_ack[1]_i_8__25/OProp_lut5_I3_O JLUT5Xhzf 0=p 0,sys/FSM_sequential_server_ack[1]_i_8__25_n_0 Jnet (fo=1, routed)XhW>Z /+sys/FSM_sequential_server_ack[1]_i_7__35/I0 JXhzfs .*sys/FSM_sequential_server_ack[1]_i_7__35/OProp_lut4_I0_O JLUT4Xhzf 0=p 0,sys/FSM_sequential_server_ack[1]_i_7__35_n_0 Jnet (fo=2, routed)Xh[>U *&sys/ram_miso[ipb_rdata][31]_i_6__21/I3 JXhzfn )%sys/ram_miso[ipb_rdata][31]_i_6__21/OProp_lut6_I3_O JLUT6Xhzf 0=X sys/addr_reg[13]_21 Jnet (fo=36, routed)Xh[ǵ?U *&sys/ram_miso[ipb_rdata][31]_i_7__21/I3 JXhzfn )%sys/ram_miso[ipb_rdata][31]_i_7__21/OProp_lut4_I3_O JLUT4Xhzr 0= fbngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso_reg[ipb_rdata][31]_5 Jnet (fo=30, routed)Xh? jfngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_2__35/I5 JXhzr iengFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_2__35/OProp_lut6_I5_O JLUT6Xhzr 0= kgngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_2__35_n_0 Jnet (fo=1, routed)Xhsğ> jfngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_1__35/I0 JXhzr iengFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_1__35/OProp_lut5_I0_O JLUT5Xhzr 0= lhngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][31]_2[4] Jnet (fo=1, routed)Xh hdngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=\ sys/ipb/trans/sm/out Jnet (fo=82108, routed)Xhn?R #sys/ipb/trans/sm/addr_reg[19]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr= [WngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)Xh0? hdngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4]/C JFDREXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 fbngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4]Setup_fdre_C_D JFDREXhC =, JXh9 J required timeXh=B8 J arrival timeXh, JXh1 JslackXh=Asys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLKUQngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23]/D*:BJZ(LUT2=1 LUT5=2)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsuɢA}BBjT]>å@jT@B3=А==>AS?y?ZAi(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)  sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23]!Prop_ramb36e1_CLKBWRCLK_DOBDO[23] JRAMB36E1Xhzrgf?a !sys/ipb/trans/iface/doutb[23] Jnet (fo=3, routed)Xh:?Q &"sys/ipb/trans/iface/hlen[7]_i_1/I0 JXhzrj %!sys/ipb/trans/iface/hlen[7]_i_1/OProp_lut5_I0_O JLUT5Xhzr 0=` sys/ipb/trans/sm/rx_data[23] Jnet (fo=8, routed)Xh?V +'sys/ipb/trans/sm/w_data_ipbus[7]_i_1/I4 JXhzro *&sys/ipb/trans/sm/w_data_ipbus[7]_i_1/OProp_lut5_I4_O JLUT5Xhzr 0=c !sys/rmw_result_reg[31]_11[23] Jnet (fo=594, routed)Xh]Aj ?;sys/bram_array[8].skip_SFP_SEC.control_reg[8][23]_i_1__3/I0 JXhzr >:sys/bram_array[8].skip_SFP_SEC.control_reg[8][23]_i_1__3/OProp_lut2_I0_O JLUT2Xhzr 0= YUngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][31]_0[23] Jnet (fo=1, routed)Xh UQngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23]/D JFDCEXhzrK J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=f "sys/uc_if/uc_trans/ram_in/clkb Jnet (fo=82108, routed)Xh ? sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK JRAMB36E1Xhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[5].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh+? UQngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh3 SOngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23]Setup_fdce_C_D JFDCEXhC =, JXh9 J required timeXhB8 J arrival timeXhn:, JXh1 JslackXh>A rxWordclkl12_1rxWordclkl12_1!)]_ff@1]_ff @9A]_ff@I]_ff @e_Lk@hq}=O]@== rise - rise rise - rise  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D*:BJZ(LUT3=1)j9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsuC>}Aྍj}94<z>j>=tho>J=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)XhJ= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1/I0 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhz> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhj> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr; Jclock pessimismXhth ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhAྐ8 J arrival timeXh7?, JXh1 JslackXh= @}⾍|_94<֣>|>4=no>{=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR) @ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh֣>o @ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh|>p A=ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C JFDREXhzr; Jclock pessimismXhn ?;ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh⾐8 J arrival timeXh% ?, JXh1 JslackXh4= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu >}۾x >x ?=S=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xhx ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhS ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh۾8 J arrival timeXhq ?, JXh1 JslackXh= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu >} ܾp= >p= ?=v=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xhp= ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh ܾ8 J arrival timeXh ?, JXh1 JslackXh= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D*:BJZ(LUT3=1)j9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsuU>}ྍpA94<>p>]=no>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1/I0 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhp> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhྐ8 J arrival timeXh ?, JXh1 JslackXh]= )%ngFEC/SFP_GEN[2].rx_data_reg[2][51]/C51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50]/D*:BJZ(LUT3=1)j9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu,W>}Aྍl_94<z>l>v=Obo>~=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)m )%ngFEC/SFP_GEN[2].rx_data_reg[2][51]/Q Prop_fdre_C_Q JFDREXhzr=u 51ngFEC/gbtbank1_l12_118/RX_Word_rx40_reg[78]_1[35] Jnet (fo=1, routed)Xh~=` 51ngFEC/gbtbank1_l12_118/RX_Word_rx40[50]_i_1__8/I0 JXhzry 40ngFEC/gbtbank1_l12_118/RX_Word_rx40[50]_i_1__8/OProp_lut3_I0_O JLUT3XhzrA`<y 95ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] Jnet (fo=1, routed)Xhd 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr\ ngFEC/RX_WORDCLK_O[1] Jnet (fo=1057, routed)Xhz>X )%ngFEC/SFP_GEN[2].rx_data_reg[2][51]/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhl>d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50]/C JFDCEXhzr; Jclock pessimismXhObt 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhAྐ8 J arrival timeXh ?, JXh1 JslackXhv=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D*:BJZ(LUT3=1)j9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu]>},ݾ5^_94<>5^>N=no>,޳=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh,޳= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1/I0 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh5^> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh,ݾ8 J arrival timeXh ?, JXh1 JslackXhN=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D*:BJZ(LUT3=1)j9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu]>}ξ 뾭A94<> >N=tho>,޳=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh,޳= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/I0 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh > ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr; Jclock pessimismXhth ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhξ8 J arrival timeXhe?, JXh1 JslackXhN= @ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsuıB>}J ¾C쾭A94<.>C>=n==g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR) @ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.>o @q B>ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/C JFDREXhzr; Jclock pessimismXhn @, JXh1 JslackXh=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D*:BJZ(LUT3=1)j9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsuCQ`>}ྍpA94<>p>Q=no>}=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_15_in Jnet (fo=2, routed)Xh}= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1/I0 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[8] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhp> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhྐ8 J arrival timeXh`?, JXh1 JslackXhQ=ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuy@}33AjN A#>k?#?33A=А=_Lk@/?Q\@@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] Jnet (fo=13, routed)Xhbi @g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2/I4 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2/OProp_lut5_I4_O JLUT5Xhzr 0=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2_n_0 Jnet (fo=6, routed)XhP ?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[25]_i_1/I3 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[25]_i_1/OProp_lut4_I3_O JLUT4Xhzr`P= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[21] Jnet (fo=1, routed)Xhߌ> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh#? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25]Setup_fdce_C_D JFDCEXhƽ, JXh9 J required timeXhjN A8 J arrival timeXh, JXh1 JslackXh_Lk@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu@}33AM A%Ѝk?%?33A=А=ol@ ?X6@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] Jnet (fo=13, routed)XhJP?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/I0 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/OProp_lut5_I0_O JLUT5Xhzr/]=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2_n_0 Jnet (fo=6, routed)Xh ?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[29]_i_1/I1 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[29]_i_1/OProp_lut4_I1_O JLUT4XhzrP> hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[25] Jnet (fo=1, routed)Xh[> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXhM A8 J arrival timeXhc, JXh1 JslackXhol@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuw@}33AiN AB`% k?B`%?33A=А=P9m@ ?7@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] Jnet (fo=13, routed)XhJP?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/I0 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/OProp_lut5_I0_O JLUT5Xhzr/]=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2_n_0 Jnet (fo=6, routed)XhV?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_1/I1 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_1/OProp_lut4_I1_O JLUT4XhzrP> hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[89] Jnet (fo=1, routed)Xh"@> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhB`%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]Setup_fdce_C_D JFDCEXhԽ, JXh9 J required timeXhiN A8 J arrival timeXh+, JXh1 JslackXhP9m@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu@}33A) Ao#ck?o#?33A=А=o@-?:@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] Jnet (fo=13, routed)Xhbi @g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2/I4 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2/OProp_lut5_I4_O JLUT5Xhzr 0=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2_n_0 Jnet (fo=6, routed)Xhm ?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_1/I3 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_1/OProp_lut4_I3_O JLUT4XhzrGa= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[85] Jnet (fo=1, routed)XhE> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xho#? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89]Setup_fdce_C_D JFDCEXhԽ, JXh9 J required timeXh) A8 J arrival timeXh6f, JXh1 JslackXho@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72]/D*:BJZ(LUT3=1 LUT6=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu4@}33A Ao#ck?o#?33A=А=p@^?=?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[0] Jnet (fo=13, routed)Xhb6@g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4/I0 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4/OProp_lut3_I0_O JLUT3XhzrGa=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4_n_0 Jnet (fo=5, routed)XhlWm?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[72]_i_1/I5 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[72]_i_1/OProp_lut6_I5_O JLUT6XhzrI > hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[68] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xho#? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72]Setup_fdce_C_D JFDCEXho=, JXh9 J required timeXh A8 J arrival timeXhk, JXh1 JslackXhp@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuVB@}33AjN Ao#ck?o#?33A=А=q@/?"9@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[14]'Prop_gtxe2_channel_RXUSRCLK2_RXDATA[14] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[16] Jnet (fo=8, routed)Xh@g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_2/I0 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_2/OProp_lut5_I0_O JLUT5Xhzr 0=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_2_n_0 Jnet (fo=6, routed)Xh\,?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_1/I3 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_1/OProp_lut4_I3_O JLUT4Xhzr`P= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[84] Jnet (fo=1, routed)Xhwa> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xho#? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88]Setup_fdce_C_D JFDCEXh[½, JXh9 J required timeXhjN A8 J arrival timeXh , JXh1 JslackXhq@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu@}33AC A%΍k?%?33A=А=q@?2@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh;A?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_2/I0 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_2/OProp_lut5_I0_O JLUT5Xhzr`P=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_2_n_0 Jnet (fo=6, routed)Xhl!?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[60]_i_1/I1 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[60]_i_1/OProp_lut4_I1_O JLUT4Xhzrt> hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[56] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]Setup_fdce_C_D JFDCEXh뽐, JXh9 J required timeXhC A8 J arrival timeXh?N, JXh1 JslackXhq@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu@}33AZ A$k?$?33A=А=2`r@5^?2@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] Jnet (fo=13, routed)XhJP?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/I0 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/OProp_lut5_I0_O JLUT5Xhzr/]=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2_n_0 Jnet (fo=6, routed)Xh ?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[61]_i_1/I1 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[61]_i_1/OProp_lut4_I1_O JLUT4Xhzrn> hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[57] Jnet (fo=1, routed)Xhѡ> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh$? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]Setup_fdce_C_D JFDCEXh9Ƚ, JXh9 J required timeXhZ A8 J arrival timeXhP, JXh1 JslackXh2`r@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuR{@}33A A"u)k?"?33A=А=t@D?5@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[2]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[2] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[2] Jnet (fo=13, routed)XhJ?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2/I4 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2/OProp_lut5_I4_O JLUT5Xhzr 0=} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2_n_0 Jnet (fo=6, routed)Xhj3?g <8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[26]_i_1/I3 JXhzr ;7ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[26]_i_1/OProp_lut4_I3_O JLUT4Xhzrj<= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[22] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh"? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXh A8 J arrival timeXh]w, JXh1 JslackXht@ 73ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15]/CB>ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5]/CE*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuEJ@}33A A8!t<?8!?33A=А=w@'1>dw@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_1rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzrZd>w 51ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh?q FBngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__5/I0 JXhzr EAngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__5/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__5_n_0 Jnet (fo=128, routed)Xh#@q B>ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5]/CE JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?f 73ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh8!?p A=ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh ?;ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXhw@ rxWordclkl12_2rxWordclkl12_2!)]_ff@1]_ff @9A]_ff@I]_ff @e/(@hq}=O]@>> rise - rise rise - rise   ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C)%ngFEC/SFP_GEN[3].rx_data_reg[3][43]/D*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu=>}l羍x A94<>x ?=t=Z_=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=a !ngFEC/GBT_rx_data[2]_1357[43] Jnet (fo=1, routed)XhZ_=X )%ngFEC/SFP_GEN[3].rx_data_reg[3][43]/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr\ ngFEC/RX_WORDCLK_O[2] Jnet (fo=1057, routed)Xhx ?X )%ngFEC/SFP_GEN[3].rx_data_reg[3][43]/C JFDREXhzr; Jclock pessimismXhth '#ngFEC/SFP_GEN[3].rx_data_reg[3][43] Hold_fdre_C_D JFDREXhq=, JXh9 J required timeXhl羐8 J arrival timeXhZ ?, JXh1 JslackXh= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu >} ܾp= >p= ?=v=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xhp= ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh ܾ8 J arrival timeXh ?, JXh1 JslackXh=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D*:BJZ(LUT3=1)j9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsuU>}K~ _94<>~ ?]=zo>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__0/I0 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__0/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh~ ? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr; Jclock pessimismXhz ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhK8 J arrival timeXh?, JXh1 JslackXh]= @ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/D*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsuy@>}aؾ_94< ->?=n=%~=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) @ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh ->o @ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/C JFDREXhzr; Jclock pessimismXhn @}r辍^ _94<>^ ?V=to>{=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh{= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__0/I2 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__0/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh^ ? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr; Jclock pessimismXht ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhr辐8 J arrival timeXh?, JXh1 JslackXhV= 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[18]/CLHngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsub]>}j t=> ?6===g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)y 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[18]/Q Prop_fdce_C_Q JFDCEXhzr=r 2.ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/Q[2] Jnet (fo=5, routed)Xh={ LHngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>d 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh ?{ LHngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C JFDREXhzr; Jclock pessimismXh JFngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2] Hold_fdre_C_D JFDREXhq=, JXh9 J required timeXhj8 J arrival timeXhd?, JXh1 JslackXh6=T c_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/Cc_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7]/D*:BJZ(LUT6=1)j9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu_d>}X `e<ˡ> ?5=tho>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) c_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[7] Jnet (fo=1, routed)Xh= gcngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[7]_i_1__0/I5 JXhzr fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[7]_i_1__0/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[7] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7]/D JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhˡ> c_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh ? c_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7]/C JFDCEXhzr; Jclock pessimismXhth a]ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhX8 J arrival timeXh?, JXh1 JslackXh5=k )%ngFEC/SFP_GEN[3].rx_data_reg[3][20]/C51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20]/D*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsugI>}x龍 `e<> ?FN=rh=w=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)m )%ngFEC/SFP_GEN[3].rx_data_reg[3][20]/Q Prop_fdre_C_Q JFDREXhzr=y 95ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]_0[12] Jnet (fo=1, routed)Xhw=d 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20]/D JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr\ ngFEC/RX_WORDCLK_O[2] Jnet (fo=1057, routed)Xh>X )%ngFEC/SFP_GEN[3].rx_data_reg[3][20]/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh ?d 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr; Jclock pessimismXhrht 3/ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20] Hold_fdce_C_D JFDCEXhq=, JXh9 J required timeXhx龐8 J arrival timeXh3f?, JXh1 JslackXhFN= @ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/D*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu]V>}۾%-\=!>%?>==g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) @ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>o @ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/C JFDREXhzr; Jclock pessimismXh @ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu1>}ھ~ >~ ?>z=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh~ ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhz ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXhھ8 J arrival timeXhE?, JXh1 JslackXh> 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/CC?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][24]/CE*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsu@}33A A%E.?%?33A=А=/(@>@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xh@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][24]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh%?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][24]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @ٜ@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xhz@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][21]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhB`%?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][21]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @ٜ@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xhz@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhB`%?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @ٜ@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xhz@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][27]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhB`%?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][27]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @ٜ@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xhz@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][29]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhB`%?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][29]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @Z@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xh @r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][23]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][23]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @Z@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xh @r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][26]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][26]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @L@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xhtk@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXh @L@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xhtk@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][28]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][28]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXh @L@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_2rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh%"@q FBngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/I0 JXhzr EAngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 Jnet (fo=128, routed)Xhtk@r C?ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][30]/CE JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$?q B>ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][30]/C JFDREXhzr; Jclock pessimismXh<= Jclock uncertaintyXh @}w澍_94<i>?Ӯ=no>.>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh.>= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__1/I2 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__1/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhi> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhw澐8 J arrival timeXh ?, JXh1 JslackXhӮ= 95ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C>:ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsub>}WAD<!>A?G=*\="=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=| <8ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] Jnet (fo=2, routed)Xh"=o >:ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D JSRL16EXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?q @}bؾ+>+?==`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh+? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhbؾ8 J arrival timeXhC?, JXh1 JslackXh=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D*:BJZ(LUT3=1)j9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuU>}l羍J _94<}?>J ?]=no>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/I0 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh}?> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhJ ? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhl羐8 J arrival timeXh?, JXh1 JslackXh]=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D*:BJZ(LUT3=1)j9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsu]>}T徍8_94<F>8?N=to>,޳=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh,޳= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__1/I2 JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__1/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhF> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh8? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr; Jclock pessimismXht ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhT徐8 J arrival timeXh?, JXh1 JslackXhN= ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C)%ngFEC/SFP_GEN[4].rx_data_reg[4][67]/D*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuX[G>}ھu<X9>?[)=(\==g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q Prop_fdre_C_Q JFDREXhzr=a !ngFEC/GBT_rx_data[3]_1358[67] Jnet (fo=1, routed)Xh=X )%ngFEC/SFP_GEN[4].rx_data_reg[4][67]/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhX9> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr\ ngFEC/RX_WORDCLK_O[3] Jnet (fo=1057, routed)Xh?X )%ngFEC/SFP_GEN[4].rx_data_reg[4][67]/C JFDREXhzr; Jclock pessimismXh(\h '#ngFEC/SFP_GEN[4].rx_data_reg[4][67] Hold_fdre_C_D JFDREXhq=, JXh9 J required timeXhھ8 J arrival timeXh ?, JXh1 JslackXh[)=& EAngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CEAngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/D*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuk>}KA94<>?=n+>W=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) EAngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q Prop_fdce_C_Q JFDCEXhzr= wsngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0][3] Jnet (fo=127, routed)XhW= wsngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gbtBank_Clk_gen[3].rx_clken_sr[3][4]_i_1/I0 JXhzr vrngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gbtBank_Clk_gen[3].rx_clken_sr[3][4]_i_1/OProp_lut2_I0_O JLUT2Xhzro=h ($ngFEC/gbtbank1_l12_118/gbt_inst_n_58 Jnet (fo=1, routed)Xht EAngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzro ,(ngFEC/gbtbank1_l12_118/MGT_RXUSRCLK_o[3] Jnet (fo=1057, routed)Xh>t EAngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzro ,(ngFEC/gbtbank1_l12_118/MGT_RXUSRCLK_o[3] Jnet (fo=1057, routed)Xh?t EAngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C JFDCEXhzr; Jclock pessimismXhn C?ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] Hold_fdce_C_D JFDCEXh=, JXh9 J required timeXhK8 J arrival timeXh5?, JXh1 JslackXh= @ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuU>}ƾV +=Q>V>p'>=@=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) @ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhQ>o @q B>ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/C JFDREXhzr; Jclock pessimismXh @ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsu1>}+־$>?>/=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh$> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh/ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXh+־8 J arrival timeXh ?, JXh1 JslackXh> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C)%ngFEC/SFP_GEN[4].rx_data_reg[4][76]/D*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsu <>}Vξ8}94<X9>8?s>n=J=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q Prop_fdre_C_Q JFDREXhzr=a !ngFEC/GBT_rx_data[3]_1358[76] Jnet (fo=1, routed)XhJ=X )%ngFEC/SFP_GEN[4].rx_data_reg[4][76]/D JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhX9> ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr\ ngFEC/RX_WORDCLK_O[3] Jnet (fo=1057, routed)Xh8?X )%ngFEC/SFP_GEN[4].rx_data_reg[4][76]/C JFDREXhzr; Jclock pessimismXhnh '#ngFEC/SFP_GEN[4].rx_data_reg[4][76] Hold_fdre_C_D JFDREXh #=, JXh9 J required timeXhVξ8 J arrival timeXh ?, JXh1 JslackXhs>ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsu۽@}33A^ A%b{i\j?%?33A=А=`hg@Ԙ?7?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? LHngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[19] Jnet (fo=8, routed)Xh7@j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/I3 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/OProp_lut5_I3_O JLUT5Xhzrj<= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_2__1/OProp_lut4_I1_O JLUT4XhzrV> hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[91] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]Setup_fdce_C_D JFDCEXhʽ, JXh9 J required timeXh^ A8 J arrival timeXhh , JXh1 JslackXh`hg@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D*:BJZ(LUT4=2)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsu/@}33A^ Aˡ%=ui\j?ˡ%?33A=А= h@?O=@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[0])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[0] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[8] Jnet (fo=5, routed)XhB?j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1/I0 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1/OProp_lut4_I0_O JLUT4Xhzr/]= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[28]_i_1__1/OProp_lut4_I3_O JLUT4XhzrNb> hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[24] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhˡ%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]Setup_fdce_C_D JFDCEXhν, JXh9 J required timeXh^ A8 J arrival timeXhz, JXh1 JslackXh h@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsu@}33A1 AB`%Oi\j?B`%?33A=А=+Dj@p?`3A@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[3]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[3] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[3] Jnet (fo=13, routed)Xhڰ @j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1/I4 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1/OProp_lut5_I4_O JLUT5Xhzr 0= @j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[27]_i_2__1/I3 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[27]_i_2__1/OProp_lut4_I3_O JLUT4XhzrY= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[23] Jnet (fo=1, routed)XhS> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhB`%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]Setup_fdce_C_D JFDCEXhS㽐, JXh9 J required timeXh1 A8 J arrival timeXhfA, JXh1 JslackXh+Dj@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsu4@}33Af AB`%Oi\j?B`%?33A=А=Jk@i?7?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[11]'Prop_gtxe2_channel_RXUSRCLK2_RXDATA[11] J GTXE2_CHANNELXhzr&? LHngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[13] Jnet (fo=5, routed)XhTT?j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2__1/I3 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2__1/OProp_lut5_I3_O JLUT5Xhzr 0= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[57]_i_1__1/OProp_lut4_I3_O JLUT4Xhzr/]= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[53] Jnet (fo=1, routed)Xhe> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhB`%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXhf A8 J arrival timeXhK, JXh1 JslackXhJk@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsubx@}33A> AB`%Oi\j?B`%?33A=А=Apm@V?i>@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[12]'Prop_gtxe2_channel_RXUSRCLK2_RXDATA[12] J GTXE2_CHANNELXhzr&? LHngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[14] Jnet (fo=5, routed)Xhψ?j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2__1/I3 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2__1/OProp_lut5_I3_O JLUT5Xhzr 0= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[58]_i_1__1/OProp_lut4_I3_O JLUT4XhzrL= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[54] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhB`%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]Setup_fdce_C_D JFDCEXh/ݽ, JXh9 J required timeXh> A8 J arrival timeXhß, JXh1 JslackXhApm@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72]/D*:BJZ(LUT3=1 LUT6=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsut@}33A‡ A̡%;ui\j?̡%?33A=А=Ǟn@Q?1@@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[0] Jnet (fo=13, routed)XhV@j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4__1/I0 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4__1/OProp_lut3_I0_O JLUT3Xhzr@= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[72]_i_1__1/OProp_lut6_I5_O JLUT6XhzrL7 > hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[68] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh̡%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72]Setup_fdce_C_D JFDCEXhC =, JXh9 J required timeXh‡ A8 J arrival timeXh!, JXh1 JslackXhǞn@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuTŁ@}33A1 AB`%Oi\j?B`%?33A=А=4n@p?V<@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[3]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[3] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[3] Jnet (fo=13, routed)Xhڰ @j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1/I4 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1/OProp_lut5_I4_O JLUT5Xhzr 0= @j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[59]_i_2__1/I3 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[59]_i_2__1/OProp_lut4_I3_O JLUT4XhzrY= hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[55] Jnet (fo=1, routed)XhX'> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhB`%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]Setup_fdce_C_D JFDCEXhS㽐, JXh9 J required timeXh1 A8 J arrival timeXh, JXh1 JslackXh4n@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuȁ@}33A‡ Aˡ%=ui\j?ˡ%?33A=А=To@r?@X7@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? LHngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[19] Jnet (fo=8, routed)Xh7@j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/I3 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/OProp_lut5_I3_O JLUT5Xhzrj<= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[23]_i_2__1/OProp_lut4_I1_O JLUT4XhzrC > hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[19] Jnet (fo=1, routed)XhE> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhˡ%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23]Setup_fdce_C_D JFDCEXh3^, JXh9 J required timeXh‡ A8 J arrival timeXhZ, JXh1 JslackXhTo@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92]/D*:BJZ(LUT4=2)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsu~F@}33AR A%b{i\j?%?33A=А=%p@?=5@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[0])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[0] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[8] Jnet (fo=5, routed)XhB?j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1/I0 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1/OProp_lut4_I0_O JLUT4Xhzr/]= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_1__1/OProp_lut4_I3_O JLUT4Xhzrz> hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[88] Jnet (fo=1, routed)Xh2> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92]Setup_fdce_C_D JFDCEXhaн, JXh9 J required timeXhR A8 J arrival timeXh , JXh1 JslackXh%p@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsu@}33A AB`%Oi\j?B`%?33A=А=8q@r?5@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_3rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? LHngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[19] Jnet (fo=8, routed)Xh7@j ?;ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/I3 JXhzr >:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/OProp_lut5_I3_O JLUT5Xhzrj<= @:ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[63]_i_2__1/OProp_lut4_I1_O JLUT4XhzrC > hdngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[59] Jnet (fo=1, routed)XhE> d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63]/D JFDCEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhB`%? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63]Setup_fdce_C_D JFDCEXh3^, JXh9 J required timeXh A8 J arrival timeXh6., JXh1 JslackXh8q@ rxWordclkl12_4rxWordclkl12_4!)]_ff@1]_ff @9A]_ff@I]_ff @eDj@hq}O=O]@@@ rise - rise rise - rise  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D*:BJZ(LUT3=1)j9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsuıB>}ྍ~j_94<>~j>O=Kbo>O}~=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)XhO}~= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__2/I2 JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__2/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh~j> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr; Jclock pessimismXhKb ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhྐ8 J arrival timeXh8?, JXh1 JslackXhO=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D*:BJZ(LUT3=1)j9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsuC>}/侍A_94<!>A?=Obo>J=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhJ= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__2/I0 JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__2/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[3] Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh!> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhA? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr; Jclock pessimismXhOb ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh/侐8 J arrival timeXh F ?, JXh1 JslackXh=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D*:BJZ(LUT3=1)j9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsucD>}Z侍A94<->?=Mbo>1=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[2] Jnet (fo=2, routed)Xh1= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__2/I2 JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__2/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh-> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr; Jclock pessimismXhMb ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhZ侐8 J arrival timeXh`A ?, JXh1 JslackXh=_ d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[12]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12]/D*:BJZ(LUT6=1)j9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsuU>}ྍlA94<>l>]=*\o>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR) d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[12]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[12] Jnet (fo=1, routed)Xh= hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[12]_i_1__2/I5 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[12]_i_1__2/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[12] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[12]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhl> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12]/C JFDCEXhzr; Jclock pessimismXh*\ b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhྐ8 J arrival timeXh ?, JXh1 JslackXh]= )%ngFEC/SFP_GEN[1].rx_data_reg[1][64]/C51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64]/D*:BJZ(LUT3=1)j9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu,W>}Z侍A}94< ->A?v=tho>~=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)m )%ngFEC/SFP_GEN[1].rx_data_reg[1][64]/Q Prop_fdre_C_Q JFDREXhzr=s 3/ngFEC/gbtbank2_l12_117/RX_Word_rx40_reg[78][48] Jnet (fo=1, routed)Xh~=` 51ngFEC/gbtbank2_l12_117/RX_Word_rx40[64]_i_1__9/I2 JXhzry 40ngFEC/gbtbank2_l12_117/RX_Word_rx40[64]_i_1__9/OProp_lut3_I2_O JLUT3XhzrA`<y 95ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[40] Jnet (fo=1, routed)Xhd 51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest21_in Jnet (fo=1057, routed)Xh ->X )%ngFEC/SFP_GEN[1].rx_data_reg[1][64]/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr; Jclock pessimismXhtht 3/ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhZ侐8 J arrival timeXh?, JXh1 JslackXhv=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D*:BJZ(LUT3=1)j9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu]>}Z侍A94<->?N=Mbo>,޳=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh,޳= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__2/I0 JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__2/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh-> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr; Jclock pessimismXhMb ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhZ侐8 J arrival timeXhV?, JXh1 JslackXhN=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D*:BJZ(LUT3=1)j9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsujWa>}/侍A_94<!>A?=Obo>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__2/I0 JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__2/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh!> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhA? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr; Jclock pessimismXhOb ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh/侐8 J arrival timeXh?, JXh1 JslackXh= @ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[3][13]/D*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsumJ>}tӾpT<>p>l>Mb==g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR) @ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[3][13]/D JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>o @q B>ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[3][13]/C JFDREXhzr; Jclock pessimismXhMb @h )%ngFEC/SFP_GEN[1].rx_data_reg[1][23]/C51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23]/D*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsugI>}nҾ~jA94<>~j>>Mb=w=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)m )%ngFEC/SFP_GEN[1].rx_data_reg[1][23]/Q Prop_fdre_C_Q JFDREXhzr=y 95ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[15] Jnet (fo=1, routed)Xhw=d 51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest21_in Jnet (fo=1057, routed)Xh>X )%ngFEC/SFP_GEN[1].rx_data_reg[1][23]/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh~j>d 51ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr; Jclock pessimismXhMbt 3/ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23] Hold_fdce_C_D JFDCEXhq=, JXh9 J required timeXhnҾ8 J arrival timeXh ?, JXh1 JslackXh> 95ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C>:ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu*>}%+=F>%?>=%>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=| <8ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] Jnet (fo=2, routed)Xh%>o >:ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D JSRL16EXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhF>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh%?q @ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu⫃@}33A A]"΍DVi?]"?33A=А=Dj@Ԙ?D:@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2/I0 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2/OProp_lut5_I0_O JLUT5Xhzr@= @:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[60]_i_1__2/OProp_lut4_I1_O JLUT4XhzrO > hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[56] Jnet (fo=1, routed)Xh > d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh]"? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]Setup_fdce_C_D JFDCEXhl罐, JXh9 J required timeXh A8 J arrival timeXh֠, JXh1 JslackXhDj@ jiengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/CeangFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CE*:BJZ(CARRY4=1 LUT4=1 LUT5=2 LUT6=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu*x@}33AA]"ƽZd;?]"?33A=А=8y@·?C4@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrq> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xhw/? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/OProp_lut4_I1_O JLUT4XhzrI > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2_n_0 Jnet (fo=3, routed)Xh ? ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/OProp_lut6_I0_O JLUT6XhzrL7 > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/O[3]Prop_carry4_S[0]_O[3] JCARRY4Xhzf> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)Xh > hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_3__2/I3 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_3__2/OProp_lut5_I3_O JLUT5Xhzro> XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[67] Jnet (fo=6, routed)XhT> ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[63]_i_1__2/I2 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[63]_i_1__2/OProp_lut5_I2_O JLUT5Xhzrt> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_0[14] Jnet (fo=4, routed)Xh-%? eangFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CE JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)XhZd;? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh]"? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]Setup_fdce_C_CE JFDCEXhP, JXh9 J required timeXhA8 J arrival timeXh́, JXh1 JslackXh8y@jiengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/CeangFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63]/CE*:BJZ(CARRY4=1 LUT4=1 LUT5=2 LUT6=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu*x@}33AA]"ƽZd;?]"?33A=А=8y@·?C4@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrq> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xhw/? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/OProp_lut4_I1_O JLUT4XhzrI > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2_n_0 Jnet (fo=3, routed)Xh ? ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/OProp_lut6_I0_O JLUT6XhzrL7 > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/O[3]Prop_carry4_S[0]_O[3] JCARRY4Xhzf> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)Xh > hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_3__2/I3 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_3__2/OProp_lut5_I3_O JLUT5Xhzro> XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[67] Jnet (fo=6, routed)XhT> ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[63]_i_1__2/I2 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[63]_i_1__2/OProp_lut5_I2_O JLUT5Xhzrt> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_0[14] Jnet (fo=4, routed)Xh-%? eangFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63]/CE JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)XhZd;? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh]"? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63]Setup_fdce_C_CE JFDCEXhP, JXh9 J required timeXhA8 J arrival timeXh́, JXh1 JslackXh8y@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24]/D*:BJZ(LUT4=2)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsuSx@}33AѴ A.iDVi?.?33A=А=`{@q=?+@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[0])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[0] J GTXE2_CHANNELXhzr&?~ >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[8] Jnet (fo=5, routed)Xh&?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[96]_i_3__2/I1 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[96]_i_3__2/OProp_lut4_I1_O JLUT4Xhzr9H= @:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[24]_i_1__2/OProp_lut4_I1_O JLUT4Xhzr+> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[20] Jnet (fo=1, routed)Xh鑺> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh.? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24]Setup_fdce_C_D JFDCEXhi, JXh9 J required timeXhѴ A8 J arrival timeXhy, JXh1 JslackXh`{@iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68]/D*:BJZ(CARRY4=1 LUT3=1 LUT4=1 LUT6=3)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu#@}33A A"ĽZd;?"?33A=А=F@?sC@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrq> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xhw/? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/OProp_lut4_I1_O JLUT4XhzrI > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2_n_0 Jnet (fo=3, routed)Xh ? ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/OProp_lut6_I0_O JLUT6XhzrL7 > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/O[3]Prop_carry4_S[0]_O[3] JCARRY4Xhzf> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhY> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[67]_i_3__2/I1 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[67]_i_3__2/OProp_lut6_I1_O JLUT6Xhzr= kgngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_i_3__2_5 Jnet (fo=41, routed)Xh~z ? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_4__2/I0 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_4__2/OProp_lut3_I0_O JLUT3Xhzr@=y 95ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[68] Jnet (fo=4, routed)Xh%?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[68]_i_1__2/I0 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[68]_i_1__2/OProp_lut6_I0_O JLUT6XhzrL7 > hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[64] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)XhZd;? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh"? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68]Setup_fdce_C_D JFDCEXho=, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXhF@)ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D*:BJZ(LUT4=2)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsuq@}33A6 AM"DVi?M"?33A=А=I*@^?9$@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[0])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[0] J GTXE2_CHANNELXhzr&?~ >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[9] Jnet (fo=5, routed)XhC?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[93]_i_3__2/I0 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[93]_i_3__2/OProp_lut4_I0_O JLUT4XhzrT= @:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[93]_i_1__2/OProp_lut4_I3_O JLUT4Xhzr)\> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[89] Jnet (fo=1, routed)Xh.> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhM"? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]Setup_fdce_C_D JFDCEXh뽐, JXh9 J required timeXh6 A8 J arrival timeXh#, JXh1 JslackXhI*@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu$p@}33A AJ "󓎾DVi?J "?33A=А=r@?&#@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[18] Jnet (fo=8, routed)Xh?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_2__2/I3 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_2__2/OProp_lut5_I3_O JLUT5Xhzr/]= @:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[62]_i_1__2/OProp_lut4_I1_O JLUT4Xhzr)\> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[58] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhJ "? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXh A8 J arrival timeXhB=, JXh1 JslackXhr@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D*:BJZ(LUT4=2)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsuho@}33A AM"DVi?M"?33A=А=ǀ@_?"@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[12]'Prop_gtxe2_channel_RXUSRCLK2_RXDATA[12] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[14] Jnet (fo=5, routed)Xhf?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_3__2/I1 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_3__2/OProp_lut4_I1_O JLUT4XhzrY= @:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_1__2/OProp_lut4_I3_O JLUT4XhzrV> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[90] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhM"? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]Setup_fdce_C_D JFDCEXh$, JXh9 J required timeXh A8 J arrival timeXh$ߔ, JXh1 JslackXhǀ@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsup@}33A9F AJ "󓎾DVi?J "?33A=А=@X?S$@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2/I0 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2/OProp_lut5_I0_O JLUT5Xhzr@= @:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[28]_i_1__2/OProp_lut4_I1_O JLUT4Xhzrrh> hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[24] Jnet (fo=1, routed)Xh"5> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/D JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhJ "? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]Setup_fdce_C_D JFDCEXhv, JXh9 J required timeXh9F A8 J arrival timeXh, JXh1 JslackXh@ 73ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15]/CC?ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[0][10]/CE*:BJZ(LUT2=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsuu@}33A5AnS㽵.?n?33A=А=@>b@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_4rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh[?q FBngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__6/I0 JXhzr EAngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__6/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__6_n_0 Jnet (fo=128, routed)Xh@r C?ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[0][10]/CE JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh.?f 73ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhn?q B>ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[0][10]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @:ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsu]>}_94<i>?=n="=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=| <8ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] Jnet (fo=2, routed)Xh"=o >:ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D JSRL16EXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?q @}E A94<> ?)=zo>z=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR) _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/Q Prop_fdce_C_Q JFDCEXhzf= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt[2] Jnet (fo=6, routed)Xhz= a]ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_i_1__3/I4 JXhzf `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_i_1__3/OProp_lut6_I4_O JLUT6XhzrA`< \XngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)Xh ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/D JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh> _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh ? ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXhz [WngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhE8 J arrival timeXh6?, JXh1 JslackXh)= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsu >}۾x >x ?=S=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xh> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xhx ? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhS ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh۾8 J arrival timeXhq ?, JXh1 JslackXh=_ d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[16]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16]/D*:BJZ(LUT6=1)j9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsul>}C =o>?A=o>:=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR) d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[16]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[16] Jnet (fo=1, routed)Xh:= hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[16]_i_1__3/I5 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[16]_i_1__3/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[16] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16]/D JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xho> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[16]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh8 J arrival timeXh[?, JXh1 JslackXhA=h )%ngFEC/SFP_GEN[9].rx_data_reg[9][28]/C51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28]/D*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsuQ>}C =o>?==^=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)m )%ngFEC/SFP_GEN[9].rx_data_reg[9][28]/Q Prop_fdre_C_Q JFDREXhzr=y 95ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] Jnet (fo=1, routed)Xh^=d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28]/D JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest13_in Jnet (fo=1055, routed)Xho>X )%ngFEC/SFP_GEN[9].rx_data_reg[9][28]/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr; Jclock pessimismXht 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28] Hold_fdce_C_D JFDCEXhq=, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXh= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C)%ngFEC/SFP_GEN[9].rx_data_reg[9][25]/D*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsuR>}13K7 C =>K7 ?==j=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q Prop_fdre_C_Q JFDREXhzr=a !ngFEC/GBT_rx_data[5]_1372[25] Jnet (fo=1, routed)Xhj=X )%ngFEC/SFP_GEN[9].rx_data_reg[9][25]/D JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest13_in Jnet (fo=1055, routed)XhK7 ?X )%ngFEC/SFP_GEN[9].rx_data_reg[9][25]/C JFDREXhzr; Jclock pessimismXhh '#ngFEC/SFP_GEN[9].rx_data_reg[9][25] Hold_fdre_C_D JFDREXhq=, JXh9 J required timeXh138 J arrival timeXhQ?, JXh1 JslackXh= @ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/D*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsuC >}_ɾ8_94<F>8?u=t=crg=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR) @ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/D JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>o @ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/C JFDREXhzr; Jclock pessimismXht @ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][10]/D*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsuB>}뾍 A94<ˡ> ?=z=aq=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR) @ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][10]/D JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhˡ>o @ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][10]/C JFDREXhzr; Jclock pessimismXhz @}l羍J _94<}?>J ?)=no>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__3/I0 JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__3/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh}?> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)XhJ ? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhl羐8 J arrival timeXh ?, JXh1 JslackXh)=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D*:BJZ(LUT3=1)j9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsujWa>}gf澍8}94<X9>8?=no>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)  ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__3/I2 JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__3/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)XhX9> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh8? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhgf澐8 J arrival timeXhr?, JXh1 JslackXh=iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/D*:BJZ(CARRY4=1 LUT4=2 LUT6=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsu@}33A A"2A9R>?"2?33A=А=y@<U ?r,f@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]_0 Jnet (fo=37, routed)Xh|o? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/OProp_lut4_I1_O JLUT4Xhzr 0= `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/S[1] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/O[1]Prop_carry4_S[1]_O[1] JCARRY4Xhzrd;= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[1] Jnet (fo=18, routed)Xh? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/I5 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/OProp_lut6_I5_O JLUT6Xhzrl=| ;7ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[43]_0 Jnet (fo=41, routed)Xhkm?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[26]_i_1__3/I2 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[26]_i_1__3/OProp_lut4_I2_O JLUT4XhzrY= hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[22] Jnet (fo=1, routed)Xh]P> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/D JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh"2? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr; Jclock pessimismXh<= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]Setup_fdce_C_D JFDCEXh~j, JXh9 J required timeXh A8 J arrival timeXh , JXh1 JslackXhy@)iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/D*:BJZ(CARRY4=1 LUT4=2 LUT6=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsuw@}33AJ A"2A9R>?"2?33A=А=$~@< ?D`@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]_0 Jnet (fo=37, routed)Xh|o? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/OProp_lut4_I1_O JLUT4Xhzr 0= `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/S[1] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/O[1]Prop_carry4_S[1]_O[1] JCARRY4Xhzrd;= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[1] Jnet (fo=18, routed)Xh? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/I5 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/OProp_lut6_I5_O JLUT6Xhzrl=| ;7ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[43]_0 Jnet (fo=41, routed)Xht?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[25]_i_1__3/I2 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[25]_i_1__3/OProp_lut4_I2_O JLUT4XhzrD= hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[21] Jnet (fo=1, routed)Xh&> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/D JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh"2? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzr; Jclock pessimismXh<= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]Setup_fdce_C_D JFDCEXhʽ, JXh9 J required timeXhJ A8 J arrival timeXhʙ, JXh1 JslackXh$~@)NiengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CE*:BJZ(CARRY4=1 LUT3=1 LUT4=1 LUT6=2)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsuѱx@}33A A2&R>?2?33A=А='@<shq?W<@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzraP> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh.? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/OProp_lut4_I1_O JLUT4XhzrC > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 Jnet (fo=3, routed)XhƵ> ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/OProp_lut6_I0_O JLUT6Xhzrp= > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3]Prop_carry4_S[0]_O[3] JCARRY4XhzfP> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ,? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/I1 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/OProp_lut6_I1_O JLUT6Xhzr= WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] Jnet (fo=33, routed)Xh7? ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/I2 JXhzr \XngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/OProp_lut3_I2_O JLUT3XhzrT= gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] Jnet (fo=4, routed)Xhk ? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CE JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh2? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/C JFDCEXhzr; Jclock pessimismXh<= Jclock uncertaintyXh a]ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]Setup_fdce_C_CE JFDCEXh, JXh9 J required timeXh A8 J arrival timeXh/, JXh1 JslackXh'@!NiengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CE*:BJZ(CARRY4=1 LUT3=1 LUT4=1 LUT6=2)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsuMu@}33A A2&R>?2?33A=А=N@<shq?8@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzraP> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh.? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/OProp_lut4_I1_O JLUT4XhzrC > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 Jnet (fo=3, routed)XhƵ> ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/OProp_lut6_I0_O JLUT6Xhzrp= > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3]Prop_carry4_S[0]_O[3] JCARRY4XhzfP> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ,? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/I1 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/OProp_lut6_I1_O JLUT6Xhzr= WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] Jnet (fo=33, routed)Xh7? ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/I2 JXhzr \XngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/OProp_lut3_I2_O JLUT3XhzrT= gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] Jnet (fo=4, routed)Xh> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CE JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh2? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/C JFDCEXhzr; Jclock pessimismXh<= Jclock uncertaintyXh a]ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]Setup_fdce_C_CE JFDCEXh+, JXh9 J required timeXh A8 J arrival timeXh~, JXh1 JslackXhN@!NiengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4]/CE*:BJZ(CARRY4=1 LUT3=1 LUT4=1 LUT6=2)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsus@}33A`w A"2@R>?"2?33A=А=G@shq?dE7@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzraP> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh.? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/OProp_lut4_I1_O JLUT4XhzrC > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 Jnet (fo=3, routed)XhƵ> ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/OProp_lut6_I0_O JLUT6Xhzrp= > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3]Prop_carry4_S[0]_O[3] JCARRY4XhzfP> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ,? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/I1 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/OProp_lut6_I1_O JLUT6Xhzr= WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] Jnet (fo=33, routed)Xh7? ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/I2 JXhzr \XngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/OProp_lut3_I2_O JLUT3XhzrT= gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] Jnet (fo=4, routed)XhQ> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4]/CE JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh"2? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4]Setup_fdce_C_CE JFDCEXh, JXh9 J required timeXh`w A8 J arrival timeXhʦ, JXh1 JslackXhG@!NiengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/CE*:BJZ(CARRY4=1 LUT3=1 LUT4=1 LUT6=2)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsus@}33A`w A"2@R>?"2?33A=А=G@shq?dE7@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzraP> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh.? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/OProp_lut4_I1_O JLUT4XhzrC > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 Jnet (fo=3, routed)XhƵ> ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/OProp_lut6_I0_O JLUT6Xhzrp= > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3]Prop_carry4_S[0]_O[3] JCARRY4XhzfP> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ,? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/I1 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/OProp_lut6_I1_O JLUT6Xhzr= WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] Jnet (fo=33, routed)Xh7? ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/I2 JXhzr \XngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/OProp_lut3_I2_O JLUT3XhzrT= gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] Jnet (fo=4, routed)XhQ> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/CE JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh"2? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]Setup_fdce_C_CE JFDCEXh, JXh9 J required timeXh`w A8 J arrival timeXhʦ, JXh1 JslackXhG@!iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Cd`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/D*:BJZ(CARRY4=1 LUT4=2 LUT6=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsu :}@}33A A"2A9R>?"2?33A=А=@<O ?Y@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]_0 Jnet (fo=37, routed)Xh|o? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/OProp_lut4_I1_O JLUT4Xhzr 0= `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/S[1] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/O[1]Prop_carry4_S[1]_O[1] JCARRY4Xhzrd;= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[1] Jnet (fo=18, routed)Xh? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/I5 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/OProp_lut6_I5_O JLUT6Xhzrl=| ;7ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[43]_0 Jnet (fo=41, routed)Xh\q?j ?;ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[24]_i_1__3/I2 JXhzr >:ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[24]_i_1__3/OProp_lut4_I2_O JLUT4Xhzr/]= hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[20] Jnet (fo=1, routed)Xhl> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/D JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh"2? d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr; Jclock pessimismXh<= Jclock uncertaintyXh b^ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]Setup_fdce_C_D JFDCEXhĽ, JXh9 J required timeXh A8 J arrival timeXht, JXh1 JslackXh@) 73ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/CB>ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7]/CE*:BJZ(LUT2=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsuFw@}33AI A333w;1?333?33A=А=Gd@> c@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh?q FBngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7/I0 JXhzr EAngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7_n_0 Jnet (fo=128, routed)Xh`.?q B>ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7]/CE JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh1?f 73ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh333?p A=ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh ?;ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXhI A8 J arrival timeXhLؑ, JXh1 JslackXhGd@ 73ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/CC?ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][12]/CE*:BJZ(LUT2=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsuFw@}33AI A333w;1?333?33A=А=Gd@> c@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR){ 73ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr>w 51ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15] Jnet (fo=154, routed)Xh?q FBngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7/I0 JXhzr EAngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7/OProp_lut2_I0_O JLUT2Xhzr 0= GCngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7_n_0 Jnet (fo=128, routed)Xh`.?r C?ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][12]/CE JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh1?f 73ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh333?q B>ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][12]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh @?1?33A=А=C@o?5@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_5rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzraP> iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh.? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/I1 JXhzr ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/OProp_lut4_I1_O JLUT4XhzrC > `\ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 Jnet (fo=3, routed)XhƵ> ^ZngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/I0 JXhzr ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/OProp_lut6_I0_O JLUT6Xhzrp= > _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 Jnet (fo=1, routed)Xh d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/S[0] JXhzr d`ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3]Prop_carry4_S[0]_O[3] JCARRY4XhzfP> ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ,? hdngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/I1 JXhzf gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/OProp_lut6_I1_O JLUT6Xhzr= WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] Jnet (fo=33, routed)Xh7? ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[3]_i_1__3/I3 JXhzr \XngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[3]_i_1__3/OProp_lut4_I3_O JLUT4Xhzr 0= gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[0] Jnet (fo=4, routed)Xh> d`ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[1]/CE JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)XhR>? iengFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh1? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[1]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh A8 J arrival timeXh', JXh1 JslackXhC@! rxWordclkl12_6rxWordclkl12_6!)]_ff@1]_ff @9A]_ff@I]_ff @eV@hq}=O]@BB rise - rise rise - rise  t +'ngFEC/SFP_GEN[10].rx_data_reg[10][27]/C62ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27]/D*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu6>};ϾXA94<1>X>=*\=GB[=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR)o +'ngFEC/SFP_GEN[10].rx_data_reg[10][27]/Q Prop_fdre_C_Q JFDREXhzr=z :6ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]_0[19] Jnet (fo=1, routed)XhGB[=e 62ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest12_in Jnet (fo=1055, routed)Xh1>Z +'ngFEC/SFP_GEN[10].rx_data_reg[10][27]/C JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[10].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhX>e 62ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr; Jclock pessimismXh*\u 40ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27] Hold_fdce_C_D JFDCEXhq=, JXh9 J required timeXh;Ͼ8 J arrival timeXh>, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D*:BJZ(LUT3=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsuA>}ھE_94<r>E>=Obo>dz=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)Xhdz= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__4/I2 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__4/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[8] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xhr> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)XhE> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr; Jclock pessimismXhOb ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhھ8 J arrival timeXh??, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D*:BJZ(LUT3=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu}(ܾK}94<>K>;=*\o>%=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh%= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__4/I2 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__4/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[9] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)XhK> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr; Jclock pessimismXh*\ ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh(ܾ8 J arrival timeXhB?, JXh1 JslackXh;=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D*:BJZ(LUT3=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu_D>}۾A94<x>>=*\o>1=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh1= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__4/I2 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__4/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xhx> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr; Jclock pessimismXh*\ ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh۾8 J arrival timeXhB?, JXh1 JslackXh= +'ngFEC/SFP_GEN[10].rx_data_reg[10][46]/C62ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46]/D*:BJZ(LUT3=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu,W>}ᾍ_94< >>=Ob>=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR)o +'ngFEC/SFP_GEN[10].rx_data_reg[10][46]/Q Prop_fdre_C_Q JFDREXhzr=z :6ngFEC/gbtbank3_l12_116/SFP_GEN[10].rx_data_reg[10][30] Jnet (fo=1, routed)Xh=] 2.ngFEC/gbtbank3_l12_116/RX_Word_rx40[46]_i_1/I2 JXhzrv 1-ngFEC/gbtbank3_l12_116/RX_Word_rx40[46]_i_1/OProp_lut3_I2_O JLUT3Xhzr<z :6ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]_0[31] Jnet (fo=1, routed)Xhe 62ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest12_in Jnet (fo=1055, routed)Xh >Z +'ngFEC/SFP_GEN[10].rx_data_reg[10][46]/C JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[10].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh>e 62ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr; Jclock pessimismXhObu 40ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46] Hold_fdce_C_D JFDCEXh=, JXh9 J required timeXhᾐ8 J arrival timeXhQf ?, JXh1 JslackXh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu >}ھrJ >r?=/=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)XhJ > ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xhr? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh/ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhھ8 J arrival timeXhh?, JXh1 JslackXh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu >}ھrJ >r?=/=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1055, routed)XhJ > ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xhr? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh/ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhھ8 J arrival timeXhh?, JXh1 JslackXh=_ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[32]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32]/D*:BJZ(LUT6=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsuU>}/ݾ_94< >>]=Obo>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[32]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[32] Jnet (fo=1, routed)Xh= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[32]_i_1__4/I5 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[32]_i_1__4/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[32] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh > d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr; Jclock pessimismXhOb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh/ݾ8 J arrival timeXh> ?, JXh1 JslackXh]= *&ngFEC/SFP_GEN[10].rx_data_reg[10][0]/C51ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0]/D*:BJZ(LUT3=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsuU>}ᾍpA94<>p>]=Mbo>=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR)n *&ngFEC/SFP_GEN[10].rx_data_reg[10][0]/Q Prop_fdre_C_Q JFDREXhzr=y 95ngFEC/gbtbank3_l12_116/SFP_GEN[10].rx_data_reg[10][0] Jnet (fo=1, routed)Xh=\ 1-ngFEC/gbtbank3_l12_116/RX_Word_rx40[0]_i_1/I2 JXhzru 0,ngFEC/gbtbank3_l12_116/RX_Word_rx40[0]_i_1/OProp_lut3_I2_O JLUT3XhzrA`<y 95ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] Jnet (fo=1, routed)Xhd 51ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest12_in Jnet (fo=1055, routed)Xh>Y *&ngFEC/SFP_GEN[10].rx_data_reg[10][0]/C JFDREXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[10].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhp>d 51ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr; Jclock pessimismXhMbt 3/ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhᾐ8 J arrival timeXh1 ?, JXh1 JslackXh]=_ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[64]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64]/D*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsuU>}ܾQA94<~>Q>]=Mbo>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[64]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[64] Jnet (fo=1, routed)Xh= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[64]_i_1__4/I1 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[64]_i_1__4/OProp_lut2_I1_O JLUT2XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[64] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh~> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[64]/C JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhQ> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhܾ8 J arrival timeXh ?, JXh1 JslackXh]=ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu͍@}33A AG!,DVi?G!?33A=А=V@X?N@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[19] Jnet (fo=8, routed)Xhz @j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4/OProp_lut5_I3_O JLUT5Xhzr`P= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_2__4/OProp_lut4_I1_O JLUT4XhzrO > hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[91] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhG!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95]Setup_fdce_C_D JFDCEXh/ݽ, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXhV@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsuhC@}33A A Q#DVi? ?33A=А=gW@?0T@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] Jnet (fo=8, routed)XhS@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4/OProp_lut5_I0_O JLUT5Xhzr 0= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[26]_i_1__4/OProp_lut4_I3_O JLUT4Xhzr@= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[22] Jnet (fo=1, routed)Xhբ> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh ? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]Setup_fdce_C_D JFDCEXhν, JXh9 J required timeXh A8 J arrival timeXh0n, JXh1 JslackXhgW@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57]/D*:BJZ(LUT4=2)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu͊@}33A- A%!>DVi?%!?33A=А=\@?jKH@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[5]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[5] J GTXE2_CHANNELXhzr&?~ >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[5] Jnet (fo=6, routed)Xh/@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[97]_i_3__4/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[97]_i_3__4/OProp_lut4_I0_O JLUT4Xhzr/]= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[57]_i_1__4/OProp_lut4_I1_O JLUT4Xhzrz> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[53] Jnet (fo=1, routed)Xhp> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh%!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57]Setup_fdce_C_D JFDCEXh[½, JXh9 J required timeXh- A8 J arrival timeXhm, JXh1 JslackXh\@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu<4@}33A A!DVi?!?33A=А==]@ ?rF@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] Jnet (fo=8, routed)Xh%3 @j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4/OProp_lut5_I3_O JLUT5Xhzr/]= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[62]_i_1__4/OProp_lut4_I1_O JLUT4XhzrP> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[58] Jnet (fo=1, routed)Xh4> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]Setup_fdce_C_D JFDCEXhԽ, JXh9 J required timeXh A8 J arrival timeXh_, JXh1 JslackXh=]@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu@}33A@ AM"DVi?M"?33A=А=6b_@5^?6D@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[19] Jnet (fo=8, routed)Xhz @j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4/OProp_lut5_I3_O JLUT5Xhzr`P= @j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[31]_i_2__4/I1 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[31]_i_2__4/OProp_lut4_I1_O JLUT4Xhzr> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[27] Jnet (fo=1, routed)XhYk> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhM"? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXh@ A8 J arrival timeXheݥ, JXh1 JslackXh6b_@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu@}33A A%!>DVi?%!?33A=А==_@?uK@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] Jnet (fo=8, routed)XhS@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4/OProp_lut5_I0_O JLUT5Xhzr 0= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[58]_i_1__4/OProp_lut4_I3_O JLUT4Xhzr@= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[54] Jnet (fo=1, routed)XhB> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh%!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58]Setup_fdce_C_D JFDCEXhν, JXh9 J required timeXh A8 J arrival timeXh,, JXh1 JslackXh=_@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74]/D*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu@}33A A cDVi? ?33A=А=a@?=6N@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] Jnet (fo=8, routed)XhS@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[98]_i_2__4/I1 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[98]_i_2__4/OProp_lut4_I1_O JLUT4Xhzr/]= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[74]_i_1__4/OProp_lut6_I0_O JLUT6XhzrI > hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[70] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh ? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74]Setup_fdce_C_D JFDCEXh+=, JXh9 J required timeXh A8 J arrival timeXhN, JXh1 JslackXha@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu@}33A- A Q#DVi? ?33A=А=B5c@i? cH@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[19] Jnet (fo=8, routed)Xh @j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[91]_i_3__4/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[91]_i_3__4/OProp_lut5_I0_O JLUT5Xhzr 0= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[27]_i_2__4/OProp_lut4_I3_O JLUT4Xhzr/]= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[23] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh ? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXh- A8 J arrival timeXh, JXh1 JslackXhB5c@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu 1@}33A) A Q#DVi? ?33A=А=c@/?G@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[88]_i_2__4/I4 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[88]_i_2__4/OProp_lut5_I4_O JLUT5Xhzr 0= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[56]_i_1__4/OProp_lut4_I3_O JLUT4Xhzr`P= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[52] Jnet (fo=1, routed)XhqB> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh ? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56]Setup_fdce_C_D JFDCEXh[½, JXh9 J required timeXh) A8 J arrival timeXh[, JXh1 JslackXhc@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsuF@}33A AG!,DVi?G!?33A=А=e@?-?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_6rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] Jnet (fo=8, routed)Xh%3 @j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4/OProp_lut5_I3_O JLUT5Xhzr/]= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_1__4/OProp_lut4_I1_O JLUT4Xhzr> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[90] Jnet (fo=1, routed)XhMb> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhG!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]Setup_fdce_C_D JFDCEXh/ݽ, JXh9 J required timeXh A8 J arrival timeXhq, JXh1 JslackXhe@ rxWordclkl12_7rxWordclkl12_7!)]_ff@1]_ff @9A]_ff@I]_ff @eN@hq}=O]@CC  rise - rise rise - rise  _ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53]/D*:BJZ(LUT6=1)j9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsu9>}Aྍl_94<z>l>=Obo>GB[=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[53] Jnet (fo=1, routed)XhGB[= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[53]_i_1__5/I5 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[53]_i_1__5/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[53] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xhz> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xhl> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53]/C JFDCEXhzr; Jclock pessimismXhOb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhAྐ8 J arrival timeXh?, JXh1 JslackXh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsu >}.ݾ ˡ> ?=v=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xhˡ> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xh ? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh.ݾ8 J arrival timeXh)w ?, JXh1 JslackXh=_ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[76]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76]/D*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuU>}M⾍v_94< >v>]=rho>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[76]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[76] Jnet (fo=1, routed)Xh= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[76]_i_1__5/I1 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[76]_i_1__5/OProp_lut2_I1_O JLUT2XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[76] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh > d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[76]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xhv> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76]/C JFDCEXhzr; Jclock pessimismXhrh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhM⾐8 J arrival timeXhr ?, JXh1 JslackXh]=_ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D*:BJZ(LUT6=1)j9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuU>}Aྍ~jA94<|>~j>]=pho>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[49] Jnet (fo=1, routed)Xh= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[49]_i_1__5/I5 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[49]_i_1__5/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[49] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh|> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh~j> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/C JFDCEXhzr; Jclock pessimismXhph b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhAྐ8 J arrival timeXhwl ?, JXh1 JslackXh]=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D*:BJZ(LUT3=1)j9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsu,W>}M⾍_94< >>v=Obo>~=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_15_in Jnet (fo=1, routed)Xh~= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__5/I2 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__5/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[6] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh > ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr; Jclock pessimismXhOb ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhM⾐8 J arrival timeXh ?, JXh1 JslackXhv=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D*:BJZ(LUT3=1)j9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsu,W>}/侍A_94<!>A?v=Obo>~=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh~= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__5/I0 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__5/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh!> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)XhA? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr; Jclock pessimismXhOb ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh/侐8 J arrival timeXh[=?, JXh1 JslackXhv= 62ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7]/C@}پ8_94<F>8?'=t=}=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)z 62ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7]/Q Prop_fdce_C_Q JFDCEXhzr=t 40ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7] Jnet (fo=2, routed)Xh}=o @e 62ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh8?o @:ngFEC/SFP_GEN[11].ngCCM_gbt/ngCCM_status_counter_reg[5][7] Hold_fdce_C_D JFDCEXh$=, JXh9 J required timeXhپ8 J arrival timeXhr ?, JXh1 JslackXh'=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D*:BJZ(LUT3=1)j9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsu5!]>} 㾍|}94<>|>-=Mbo>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__5/I2 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__5/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh|> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr; Jclock pessimismXhMb ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh 㾐8 J arrival timeXhK?, JXh1 JslackXh-=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D*:BJZ(LUT3=1)j9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuw>}ヘAv=!>A?i=o>K=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)XhK= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__5/I0 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__5/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh!> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)XhA? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr; Jclock pessimismXh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhミ8 J arrival timeXh?, JXh1 JslackXhi= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsu1>}"۾ ˡ> ?>v=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xhˡ> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xh ? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXh"۾8 J arrival timeXh?, JXh1 JslackXh>ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuWX@}33A5 A!5k?!?33A=А=N@?U@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? IEngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] Jnet (fo=13, routed)Xh2@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/OProp_lut5_I0_O JLUT5Xhzr`P= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[28]_i_1__5/OProp_lut4_I1_O JLUT4Xhzr)\> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[24] Jnet (fo=1, routed)Xhq> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]Setup_fdce_C_D JFDCEXhl罐, JXh9 J required timeXh5 A8 J arrival timeXh ծ, JXh1 JslackXhN@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu@}33A AM"/k?M"?33A=А=AY@~?J@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][18] Jnet (fo=8, routed)XhH@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5/OProp_lut5_I3_O JLUT5Xhzr/]= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[62]_i_1__5/OProp_lut4_I1_O JLUT4Xhzrt> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[58] Jnet (fo=1, routed)Xh;? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhM"? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62]Setup_fdce_C_D JFDCEXhS㽐, JXh9 J required timeXh A8 J arrival timeXhM`, JXh1 JslackXhAY@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu&@}33A A8!Ѹk?8!?33A=А=HZ@?>I@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? IEngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] Jnet (fo=13, routed)Xh2@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/OProp_lut5_I0_O JLUT5Xhzr`P= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[60]_i_1__5/OProp_lut4_I1_O JLUT4Xhzrt> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[56] Jnet (fo=1, routed)XhO > d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh8!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]Setup_fdce_C_D JFDCEXh뽐, JXh9 J required timeXh A8 J arrival timeXhZ, JXh1 JslackXhHZ@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu=C@}33A& A!5k?!?33A=А=a@"ۙ?A@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[15]'Prop_gtxe2_channel_RXUSRCLK2_RXDATA[15] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][17] Jnet (fo=8, routed)Xh.@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/OProp_lut5_I3_O JLUT5Xhzr`P= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[29]_i_1__5/OProp_lut4_I1_O JLUT4Xhzrrh> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[25] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXh& A8 J arrival timeXh, JXh1 JslackXha@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuKu@}33A A8!Ѹk?8!?33A=А=c@~??@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[15]'Prop_gtxe2_channel_RXUSRCLK2_RXDATA[15] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][17] Jnet (fo=8, routed)Xh.@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/OProp_lut5_I3_O JLUT5Xhzr`P= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[61]_i_1__5/OProp_lut4_I1_O JLUT4Xhzr+> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[57] Jnet (fo=1, routed)Xhؽ> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh8!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61]Setup_fdce_C_D JFDCEXh, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXhc@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu^@}33A5 A!5k?!?33A=А=f@ ?<@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1])Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][18] Jnet (fo=8, routed)XhH@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5/OProp_lut5_I3_O JLUT5Xhzr/]= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[30]_i_1__5/OProp_lut4_I1_O JLUT4XhzrP> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[26] Jnet (fo=1, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30]Setup_fdce_C_D JFDCEXhl罐, JXh9 J required timeXh5 A8 J arrival timeXh, JXh1 JslackXhf@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuCE@}33A Ao#ck?o#?33A=А=Ύh@?;@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? IEngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] Jnet (fo=13, routed)Xh2@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/OProp_lut5_I0_O JLUT5Xhzr`P= @j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_1__5/I1 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_1__5/OProp_lut4_I1_O JLUT4Xhzr)\> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[88] Jnet (fo=1, routed)Xh.E> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xho#? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92]Setup_fdce_C_D JFDCEXhl罐, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXhΎh@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu@}33Ap Ao#ck?o#?33A=А=fn@?34@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[15]'Prop_gtxe2_channel_RXUSRCLK2_RXDATA[15] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][17] Jnet (fo=8, routed)Xh.@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/I3 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/OProp_lut5_I3_O JLUT5Xhzr`P= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_1__5/OProp_lut4_I1_O JLUT4Xhzrt> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[89] Jnet (fo=1, routed)Xha> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xho#? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]Setup_fdce_C_D JFDCEXh%, JXh9 J required timeXhp A8 J arrival timeXhyk, JXh1 JslackXhfn@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu^@}33Ae AM"/k?M"?33A=А=2~q@?2>@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzr&? IEngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] Jnet (fo=13, routed)Xh2@j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/OProp_lut5_I0_O JLUT5Xhzr`P= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[20]_i_1__5/OProp_lut4_I1_O JLUT4XhzrC > hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[16] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhM"? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20]Setup_fdce_C_D JFDCEXho=, JXh9 J required timeXhe A8 J arrival timeXhۢ, JXh1 JslackXh2~q@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuz~@}33A A!5k?!?33A=А=r@H? 1@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_7rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[3]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[3] J GTXE2_CHANNELXhzr&? IEngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][3] Jnet (fo=13, routed)Xhgp?j ?;ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__5/I0 JXhzr >:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__5/OProp_lut5_I0_O JLUT5XhzrGa= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[31]_i_2__5/OProp_lut4_I1_O JLUT4Xhzr> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[27] Jnet (fo=1, routed)XhCa> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31]/D JFDCEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh!? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31]Setup_fdce_C_D JFDCEXh/ݽ, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXhr@  rxWordclkl12_8rxWordclkl12_8!)]_ff@1]_ff @9A]_ff@I]_ff @e-x@hq}=O]@DD rise - rise rise - rise  _ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[38]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38]/D*:BJZ(LUT6=1)j9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsu$:>}&ffA94<>ff?=Mbo>Z_=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[38]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[38] Jnet (fo=1, routed)XhZ_= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[38]_i_1__6/I5 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[38]_i_1__6/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[38] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38]/D JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[38]/C JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xhff? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh&8 J arrival timeXh77?, JXh1 JslackXh= +'ngFEC/SFP_GEN[12].rx_data_reg[12][32]/C62ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D*:BJZ(LUT3=1)j9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsuK;>}{/}94<l>/?Z*=Mbo>nsc=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR)o +'ngFEC/SFP_GEN[12].rx_data_reg[12][32]/Q Prop_fdre_C_Q JFDREXhzr=s 3/ngFEC/gbtbank3_l12_116/RX_Word_rx40_reg[78][16] Jnet (fo=1, routed)Xhnsc=` 51ngFEC/gbtbank3_l12_116/RX_Word_rx40[32]_i_1__1/I2 JXhzry 40ngFEC/gbtbank3_l12_116/RX_Word_rx40[32]_i_1__1/OProp_lut3_I2_O JLUT3XhzrA`<z :6ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] Jnet (fo=1, routed)Xhe 62ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrc ngFEC/gbtbank3_l12_116_n_137 Jnet (fo=1055, routed)Xhl>Z +'ngFEC/SFP_GEN[12].rx_data_reg[12][32]/C JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[12].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh/?e 62ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr; Jclock pessimismXhMbu 40ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh{8 J arrival timeXh ?, JXh1 JslackXhZ*= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsu >}(ܾ > ?=v=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xh> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xh ? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh(ܾ8 J arrival timeXh ?, JXh1 JslackXh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsu >}"۾L7 o>L7 ?=S=`=g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1055, routed)Xho> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1055, routed)XhL7 ? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhS ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh"۾8 J arrival timeXh{/ ?, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D*:BJZ(LUT3=1)j9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsuU>}ヘB`_94<>B`?]=Obo>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__6/I0 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__6/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)XhB`? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr; Jclock pessimismXhOb ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhミ8 J arrival timeXh?, JXh1 JslackXh]=_ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[54]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54]/D*:BJZ(LUT6=1)j9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsuU>}أ$}94<v>$?]=Mbo>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[54]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[54] Jnet (fo=1, routed)Xh= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[54]_i_1__6/I5 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[54]_i_1__6/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[54] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54]/D JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xhv> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[54]/C JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh$? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhأ8 J arrival timeXh?, JXh1 JslackXh]=_ d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/Cd`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59]/D*:BJZ(LUT6=1)j9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsun>}j+=>?+=o>j=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[59] Jnet (fo=1, routed)Xhj= hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[59]_i_1__6/I5 JXhzr gcngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[59]_i_1__6/OProp_lut6_I5_O JLUT6XhzrA`< a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[59] Jnet (fo=1, routed)Xh d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59]/D JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhj8 J arrival timeXh.?, JXh1 JslackXh+=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D*:BJZ(LUT3=1)j9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsuQ]>}أgf}94<v>gf?=tho>%~=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh%~= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__6/I0 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__6/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xhv> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xhgf? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr; Jclock pessimismXhth ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhأ8 J arrival timeXhď?, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D*:BJZ(LUT3=1)j9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsuD]>}֣ffA94<v>ff?N=tho>=g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__6/I0 JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__6/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xhv> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xhff? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr; Jclock pessimismXhth ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh֣8 J arrival timeXh?, JXh1 JslackXhN=' ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'ngFEC/SFP_GEN[12].rx_data_reg[12][67]/D*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsu7qQ>}辍+C =|>+?===g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FastrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q Prop_fdre_C_Q JFDREXhzr=a !ngFEC/GBT_rx_data[8]_1383[67] Jnet (fo=1, routed)Xh=Z +'ngFEC/SFP_GEN[12].rx_data_reg[12][67]/D JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh|> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrc ngFEC/gbtbank3_l12_116_n_137 Jnet (fo=1055, routed)Xh+?Z +'ngFEC/SFP_GEN[12].rx_data_reg[12][67]/C JFDREXhzr; Jclock pessimismXhj )%ngFEC/SFP_GEN[12].rx_data_reg[12][67] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh辐8 J arrival timeXh?, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1]/CE*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuv@}33A A1i*'l?1?33A=А=-x@(?x0@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)XhG?? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/I1 JXhzr hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/OProp_lut6_I1_O JLUT6Xhzr 0= ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh:> fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1]/CE JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xh1? eangFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh c_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXh-x@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5]/CE*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuv@}33A A1i*'l?1?33A=А=-x@(?x0@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)XhG?? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/I1 JXhzr hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/OProp_lut6_I1_O JLUT6Xhzr 0= ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh:> fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5]/CE JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xh1? eangFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh c_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXh-x@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]/CE*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuv@}33A A1i*'l?1?33A=А=-x@(?x0@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)XhG?? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/I1 JXhzr hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/OProp_lut6_I1_O JLUT6Xhzr 0= ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh:> fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]/CE JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xh1? eangFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh c_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXh-x@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/D*:BJZ(LUT4=2 LUT5=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsug@}33A7Aף0L n*'l?ף0?33A=А=z@+?Q7@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)Xh@^;? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6/I0 JXhzr lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6/OProp_lut5_I0_O JLUT5Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6_n_0 Jnet (fo=1, routed)XhRv?> mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6/I0 JXhzr lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6/OProp_lut6_I0_O JLUT6Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6_n_0 Jnet (fo=2, routed)Xhސ> mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[0]_i_1__7/I2 JXhzr lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[0]_i_1__7/OProp_lut4_I2_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[0]_i_1__7_n_0 Jnet (fo=1, routed)Xh iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/D JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xhף0? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]Setup_fdce_C_D JFDCEXhC =, JXh9 J required timeXh7A8 J arrival timeXhL,, JXh1 JslackXhz@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/D*:BJZ(LUT4=1 LUT5=2 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsu؁@}33A1Aף0L n*'l?ף0?33A=А=ۭ{@?Q7@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)Xh@^;? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6/I0 JXhzr lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6/OProp_lut5_I0_O JLUT5Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6_n_0 Jnet (fo=1, routed)XhRv?> mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6/I0 JXhzr lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6/OProp_lut6_I0_O JLUT6Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6_n_0 Jnet (fo=2, routed)Xhސ> mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_1__7/I3 JXhzr lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_1__7/OProp_lut5_I3_O JLUT5Xhzr9H= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 Jnet (fo=1, routed)Xh iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/D JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xhף0? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]Setup_fdce_C_D JFDCEXhim=, JXh9 J required timeXh1A8 J arrival timeXht], JXh1 JslackXhۭ{@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0]/CE*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsudUr@}33Aly A`0(m*'l?`0?33A=А=|@(?@,@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)XhG?? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/I1 JXhzr hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/OProp_lut6_I1_O JLUT6Xhzr 0= ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhT> fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0]/CE JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xh`0? eangFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh c_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXhly A8 J arrival timeXh, JXh1 JslackXh|@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2]/CE*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuq@}33A Ash1j*'l?sh1?33A=А=`}@(?+@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)XhG?? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/I1 JXhzr hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/OProp_lut6_I1_O JLUT6Xhzr 0= ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh艗> fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2]/CE JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xhsh1? eangFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh c_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXh A8 J arrival timeXhR, JXh1 JslackXh`}@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/CE*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuq@}33A Ash1j*'l?sh1?33A=А=`}@(?+@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)XhG?? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/I1 JXhzr hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/OProp_lut6_I1_O JLUT6Xhzr 0= ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh艗> fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/CE JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xhsh1? eangFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh c_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXh A8 J arrival timeXhR, JXh1 JslackXh`}@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4]/CE*:BJZ(LUT4=1 LUT6=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuq@}33A Ash1j*'l?sh1?33A=А=`}@(?+@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowrxWordclkl12_8rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0] J GTXE2_CHANNELXhzf&? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] Jnet (fo=13, routed)Xh0? mingFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/I1 JXhzf lhngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/OProp_lut4_I1_O JLUT4Xhzr 0= njngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 Jnet (fo=3, routed)XhG?? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/I1 JXhzr hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/OProp_lut6_I1_O JLUT6Xhzr 0= ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh艗> fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4]/CE JFDREXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xhsh1? eangFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4]/C JFDREXhzr; Jclock pessimismXh= Jclock uncertaintyXh c_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4]Setup_fdre_C_CE JFDREXhM, JXh9 J required timeXh A8 J arrival timeXhR, JXh1 JslackXh`}@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D*:BJZ(LUT4=1 LUT5=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsus@}33A3 A:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__6/OProp_lut5_I0_O JLUT5XhzrT= @:ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_2__6/OProp_lut4_I1_O JLUT4XhzrV> hdngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[91] Jnet (fo=1, routed)XhD> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D JFDCEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh}.ݾ ˡ> ?=v=`=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xhˡ> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh.ݾ8 J arrival timeXh)w ?, JXh1 JslackXh=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsuU>}!A94<>?]=no>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_33_in Jnet (fo=1, routed)Xh= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__7/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__7/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh!8 J arrival timeXhã?, JXh1 JslackXh]=G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D*:BJZ(LUT2=1)j7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsuU>}^ _94<>^ ?]=zo>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[76] Jnet (fo=1, routed)Xh= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[76]_i_1__7/I1 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[76]_i_1__7/OProp_lut2_I1_O JLUT2XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[76] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh^ ? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/C JFDCEXhzr; Jclock pessimismXhz a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh8 J arrival timeXh,?, JXh1 JslackXh]= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu#>}.ݾ ˡ> ?^=v=:^v=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh:^v= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xhˡ> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh.ݾ8 J arrival timeXhc ?, JXh1 JslackXh^=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu5!]>}gf澍8}94<X9>8?-=no>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__7/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__7/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhX9> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh8? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhgf澐8 J arrival timeXhd?, JXh1 JslackXh-=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsuQ]>}FrA94<8>r?=to>%~=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh%~= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__7/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__7/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[7] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh8> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhr? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr; Jclock pessimismXht ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhF8 J arrival timeXh?, JXh1 JslackXh= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C)%ngFEC/SFP_GEN[5].rx_data_reg[5][34]/D*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu OE>}cؾ%T<23>?X)=*\=Pѽ=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q Prop_fdre_C_Q JFDREXhzr=a !ngFEC/GBT_rx_data[9]_1396[34] Jnet (fo=1, routed)XhPѽ=X )%ngFEC/SFP_GEN[5].rx_data_reg[5][34]/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh23> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest17_in Jnet (fo=1057, routed)Xh?X )%ngFEC/SFP_GEN[5].rx_data_reg[5][34]/C JFDREXhzr; Jclock pessimismXh*\h '#ngFEC/SFP_GEN[5].rx_data_reg[5][34] Hold_fdre_C_D JFDREXhq=, JXh9 J required timeXhcؾ8 J arrival timeXh\ ?, JXh1 JslackXhX)=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsujWa>}l羍J _94<}?>J ?=no>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__7/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__7/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh}?> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhJ ? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhl羐8 J arrival timeXh?, JXh1 JslackXh=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu͙F>}l羍L7 A94<o>L7 ?*=to>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__7/I2 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__7/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xho> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhL7 ? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr; Jclock pessimismXht ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhl羐8 J arrival timeXh/?, JXh1 JslackXh*= ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C\XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/D*:BJZ(LUT6=1)j7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsumP>}羍L7 A94<>L7 ?5>no>y=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR) ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/Q Prop_fdce_C_Q JFDCEXhzf= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt[2] Jnet (fo=6, routed)Xhy= `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_i_1__7/I4 JXhzf _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_i_1__7/OProp_lut6_I4_O JLUT6XhzrA`< [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)Xh \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/D JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh> ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)XhL7 ? \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXhn ZVngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh羐8 J arrival timeXh?, JXh1 JslackXh5> D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsuoʏ@}33AK AU%ƽR>?U%?33A=А=9W@'1>\G@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)XhƸ@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhU%?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhK A8 J arrival timeXhy, JXh1 JslackXh9W@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsuoʏ@}33AK AU%ƽR>?U%?33A=А=9W@'1>\G@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)XhƸ@d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhU%?c 40ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhu 2.ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhK A8 J arrival timeXhy, JXh1 JslackXh9W@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu\@}33A+ A$&ĽR>?$&?33A=А=FZ@'1>ن@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh~@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXh3, JXh1 JslackXhFZ@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu\@}33A+ A$&ĽR>?$&?33A=А=FZ@'1>ن@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh~@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXh3, JXh1 JslackXhFZ@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsul@}33A+ A$&ĽR>?$&?33A=А=xg@'1>Y;@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXhv, JXh1 JslackXhxg@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsul@}33A+ A$&ĽR>?$&?33A=А=xg@'1>Y;@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXhv, JXh1 JslackXhxg@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsul@}33A+ A$&ĽR>?$&?33A=А=xg@'1>Y;@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXhv, JXh1 JslackXhxg@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsul@}33A+ A$&ĽR>?$&?33A=А=xg@'1>Y;@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXhv, JXh1 JslackXhxg@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsul@}33A+ A$&ĽR>?$&?33A=А=xg@'1>Y;@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXhv, JXh1 JslackXhxg@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70]/CE*:BJZ(LUT3=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsul@}33A+ A$&ĽR>?$&?33A=А=xg@'1>Y;@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_1 rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] Jnet (fo=127, routed)Xh?d 95ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/I2 JXhzr} 84ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70]/CE JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] Jnet (fo=1057, routed)XhR>?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh$&?d 51ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh+ A8 J arrival timeXhv, JXh1 JslackXhxg@  rxWordclkl8_2 rxWordclkl8_2!)]_ff@1]_ff @9A]_ff@I]_ff @eV&@hq}=O]@FF  rise - rise rise - rise  G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D*:BJZ(LUT6=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu$:>}ᾍA94<>>=to>Z_=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[49] Jnet (fo=1, routed)XhZ_= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[49]_i_1__8/I5 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[49]_i_1__8/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[49] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/C JFDCEXhzr; Jclock pessimismXht a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhᾐ8 J arrival timeXh"?, JXh1 JslackXh=G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[54]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54]/D*:BJZ(LUT6=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu$:>}M⾍vA94< >v>=tho>Z_=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[54]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[54] Jnet (fo=1, routed)XhZ_= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[54]_i_1__8/I5 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[54]_i_1__8/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[54] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54]/D JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh > c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[54]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhv> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54]/C JFDCEXhzr; Jclock pessimismXhth a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhM⾐8 J arrival timeXh?, JXh1 JslackXh=< b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/Cb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/D*:BJZ(LUT6=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu$:>}ᾍA94<>>=to>Z_=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/Q Prop_fdce_C_Q JFDCEXhzr= \XngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[6] Jnet (fo=1, routed)XhZ_= fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[6]_i_1__8/I5 JXhzr eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[6]_i_1__8/OProp_lut6_I5_O JLUT6XhzrA`< _[ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[6] Jnet (fo=1, routed)Xh b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/D JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/C JFDCEXhzr; Jclock pessimismXht `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhᾐ8 J arrival timeXh"?, JXh1 JslackXh=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuC>}@5޾I_94<1>I>=no>J=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)XhJ= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__8/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__8/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh1> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhI> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh@5޾8 J arrival timeXh?, JXh1 JslackXh= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu >}پ'18>'1?=,=`=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh8> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh'1? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhپ8 J arrival timeXhj?, JXh1 JslackXh= ($ngFEC/SFP_GEN[6].rx_data_reg[6][7]/C40ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6]/D*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuU>}Aྍl_94<z>l>]=Obo>=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR)l ($ngFEC/SFP_GEN[6].rx_data_reg[6][7]/Q Prop_fdre_C_Q JFDREXhzr=s 3/ngFEC/gbtbank4_l8_112/RX_Word_rx40_reg[78]_0[7] Jnet (fo=1, routed)Xh=^ 3/ngFEC/gbtbank4_l8_112/RX_Word_rx40[6]_i_1__4/I0 JXhzrw 2.ngFEC/gbtbank4_l8_112/RX_Word_rx40[6]_i_1__4/OProp_lut3_I0_O JLUT3XhzrA`<x 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[83]_0[3] Jnet (fo=1, routed)Xhc 40ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6]/D JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest16_in Jnet (fo=1057, routed)Xhz>W ($ngFEC/SFP_GEN[6].rx_data_reg[6][7]/C JFDREXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhl>c 40ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr; Jclock pessimismXhObs 2.ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhAྐ8 J arrival timeXhul ?, JXh1 JslackXh]=< b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/Cb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/D*:BJZ(LUT6=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuU>}ᾍA94<>>]=to>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/Q Prop_fdce_C_Q JFDCEXhzr= \XngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[5] Jnet (fo=1, routed)Xh= fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[5]_i_1__8/I5 JXhzr eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[5]_i_1__8/OProp_lut6_I5_O JLUT6XhzrA`< _[ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[5] Jnet (fo=1, routed)Xh b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/D JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/C JFDCEXhzr; Jclock pessimismXht `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhᾐ8 J arrival timeXh1 ?, JXh1 JslackXh]=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuU>}S㾍|_94<&>|>]=rho>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__8/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__8/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh&> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh|> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr; Jclock pessimismXhrh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhS㾐8 J arrival timeXh ?, JXh1 JslackXh]=G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47]/D*:BJZ(LUT6=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu,W>}⾍}94<֣>>v=tho>~=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47] Jnet (fo=1, routed)Xh~= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[47]_i_1__8/I5 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[47]_i_1__8/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[47] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47]/D JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh֣> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47]/C JFDCEXhzr; Jclock pessimismXhth a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh⾐8 J arrival timeXh67?, JXh1 JslackXhv=G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[42]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42]/D*:BJZ(LUT6=1)j7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu,W>}S㾍A94<&>?#v=no>~=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[42]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[42] Jnet (fo=1, routed)Xh~= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[42]_i_1__8/I5 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[42]_i_1__8/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[42] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42]/D JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[42]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42]/C JFDCEXhzr; Jclock pessimismXhn a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhS㾐8 J arrival timeXhx?, JXh1 JslackXh#v= D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu@}33AA!gNb0?!?33A=А=V&@'1>q@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhV&@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu@}33AA!gNb0?!?33A=А=V&@'1>q@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhV&@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuؤ@}33A1A뽵Nb0??33A=А=$,@'1>uU@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh1A8 J arrival timeXh, JXh1 JslackXh$,@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuؤ@}33A1A뽵Nb0??33A=А=$,@'1>uU@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh1A8 J arrival timeXh, JXh1 JslackXh$,@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuؤ@}33A1A뽵Nb0??33A=А=$,@'1>uU@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh1A8 J arrival timeXh, JXh1 JslackXh$,@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuؤ@}33A1A뽵Nb0??33A=А=$,@'1>uU@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh@e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh1A8 J arrival timeXh, JXh1 JslackXh$,@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu@}33AgA뽵Nb0??33A=А=ɞ3@'1> @f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xhuk?e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXhgA8 J arrival timeXhh!, JXh1 JslackXhɞ3@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu@}33AgA뽵Nb0??33A=А=ɞ3@'1> @f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xhuk?e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXhgA8 J arrival timeXhh!, JXh1 JslackXhɞ3@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu@}33A AG!qNb0?G!?33A=А=XK@'1>@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh"?e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhG!?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh A8 J arrival timeXh4, JXh1 JslackXhXK@ D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50]/CE*:BJZ(LUT3=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu@}33A AG!qNb0?G!?33A=А=XK@'1>@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_2 rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q Prop_fdce_C_Q JFDCEXhzrZd> GCngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] Jnet (fo=127, routed)Xh`6@d 95ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/I2 JXhzr} 84ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/OProp_lut3_I2_O JLUT3Xhzr 0=l +'ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 Jnet (fo=48, routed)Xh"?e 62ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50]/CE JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrn +'ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] Jnet (fo=1057, routed)XhNb0?s D@ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhG!?d 51ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXhv 3/ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh A8 J arrival timeXh4, JXh1 JslackXhXK@  rxWordclkl8_3 rxWordclkl8_3!)]_ff@1]_ff @9A]_ff@I]_ff @e7e@hq}^*=O]@GG rise - rise rise - rise  )%ngFEC/SFP_GEN[7].rx_data_reg[7][33]/C51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32]/D*:BJZ(LUT3=1)j7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuK;>} -+_94<>+?^*=rho>nsc=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)m )%ngFEC/SFP_GEN[7].rx_data_reg[7][33]/Q Prop_fdre_C_Q JFDREXhzr=r 2.ngFEC/gbtbank4_l8_112/RX_Word_rx40_reg[78][17] Jnet (fo=1, routed)Xhnsc=_ 40ngFEC/gbtbank4_l8_112/RX_Word_rx40[32]_i_1__3/I0 JXhzrx 3/ngFEC/gbtbank4_l8_112/RX_Word_rx40[32]_i_1__3/OProp_lut3_I0_O JLUT3XhzrA`<y 95ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] Jnet (fo=1, routed)Xhd 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrY ngFEC/clktest15_in Jnet (fo=1057, routed)Xh>X )%ngFEC/SFP_GEN[7].rx_data_reg[7][33]/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh+?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr; Jclock pessimismXhrht 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh -8 J arrival timeXh?, JXh1 JslackXh^*= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsu >}پ$>?=/=`=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh$> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh/ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhپ8 J arrival timeXhU)?, JXh1 JslackXh=u ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsu >}vؾ>?=,=`=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhvؾ8 J arrival timeXh?, JXh1 JslackXh=G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[44]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44]/D*:BJZ(LUT6=1)j7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuU>}ᾍpA94<>p>]=Mbo>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[44]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[44] Jnet (fo=1, routed)Xh= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[44]_i_1__9/I5 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[44]_i_1__9/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[44] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[44]/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44]/C JFDCEXhzr; Jclock pessimismXhMb a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhᾐ8 J arrival timeXh1 ?, JXh1 JslackXh]=G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[20]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20]/D*:BJZ(LUT6=1)j7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuU>}֣ff_94<v>ff?]=rho>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[20]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[20] Jnet (fo=1, routed)Xh= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[20]_i_1__9/I5 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[20]_i_1__9/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[20] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhv> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[20]/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhff? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20]/C JFDCEXhzr; Jclock pessimismXhrh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh֣8 J arrival timeXh?, JXh1 JslackXh]=< b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[4]/Cb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4]/D*:BJZ(LUT6=1)j7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuU>}ヘU_94<p>U?]=rho>=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[4]/Q Prop_fdce_C_Q JFDCEXhzr= \XngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[4] Jnet (fo=1, routed)Xh= fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[4]_i_1__9/I5 JXhzr eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[4]_i_1__9/OProp_lut6_I5_O JLUT6XhzrA`< _[ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[4] Jnet (fo=1, routed)Xh b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[4]/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhU? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4]/C JFDCEXhzr; Jclock pessimismXhrh `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhミ8 J arrival timeXh?, JXh1 JslackXh]=G c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[15]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15]/D*:BJZ(LUT6=1)j7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsu<>}⾍gf}94<v>gf?u=tho>crg=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR) c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[15] Jnet (fo=1, routed)Xhcrg= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[15]_i_1__9/I5 JXhzr fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[15]_i_1__9/OProp_lut6_I5_O JLUT6XhzrA`< `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[15] Jnet (fo=1, routed)Xh c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhv> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[15]/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhgf? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15]/C JFDCEXhzr; Jclock pessimismXhth a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh⾐8 J arrival timeXh&w?, JXh1 JslackXhu=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D*:BJZ(LUT3=1)j7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsu]>}S㾍|A94<&>|>N=tho>,޳=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh,޳= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__9/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__9/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[7] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh&> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh|> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr; Jclock pessimismXhth ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhS㾐8 J arrival timeXh?, JXh1 JslackXhN=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D*:BJZ(LUT3=1)j7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuQ]>}Gᾍp_94<>p>=rho>%~=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh%~= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__9/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__9/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhp> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr; Jclock pessimismXhrh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhGᾐ8 J arrival timeXh?, JXh1 JslackXh= @ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_o_reg[1][13]/D*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuV%>}^ɾGA94<F>G?Y=n={=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR) @ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_o_reg[1][13]/D JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhF>o @ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_o_reg[1][13]/C JFDREXhzr; Jclock pessimismXhn @:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9/I0 JXhzr =9ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9/OProp_lut4_I0_O JLUT4Xhzr`P= ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9_n_0 Jnet (fo=6, routed)XhN6?i >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[24]_i_1__9/I1 JXhzr =9ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[24]_i_1__9/OProp_lut4_I1_O JLUT4XhzrP> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[20] Jnet (fo=1, routed)Xh)? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhS#? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]Setup_fdce_C_D JFDCEXhʽ, JXh9 J required timeXh B A8 J arrival timeXh%, JXh1 JslackXh7e@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/D*:BJZ(LUT4=2)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsuE@}33A) AI "@i\j?I "?33A=А=m@"ۙ?.7@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[4]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[4] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[4] Jnet (fo=6, routed)Xh9?i >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9/I0 JXhzr =9ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9/OProp_lut4_I0_O JLUT4Xhzr`P= ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9_n_0 Jnet (fo=6, routed)Xh4&?i >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[56]_i_1__9/I1 JXhzr =9ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[56]_i_1__9/OProp_lut4_I1_O JLUT4Xhzrrh> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[52] Jnet (fo=1, routed)XhI(> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhI "? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]Setup_fdce_C_D JFDCEXh̽, JXh9 J required timeXh) A8 J arrival timeXhY, JXh1 JslackXhm@/]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/CE*:BJZ(CARRY4=1 LUT4=1 LUT5=2)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsuU<@}33A B A)\/@Hm;?)\/?33A=А=o@S?zQ@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 Jnet (fo=16, routed)XhQ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/OProp_lut4_I0_O JLUT4Xhzr`P= _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 Jnet (fo=3, routed)Xh> d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/DI[1] JXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/O[3]Prop_carry4_DI[1]_O[3] JCARRY4Xhzf> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[3] Jnet (fo=11, routed)Xh&je? gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_3__9/I4 JXhzf fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_3__9/OProp_lut5_I4_O JLUT5Xhzr= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35] Jnet (fo=5, routed)Xhv'? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[31]_i_1__9/I2 JXhzr \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[31]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr`P= fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[6] Jnet (fo=4, routed)Xhhv? d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/CE JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhm;? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh)\/? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]Setup_fdce_C_CE JFDCEXh, JXh9 J required timeXh B A8 J arrival timeXhB, JXh1 JslackXho@/]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31]/CE*:BJZ(CARRY4=1 LUT4=1 LUT5=2)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsuU<@}33A B A)\/@Hm;?)\/?33A=А=o@S?zQ@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 Jnet (fo=16, routed)XhQ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/OProp_lut4_I0_O JLUT4Xhzr`P= _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 Jnet (fo=3, routed)Xh> d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/DI[1] JXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/O[3]Prop_carry4_DI[1]_O[3] JCARRY4Xhzf> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[3] Jnet (fo=11, routed)Xh&je? gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_3__9/I4 JXhzf fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_3__9/OProp_lut5_I4_O JLUT5Xhzr= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35] Jnet (fo=5, routed)Xhv'? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[31]_i_1__9/I2 JXhzr \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[31]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr`P= fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[6] Jnet (fo=4, routed)Xhhv? d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31]/CE JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhm;? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh)\/? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31]Setup_fdce_C_CE JFDCEXh, JXh9 J required timeXh B A8 J arrival timeXhB, JXh1 JslackXho@"]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1 LUT6=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsue'~@}33AAI "νm;?I "?33A=А=r@o??B@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 Jnet (fo=16, routed)XhQ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/OProp_lut4_I0_O JLUT4Xhzr`P= _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 Jnet (fo=3, routed)Xh> d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/DI[1] JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3]Prop_carry4_DI[1]_CO[3] JCARRY4Xhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 Jnet (fo=1, routed)Xh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/CI JXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3]Prop_carry4_CI_O[3] JCARRY4Xhzfu> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ? gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/I1 JXhzf fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/OProp_lut6_I1_O JLUT6Xhzr= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 Jnet (fo=41, routed)XhB? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/I2 JXhzr \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr`P= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] Jnet (fo=4, routed)Xh\V? d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/CE JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhm;? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhI "? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]Setup_fdce_C_CE JFDCEXhP, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhr@)"]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1 LUT6=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsue'~@}33AAI "νm;?I "?33A=А=r@o??B@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 Jnet (fo=16, routed)XhQ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/OProp_lut4_I0_O JLUT4Xhzr`P= _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 Jnet (fo=3, routed)Xh> d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/DI[1] JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3]Prop_carry4_DI[1]_CO[3] JCARRY4Xhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 Jnet (fo=1, routed)Xh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/CI JXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3]Prop_carry4_CI_O[3] JCARRY4Xhzfu> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ? gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/I1 JXhzf fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/OProp_lut6_I1_O JLUT6Xhzr= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 Jnet (fo=41, routed)XhB? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/I2 JXhzr \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr`P= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] Jnet (fo=4, routed)Xh\V? d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/CE JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhm;? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhI "? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]Setup_fdce_C_CE JFDCEXhP, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhr@)"]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1 LUT6=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsue'~@}33AAI "νm;?I "?33A=А=r@o??B@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 Jnet (fo=16, routed)XhQ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/OProp_lut4_I0_O JLUT4Xhzr`P= _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 Jnet (fo=3, routed)Xh> d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/DI[1] JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3]Prop_carry4_DI[1]_CO[3] JCARRY4Xhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 Jnet (fo=1, routed)Xh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/CI JXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3]Prop_carry4_CI_O[3] JCARRY4Xhzfu> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ? gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/I1 JXhzf fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/OProp_lut6_I1_O JLUT6Xhzr= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 Jnet (fo=41, routed)XhB? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/I2 JXhzr \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr`P= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] Jnet (fo=4, routed)Xh\V? d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/CE JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhm;? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhI "? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]Setup_fdce_C_CE JFDCEXhP, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhr@)"]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1 LUT6=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsue'~@}33AAI "νm;?I "?33A=А=r@o??B@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 Jnet (fo=16, routed)XhQ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/OProp_lut4_I0_O JLUT4Xhzr`P= _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 Jnet (fo=3, routed)Xh> d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/DI[1] JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3]Prop_carry4_DI[1]_CO[3] JCARRY4Xhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 Jnet (fo=1, routed)Xh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/CI JXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3]Prop_carry4_CI_O[3] JCARRY4Xhzfu> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] Jnet (fo=11, routed)XhZ? gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/I1 JXhzf fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/OProp_lut6_I1_O JLUT6Xhzr= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 Jnet (fo=41, routed)XhB? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/I2 JXhzr \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr`P= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] Jnet (fo=4, routed)Xh\V? d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/CE JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhm;? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhI "? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]Setup_fdce_C_CE JFDCEXhP, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhr@)ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D*:BJZ(LUT4=2)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsu|@}33A\! AI "@i\j?I "?33A=А=:t@?P(0@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[9]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[9] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[11] Jnet (fo=5, routed)XhV?i >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[99]_i_9__9/I1 JXhzr =9ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[99]_i_9__9/OProp_lut4_I1_O JLUT4Xhzr@= ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[99]_i_9__9_n_0 Jnet (fo=6, routed)XhXM%?i >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[59]_i_2__9/I1 JXhzr =9ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[59]_i_2__9/OProp_lut4_I1_O JLUT4Xhzrt> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[55] Jnet (fo=1, routed)Xh? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhI "? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]Setup_fdce_C_D JFDCEXhaн, JXh9 J required timeXh\! A8 J arrival timeXhƛ, JXh1 JslackXh:t@]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1 LUT6=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsu|@}33A+AS#Ľm;?S#?33A=А=pu@kt?k?@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_3 rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 Jnet (fo=16, routed)XhQ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/OProp_lut4_I0_O JLUT4Xhzr`P= _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 Jnet (fo=3, routed)Xh> d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/DI[1] JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3]Prop_carry4_DI[1]_CO[3] JCARRY4Xhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 Jnet (fo=1, routed)Xh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/CI JXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[1]Prop_carry4_CI_O[1] JCARRY4Xhzf)> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[5] Jnet (fo=11, routed)Xh? gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[47]_i_3__9/I2 JXhzf fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[47]_i_3__9/OProp_lut6_I2_O JLUT6Xhzrl= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[43] Jnet (fo=41, routed)Xh=? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[27]_i_1__9/I0 JXhzr \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[27]_i_1__9/OProp_lut5_I0_O JLUT5Xhzr`P= fbngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[5] Jnet (fo=4, routed)Xh{? d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/CE JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhm;? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhS#? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]Setup_fdce_C_CE JFDCEXh, JXh9 J required timeXh+A8 J arrival timeXhzʕ, JXh1 JslackXhpu@)  rxWordclkl8_4 rxWordclkl8_4!)]_ff@1]_ff @9A]_ff@I]_ff @et@hq}=O]@HH  rise - rise rise - rise  95ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C>:ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu3c>}֣M=`e<}?>M?=Ob=m=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})h(rising edge-triggered cell SRL16E clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=| <8ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] Jnet (fo=2, routed)Xhm=o >:ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D JSRL16EXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh}?>h 95ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhM?q @} ܾp= >p= ?=v=`=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xhp= ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh ܾ8 J arrival timeXh ?, JXh1 JslackXh=u ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu >}(ܾ > ?=v=`=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in Jnet (fo=1057, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh(ܾ8 J arrival timeXh ?, JXh1 JslackXh= @ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[1][11]/D*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsuy@>} 뾍~ _94<>~ ?=z=%~=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) @ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[1][11]/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>o @ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[1][11]/C JFDREXhzr; Jclock pessimismXhz @ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[7][10]/D*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsuB>}뾍 A94<ˡ> ?=z=aq=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) @ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[7][10]/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhˡ>o @ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[7][10]/C JFDREXhzr; Jclock pessimismXhz @}gf澍:_94<J >:?a=to>z=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xhz= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__10/I2 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__10/OProp_lut3_I2_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhJ > ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh:? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr; Jclock pessimismXht ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhgf澐8 J arrival timeXhr?, JXh1 JslackXha= ?;ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[6][1]/CA=ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1]/D*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu4[>}~ <\=ɡ>~ ?N===f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) ?;ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[6][1]/Q Prop_fdce_C_Q JFDCEXhzr= B>ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg_n_0_[6][1] Jnet (fo=2, routed)Xh=p A=ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1]/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhɡ>n ?;ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[6][1]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh~ ?p A=ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1]/C JFDREXhzr; Jclock pessimismXh ?;ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1] Hold_fdre_C_D JFDREXhq=, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXhN=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D*:BJZ(LUT3=1)j7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsutXD>}پ_94<i>?tH=no> =f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh = ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__10/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__10/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhi> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr; Jclock pessimismXhn ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhپ8 J arrival timeXhRt ?, JXh1 JslackXhtH=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D*:BJZ(LUT3=1)j7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu'f>}r辍[`e<i>?57=*\o>t=f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q Prop_fdce_C_Q JFDCEXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)Xht= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__10/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__10/OProp_lut3_I0_O JLUT3XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[3] Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhi> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr; Jclock pessimismXh*\ ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXhr辐8 J arrival timeXh>?, JXh1 JslackXh57= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C)%ngFEC/SFP_GEN[8].rx_data_reg[8][34]/D*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsuf|N>}ھJ <\=i>J ?>=,=f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q Prop_fdre_C_Q JFDREXhzr=b "ngFEC/GBT_rx_data[12]_1399[34] Jnet (fo=1, routed)Xh,=X )%ngFEC/SFP_GEN[8].rx_data_reg[8][34]/D JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xhi> ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrb ngFEC/gbtbank4_l8_112_n_187 Jnet (fo=1057, routed)XhJ ?X )%ngFEC/SFP_GEN[8].rx_data_reg[8][34]/C JFDREXhzr; Jclock pessimismXhh '#ngFEC/SFP_GEN[8].rx_data_reg[8][34] Hold_fdre_C_D JFDREXh=, JXh9 J required timeXhھ8 J arrival timeXhN ?, JXh1 JslackXh>ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D*:BJZ(LUT4=2)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu@}33AY A1h*'l?1?33A=А=t@x?=)3@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[6]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[6] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[6] Jnet (fo=6, routed)Xh?j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/I0 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/OProp_lut4_I0_O JLUT4XhzrL= @:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[90]_i_1__10/OProp_lut4_I1_O JLUT4Xhzr)\> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[86] Jnet (fo=1, routed)Xhq> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]Setup_fdce_C_D JFDCEXhB`彐, JXh9 J required timeXhY A8 J arrival timeXhw, JXh1 JslackXht@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]/D*:BJZ(LUT4=2)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu5z@}33AEH A&1l*'l?&1?33A=А=-{@?g.@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[6]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[6] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[6] Jnet (fo=6, routed)Xh?j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/I0 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/OProp_lut4_I0_O JLUT4XhzrL= @:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[26]_i_1__10/OProp_lut4_I1_O JLUT4XhzrNb> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[22] Jnet (fo=1, routed)Xhe> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]/D JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]Setup_fdce_C_D JFDCEXhE, JXh9 J required timeXhEH A8 J arrival timeXh, JXh1 JslackXh-{@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]/D*:BJZ(LUT4=2)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuo@}33AEH A&1l*'l?&1?33A=А=) @X?P#@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[6]&Prop_gtxe2_channel_RXUSRCLK2_RXDATA[6] J GTXE2_CHANNELXhzr&? JFngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[6] Jnet (fo=6, routed)Xh?j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/I0 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/OProp_lut4_I0_O JLUT4XhzrL= @:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[58]_i_1__10/OProp_lut4_I1_O JLUT4XhzrV> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[54] Jnet (fo=1, routed)Xh`> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]/D JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]Setup_fdce_C_D JFDCEXhE, JXh9 J required timeXhEH A8 J arrival timeXhb, JXh1 JslackXh) @ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23]/D*:BJZ(LUT4=1 LUT5=1)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsueh@}33AZ A1i*'l?1?33A=А= @L7?@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[19] Jnet (fo=8, routed)XhW?j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10/I3 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10/OProp_lut5_I3_O JLUT5XhzrD= @j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[23]_i_2__10/I1 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[23]_i_2__10/OProp_lut4_I1_O JLUT4Xhzr)\> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[19] Jnet (fo=1, routed)Xh> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23]/D JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23]Setup_fdce_C_D JFDCEXhS㽐, JXh9 J required timeXhZ A8 J arrival timeXh, JXh1 JslackXh @ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63]/D*:BJZ(LUT4=1 LUT5=1)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuGe@}33As A1h*'l?1?33A=А=]@x?X@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1])Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1] J GTXE2_CHANNELXhzr&? KGngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[19] Jnet (fo=8, routed)XhW?j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10/I3 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10/OProp_lut5_I3_O JLUT5XhzrD= @j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[63]_i_2__10/I1 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[63]_i_2__10/OProp_lut4_I1_O JLUT4Xhzrrh> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[59] Jnet (fo=1, routed)Xh\> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63]/D JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63]Setup_fdce_C_D JFDCEXhS㽐, JXh9 J required timeXhs A8 J arrival timeXh, JXh1 JslackXh]@hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]/Cc_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]/D*:BJZ(CARRY4=1 LUT4=3)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu:p@}33A A&1=`e|??&1?33A=А=@:o?LB4@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]/Q Prop_fdce_C_Q JFDCEXhzf> hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]_0 Jnet (fo=37, routed)Xh=? _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_14__10/I2 JXhzf ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_14__10/OProp_lut4_I2_O JLUT4XhzrY= `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_14__10_n_0 Jnet (fo=3, routed)Xhlzi> eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/DI[1] JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/O[2]Prop_carry4_DI[1]_O[2] JCARRY4Xhzr}?>w 62ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg01_8[2] Jnet (fo=65, routed)XhL?j ?;ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[97]_i_3__10/I2 JXhzr >:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[97]_i_3__10/OProp_lut4_I2_O JLUT4Xhzr%> @:ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[57]_i_1__10/OProp_lut4_I1_O JLUT4Xhzrz> gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[53] Jnet (fo=1, routed)Xh&> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]/D JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK Jnet (fo=1057, routed)Xh|?? hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]Setup_fdce_C_D JFDCEXhԽ, JXh9 J required timeXh A8 J arrival timeXh , JXh1 JslackXh@AZhdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1 LUT6=1)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu2Xk@}33A A&1=`e|??&1?33A=А=@Sc?42@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrq> hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh->? _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/I1 JXhzr ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/OProp_lut4_I1_O JLUT4Xhzrl= `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 Jnet (fo=1, routed)XhX> eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/DI[2] JXhzr eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3]Prop_carry4_DI[2]_CO[3] JCARRY4Xhzr^I> c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 Jnet (fo=1, routed)Xh b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/CI JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1]Prop_carry4_CI_O[1] JCARRY4Xhzf)> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] Jnet (fo=11, routed)Xhj? hdngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/I2 JXhzf gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/OProp_lut6_I2_O JLUT6Xhzrl= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 Jnet (fo=40, routed)Xh ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[67]_i_1__10/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[67]_i_1__10/OProp_lut5_I0_O JLUT5Xhzr 0= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[15] Jnet (fo=4, routed)Xh{> d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65]/CE JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK Jnet (fo=1057, routed)Xh|?? hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXh@(ZhdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1 LUT6=1)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu2Xk@}33A A&1=`e|??&1?33A=А=@Sc?42@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrq> hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh->? _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/I1 JXhzr ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/OProp_lut4_I1_O JLUT4Xhzrl= `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 Jnet (fo=1, routed)XhX> eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/DI[2] JXhzr eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3]Prop_carry4_DI[2]_CO[3] JCARRY4Xhzr^I> c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 Jnet (fo=1, routed)Xh b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/CI JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1]Prop_carry4_CI_O[1] JCARRY4Xhzf)> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] Jnet (fo=11, routed)Xhj? hdngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/I2 JXhzf gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/OProp_lut6_I2_O JLUT6Xhzrl= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 Jnet (fo=40, routed)Xh ? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[67]_i_1__10/I0 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[67]_i_1__10/OProp_lut5_I0_O JLUT5Xhzr 0= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[15] Jnet (fo=4, routed)Xh{> d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67]/CE JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK Jnet (fo=1057, routed)Xh|?? hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh A8 J arrival timeXh, JXh1 JslackXh@(ShdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68]/CE*:BJZ(CARRY4=2 LUT4=1 LUT6=2)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuAOh@}33A A1/]|??1?33A=А=.@Sc?Cz/@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrq> hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh->? _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/I1 JXhzr ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/OProp_lut4_I1_O JLUT4Xhzrl= `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 Jnet (fo=1, routed)XhX> eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/DI[2] JXhzr eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3]Prop_carry4_DI[2]_CO[3] JCARRY4Xhzr^I> c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 Jnet (fo=1, routed)Xh b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/CI JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1]Prop_carry4_CI_O[1] JCARRY4Xhzf)> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] Jnet (fo=11, routed)Xhj? hdngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/I2 JXhzf gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/OProp_lut6_I2_O JLUT6Xhzrl= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 Jnet (fo=40, routed)XhJ=*? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[71]_i_1__10/I3 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[71]_i_1__10/OProp_lut6_I3_O JLUT6Xhzr 0= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[16] Jnet (fo=4, routed)XhbY> d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68]/CE JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK Jnet (fo=1057, routed)Xh|?? hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh A8 J arrival timeXh>, JXh1 JslackXh.@(ShdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69]/CE*:BJZ(CARRY4=2 LUT4=1 LUT6=2)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuAOh@}33A A1/]|??1?33A=А=.@Sc?Cz/@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow rxWordclkl8_4 rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrq> hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 Jnet (fo=23, routed)Xh->? _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/I1 JXhzr ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/OProp_lut4_I1_O JLUT4Xhzrl= `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 Jnet (fo=1, routed)XhX> eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/DI[2] JXhzr eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3]Prop_carry4_DI[2]_CO[3] JCARRY4Xhzr^I> c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 Jnet (fo=1, routed)Xh b^ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/CI JXhzr d`ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1]Prop_carry4_CI_O[1] JCARRY4Xhzf)> ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] Jnet (fo=11, routed)Xhj? hdngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/I2 JXhzf gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/OProp_lut6_I2_O JLUT6Xhzrl= YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 Jnet (fo=40, routed)XhJ=*? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[71]_i_1__10/I3 JXhzr ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[71]_i_1__10/OProp_lut6_I3_O JLUT6Xhzr 0= gcngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[16] Jnet (fo=4, routed)XhbY> d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69]/CE JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK Jnet (fo=1057, routed)Xh|?? hdngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh A8 J arrival timeXh>, JXh1 JslackXh.@( ttc_mgt_xpoint_attc_mgt_xpoint_a!)!~@1!~ @9A!~@I!~ @e@hq} 0>ea@-KK rise - rise rise - rise  &ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>}fՄǷRp?Ƿ? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhA> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXhfՄ8 J arrival timeXhٚ?, JXh1 JslackXh 0>>ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>}q?? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhS> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXh 0>&ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>}1ᶿ o?? 0>p>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh)\> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhp ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh18 J arrival timeXh5?, JXh1 JslackXh 0>&ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>}1ᶿ o?? 0>p>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh)\> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhp ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh18 J arrival timeXh5?, JXh1 JslackXh 0>>ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>}}bn?b? 0>>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhO> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh"> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh}8 J arrival timeXh?, JXh1 JslackXh 0>&ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>},緿Fp?? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhn> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh,8 J arrival timeXhD?, JXh1 JslackXh 0>>ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>}L3p?L? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhrh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhw> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXh 0>>ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsu>}n?? 0>p>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhَ> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh(> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhp ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXh 0>BngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsuO>}bn?b? -2>O>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzrO> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhO> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh"> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr; Jclock pessimismXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31Hold_srlc32e_CLK_D JSRLC32EXha=, JXh9 J required timeXh8 J arrival timeXhlV?, JXh1 JslackXh -2>&ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D*:BJZj=ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000nsuO>}7ǷRp?Ƿ?-2>vO>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzrO> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh,B> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh6a> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhA> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31Hold_srlc32e_CLK_D JSRLC32EXha=, JXh9 J required timeXh78 J arrival timeXhV}?, JXh1 JslackXh-2>}ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SA@AW'l@W'@SA=А=@ ۉ??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhF? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXh ۉ?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh@A8 J arrival timeXhtd, JXh1 JslackXh@]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SA4AA(Hm@(@SA=А=@n=??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhK? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhC ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXhn=?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh4AA8 J arrival timeXh$ז, JXh1 JslackXh@]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SAAA(m@(@SA=А=@??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhx ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhAA8 J arrival timeXhj, JXh1 JslackXh@}ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SA AA (q m@ (@SA=А=@??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhk? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhL7 ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh AA8 J arrival timeXh8, JXh1 JslackXh@]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SAAA(m@(@SA=А=@??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhx ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhAA8 J arrival timeXhj, JXh1 JslackXh@]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SA4AA(Hm@(@SA=А=@n=??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhK? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhC ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXhn=?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh4AA8 J arrival timeXh$ז, JXh1 JslackXh@}ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SA,AAn(m@n(@SA=А=@n=??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXhn=?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh,AA8 J arrival timeXhƖ, JXh1 JslackXh@}ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu?}SAZIAA(3n@(@SA=А=@3^??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_attc_mgt_xpoint_attc_mgt_xpoint_a#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhM "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut1IbufdsAGtxe2/I JXhzrr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh$*? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhu? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_a rise edge)XhzrSAG ttc_mgt_xpoint_a_p JXhzrN ttc_mgt_xpoint_a_p J net (fo=0)XhJ "ttc_mgt_xpoint_a_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_a_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut1IbufdsAGtxe2/I JXhr ngFEC/cdceOut1IbufdsAGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=8, routed)Xh+ ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhI ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXh3^?= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhZIAA8 J arrival timeXh, JXh1 JslackXh@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLKngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000nsu <ea@_MM fall - rise rise - rise  8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}6+Igq?+I? 0>>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh68 J arrival timeXh:?, JXh1 JslackXh 0>PngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}2淿Sp?? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhA> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh28 J arrival timeXhJ?, JXh1 JslackXh 0>8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}6+Igq?+I? 0>>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh68 J arrival timeXh:?, JXh1 JslackXh 0>PngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}p?? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhn> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXh 0>8ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}ιxr?x? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhS> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXhι8 J arrival timeXh罛?, JXh1 JslackXh 0>PngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}p?? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhn> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXh 0>8ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}\Q}Jo?}? 0>p>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh)\> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhp ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh\Q8 J arrival timeXhtU?, JXh1 JslackXh 0>PngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>} rA"0o?A"? 0>p>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh;ߏ> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh/> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhp ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh r8 J arrival timeXh9v?, JXh1 JslackXh 0>8ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}2淿Sp?? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhA> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh28 J arrival timeXhJ?, JXh1 JslackXh 0>PngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D*:BJZj=ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000nsu>}2淿Sp?? 0>v>l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Fastttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31Prop_srlc32e_CLK_Q31 JSRLC32EXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xh!+C> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrj< ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhb> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzrQ8= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhA> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK JSRLC32EXhzr; Jclock pessimismXhv ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32Hold_srlc32e_CLK_D JSRLC32EXh=, JXh9 J required timeXh28 J arrival timeXhJ?, JXh1 JslackXh 0> ngFEC/phmon/neg_cnt_reg[1]/C ngFEC/phmon/pos_cnt_reg[1]/D*:BJZ(LUT5=1)j=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c fall@4.167nsuGN?}S@Fv?Ab.̼s@S@b.@SA=А= 1@l?>:_?j(falling edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)d ngFEC/phmon/neg_cnt_reg[1]/Q Prop_fdre_C_Q JFDREXhzrV>Z ngFEC/phmon/neg_cnt[1] Jnet (fo=4, routed)Xhn?L !ngFEC/phmon/pos_cnt[1]_i_1/I3 JXhzre ngFEC/phmon/pos_cnt[1]_i_1/OProp_lut5_I3_O JLUT5Xhzr'1>b "ngFEC/phmon/pos_cnt[1]_i_1_n_0 Jnet (fo=1, routed)XhO>O ngFEC/phmon/pos_cnt_reg[1]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c fall edge)XhzfS@G ttc_mgt_xpoint_c_p JXhzfN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzff "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzfa !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzfr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzfR@i ($ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 Jnet (fo=17, routed)Xhbd*?[ 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/I JXhzft 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O Prop_bufh_I_O JBUFHXhzf=r 2.ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf Jnet (fo=7, routed)Xh/?O ngFEC/phmon/neg_cnt_reg[1]/C JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?i ($ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 Jnet (fo=17, routed)XhI?X 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/I JXht 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O Prop_bufh_I_O JBUFHXhzr+=r 2.ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf Jnet (fo=7, routed)XhM"?O ngFEC/phmon/pos_cnt_reg[1]/C JFDREXhzr; Jclock pessimismXhl?= Jclock uncertaintyXh` ngFEC/phmon/pos_cnt_reg[1]Setup_fdre_C_D JFDREXhx齐, JXh9 J required timeXhFv?A8 J arrival timeXh>, JXh1 JslackXh 1@ ngFEC/phmon/neg_cnt_reg[1]/C ngFEC/phmon/pos_cnt_reg[0]/D*:BJZ(LUT4=1)j=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c fall@4.167nsur?}S@cAAb.̼s@S@b.@SA=А=w<@l?>[?j(falling edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)d ngFEC/phmon/neg_cnt_reg[1]/Q Prop_fdre_C_Q JFDREXhzrV>Z ngFEC/phmon/neg_cnt[1] Jnet (fo=4, routed)Xh[?L !ngFEC/phmon/pos_cnt[0]_i_1/I2 JXhzre ngFEC/phmon/pos_cnt[0]_i_1/OProp_lut4_I2_O JLUT4Xhzrl=b "ngFEC/phmon/pos_cnt[0]_i_1_n_0 Jnet (fo=1, routed)XhO ngFEC/phmon/pos_cnt_reg[0]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c fall edge)XhzfS@G ttc_mgt_xpoint_c_p JXhzfN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzff "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzfa !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzfr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzfR@i ($ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 Jnet (fo=17, routed)Xhbd*?[ 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/I JXhzft 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O Prop_bufh_I_O JBUFHXhzf=r 2.ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf Jnet (fo=7, routed)Xh/?O ngFEC/phmon/neg_cnt_reg[1]/C JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?i ($ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 Jnet (fo=17, routed)XhI?X 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/I JXht 0,ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O Prop_bufh_I_O JBUFHXhzr+=r 2.ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf Jnet (fo=7, routed)XhM"?O ngFEC/phmon/pos_cnt_reg[0]/C JFDREXhzr; Jclock pessimismXhl?= Jclock uncertaintyXh` ngFEC/phmon/pos_cnt_reg[0]Setup_fdre_C_D JFDREXh+=, JXh9 J required timeXhcAA8 J arrival timeXhƤ, JXh1 JslackXhw<@ongFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SASMAA(n@(@SA=А=@5^??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhu? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhI ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXh5^?= Jclock uncertaintyXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhSMAA8 J arrival timeXh, JXh1 JslackXh@ongFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SAAA,(*m@,(@SA=А=@??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhx ? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhAA8 J arrival timeXh], JXh1 JslackXh@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SAAA(=(;m@(=(@SA=А=@??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh}?? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xh^ ? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXh?= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhAA8 J arrival timeXh, JXh1 JslackXh@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SASMAA(n@(@SA=А=@5^??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)Xhu? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhI ? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXh5^?= Jclock uncertaintyXh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXhSMAA8 J arrival timeXh, JXh1 JslackXh@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SA8AAw(/m@w(@SA=А=@p=??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhK? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhC ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXhp=?= Jclock uncertaintyXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh8AA8 J arrival timeXhߖ, JXh1 JslackXh@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SA8AAw(/m@w(@SA=А=@p=??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhK? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhC ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXhp=?= Jclock uncertaintyXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh8AA8 J arrival timeXhߖ, JXh1 JslackXh@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SA8AAw(/m@w(@SA=А=@p=??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhK? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhC ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C JFDREXhzr; Jclock pessimismXhp=?= Jclock uncertaintyXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh8AA8 J arrival timeXhߖ, JXh1 JslackXh@ongFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D*:BJZj=ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000nsu?}SA8AAw(/m@w(@SA=А=@p=??l(rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})i(rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns})Slowttc_mgt_xpoint_cttc_mgt_xpoint_cttc_mgt_xpoint_c#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/QProp_srlc32e_CLK_Q JSRLC32EXhzr? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D JFDREXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhM "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhzrf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9K ngFEC/cdceOut0IbufdsCGtxe2/I JXhzrr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)Xhbd*? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhK? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK JSRLC32EXhzr Q J"(clock ttc_mgt_xpoint_c rise edge)XhzrSAG ttc_mgt_xpoint_c_p JXhzrN ttc_mgt_xpoint_c_p J net (fo=0)XhJ "ttc_mgt_xpoint_c_p_IBUF_inst/I JXhf "ttc_mgt_xpoint_c_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzra !ngFEC/ttc_mgt_xpoint_c_p_IBUF Jnet (fo=1, routed)Xhd\9H ngFEC/cdceOut0IbufdsCGtxe2/I JXhr ngFEC/cdceOut0IbufdsCGtxe2/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in Jnet (fo=17, routed)XhI? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I JXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O Prop_bufh_I_O JBUFHXhzr+= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 Jnet (fo=9, routed)XhC ? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C JFDREXhzr; Jclock pessimismXhp=?= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]Setup_fdre_C_D JFDREXho=, JXh9 J required timeXh8AA8 J arrival timeXhߖ, JXh1 JslackXh@ txWordclkl12_1txWordclkl12_1!)]_ff@1]_ff @9A]_ff@I]_ff @eXL@hq}=O]@NN rise - rise rise - rise  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu >}Y9T'1H??=~=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh'1H? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh~ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhY9T8 J arrival timeXhjo?, JXh1 JslackXh= QMngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu >}q=J/}?5>?/}?=t{=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) QMngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= KGngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= QMngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh?5>? QMngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh/}? QMngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXht{ OKngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhq=J8 J arrival timeXhe?, JXh1 JslackXh=5 FBngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu#>} K}>?}?^=l{=:^v=g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) FBngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @?u FBngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrz 84ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xh}?u FBngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhl{ D@ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh K8 J arrival timeXhYg?, JXh1 JslackXh^= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu#>}S ׃G? ׃?^=~=:^v=g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh:^v= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)XhG? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh ׃? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh~ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhS8 J arrival timeXhp?, JXh1 JslackXh^= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C|ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu1>}M"ELP?EL?>S=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhP? |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhEL? |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhS ~zngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXhM"8 J arrival timeXh9C?, JXh1 JslackXh>;zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/CzvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D*:BJZ(LUT6=1)j9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu@[>}&ILK?IL?L>S >k=g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr5^= `\ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/address[1] Jnet (fo=42, routed)Xhk= {wngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1/I0 JXhzr zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1/OProp_lut6_I0_O JLUT6Xhzr+= |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1_n_0 Jnet (fo=1, routed)Xh zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhK? zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhIL? zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C JFDCEXhzr; Jclock pessimismXhS xtngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh&8 J arrival timeXh;N?, JXh1 JslackXhL>*IzvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C|xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D*:BJZ(LUT6=1)j9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsup>}p=*IL`e<K?IL? %>ӡEo>2|=g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/Q Prop_fdce_C_Q JFDCEXhzr= `\ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/address[2] Jnet (fo=21, routed)Xh2|= }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1/I4 JXhzr |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1/OProp_lut6_I4_O JLUT6XhzrA`< ~zngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhK? zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhIL? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C JFDCEXhzr; Jclock pessimismXhӡE zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhp=*8 J arrival timeXhS?, JXh1 JslackXh %>ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[96]/C}yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D*:BJZ(LUT6=1)j9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsup>}E633St=.?33S?1>&1>=g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[96]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[16] Jnet (fo=1, routed)Xh= ~zngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1/I0 JXhzr }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1/OProp_lut6_I0_O JLUT6XhzrA`< {ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh.? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[96]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh33S? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C JFDCEXhzr; Jclock pessimismXh&1 {wngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhE68 J arrival timeXhfb?, JXh1 JslackXh1> -)ngFEC/g_pm[2].phase_mon/inh_cntr_reg[3]/C-)ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4]/D*:BJZ(LUT6=1)j9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsuCw>}Nv~e;??v~?9>|o>b=g(rising edge-triggered cell FDPE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR)q -)ngFEC/g_pm[2].phase_mon/inh_cntr_reg[3]/Q Prop_fdpe_C_Q JFDPEXhzr=p 0,ngFEC/g_pm[2].phase_mon/inh_cntr_reg_n_0_[3] Jnet (fo=2, routed)Xhb=\ 1-ngFEC/g_pm[2].phase_mon/inh_cntr[4]_i_2__0/I4 JXhzru 0,ngFEC/g_pm[2].phase_mon/inh_cntr[4]_i_2__0/OProp_lut6_I4_O JLUT6XhzrA`<h ($ngFEC/g_pm[2].phase_mon/p_0_in__0[4] Jnet (fo=1, routed)Xh\ -)ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4]/D JFDPEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[2].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhe;??\ -)ngFEC/g_pm[2].phase_mon/inh_cntr_reg[3]/C JFDPEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[2].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhv~?\ -)ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4]/C JFDPEXhzr; Jclock pessimismXh|l +'ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4] Hold_fdpe_C_D JFDPEXhu=, JXh9 J required timeXhN8 J arrival timeXhQ }?, JXh1 JslackXh9>&uqngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/CzvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/D*:BJZ(LUT5=1)j9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsurK>}O-ILA94<K?IL?>>@HP>-=g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_1txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) uqngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/Q Prop_fdce_C_Q JFDCEXhzr= [WngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/ready Jnet (fo=3, routed)Xh-= {wngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[1]_i_1/I3 JXhzr zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[1]_i_1/OProp_lut5_I3_O JLUT5Xhzr< |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[1]_i_1_n_0 Jnet (fo=1, routed)Xh zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/D JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhK? uqngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhIL? zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C JFDCEXhzr; Jclock pessimismXh@H xtngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1] Hold_fdce_C_D JFDCEXh=, JXh9 J required timeXhO-8 J arrival timeXh\?, JXh1 JslackXh>>: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsu/@}33AA俭y>V??33A=А=XL@T<Zd>?p@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[4] Jnet (fo=1, routed)Xh?p@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhV? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[4] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhr-, JXh1 JslackXhXL@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsu~@}33AA俭Vy>??33A=А=!z@T<Zd>mp@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] Jnet (fo=1, routed)Xhmp@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh!z@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsuȏz@}33AA俭c>v??33A=А=4@T<>Ri@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] Jnet (fo=1, routed)XhRi@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhv? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh4@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsuqx@}33AA俭Vy>??33A=А=҉@T<Zd>ϼi@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] Jnet (fo=1, routed)Xhϼi@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh҉@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsuw@}33AA俭Vy>??33A=А= @T<Zd>Gi@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] Jnet (fo=1, routed)XhGi@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh7l, JXh1 JslackXh @V }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsuNs@}33AA俭k>v??33A=А=q@T<Zd>e@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[19] Jnet (fo=1, routed)Xhe@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhv? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhY, JXh1 JslackXhq@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsu@r@}33AA俭Vy>??33A=А=Gt@T<Zd>yd@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] Jnet (fo=1, routed)Xhyd@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhGt@A }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsuq@}33AA俭c>v??33A=А=Z@T<>mo`@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[15] Jnet (fo=1, routed)Xhmo`@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhv? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[13] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh#, JXh1 JslackXhZ@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsu3 n@}33AA俭Vy>??33A=А=Mώ@T<Zd>_@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[0] Jnet (fo=1, routed)Xh_@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh}, JXh1 JslackXhMώ@S }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1]*:BJZj9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsuNk@}33AA俭y>V??33A=А=<@T<Zd>S ]@g(rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_1txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] Jnet (fo=1, routed)XhS ]@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhV? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C JFDCEXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh<, JXh1 JslackXh<@ txWordclkl12_2txWordclkl12_2!)]_ff@1]_ff @9A]_ff@I]_ff @e@hq}=O]@OO rise - rise rise - rise  QMngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu >}K7ˡeC+?ˡe?=xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) QMngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= KGngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= QMngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)XhC+? QMngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xhˡe? QMngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhxi OKngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhK78 J arrival timeXhR?, JXh1 JslackXh=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[93]/C}yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/D*:BJZ(LUT6=1)j9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsuU>}AbA94<9(?b?]=/]o>=g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[93]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[13] Jnet (fo=1, routed)Xh= }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[13]_i_1__0/I0 JXhzr |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[13]_i_1__0/OProp_lut6_I0_O JLUT6XhzrA`< ~ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[13]_i_1__0_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/D JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh9(? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[93]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhb? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C JFDCEXhzr; Jclock pessimismXh/] {wngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhA8 J arrival timeXhr^?, JXh1 JslackXh]= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C|ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu#>}6 c)? c?^=lg=:^v=g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh:^v= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh)? |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh c? |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhlg ~zngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh68 J arrival timeXheR?, JXh1 JslackXh^=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C|xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D*:BJZ(LUT6=1)j9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu<c>}J BMbT<r(?Mb?5=Zo>ݿ=g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[7] Jnet (fo=1, routed)Xhݿ= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__0/I0 JXhzr {ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__0/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__0_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhr(? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhMb? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzr; Jclock pessimismXhZ zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhJ B8 J arrival timeXh2a?, JXh1 JslackXh5= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu1>}hff [? ?>P7=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh[? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhP7 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXhhff8 J arrival timeXh?, JXh1 JslackXh> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu1>}hff[??>:=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh[? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXhhff8 J arrival timeXh?, JXh1 JslackXh>5 FBngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu1>},6$f+?$f?>xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) FBngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[102]/C|xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D*:BJZ(LUT6=1)j9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsuit>}\Bb[`e<9(?b? >Z>Pѽ=g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[102]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data5[2] Jnet (fo=1, routed)XhPѽ= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__0/I2 JXhzr {ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__0/OProp_lut6_I2_O JLUT6XhzrA`< }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__0_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh9(? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[102]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhb? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C JFDCEXhzr; Jclock pessimismXhZ zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh\B8 J arrival timeXhe?, JXh1 JslackXh >ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[83]/C|xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/D*:BJZ(LUT6=1)j9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu_d>}m;Sc[`e<(?Sc?@>"[o>=g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[83]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[3] Jnet (fo=1, routed)Xh= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[3]_i_1__0/I0 JXhzr {ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[3]_i_1__0/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[3]_i_1__0_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/D JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh(? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[83]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhSc? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C JFDCEXhzr; Jclock pessimismXh"[ zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhm;8 J arrival timeXha?, JXh1 JslackXh@>ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/C}yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/D*:BJZ(LUT6=1)j9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu˄>}AbA94<9(?b?*>/]o>=g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_2txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[14] Jnet (fo=1, routed)Xh= }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[14]_i_1__0/I0 JXhzr |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[14]_i_1__0/OProp_lut6_I0_O JLUT6XhzrA`< ~ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[14]_i_1__0_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/D JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh9(? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhb? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/C JFDCEXhzr; Jclock pessimismXh/] {wngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhA8 J arrival timeXhlh?, JXh1 JslackXh*>: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsuV@}33A7A俭+> ??33A=А=@ 0=>9u@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] Jnet (fo=1, routed)Xh9u@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh ? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXhα, JXh1 JslackXh@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsu#@}33A7A俭o>"??33A=А=@ 0=>du@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] Jnet (fo=1, routed)Xhdu@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh"? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXhı, JXh1 JslackXh@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsuK'@}33A7A俭o>"??33A=А=@ 0=Zd>r@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[0] Jnet (fo=1, routed)Xhr@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh"? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXh, JXh1 JslackXh@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsu?}@}33A7A俭a%>C??33A=А=@ 0=Zd>o@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] Jnet (fo=1, routed)Xho@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhC? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXh, JXh1 JslackXh@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsu{}@}33A7A俭+> ??33A=А=L+@ 0=>tl@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[5] Jnet (fo=1, routed)Xhtl@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh ? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[5] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXhAD, JXh1 JslackXhL+@A }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsuh{@}33A7A俭o>"??33A=А=$Ѕ@ 0=Zd>gm@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[15] Jnet (fo=1, routed)Xhgm@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh"? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[13] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXhi, JXh1 JslackXh$Ѕ@A }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsu{@}33A7A俭1>??33A=А=<@ 0=>yqj@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] Jnet (fo=1, routed)Xhyqj@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXh2, JXh1 JslackXh<@> }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsu!z@}33A7A俭1>??33A=А=箆@ 0=>i@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[11] Jnet (fo=1, routed)Xhi@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[9] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXh, JXh1 JslackXh箆@O |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsu?y@}33A7A俭o>"??33A=А=@ 0=>Nh@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] Jnet (fo=1, routed)XhNh@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh"? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXhh, JXh1 JslackXh@R |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0]*:BJZj9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsuy@}33A7A俭a%>C??33A=А=@ 0=Zd>ej@g(rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_2txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] Jnet (fo=1, routed)Xhej@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhC? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C JFDCEXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7A8 J arrival timeXhY, JXh1 JslackXh@ txWordclkl12_3txWordclkl12_3!)]_ff@1]_ff @9A]_ff@I]_ff @e4@hq}=O]@PP rise - rise rise - rise  ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu >}dA5vX?A5?==`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhvX? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhA5? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhd8 J arrival timeXh?, JXh1 JslackXh= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu >}̡eَY?َ?=+1=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)XhY? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xhَ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh+1 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh̡e8 J arrival timeXh?, JXh1 JslackXh=5 FBngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu >},6d~*?d?=rh=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) FBngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @%R?, JXh1 JslackXh= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C|ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu >}~?5cL7)?c?=xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhL7)? |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhc? |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhxi ~zngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh~?58 J arrival timeXhP?, JXh1 JslackXh=ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C|xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D*:BJZ(LUT6=1)j9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu:}>}>ZC = ?Z?mS>ˡE>s=g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[7] Jnet (fo=1, routed)Xhs= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__1/I2 JXhzr {ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__1/OProp_lut6_I2_O JLUT6XhzrA`< }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__1_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh ? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhZ? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzr; Jclock pessimismXhˡE zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh>8 J arrival timeXhN_?, JXh1 JslackXhmS> QMngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu1>}5/d*?/d?>rh=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) QMngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= KGngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= QMngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh*? QMngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh/d? QMngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhrh OKngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXh58 J arrival timeXhlW?, JXh1 JslackXh> |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CokngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu/~>}+G cUu<L7)? c??`>"[=>g(rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ^ZngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xh> okngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhL7)? |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh c? qmngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXh"[ mingFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXh+G8 J arrival timeXhh?, JXh1 JslackXh?`>ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C|xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D*:BJZ(LUT6=1)j9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsuT>}!2ZA94< ?Z?c >/]o>ZP=g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[5] Jnet (fo=1, routed)XhZP= |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__1/I0 JXhzr {ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__1/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__1_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh ? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhZ? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C JFDCEXhzr; Jclock pessimismXh/] zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh!28 J arrival timeXhU?, JXh1 JslackXhc >ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/C}yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/D*:BJZ(LUT6=1)j9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsuuv>}:4^Z`e<A ?4^Z?l >Z>=g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[17] Jnet (fo=1, routed)Xh= }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[17]_i_1__1/I2 JXhzr |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[17]_i_1__1/OProp_lut6_I2_O JLUT6XhzrA`< ~ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[17]_i_1__1_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/D JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhA ? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh4^Z? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C JFDCEXhzr; Jclock pessimismXhZ {wngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh:8 J arrival timeXh]?, JXh1 JslackXhl >ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C|xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D*:BJZ(LUT6=1)j9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsur,>}8Z~C = ?Z?=#>ˡEo>xF>g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_3txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[0] Jnet (fo=1, routed)XhxF> |ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__1/I0 JXhzr {ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__1/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__1_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh ? ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhZ? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C JFDCEXhzr; Jclock pessimismXhˡE zvngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] Hold_fdce_C_D JFDCEXh$y=, JXh9 J required timeXh88 J arrival timeXhLa?, JXh1 JslackXh=#>+'ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C,(ngFEC/g_pm[4].phase_mon/PS_min_reg[4]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuwd@}33ADAҝ? ׽ ?ҝ?33A=А=4@t=V?I.@g(rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[4].phase_mon/PS_min_reg_n_0_[3] Jnet (fo=3, routed)Xh?[ 0,ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2/I0 JXhzrt /+ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2/S[1] JXhzr 62ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2/CO[3]Prop_carry4_S[1]_CO[3] JCARRY4Xhzr:>t 40ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_2__2/CI JXhzr 62ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_2__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[4].phase_mon/ltOp Jnet (fo=1, routed)Xhp2?Z /+ngFEC/g_pm[4].phase_mon/PS_min[9]_i_1__2/I2 JXhzrs .*ngFEC/g_pm[4].phase_mon/PS_min[9]_i_1__2/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[4].phase_mon/PS_min Jnet (fo=10, routed)Xhl?[ ,(ngFEC/g_pm[4].phase_mon/PS_min_reg[4]/CE JFDPEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh ?Z +'ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C JFDPEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhҝ?Z +'ngFEC/g_pm[4].phase_mon/PS_min_reg[4]/C JFDPEXhzr; Jclock pessimismXht== Jclock uncertaintyXhl )%ngFEC/g_pm[4].phase_mon/PS_min_reg[4]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhDA8 J arrival timeXh, JXh1 JslackXh4@ +'ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C,(ngFEC/g_pm[4].phase_mon/PS_min_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuwd@}33ADAҝ? ׽ ?ҝ?33A=А=4@t=V?I.@g(rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[4].phase_mon/PS_min_reg_n_0_[3] Jnet (fo=3, routed)Xh?[ 0,ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2/I0 JXhzrt /+ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2/S[1] JXhzr 62ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2/CO[3]Prop_carry4_S[1]_CO[3] JCARRY4Xhzr:>t 40ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_2__2/CI JXhzr 62ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_2__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[4].phase_mon/ltOp Jnet (fo=1, routed)Xhp2?Z /+ngFEC/g_pm[4].phase_mon/PS_min[9]_i_1__2/I2 JXhzrs .*ngFEC/g_pm[4].phase_mon/PS_min[9]_i_1__2/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[4].phase_mon/PS_min Jnet (fo=10, routed)Xhl?[ ,(ngFEC/g_pm[4].phase_mon/PS_min_reg[6]/CE JFDPEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh ?Z +'ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C JFDPEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhҝ?Z +'ngFEC/g_pm[4].phase_mon/PS_min_reg[6]/C JFDPEXhzr; Jclock pessimismXht== Jclock uncertaintyXhl )%ngFEC/g_pm[4].phase_mon/PS_min_reg[6]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhDA8 J arrival timeXh, JXh1 JslackXh4@ R |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsux@}33AA㿭>F??33A=А=9@@ 0=>a}g@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] Jnet (fo=1, routed)Xha}g@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhF? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh9@@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuv@}33AA㿭>F??33A=А=׉@ 0=Zd>|h@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] Jnet (fo=1, routed)Xh|h@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhF? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh!_, JXh1 JslackXh׉@S }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuv@}33AA㿭>F??33A=А=!@ 0=>7f@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] Jnet (fo=1, routed)Xh7f@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhF? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhS, JXh1 JslackXh!@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuVs@}33AA㿭-H>??33A=А=@ 0=>*b@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] Jnet (fo=1, routed)Xh*b@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh@: |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsu*s@}33AA㿭-H>??33A=А=y@ 0=>Bb@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] Jnet (fo=1, routed)XhBb@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? |xngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhz, JXh1 JslackXhy@A }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsu7(r@}33AA㿭>F??33A=А=4@ 0=>”a@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[16] Jnet (fo=1, routed)Xh”a@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhF? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[14] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh4@A }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuMkq@}33AA㿭>F??33A=А=@ 0=>`@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] Jnet (fo=1, routed)Xh`@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhF? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh8, JXh1 JslackXh@> }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/CngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9]*:BJZj9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsu]:q@}33AA㿭>F??33A=А=u@ 0=>`@g(rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_3txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[11] Jnet (fo=1, routed)Xh`@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhF? }yngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C JFDCEXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh 0== Jclock uncertaintyXh }yngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[9] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhu@ txWordclkl12_4txWordclkl12_4!)]_ff@1]_ff @9A]_ff@I]_ff @ep @hq}=O]@QQ rise - rise rise - rise   |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CokngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsu5T>}(<jTA94<d;?jT?=J=g=g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xhg= okngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=225, routed)Xhd;? |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhjT? qmngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXhJ mingFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXh(<8 J arrival timeXhHT?, JXh1 JslackXh= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsu >}RoyF?o?=|=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=225, routed)XhyF? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=225, routed)Xho? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh| ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhR8 J arrival timeXhn?, JXh1 JslackXh= QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsu >}5 cx)? c?=xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= KGngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=225, routed)Xhx)? QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=225, routed)Xh c? QMngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhxi OKngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh58 J arrival timeXhQ?, JXh1 JslackXh=5 FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsu >}5 cx)? c?=xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @}C+jTd;?jT?=V=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=225, routed)Xhd;? |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=225, routed)XhjT? |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhV ~zngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhC+8 J arrival timeXhF?, JXh1 JslackXh= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsu >}nR!gfF?!?=l{=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=225, routed)XhgfF? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=225, routed)Xh!? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhl{ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhnR8 J arrival timeXh n?, JXh1 JslackXh=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C}yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D*:BJZ(LUT6=1)j9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsuѷX>}`0Y9TA94<R?Y9T?>Jo>J=g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[16] Jnet (fo=1, routed)XhJ= }ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__2/I2 JXhzr |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__2/OProp_lut6_I2_O JLUT6XhzrA`< ~ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__2_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhR? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhY9T? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C JFDCEXhzr; Jclock pessimismXhJ {wngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh`08 J arrival timeXhFT?, JXh1 JslackXh>5 FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/CFBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/D*:BJZj9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsuh>}:( cx)? c?J{>xi5^=P=g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) FBngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/Q Prop_fdre_C_Q JFDREXhzr5^= @ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[111]/C}yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/D*:BJZ(LUT6=1)j9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsua>}1Y9T[`e<R?Y9T?k4>Go>Pѽ=g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[111]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[11] Jnet (fo=1, routed)XhPѽ= }ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__2/I2 JXhzr |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__2/OProp_lut6_I2_O JLUT6XhzrA`< ~ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__2_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/D JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhR? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[111]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhY9T? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C JFDCEXhzr; Jclock pessimismXhG {wngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh18 J arrival timeXh7W?, JXh1 JslackXhk4>ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C|xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D*:BJZ(LUT6=1)j9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsu`>}`0tSwD<v?tS?:>Go>Ż=g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_4txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[4] Jnet (fo=1, routed)XhŻ= |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__2/I0 JXhzr {ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__2/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__2_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xhv? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhtS? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C JFDCEXhzr; Jclock pessimismXhG zvngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh`08 J arrival timeXhV?, JXh1 JslackXh:>R |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu8@}33AABӿdј>S?B?33A=А=p @T<Zd>Pr*@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] Jnet (fo=1, routed)XhPr*@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhS? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh , JXh1 JslackXhp @O |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu0@}33AABӿVN>ٮ?B?33A=А=Z@T<Zd>V"@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] Jnet (fo=1, routed)XhV"@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh#, JXh1 JslackXhZ@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsuz/@}33AABӿdј>S?B?33A=А=٩@T<Zd> @g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[5] Jnet (fo=1, routed)Xh @ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhS? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[5] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh=, JXh1 JslackXh٩@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsuAG-@}33AABӿVN>ٮ?B?33A=А=@T<Zd>@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] Jnet (fo=1, routed)Xh@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhY, JXh1 JslackXh@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsuq+@}33AABӿdј>S?B?33A=А=ڰ@T<Zd>y+@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[4] Jnet (fo=1, routed)Xhy+@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)XhS? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[4] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhf, JXh1 JslackXhڰ@A }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu*+@}33AABӿVN>ٮ?B?33A=А=˫@T<Zd>@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] Jnet (fo=1, routed)Xh@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xhٮ? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhK, JXh1 JslackXh˫@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu.)@}33AABӿVN>ٮ?B?33A=А=ɬ@T<Zd>F@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] Jnet (fo=1, routed)XhF@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhM, JXh1 JslackXhɬ@A }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[10]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsuK(@}33AABӿVN>ٮ?B?33A=А=7;@T<Zd>]@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[12] Jnet (fo=1, routed)Xh]@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[10] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xhٮ? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[10] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh7;@A }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu6'@}33AABӿA˗>?B?33A=А=k@T<Zd>O@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[13] Jnet (fo=1, routed)XhO@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xh? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[11] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh$, JXh1 JslackXhk@S }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1]*:BJZj9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu$@}33AABӿA˗>?B?33A=А=@T<Zd>@g(rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_4txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] Jnet (fo=1, routed)Xh@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=225, routed)Xh? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C JFDCEXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)XhB? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhQ|, JXh1 JslackXh@ txWordclkl12_5txWordclkl12_5!)]_ff@1]_ff @9A]_ff@I]_ff @em@hq}=O]@RR rise - rise rise - rise  QMngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu >}H(|}nRЂgfF?Ђ?=|=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)XhgfF? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)XhЂ? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh| ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhnR8 J arrival timeXh n?, JXh1 JslackXh=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/C}yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/D*:BJZ(LUT6=1)j9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsuq>}-=FSt=@5?FS?^,=&1o>=g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[15] Jnet (fo=1, routed)Xh= }ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[15]_i_1__3/I0 JXhzr |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[15]_i_1__3/OProp_lut6_I0_O JLUT6XhzrA`< ~ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[15]_i_1__3_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/D JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh@5? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhFS? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C JFDCEXhzr; Jclock pessimismXh&1 {wngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh-=8 J arrival timeXhZ?, JXh1 JslackXh^,=5 FBngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu#>}%As4?s?^=l{=:^v=g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) FBngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @}*Y9TR?Y9T?^=V=:^v=g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh:^v= |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhR? |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhY9T? |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhV ~zngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh*8 J arrival timeXhϷG?, JXh1 JslackXh^=ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C|xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D*:BJZ(LUT6=1)j9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsua>}c8FST<v?FS?[)=Go>Pѽ=g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[7] Jnet (fo=1, routed)XhPѽ= |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__3/I0 JXhzr {ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__3/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__3_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhv? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhFS? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzr; Jclock pessimismXhG zvngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhc88 J arrival timeXhV?, JXh1 JslackXh[)= |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CokngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu}j<Y9T[`e<R?Y9T? )=G=v >g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ^ZngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xhv > okngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhR? |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhY9T? qmngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXhG mingFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXhj<8 J arrival timeXho[?, JXh1 JslackXh )= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu1>}nRGG?G?>~=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhG? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhG? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh~ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXhnR8 J arrival timeXhs?, JXh1 JslackXh>ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C}yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D*:BJZ(LUT6=1)j9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu_*>}c8FS`e<@5?FS?3>Go>=g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data5[18] Jnet (fo=1, routed)Xh= }ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__3/I2 JXhzr |ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__3/OProp_lut6_I2_O JLUT6XhzrA`< ~ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__3_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh@5? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhFS? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C JFDCEXhzr; Jclock pessimismXhG {wngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhc88 J arrival timeXhpJ^?, JXh1 JslackXh3> :6ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg/C-)ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3]/D*:BJZ(LUT6=1)j9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu삂>}QX.}u<?5>?.}?">n> =g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_5txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR)~ :6ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg/Q Prop_fdce_C_Q JFDCEXhzr=| <8ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg_n_0 Jnet (fo=9, routed)Xh =\ 1-ngFEC/g_pm[9].phase_mon/inh_cntr[3]_i_1__7/I0 JXhzru 0,ngFEC/g_pm[9].phase_mon/inh_cntr[3]_i_1__7/OProp_lut6_I0_O JLUT6XhzrA`<h ($ngFEC/g_pm[9].phase_mon/p_0_in__0[3] Jnet (fo=1, routed)Xh\ -)ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3]/D JFDPEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[9].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?5>?i :6ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[9].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh.}?\ -)ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3]/C JFDPEXhzr; Jclock pessimismXhnl +'ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3] Hold_fdpe_C_D JFDPEXh-=, JXh9 J required timeXhQX8 J arrival timeXhv?, JXh1 JslackXh"> A }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuD0R@}33AjA(Կ>ٮ?(?33A=А=m@T<Zd>C@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[13] Jnet (fo=1, routed)XhC@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[11] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXhgΔ, JXh1 JslackXhm@O |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuQQ@}33AjA(Կ>ٮ?(?33A=А=@T<>@@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] Jnet (fo=1, routed)Xh@@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXhC_, JXh1 JslackXh@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuKM@}33AjA(Կ>ٮ?(?33A=А=@T<>9<@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] Jnet (fo=1, routed)Xh9<@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXh\, JXh1 JslackXh@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuL@}33AjA(Կ>ٮ?(?33A=А=!@T<>_<@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] Jnet (fo=1, routed)Xh_<@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXh/, JXh1 JslackXh!@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsu\L@}33AjA(Կf>S?(?33A=А=%@T<>f<@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] Jnet (fo=1, routed)Xhf<@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhS? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXhC+, JXh1 JslackXh%@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuL@}33AjA(Կ>ٮ?(?33A=А=(@T<Zd>.>@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] Jnet (fo=1, routed)Xh.>@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXh.(, JXh1 JslackXh(@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuL@}33AjA(Կf>S?(?33A=А={L@T<Zd>f>@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] Jnet (fo=1, routed)Xhf>@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhS? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXhY, JXh1 JslackXh{L@: |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuH@}33AjA(Կ>ٮ?(?33A=А=@T<>5j8@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[4] Jnet (fo=1, routed)Xh5j8@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[4] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXh5, JXh1 JslackXh@V }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsu1B@}33AjA(Կ>ٮ?(?33A=А=@T<Zd>3@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[19] Jnet (fo=1, routed)Xh3@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXhό, JXh1 JslackXh@A }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/CngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14]*:BJZj9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsu?@}33AjA(Կ>ٮ?(?33A=А=AС@T<Zd>N1@g(rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_5txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[16] Jnet (fo=1, routed)XhN1@ ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhٮ? }yngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C JFDCEXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh(? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[14] J GTXE2_CHANNELXh+־, JXh9 J required timeXhjA8 J arrival timeXh, JXh1 JslackXhAС@ txWordclkl12_6txWordclkl12_6!)]_ff@1]_ff @9A]_ff@I]_ff @ev@hq}=O]@SS rise - rise rise - rise  ? GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CGCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu >}5cx)?c?=rh=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`=v GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr{ 95ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xhx)?v GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr{ 95ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xhc?v GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhrh EAngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh58 J arrival timeXhQ?, JXh1 JslackXh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu >}< ka0? k?=rh=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xha0? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh k? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhrh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh<8 J arrival timeXhX?, JXh1 JslackXh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu >}/= k&1? k?=lg=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh&1? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh k? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhlg ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh/=8 J arrival timeXh-X?, JXh1 JslackXh= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CokngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsub>}ASt=v?S?=&1=,>g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xh,> okngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhv? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhS? qmngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXh&1 mingFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXhA8 J arrival timeXh'a?, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C|xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D*:BJZ(LUT6=1)j9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu*?I>}/-RA94</?-R? =5H>N=g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[0] Jnet (fo=1, routed)XhN= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__4/I0 JXhzr {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__4/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__4_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh/? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh-R? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C JFDCEXhzr; Jclock pessimismXh5H zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] Hold_fdce_C_D JFDCEXh$y=, JXh9 J required timeXh/8 J arrival timeXh~O?, JXh1 JslackXh = RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CRNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu1>}6ˡeC+?ˡe?>xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= LHngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)XhC+? RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xhˡe? RNngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhxi PLngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXh68 J arrival timeXhW?, JXh1 JslackXh> |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C|ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu1>}K7)Sv?S?>V=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhv? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhS? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhV ~zngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXhK7)8 J arrival timeXhJ?, JXh1 JslackXh>ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C}yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D*:BJZ(LUT6=1)j9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsuT>}/nRA94<p?nR?c >5Ho>ZP=g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[16] Jnet (fo=1, routed)XhZP= }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__4/I2 JXhzr |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__4/OProp_lut6_I2_O JLUT6XhzrA`< ~ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__4_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhp? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhnR? }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C JFDCEXhzr; Jclock pessimismXh5H {wngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXh/8 J arrival timeXhLR?, JXh1 JslackXhc >/ GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/C3/ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg/D*:BJZ(LUT5=1)j9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsuC>}/Dc`e<x)?c?>Z>=g(rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr=k +'ngFEC/g_pm[10].phase_mon/sample_PS_Sync Jnet (fo=2, routed)Xh=b 73ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_i_1__8/I0 JXhzr{ 62ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_i_1__8/OProp_lut5_I0_O JLUT5Xhzr<x 84ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_i_1__8_n_0 Jnet (fo=1, routed)Xhb 3/ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg/D JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr{ 95ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xhx)?v GCngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/C JFDREXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhc?b 3/ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg/C JFDCEXhzr; Jclock pessimismXhZr 1-ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg Hold_fdce_C_D JFDCEXhv=, JXh9 J required timeXh/D8 J arrival timeXh&di?, JXh1 JslackXh>ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C|xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D*:BJZ(LUT6=1)j9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu|>},6QwD</?Q?pD>FR>ػ=g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_6txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/Q Prop_fdce_C_Q JFDCEXhzr5^= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[5] Jnet (fo=1, routed)Xhػ= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__4/I0 JXhzr {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__4/OProp_lut6_I0_O JLUT6Xhzro= }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__4_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh/? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhQ? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C JFDCEXhzr; Jclock pessimismXhF zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXh,68 J arrival timeXhHX\?, JXh1 JslackXhpD>,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[0]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsuX@}33A1AȦL?Ȧ?33A=А=v@t=4?q+@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhøO?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[0]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhȦ?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[0]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[0]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh1A8 J arrival timeXh듛, JXh1 JslackXhv@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[1]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsuX@}33A1AȦL?Ȧ?33A=А=v@t=4?q+@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhøO?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[1]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhȦ?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[1]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[1]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh1A8 J arrival timeXh듛, JXh1 JslackXhv@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsuX@}33A1AȦL?Ȧ?33A=А=v@t=4?q+@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhøO?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[5]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhȦ?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[5]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[5]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh1A8 J arrival timeXh듛, JXh1 JslackXhv@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[7]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsuX@}33A1AȦL?Ȧ?33A=А=v@t=4?q+@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhøO?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[7]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhȦ?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[7]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[7]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh1A8 J arrival timeXh듛, JXh1 JslackXhv@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsuX@}33A1AȦL?Ȧ?33A=А=v@t=4?q+@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhøO?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhȦ?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[8]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh1A8 J arrival timeXh듛, JXh1 JslackXhv@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsuX@}33A1AȦL?Ȧ?33A=А=v@t=4?q+@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhøO?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhȦ?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[9]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXh1A8 J arrival timeXh듛, JXh1 JslackXhv@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[2]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsu_W@}33AAy馿?y?33A=А=-&@ 0>4? *@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhtJ?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[2]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhy?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[2]/C JFDCEXhzr; Jclock pessimismXh 0>= Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[2]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhA8 J arrival timeXhc, JXh1 JslackXh-&@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[4]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsu_W@}33AAy馿?y?33A=А=-&@ 0>4? *@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhtJ?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[4]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhy?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[4]/C JFDCEXhzr; Jclock pessimismXh 0>= Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[4]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhA8 J arrival timeXhc, JXh1 JslackXh-&@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsu_W@}33AAy馿?y?33A=А=-&@ 0>4? *@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)XhtJ?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhy?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzr; Jclock pessimismXh 0>= Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[6]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhA8 J arrival timeXhc, JXh1 JslackXh-&@ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C-)ngFEC/g_pm[10].phase_mon/PS_max_reg[3]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsuE@}33A;AȦL?Ȧ?33A=А=h@t=4?h@g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_6txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] Jnet (fo=3, routed)Xh?\ 1-ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/I2 JXhzru 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/S[3] JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CI JXhzr 73ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[10].phase_mon/gtOp Jnet (fo=1, routed)Xh?R?[ 0,ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/I2 JXhzrt /+ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[10].phase_mon/PS_max Jnet (fo=10, routed)Xh~?\ -)ngFEC/g_pm[10].phase_mon/PS_max_reg[3]/CE JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhȦ?[ ,(ngFEC/g_pm[10].phase_mon/PS_max_reg[3]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXhm *&ngFEC/g_pm[10].phase_mon/PS_max_reg[3]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh;A8 J arrival timeXhb, JXh1 JslackXhh@  txWordclkl12_7txWordclkl12_7!)]_ff@1]_ff @9A]_ff@I]_ff @eV$@hq}=O]@TT rise - rise rise - rise   |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CokngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsubG>}8ףP #<(?ףP?=G=K=g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)XhK= okngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh(? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhףP? qmngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXhG mingFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXh88 J arrival timeXh N?, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/D*:BJZ(CARRY4=4 LUT1=1)j9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsuь>}S~n>|?n?X=r~> >g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q Prop_fdre_C_Q JFDREXhzf= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] Jnet (fo=2, routed)Xhe > ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/I0 JXhzf ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/OProp_lut1_I0_O JLUT1XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/S[0] JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrx= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 Jnet (fo=1, routed)Xh|5: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[0]Prop_carry4_CI_O[0] JCARRY4Xhzr'= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_7 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh|? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xhn? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/C JFDREXhzr; Jclock pessimismXhr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12] Hold_fdre_C_D JFDREXhsh=, JXh9 J required timeXhS~8 J arrival timeXh?, JXh1 JslackXhX= RNngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CRNngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu >}K7ˡeC+?ˡe?=xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) RNngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= LHngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= RNngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr D@ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)XhC+? RNngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr D@ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xhˡe? RNngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhxi PLngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhK78 J arrival timeXhR?, JXh1 JslackXh=? GCngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CGCngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu >}+6d~*?d?=rh=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) GCngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`=v GCngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr{ 95ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xh~*?v GCngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr{ 95ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xhd?v GCngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhrh EAngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh+68 J arrival timeXh=%R?, JXh1 JslackXh= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C|ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu >}'1(`P(?`P?=R=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh(? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh`P? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhR ~zngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh'1(8 J arrival timeXh9C?, JXh1 JslackXh= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu >} +kT|?kT?=T=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh|? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)XhkT? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhT ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh +8 J arrival timeXh2#G?, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/D*:BJZ(CARRY4=4 LUT1=1)j9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu.>}S~n>|?n?D=r > >g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q Prop_fdre_C_Q JFDREXhzf= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] Jnet (fo=2, routed)Xhe > ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/I0 JXhzf ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/OProp_lut1_I0_O JLUT1XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/S[0] JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrx= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 Jnet (fo=1, routed)Xh|5: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[2]Prop_carry4_CI_O[2] JCARRY4XhzrT= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_5 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh|? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xhn? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/C JFDREXhzr; Jclock pessimismXhr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14] Hold_fdre_C_D JFDREXhsh=, JXh9 J required timeXhS~8 J arrival timeXhJ?, JXh1 JslackXhD= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu#>}+Tw?T?^=T=:^v=g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh:^v= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xhw? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhT? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhT ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh+8 J arrival timeXhH?, JXh1 JslackXh^=ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/D*:BJZ(CARRY4=4 LUT1=1)j9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu0G>}S~n>|?n?A=rX9> >g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q Prop_fdre_C_Q JFDREXhzf= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] Jnet (fo=2, routed)Xhe > ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/I0 JXhzf ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/OProp_lut1_I0_O JLUT1XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/S[0] JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrx= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 Jnet (fo=1, routed)Xh|5: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[1]Prop_carry4_CI_O[1] JCARRY4Xhzru= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_6 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh|? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xhn? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/C JFDREXhzr; Jclock pessimismXhr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13] Hold_fdre_C_D JFDREXhsh=, JXh9 J required timeXhS~8 J arrival timeXhCP?, JXh1 JslackXhA=ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/D*:BJZ(CARRY4=4 LUT1=1)j9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu>}S~n>|?n? =rȶ> >g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_7txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q Prop_fdre_C_Q JFDREXhzf= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] Jnet (fo=2, routed)Xhe > ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/I0 JXhzf ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/OProp_lut1_I0_O JLUT1XhzrA`< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/S[0] JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrx= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3]Prop_carry4_CI_CO[3] JCARRY4Xhzr< ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 Jnet (fo=1, routed)Xh|5: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/CI JXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[3]Prop_carry4_CI_O[3] JCARRY4Xhzr= ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_4 Jnet (fo=1, routed)Xh ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/D JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh|? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C JFDREXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr zvngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xhn? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C JFDREXhzr; Jclock pessimismXhr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15] Hold_fdre_C_D JFDREXhsh=, JXh9 J required timeXhS~8 J arrival timeXh?, JXh1 JslackXh =,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[1]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsu-@}33AlyA̼㥻??33A=А=V$@T>VM? ?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xh$?\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[1]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[1]/C JFDPEXhzr; Jclock pessimismXhT>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[1]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhlyA8 J arrival timeXh΅, JXh1 JslackXhV$@ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[8]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsu-@}33AlyA̼㥻??33A=А=V$@T>VM? ?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xh$?\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[8]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[8]/C JFDPEXhzr; Jclock pessimismXhT>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[8]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhlyA8 J arrival timeXh΅, JXh1 JslackXhV$@ ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C-)ngFEC/g_pm[11].phase_mon/PS_max_reg[2]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsuc'@}33AaAy馿̼?y?33A=А=W@)> K??g(rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[11].phase_mon/PS_max_reg_n_0_[0] Jnet (fo=3, routed)XhP?\ 1-ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9/I2 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5/S[0] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>u 51ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_2__5/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>a !ngFEC/g_pm[11].phase_mon/gtOp Jnet (fo=1, routed)Xh)>[ 0,ngFEC/g_pm[11].phase_mon/PS_max[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_max[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr$>d #ngFEC/g_pm[11].phase_mon/PS_max Jnet (fo=10, routed)Xh?\ -)ngFEC/g_pm[11].phase_mon/PS_max_reg[2]/CE JFDCEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C JFDCEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhy?[ ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[2]/C JFDCEXhzr; Jclock pessimismXh)>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_max_reg[2]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhaA8 J arrival timeXh?, JXh1 JslackXhW@ ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C-)ngFEC/g_pm[11].phase_mon/PS_max_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsuc'@}33AaAy馿̼?y?33A=А=W@)> K??g(rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd>o /+ngFEC/g_pm[11].phase_mon/PS_max_reg_n_0_[0] Jnet (fo=3, routed)XhP?\ 1-ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9/I2 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9/OProp_lut4_I2_O JLUT4Xhzr 0=r 2.ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5/S[0] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>u 51ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_2__5/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>a !ngFEC/g_pm[11].phase_mon/gtOp Jnet (fo=1, routed)Xh)>[ 0,ngFEC/g_pm[11].phase_mon/PS_max[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_max[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzr$>d #ngFEC/g_pm[11].phase_mon/PS_max Jnet (fo=10, routed)Xh?\ -)ngFEC/g_pm[11].phase_mon/PS_max_reg[6]/CE JFDCEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C JFDCEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhy?[ ,(ngFEC/g_pm[11].phase_mon/PS_max_reg[6]/C JFDCEXhzr; Jclock pessimismXh)>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_max_reg[6]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXhaA8 J arrival timeXh?, JXh1 JslackXhW@ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[0]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsua"@}33A >A㥻??33A=А=a@&1>VM?;?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xhxf>\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[0]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[0]/C JFDPEXhzr; Jclock pessimismXh&1>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[0]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXh >A8 J arrival timeXh:, JXh1 JslackXha@ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[2]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsua"@}33A >A㥻??33A=А=a@&1>VM?;?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xhxf>\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[2]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[2]/C JFDPEXhzr; Jclock pessimismXh&1>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[2]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXh >A8 J arrival timeXh:, JXh1 JslackXha@ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[3]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsua"@}33A >A㥻??33A=А=a@&1>VM?;?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xhxf>\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[3]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[3]/C JFDPEXhzr; Jclock pessimismXh&1>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[3]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXh >A8 J arrival timeXh:, JXh1 JslackXha@ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[4]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsua"@}33A >A㥻??33A=А=a@&1>VM?;?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xhxf>\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[4]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[4]/C JFDPEXhzr; Jclock pessimismXh&1>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[4]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXh >A8 J arrival timeXh:, JXh1 JslackXha@ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsua"@}33A >A㥻??33A=А=a@&1>VM?;?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xhxf>\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[5]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[5]/C JFDPEXhzr; Jclock pessimismXh&1>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[5]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXh >A8 J arrival timeXh:, JXh1 JslackXha@ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C-)ngFEC/g_pm[11].phase_mon/PS_min_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsua"@}33A >A㥻??33A=А=a@&1>VM?;?g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_7txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) p ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzrq>o /+ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] Jnet (fo=3, routed)Xh2&?\ 1-ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/I0 JXhzru 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/OProp_lut4_I0_O JLUT4Xhzr=r 2.ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 Jnet (fo=1, routed)Xha 62ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/S[3] JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3]Prop_carry4_S[3]_CO[3] JCARRY4XhzrQ8>u 51ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 Jnet (fo=1, routed)Xh_ 40ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CI JXhzr 73ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>a !ngFEC/g_pm[11].phase_mon/ltOp Jnet (fo=1, routed)XhHM?[ 0,ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/I2 JXhzrt /+ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/OProp_lut5_I2_O JLUT5Xhzro>d #ngFEC/g_pm[11].phase_mon/PS_min Jnet (fo=10, routed)Xhxf>\ -)ngFEC/g_pm[11].phase_mon/PS_min_reg[6]/CE JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh㥻?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C JFDPEXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzrp .*ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?[ ,(ngFEC/g_pm[11].phase_mon/PS_min_reg[6]/C JFDPEXhzr; Jclock pessimismXh&1>= Jclock uncertaintyXhm *&ngFEC/g_pm[11].phase_mon/PS_min_reg[6]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXh >A8 J arrival timeXh:, JXh1 JslackXha@  txWordclkl12_8txWordclkl12_8!)]_ff@1]_ff @9A]_ff@I]_ff @e肍@hq}1Q=O]@UU rise - rise rise - rise  ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[112]/C}yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/D*:BJZ(LUT6=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsuP>}CkTˡE>#?T?1Q=o>,P>g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[112]/Q Prop_fdce_C_Q JFDCEXhzr= _[ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[12] Jnet (fo=1, routed)Xh,P> }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[12]_i_1__6/I2 JXhzr |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[12]_i_1__6/OProp_lut6_I2_O JLUT6XhzrA`< ~ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[12]_i_1__6_n_0 Jnet (fo=1, routed)Xh }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/D JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh#? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[112]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhT? }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C JFDCEXhzr; Jclock pessimismXh {wngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhCk8 J arrival timeXh]x?, JXh1 JslackXh1Q=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[106]/C|xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D*:BJZ(LUT6=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu'>}CkTC>$?T?ʏf=>@>g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[106]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[6] Jnet (fo=1, routed)Xh@> |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__6/I2 JXhzr {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__6/OProp_lut6_I2_O JLUT6XhzrA`< }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__6_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh$? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[106]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhT? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C JFDCEXhzr; Jclock pessimismXh zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhCk8 J arrival timeXhy?, JXh1 JslackXhʏf=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C|xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D*:BJZ(LUT6=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu{>}CkTD> #?T?}m=o>U>g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[7] Jnet (fo=1, routed)XhU> |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__6/I2 JXhzr {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__6/OProp_lut6_I2_O JLUT6XhzrA`< }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__6_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh #? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhT? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzr; Jclock pessimismXh zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhCk8 J arrival timeXhz?, JXh1 JslackXh}m=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C|xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D*:BJZ(LUT6=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsuH>}CkTC>$?T?ȃ=R>?>g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/Q Prop_fdce_C_Q JFDCEXhzr5^= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[4] Jnet (fo=1, routed)Xh?> |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__6/I0 JXhzr {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__6/OProp_lut6_I0_O JLUT6Xhzro= }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__6_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh$? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhT? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C JFDCEXhzr; Jclock pessimismXh zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhCk8 J arrival timeXh{?, JXh1 JslackXhȃ= mingFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/CzvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D*:BJZ(LUT6=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsuu>}nQX!Zd>d;?QX?=/>Hb>g(rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) mingFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q Prop_fdre_C_Q JFDREXhzr"= d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] Jnet (fo=5, routed)XhHb> ~zngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1__6/I3 JXhzr }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1__6/OProp_lut6_I3_O JLUT6Xhzro= {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1__6_n_0 Jnet (fo=1, routed)Xh zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhd;? mingFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C JFDREXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhQX? zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C JFDCEXhzr; Jclock pessimismXh xtngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhn8 J arrival timeXhց?, JXh1 JslackXh=ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C|xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D*:BJZ(LUT6=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsuC>}CkTC>$?T? =R>W>g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/Q Prop_fdce_C_Q JFDCEXhzr5^= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[5] Jnet (fo=1, routed)XhW> |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__6/I0 JXhzr {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__6/OProp_lut6_I0_O JLUT6Xhzro= }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__6_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh$? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhT? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C JFDCEXhzr; Jclock pessimismXh zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhCk8 J arrival timeXh ݀?, JXh1 JslackXh =ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C|xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D*:BJZ(LUT6=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu˽>}gQXSc>|?QX?=o>vx>g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[1] Jnet (fo=1, routed)Xhvx> |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__6/I0 JXhzr {ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__6/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__6_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh|? ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhQX? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzr; Jclock pessimismXh zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhg8 J arrival timeXhb~?, JXh1 JslackXh= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CokngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu5T>}(<jTA94<d;?jT?=J=g=g(rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})i(rising edge-triggered cell SRL16E clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ^ZngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xhg= okngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhd;? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhjT? qmngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXhJ mingFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXh(<8 J arrival timeXhHT?, JXh1 JslackXh=? GCngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CGCngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu >}5 cx)? c?=xi=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) GCngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= A=ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`=v GCngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr{ 95ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xhx)?v GCngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr{ 95ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/dest_clk Jnet (fo=221, routed)Xh c?v GCngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhxi EAngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh58 J arrival timeXhQ?, JXh1 JslackXh= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C|ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu >}C+jTd;?jT?=V=`=g(rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})g(rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})FasttxWordclkl12_8txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= zvngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhd;? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr rnngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhjT? |ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhV ~zngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhC+8 J arrival timeXhF?, JXh1 JslackXh=: |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsu]@}33A^A9ÿ>$?9?33A=А=肍@Zd>:O@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] Jnet (fo=1, routed)Xh:O@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh$? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXhw:, JXh1 JslackXh肍@O |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuuV@}33A^A9ÿ>a?9?33A=А=#I@>RE@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] Jnet (fo=1, routed)XhRE@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xha? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXh;t, JXh1 JslackXh#I@S }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuU@}33A^A9ÿ>a?9?33A=А=@Zd>G@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] Jnet (fo=1, routed)XhG@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xha? }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i.Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXh4, JXh1 JslackXh@A }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsu;VT@}33A^A9ÿ>a?9?33A=А=X@Zd>F@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] Jnet (fo=1, routed)XhF@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xha? }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXhvd, JXh1 JslackXhX@: |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuS@}33A^A9ÿ>$?9?33A=А=z@Zd>E@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] Jnet (fo=1, routed)XhE@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh$? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXh,, JXh1 JslackXhz@: |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuS@}33AA9ÿ/>e;?9?33A=А=@T<>C@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] Jnet (fo=1, routed)XhC@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhe;? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh@R |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuN@}33A^A9ÿ>a?9?33A=А= @>,3>@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] Jnet (fo=1, routed)Xh,3>@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xha? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXh, JXh1 JslackXh @: |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuL@}33AA9ÿ/>e;?9?33A=А=*K@T<>C;@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[5] Jnet (fo=1, routed)XhC;@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhe;? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[5] J GTXE2_CHANNELXh+־, JXh9 J required timeXhA8 J arrival timeXhܑ, JXh1 JslackXh*K@A }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuŕH@}33A^A9ÿ>a?9?33A=А=$9@>O8@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[15] Jnet (fo=1, routed)XhO8@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xha? }yngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i(Setup_gtxe2_channel_TXUSRCLK2_TXDATA[13] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXh;, JXh1 JslackXh$9@: |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/CngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0]*:BJZj9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsuG@}33A^A9ÿ>$?9?33A=А=c@Zd>Cy9@g(rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})SlowtxWordclkl12_8txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/Q Prop_fdce_C_Q JFDCEXhzrZd> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[0] Jnet (fo=1, routed)XhCy9@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh$? |xngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C JFDCEXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh9? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXh= Jclock uncertaintyXh }yngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[0] J GTXE2_CHANNELXh+־, JXh9 J required timeXh^A8 J arrival timeXh , JXh1 JslackXhc@  txWordclkl8_1 txWordclkl8_1!)]_ff@1]_ff @9A]_ff@I]_ff @e9"@hq}=O]@VV rise - rise rise - rise  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsu >}KWlCK?l?=+=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhCK? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xhl? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh+ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhKW8 J arrival timeXhr?, JXh1 JslackXh= QMngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsu >} K@5~>?@5~?=|=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) QMngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= KGngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= QMngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh>? QMngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh@5~? QMngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXh| OKngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh K8 J arrival timeXhf?, JXh1 JslackXh=* FBngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsu >} Kv~|??v~?=i{=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) FBngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @}KWlCK?l?=+=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhCK? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhl? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXh+ }yngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhKW8 J arrival timeXhr?, JXh1 JslackXh= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CnjngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsuAAq>}M7iQu<CK?Q?== >f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})h(rising edge-triggered cell SRL16E clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xh > njngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhCK? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhQ? plngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXh lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXhM7i8 J arrival timeXhɃ?, JXh1 JslackXh=s ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsu1>}:Hj|=?j|?>&y=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh=? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xhj|? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXh&y ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXh:H8 J arrival timeXh5j?, JXh1 JslackXh>zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[82]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D*:BJZ(LUT6=1)j7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsu$j>}cK9\=CK?K?>xio>$=f(rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[82]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[2] Jnet (fo=1, routed)Xh$= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__7/I0 JXhzr ~zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__7/OProp_lut6_I0_O JLUT6XhzrA`< |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__7_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D JFDCEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhCK? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[82]/C JFDCEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhK? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C JFDCEXhzr; Jclock pessimismXhxi yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhc8 J arrival timeXhd?, JXh1 JslackXh>ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C|xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D*:BJZ(LUT6=1)j7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsuT>}p]K}94<CK?K?` >(o>ZP=f(rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[18] Jnet (fo=1, routed)XhZP= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__7/I2 JXhzr {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__7/OProp_lut6_I2_O JLUT6XhzrA`< }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__7_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D JFDCEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhCK? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C JFDCEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhK? |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C JFDCEXhzr; Jclock pessimismXh( zvngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhp]8 J arrival timeXh9?, JXh1 JslackXh` >ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D*:BJZ(LUT4=1)j7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsuz\>}OMj|=?j|? >&y >n=f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/Q Prop_fdre_C_Q JFDREXhzf5^= ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3 Jnet (fo=2, routed)Xhn= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/I2 JXhzf ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/OProp_lut4_I2_O JLUT4Xhzr+= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh=? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xhj|? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C JFDREXhzr; Jclock pessimismXh&y ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhOM8 J arrival timeXh_u?, JXh1 JslackXh >}ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[100]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D*:BJZ(LUT6=1)j7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsucs>}v^l[`e<CK?l?–&>>Ż=f(rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_1 txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[100]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[0] Jnet (fo=1, routed)XhŻ= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__7/I2 JXhzr ~zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__7/OProp_lut6_I2_O JLUT6XhzrA`< |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__7_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D JFDCEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhCK? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[100]/C JFDCEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhl? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C JFDCEXhzr; Jclock pessimismXh yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] Hold_fdce_C_D JFDCEXh$y=, JXh9 J required timeXhv^8 J arrival timeXh=?, JXh1 JslackXh–&>+'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C,(ngFEC/g_pm[5].phase_mon/PS_min_reg[7]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu'@}33AA@??33A=А=9"@>>?q@?f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[5] Jnet (fo=3, routed)Xh>[ 0,ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/I0 JXhzrt /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/S[2] JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3]Prop_carry4_S[2]_CO[3] JCARRY4XhzrZd;>t 40ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CI JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[5].phase_mon/ltOp Jnet (fo=1, routed)Xh#M?Z /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/I2 JXhzrs .*ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[5].phase_mon/PS_min Jnet (fo=10, routed)Xhi[?[ ,(ngFEC/g_pm[5].phase_mon/PS_min_reg[7]/CE JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[7]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[5].phase_mon/PS_min_reg[7]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh9"@ +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C,(ngFEC/g_pm[5].phase_mon/PS_min_reg[8]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu'@}33AA@??33A=А=9"@>>?q@?f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[5] Jnet (fo=3, routed)Xh>[ 0,ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/I0 JXhzrt /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/S[2] JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3]Prop_carry4_S[2]_CO[3] JCARRY4XhzrZd;>t 40ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CI JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[5].phase_mon/ltOp Jnet (fo=1, routed)Xh#M?Z /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/I2 JXhzrs .*ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[5].phase_mon/PS_min Jnet (fo=10, routed)Xhi[?[ ,(ngFEC/g_pm[5].phase_mon/PS_min_reg[8]/CE JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[8]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[5].phase_mon/PS_min_reg[8]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh9"@ +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C,(ngFEC/g_pm[5].phase_mon/PS_min_reg[1]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu3"@}33AQJAA` ̼e;?A`?33A=А=ѫ@{?5>5??f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[4] Jnet (fo=3, routed)Xhl>[ 0,ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/I2 JXhzrt /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/S[2] JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3]Prop_carry4_S[2]_CO[3] JCARRY4XhzrZd;>t 40ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CI JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[5].phase_mon/ltOp Jnet (fo=1, routed)Xh#M?Z /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/I2 JXhzrs .*ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[5].phase_mon/PS_min Jnet (fo=10, routed)XhnF?[ ,(ngFEC/g_pm[5].phase_mon/PS_min_reg[1]/CE JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhe;?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA`?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[1]/C JFDPEXhzr; Jclock pessimismXh{?5>= Jclock uncertaintyXhl )%ngFEC/g_pm[5].phase_mon/PS_min_reg[1]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhQJA8 J arrival timeXh, JXh1 JslackXhѫ@ +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C,(ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu3"@}33AQJAA` ̼e;?A`?33A=А=ѫ@{?5>5??f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[4] Jnet (fo=3, routed)Xhl>[ 0,ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/I2 JXhzrt /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/S[2] JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3]Prop_carry4_S[2]_CO[3] JCARRY4XhzrZd;>t 40ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CI JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[5].phase_mon/ltOp Jnet (fo=1, routed)Xh#M?Z /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/I2 JXhzrs .*ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[5].phase_mon/PS_min Jnet (fo=10, routed)XhnF?[ ,(ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/CE JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhe;?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA`?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C JFDPEXhzr; Jclock pessimismXh{?5>= Jclock uncertaintyXhl )%ngFEC/g_pm[5].phase_mon/PS_min_reg[5]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhQJA8 J arrival timeXh, JXh1 JslackXhѫ@ +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C,(ngFEC/g_pm[5].phase_mon/PS_min_reg[9]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu3"@}33AQJAA` ̼e;?A`?33A=А=ѫ@{?5>5??f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[4] Jnet (fo=3, routed)Xhl>[ 0,ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/I2 JXhzrt /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/S[2] JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3]Prop_carry4_S[2]_CO[3] JCARRY4XhzrZd;>t 40ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CI JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[5].phase_mon/ltOp Jnet (fo=1, routed)Xh#M?Z /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/I2 JXhzrs .*ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[5].phase_mon/PS_min Jnet (fo=10, routed)XhnF?[ ,(ngFEC/g_pm[5].phase_mon/PS_min_reg[9]/CE JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhe;?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA`?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[9]/C JFDPEXhzr; Jclock pessimismXh{?5>= Jclock uncertaintyXhl )%ngFEC/g_pm[5].phase_mon/PS_min_reg[9]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhQJA8 J arrival timeXh, JXh1 JslackXhѫ@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE*:BJZ(LUT2=1 LUT4=2)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu@}33AѴANb࿭̼\?Nb?33A=А=k[@=>?f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q Prop_fdre_C_Q JFDREXhzf> ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] Jnet (fo=2, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/I2 JXhzf ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/OProp_lut4_I2_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 Jnet (fo=1, routed)Xh_> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut4_I0_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=16, routed)Xh~> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh\? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)XhNb? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C JFDREXhzr; Jclock pessimismXh== Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhѴA8 J arrival timeXh7, JXh1 JslackXhk[@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/CE*:BJZ(LUT2=1 LUT4=2)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu@}33AѴANb࿭̼\?Nb?33A=А=k[@=>?f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q Prop_fdre_C_Q JFDREXhzf> ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] Jnet (fo=2, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/I2 JXhzf ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/OProp_lut4_I2_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 Jnet (fo=1, routed)Xh_> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut4_I0_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=16, routed)Xh~> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/CE JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh\? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)XhNb? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/C JFDREXhzr; Jclock pessimismXh== Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhѴA8 J arrival timeXh7, JXh1 JslackXhk[@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/CE*:BJZ(LUT2=1 LUT4=2)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu@}33AѴANb࿭̼\?Nb?33A=А=k[@=>?f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q Prop_fdre_C_Q JFDREXhzf> ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] Jnet (fo=2, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/I2 JXhzf ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/OProp_lut4_I2_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 Jnet (fo=1, routed)Xh_> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut4_I0_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=16, routed)Xh~> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/CE JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh\? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)XhNb? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/C JFDREXhzr; Jclock pessimismXh== Jclock uncertaintyXh ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhѴA8 J arrival timeXh7, JXh1 JslackXhk[@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/CE*:BJZ(LUT2=1 LUT4=2)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu@}33AѴANb࿭̼\?Nb?33A=А=k[@=>?f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q Prop_fdre_C_Q JFDREXhzf> ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] Jnet (fo=2, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/I2 JXhzf ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/OProp_lut4_I2_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 Jnet (fo=1, routed)Xh_> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/OProp_lut4_I0_O JLUT4Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 Jnet (fo=2, routed)Xh ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/I0 JXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/OProp_lut2_I0_O JLUT2Xhzr 0= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 Jnet (fo=16, routed)Xh~> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/CE JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xh\? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C JFDREXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)XhNb? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/C JFDREXhzr; Jclock pessimismXh== Jclock uncertaintyXh ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]Setup_fdre_C_CE JFDREXhE6, JXh9 J required timeXhѴA8 J arrival timeXh7, JXh1 JslackXhk[@+'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C,(ngFEC/g_pm[5].phase_mon/PS_min_reg[0]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu@}33AAA`ļ?A`?33A=А=Ɯ@{?5>>?7V?f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_1 txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[5] Jnet (fo=3, routed)Xh>[ 0,ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/I0 JXhzrt /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/S[2] JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3]Prop_carry4_S[2]_CO[3] JCARRY4XhzrZd;>t 40ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CI JXhzr 62ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[5].phase_mon/ltOp Jnet (fo=1, routed)Xh#M?Z /+ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/I2 JXhzrs .*ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[5].phase_mon/PS_min Jnet (fo=10, routed)Xh?[ ,(ngFEC/g_pm[5].phase_mon/PS_min_reg[0]/CE JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C JFDPEXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA`?Z +'ngFEC/g_pm[5].phase_mon/PS_min_reg[0]/C JFDPEXhzr; Jclock pessimismXh{?5>= Jclock uncertaintyXhl )%ngFEC/g_pm[5].phase_mon/PS_min_reg[0]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXhv~, JXh1 JslackXhƜ@   txWordclkl8_2 txWordclkl8_2!)]_ff@1]_ff @9A]_ff@I]_ff @e)@hq}=O]@WW  rise - rise rise - rise  {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CnjngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsu5T>}-Rts}94<}?5?ts?=rm=g=f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})h(rising edge-triggered cell SRL16E clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xhg= njngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh}?5? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhts? plngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXhrm lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXh-R8 J arrival timeXhLj?, JXh1 JslackXh= QMngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsu >}r=J.}@5>?.}?=}=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) QMngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= KGngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= QMngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh@5>? QMngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh.}? QMngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXh} OKngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhr=J8 J arrival timeXhe?, JXh1 JslackXh=i {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C{ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsu >}GAts}?5?ts?= x=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh}?5? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhts? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXh x }yngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhGA8 J arrival timeXh\?, JXh1 JslackXh= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsu >}rH5^zj}Y9T53s*\=4?53s?=To>:=f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[91]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[11] Jnet (fo=1, routed)Xh:= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__8/I0 JXhzr {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__8/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__8_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/D JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh4? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[91]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh53s? |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C JFDCEXhzr; Jclock pessimismXhT zvngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhY9T8 J arrival timeXh4p?, JXh1 JslackXh=zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[89]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D*:BJZ(LUT6=1)j7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsua>}VNnrT<k4?nr?c)=xio>Pѽ=f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[89]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[9] Jnet (fo=1, routed)XhPѽ= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__8/I0 JXhzr ~zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__8/OProp_lut6_I0_O JLUT6XhzrA`< |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__8_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhk4? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[89]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhnr? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C JFDCEXhzr; Jclock pessimismXhxi yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhVN8 J arrival timeXh1;m?, JXh1 JslackXhc)=* FBngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsu1>}A@zt5?zt?>p{=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) FBngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @s ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsu1>}GIzw=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)XhzngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D*:BJZ(LUT6=1)j7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsuh>}L!r~C =k4?!r?w~>To>[=f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[1] Jnet (fo=1, routed)Xh[= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__8/I0 JXhzr ~zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__8/OProp_lut6_I0_O JLUT6XhzrA`< |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__8_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhk4? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh!r? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzr; Jclock pessimismXhT yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhL8 J arrival timeXhjn?, JXh1 JslackXhw~>ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D*:BJZ(LUT4=1)j7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsuS>}N5^zA94<jCl>'Lv=f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_2 txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR)  ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/Q Prop_fdre_C_Q JFDREXhzf= ~ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3 Jnet (fo=2, routed)Xh'Lv= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/I2 JXhzf ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/OProp_lut4_I2_O JLUT4XhzrA`< ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1_n_0 Jnet (fo=1, routed)Xh ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D JFDREXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr yungFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in Jnet (fo=221, routed)Xhj+'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[6].phase_mon/PS_min_reg[4]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsucN*@}33AAGήA??33A=А=)@>kT?>?f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)XhV>[ 0,ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/I2 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/ltOp Jnet (fo=1, routed)Xhѕ?Z /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_min Jnet (fo=10, routed)Xh:?[ ,(ngFEC/g_pm[6].phase_mon/PS_min_reg[4]/CE JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[4]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_min_reg[4]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh7, JXh1 JslackXh)@ +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[6].phase_mon/PS_min_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsucN*@}33AAGήA??33A=А=)@>kT?>?f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)XhV>[ 0,ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/I2 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/ltOp Jnet (fo=1, routed)Xhѕ?Z /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_min Jnet (fo=10, routed)Xh:?[ ,(ngFEC/g_pm[6].phase_mon/PS_min_reg[5]/CE JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[5]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_min_reg[5]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh7, JXh1 JslackXh)@ +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[6].phase_mon/PS_min_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsucN*@}33AAGήA??33A=А=)@>kT?>?f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)XhV>[ 0,ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/I2 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/ltOp Jnet (fo=1, routed)Xhѕ?Z /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_min Jnet (fo=10, routed)Xh:?[ ,(ngFEC/g_pm[6].phase_mon/PS_min_reg[6]/CE JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[6]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_min_reg[6]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh7, JXh1 JslackXh)@ +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[6].phase_mon/PS_min_reg[9]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsucN*@}33AAGήA??33A=А=)@>kT?>?f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)XhV>[ 0,ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/I2 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/ltOp Jnet (fo=1, routed)Xhѕ?Z /+ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_min Jnet (fo=10, routed)Xh:?[ ,(ngFEC/g_pm[6].phase_mon/PS_min_reg[9]/CE JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhA?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[6].phase_mon/PS_min_reg[9]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_min_reg[9]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh7, JXh1 JslackXh)@ +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C,(ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu@]2@}33AZAOsh?O?33A=А=c@N>kT?M\?f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] Jnet (fo=3, routed)Xh E>[ 0,ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/I0 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/gtOp Jnet (fo=1, routed)Xh5?Z /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_max Jnet (fo=10, routed)XhhPN?[ ,(ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/CE JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhsh?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhO?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C JFDCEXhzr; Jclock pessimismXhN>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_max_reg[1]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXhZA8 J arrival timeXh, JXh1 JslackXhc@ +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C,(ngFEC/g_pm[6].phase_mon/PS_max_reg[2]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu@]2@}33AZAOsh?O?33A=А=c@N>kT?M\?f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] Jnet (fo=3, routed)Xh E>[ 0,ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/I0 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/gtOp Jnet (fo=1, routed)Xh5?Z /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_max Jnet (fo=10, routed)XhhPN?[ ,(ngFEC/g_pm[6].phase_mon/PS_max_reg[2]/CE JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhsh?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhO?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[2]/C JFDCEXhzr; Jclock pessimismXhN>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_max_reg[2]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXhZA8 J arrival timeXh, JXh1 JslackXhc@ +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C,(ngFEC/g_pm[6].phase_mon/PS_max_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu@]2@}33AZAOsh?O?33A=А=c@N>kT?M\?f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] Jnet (fo=3, routed)Xh E>[ 0,ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/I0 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/gtOp Jnet (fo=1, routed)Xh5?Z /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_max Jnet (fo=10, routed)XhhPN?[ ,(ngFEC/g_pm[6].phase_mon/PS_max_reg[5]/CE JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhsh?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhO?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[5]/C JFDCEXhzr; Jclock pessimismXhN>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_max_reg[5]Setup_fdce_C_CE JFDCEXhE6, JXh9 J required timeXhZA8 J arrival timeXh, JXh1 JslackXhc@ +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C,(ngFEC/g_pm[6].phase_mon/PS_max_reg[0]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu2'@}33A1AO ̼sh?O?33A=А=E-@{?5>kT?,?f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] Jnet (fo=3, routed)Xh E>[ 0,ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/I0 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/gtOp Jnet (fo=1, routed)Xh5?Z /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_max Jnet (fo=10, routed)Xh(#?[ ,(ngFEC/g_pm[6].phase_mon/PS_max_reg[0]/CE JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhsh?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhO?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[0]/C JFDCEXhzr; Jclock pessimismXh{?5>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_max_reg[0]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh1A8 J arrival timeXh56, JXh1 JslackXhE-@ +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C,(ngFEC/g_pm[6].phase_mon/PS_max_reg[3]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu2'@}33A1AO ̼sh?O?33A=А=E-@{?5>kT?,?f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] Jnet (fo=3, routed)Xh E>[ 0,ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/I0 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/gtOp Jnet (fo=1, routed)Xh5?Z /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_max Jnet (fo=10, routed)Xh(#?[ ,(ngFEC/g_pm[6].phase_mon/PS_max_reg[3]/CE JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhsh?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhO?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[3]/C JFDCEXhzr; Jclock pessimismXh{?5>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_max_reg[3]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh1A8 J arrival timeXh56, JXh1 JslackXhE-@ +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C,(ngFEC/g_pm[6].phase_mon/PS_max_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu2'@}33A1AO ̼sh?O?33A=А=E-@{?5>kT?,?f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_2 txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr>n .*ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] Jnet (fo=3, routed)Xh E>[ 0,ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/I0 JXhzrt /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/S[0] JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CI JXhzr 62ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[6].phase_mon/gtOp Jnet (fo=1, routed)Xh5?Z /+ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/I2 JXhzrs .*ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[6].phase_mon/PS_max Jnet (fo=10, routed)Xh(#?[ ,(ngFEC/g_pm[6].phase_mon/PS_max_reg[6]/CE JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhsh?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C JFDCEXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhO?Z +'ngFEC/g_pm[6].phase_mon/PS_max_reg[6]/C JFDCEXhzr; Jclock pessimismXh{?5>= Jclock uncertaintyXhl )%ngFEC/g_pm[6].phase_mon/PS_max_reg[6]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh1A8 J arrival timeXh56, JXh1 JslackXhE-@   txWordclkl8_3 txWordclkl8_3!)]_ff@1]_ff @9A]_ff@I]_ff @e]@hq}{=O]@XX rise - rise rise - rise  {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/CnjngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D*:BJZj7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu;F>}VNi`e<ף0?i?{=B W=?=f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})h(rising edge-triggered cell SRL16E clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q Prop_fdre_C_Q JFDREXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/dest_out Jnet (fo=1, routed)Xh?= njngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D JSRL16EXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhף0? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhi? plngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK JSRL16EXhzr; Jclock pessimismXhB W lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3Hold_srl16e_CLK_D JSRL16EXha=, JXh9 J required timeXhVN8 J arrival timeXhfEb?, JXh1 JslackXh{= QMngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu >} K@5~>?@5~?=|=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) QMngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= KGngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= QMngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh>? QMngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr C?ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk Jnet (fo=221, routed)Xh@5~? QMngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXh| OKngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh K8 J arrival timeXhf?, JXh1 JslackXh=i {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C{ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu >}<iף0?i?=D`e=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhף0? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xhi? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhD`e }yngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXh<8 J arrival timeXhJX?, JXh1 JslackXh= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu >}lGXyZd;?Xy?=w=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhZd;? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)XhXy? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhw ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhlG8 J arrival timeXh c?, JXh1 JslackXh=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C|xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D*:BJZ(LUT6=1)j7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsui>}Jr=ju<ף0?r=j?mS>B Wo>]g=f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[18] Jnet (fo=1, routed)Xh]g= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__9/I2 JXhzr {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__9/OProp_lut6_I2_O JLUT6XhzrA`< }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__9_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhף0? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhr=j? |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C JFDCEXhzr; Jclock pessimismXhB W zvngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhJ8 J arrival timeXh_k?, JXh1 JslackXhmS>* FBngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/CFBngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu1>}Je;@?e;?>|=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) FBngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @s ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu1>}UEy";?y?>w=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh";? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xhy? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C JFDREXhzr; Jclock pessimismXhw ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXhUE8 J arrival timeXhdg?, JXh1 JslackXh>zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[86]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D*:BJZ(LUT6=1)j7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu>}NbPr=jt=a0?r=j?~9 >@o>>f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[86]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[6] Jnet (fo=1, routed)Xh> {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__9/I0 JXhzr ~zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__9/OProp_lut6_I0_O JLUT6XhzrA`< |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__9_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xha0? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[86]/C JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhr=j? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C JFDCEXhzr; Jclock pessimismXh@ yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhNbP8 J arrival timeXhps?, JXh1 JslackXh~9 > -)ngFEC/g_pm[7].phase_mon/inh_cntr_reg[0]/C-)ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2]/D*:BJZ(LUT5=1)j7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsuIg>}T@5~}94<>?@5~? >q>&=f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR)q -)ngFEC/g_pm[7].phase_mon/inh_cntr_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr=p 0,ngFEC/g_pm[7].phase_mon/inh_cntr_reg_n_0_[0] Jnet (fo=5, routed)Xh&=\ 1-ngFEC/g_pm[7].phase_mon/inh_cntr[2]_i_1__5/I3 JXhzru 0,ngFEC/g_pm[7].phase_mon/inh_cntr[2]_i_1__5/OProp_lut5_I3_O JLUT5Xhzr<h ($ngFEC/g_pm[7].phase_mon/p_0_in__0[2] Jnet (fo=1, routed)Xh\ -)ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2]/D JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh>?\ -)ngFEC/g_pm[7].phase_mon/inh_cntr_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh@5~?\ -)ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2]/C JFDPEXhzr; Jclock pessimismXhql +'ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2] Hold_fdpe_C_D JFDPEXh=, JXh9 J required timeXhT8 J arrival timeXhx?, JXh1 JslackXh >zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D*:BJZ(LUT6=1)j7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsu\>}Jr=j`e<a0?r=j?K>B W >=f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_3 txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q Prop_fdce_C_Q JFDCEXhzr5^= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[1] Jnet (fo=1, routed)Xh= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__9/I0 JXhzr ~zngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__9/OProp_lut6_I0_O JLUT6Xhzr+= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__9_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xha0? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhr=j? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzr; Jclock pessimismXhB W yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhJ8 J arrival timeXhjq?, JXh1 JslackXhK>+'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C,(ngFEC/g_pm[7].phase_mon/PS_min_reg[9]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsuI6@}33AAff@/ݼ֣?ff?33A=А=]@E6>TE?z?f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] Jnet (fo=3, routed)XhQ ?[ 0,ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/I0 JXhzrt /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/S[0] JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrl{>t 40ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CI JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[7].phase_mon/ltOp Jnet (fo=1, routed)XhE?Z /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/I2 JXhzrs .*ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[7].phase_mon/PS_min Jnet (fo=10, routed)Xh4W ?[ ,(ngFEC/g_pm[7].phase_mon/PS_min_reg[9]/CE JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh֣?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xhff?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[9]/C JFDPEXhzr; Jclock pessimismXhE6>= Jclock uncertaintyXhl )%ngFEC/g_pm[7].phase_mon/PS_min_reg[9]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXhā, JXh1 JslackXh]@ +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C,(ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu!@}33AA𧶿֣??33A=А=S@1O>TE??f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] Jnet (fo=3, routed)XhQ ?[ 0,ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/I0 JXhzrt /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/S[0] JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrl{>t 40ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CI JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[7].phase_mon/ltOp Jnet (fo=1, routed)XhE?Z /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/I2 JXhzrs .*ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[7].phase_mon/PS_min Jnet (fo=10, routed)Xh?[ ,(ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/CE JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh֣?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C JFDPEXhzr; Jclock pessimismXh1O>= Jclock uncertaintyXhl )%ngFEC/g_pm[7].phase_mon/PS_min_reg[1]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhS@ +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C,(ngFEC/g_pm[7].phase_mon/PS_min_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu!@}33AA𧶿֣??33A=А=S@1O>TE??f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] Jnet (fo=3, routed)XhQ ?[ 0,ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/I0 JXhzrt /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/S[0] JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrl{>t 40ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CI JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[7].phase_mon/ltOp Jnet (fo=1, routed)XhE?Z /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/I2 JXhzrs .*ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[7].phase_mon/PS_min Jnet (fo=10, routed)Xh?[ ,(ngFEC/g_pm[7].phase_mon/PS_min_reg[5]/CE JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh֣?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[5]/C JFDPEXhzr; Jclock pessimismXh1O>= Jclock uncertaintyXhl )%ngFEC/g_pm[7].phase_mon/PS_min_reg[5]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXhS@ +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C,(ngFEC/g_pm[7].phase_mon/PS_min_reg[4]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu7@}33AA+%Լ֣?+?33A=А= @E6>TE??f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] Jnet (fo=3, routed)XhQ ?[ 0,ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/I0 JXhzrt /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/S[0] JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrl{>t 40ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CI JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[7].phase_mon/ltOp Jnet (fo=1, routed)XhE?Z /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/I2 JXhzrs .*ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[7].phase_mon/PS_min Jnet (fo=10, routed)Xh>[ ,(ngFEC/g_pm[7].phase_mon/PS_min_reg[4]/CE JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh֣?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh+?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[4]/C JFDPEXhzr; Jclock pessimismXhE6>= Jclock uncertaintyXhl )%ngFEC/g_pm[7].phase_mon/PS_min_reg[4]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh"~, JXh1 JslackXh @ +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C,(ngFEC/g_pm[7].phase_mon/PS_min_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu7@}33AA+%Լ֣?+?33A=А= @E6>TE??f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] Jnet (fo=3, routed)XhQ ?[ 0,ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/I0 JXhzrt /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/S[0] JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrl{>t 40ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CI JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[7].phase_mon/ltOp Jnet (fo=1, routed)XhE?Z /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/I2 JXhzrs .*ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[7].phase_mon/PS_min Jnet (fo=10, routed)Xh>[ ,(ngFEC/g_pm[7].phase_mon/PS_min_reg[6]/CE JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh֣?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh+?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[6]/C JFDPEXhzr; Jclock pessimismXhE6>= Jclock uncertaintyXhl )%ngFEC/g_pm[7].phase_mon/PS_min_reg[6]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh"~, JXh1 JslackXh @ +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C,(ngFEC/g_pm[7].phase_mon/PS_min_reg[7]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu7@}33AA+%Լ֣?+?33A=А= @E6>TE??f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzrZd>n .*ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] Jnet (fo=3, routed)XhQ ?[ 0,ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/I0 JXhzrt /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/S[0] JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzrl{>t 40ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CI JXhzr 62ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0]Prop_carry4_CI_CO[0] JCARRY4Xhzr'1>` ngFEC/g_pm[7].phase_mon/ltOp Jnet (fo=1, routed)XhE?Z /+ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/I2 JXhzrs .*ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/OProp_lut5_I2_O JLUT5Xhzro>c "ngFEC/g_pm[7].phase_mon/PS_min Jnet (fo=10, routed)Xh>[ ,(ngFEC/g_pm[7].phase_mon/PS_min_reg[7]/CE JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh֣?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C JFDPEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh+?Z +'ngFEC/g_pm[7].phase_mon/PS_min_reg[7]/C JFDPEXhzr; Jclock pessimismXhE6>= Jclock uncertaintyXhl )%ngFEC/g_pm[7].phase_mon/PS_min_reg[7]Setup_fdpe_C_CE JFDPEXhM, JXh9 J required timeXhA8 J arrival timeXh"~, JXh1 JslackXh @ lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5]/CE*:BJZ(LUT2=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu8@}33A/oA/ݴT?/ݴ?33A=А=̏@X9=η>}?f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q Prop_fdre_C_Q JFDREXhzrq> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] Jnet (fo=5, routed)Xhq> xtngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/I0 JXhzr wsngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/OProp_lut2_I0_O JLUT2Xhzrl= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 Jnet (fo=119, routed)Xh}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5]/CE JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh/ݴ? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5]/C JFDCEXhzr; Jclock pessimismXhX9== Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh/oA8 J arrival timeXh#r, JXh1 JslackXh̏@wlhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/CE*:BJZ(LUT2=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu8@}33A/oA/ݴT?/ݴ?33A=А=̏@X9=η>}?f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q Prop_fdre_C_Q JFDREXhzrq> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] Jnet (fo=5, routed)Xhq> xtngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/I0 JXhzr wsngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/OProp_lut2_I0_O JLUT2Xhzrl= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 Jnet (fo=119, routed)Xh}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/CE JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh/ݴ? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/C JFDCEXhzr; Jclock pessimismXhX9== Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh/oA8 J arrival timeXh#r, JXh1 JslackXh̏@wlhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75]/CE*:BJZ(LUT2=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu8@}33A/oA/ݴT?/ݴ?33A=А=̏@X9=η>}?f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q Prop_fdre_C_Q JFDREXhzrq> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] Jnet (fo=5, routed)Xhq> xtngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/I0 JXhzr wsngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/OProp_lut2_I0_O JLUT2Xhzrl= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 Jnet (fo=119, routed)Xh}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75]/CE JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh/ݴ? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75]/C JFDCEXhzr; Jclock pessimismXhX9== Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh/oA8 J arrival timeXh#r, JXh1 JslackXh̏@wlhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]/CE*:BJZ(LUT2=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu8@}33A/oA/ݴT?/ݴ?33A=А=̏@X9=η>}?f(rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_3 txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q Prop_fdre_C_Q JFDREXhzrq> c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] Jnet (fo=5, routed)Xhq> xtngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/I0 JXhzr wsngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/OProp_lut2_I0_O JLUT2Xhzrl= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 Jnet (fo=119, routed)Xh}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]/CE JFDCEXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh? lhngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C JFDREXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh/ݴ? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]/C JFDCEXhzr; Jclock pessimismXhX9== Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh/oA8 J arrival timeXh#r, JXh1 JslackXh̏@w  txWordclkl8_4 txWordclkl8_4!)]_ff@1]_ff @9A]_ff@I]_ff @e.@hq}=O]@YY rise - rise rise - rise  ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[109]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D*:BJZ(LUT6=1)j7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsu9>}M#r}94<j4?#r?=Klo>GB[=f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[109]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data5[9] Jnet (fo=1, routed)XhGB[= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__10/I2 JXhzr {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__10/OProp_lut6_I2_O JLUT6XhzrA`< }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__10_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhj4? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[109]/C JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh#r? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C JFDCEXhzr; Jclock pessimismXhKl yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhM8 J arrival timeXh*5c?, JXh1 JslackXh=ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[110]/C|xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/D*:BJZ(LUT6=1)j7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsuK;>}M#r}94<j4?#r?W*=Klo>nsc=f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[110]/Q Prop_fdce_C_Q JFDCEXhzr= ^ZngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data5[10] Jnet (fo=1, routed)Xhnsc= }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[10]_i_1__10/I2 JXhzr |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[10]_i_1__10/OProp_lut6_I2_O JLUT6XhzrA`< ~ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[10]_i_1__10_n_0 Jnet (fo=1, routed)Xh |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/D JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhj4? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[110]/C JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh#r? |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C JFDCEXhzr; Jclock pessimismXhKl zvngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10] Hold_fdce_C_D JFDCEXh-=, JXh9 J required timeXhM8 J arrival timeXh=c?, JXh1 JslackXhW*= QMngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/CQMngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsu >}Hl{}%As4?s?=t{=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) FBngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= @}Gts}94<}?5?ts?W=jmo>xD\=f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data4[0] Jnet (fo=1, routed)XhxD\= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__10/I0 JXhzr {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__10/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__10_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh}?5? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhts? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C JFDCEXhzr; Jclock pessimismXhjm yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] Hold_fdce_C_D JFDCEXh$y=, JXh9 J required timeXhG8 J arrival timeXh_c?, JXh1 JslackXhW=~ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D*:BJZ(LUT6=1)j7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsum@;>}lGts}94<}?5?ts?a=jmo>`=f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data4[1] Jnet (fo=1, routed)Xh`= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__10/I0 JXhzr {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__10/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__10_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh}?5? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhts? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C JFDCEXhzr; Jclock pessimismXhjm yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] Hold_fdce_C_D JFDCEXhu=, JXh9 J required timeXhlG8 J arrival timeXhd?, JXh1 JslackXha=i {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C{ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D*:BJZj7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsu1>}>-rX94?-r?>w=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q Prop_fdre_C_Q JFDREXhzr= yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] Jnet (fo=1, routed)Xh`= {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D JFDREXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)XhX94? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C JFDREXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr qmngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk Jnet (fo=221, routed)Xh-r? {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C JFDREXhzr; Jclock pessimismXhw }yngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] Hold_fdre_C_D JFDREXh2,=, JXh9 J required timeXh>8 J arrival timeXhA{`?, JXh1 JslackXh> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D*:BJZj7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsu1>}lGzw=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D JFDREXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in Jnet (fo=221, routed)Xhs ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D*:BJZj7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsu1>}GIzw=`=f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q Prop_fdre_C_Q JFDREXhzr= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 Jnet (fo=1, routed)Xh`= ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D JFDREXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in Jnet (fo=221, routed)Xh~ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C{wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D*:BJZ(LUT6=1)j7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsuWX>}Gts}94<}?5?ts?3>jmo>G=f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast txWordclkl8_4 txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/Q Prop_fdce_C_Q JFDCEXhzr= ]YngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data4[7] Jnet (fo=1, routed)XhG= |ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__10/I0 JXhzr {ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__10/OProp_lut6_I0_O JLUT6XhzrA`< }ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__10_n_0 Jnet (fo=1, routed)Xh {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xh}?5? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)Xhts? {wngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C JFDCEXhzr; Jclock pessimismXhjm yungFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] Hold_fdce_C_D JFDCEXh$y=, JXh9 J required timeXhG8 J arrival timeXhaUk?, JXh1 JslackXh3>+'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[1]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsuj4@}33AAVN ׽(\?V?33A=А=.@>kT?v?f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)Xhұ>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/I2 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[0] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)XhP?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[1]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh(\?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhV?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[1]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[1]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXhI , JXh1 JslackXh.@ +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[2]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsuj4@}33AAVN ׽(\?V?33A=А=.@>kT?v?f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)Xhұ>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/I2 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[0] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)XhP?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[2]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh(\?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhV?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[2]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[2]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXhI , JXh1 JslackXh.@ +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsuj4@}33AAVN ׽(\?V?33A=А=.@>kT?v?f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)Xhұ>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/I2 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[0] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)XhP?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh(\?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhV?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[3]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXhI , JXh1 JslackXh.@ +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[4]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsuj4@}33AAVN ׽(\?V?33A=А=.@>kT?v?f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)Xhұ>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/I2 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[0] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)XhP?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[4]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh(\?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhV?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[4]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[4]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXhI , JXh1 JslackXh.@ +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[6]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsuj4@}33AAVN ׽(\?V?33A=А=.@>kT?v?f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)Xhұ>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/I2 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[0] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)XhP?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[6]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh(\?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhV?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[6]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[6]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXhI , JXh1 JslackXh.@ +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[9]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsu,$@}33AA>5ٽ(\?>5?33A=А=@>kT??f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] Jnet (fo=3, routed)Xhұ>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/I2 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[0] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[0]_CO[3] JCARRY4Xhzr>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)Xh?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[9]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh(\?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh>5?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[9]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[9]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXh}, JXh1 JslackXh@ +'ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsup'@}33AA`;%1??33A=А=@>V?|?f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[3] Jnet (fo=3, routed)Xhi.>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6/I0 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[1] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[1]_CO[3] JCARRY4Xhzr:>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)Xh/?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh%1?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[0]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXhą, JXh1 JslackXh@ +'ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C,(ngFEC/g_pm[8].phase_mon/PS_min_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsup'@}33AA`;%1??33A=А=@>V?|?f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/Q Prop_fdpe_C_Q JFDPEXhzr>n .*ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[3] Jnet (fo=3, routed)Xhi.>[ 0,ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6/I0 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6/OProp_lut4_I0_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/S[1] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3]Prop_carry4_S[1]_CO[3] JCARRY4Xhzr:>t 40ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/ltOp Jnet (fo=1, routed)Xh4?Z /+ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_min Jnet (fo=10, routed)Xh/?[ ,(ngFEC/g_pm[8].phase_mon/PS_min_reg[5]/CE JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh%1?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C JFDPEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)Xh?Z +'ngFEC/g_pm[8].phase_mon/PS_min_reg[5]/C JFDPEXhzr; Jclock pessimismXh>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_min_reg[5]Setup_fdpe_C_CE JFDPEXhE6, JXh9 J required timeXhA8 J arrival timeXhą, JXh1 JslackXh@ ) |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/CngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[8]*:BJZj7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsu8T@}33A7uAT࿭6>B`?T?33A=А=B@Q=> @f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/Q Prop_fdce_C_Q JFDCEXhzr> ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[10] Jnet (fo=1, routed)Xh @ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[8] J GTXE2_CHANNELXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK Jnet (fo=221, routed)XhB`? |xngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhT? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh |xngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i'Setup_gtxe2_channel_TXUSRCLK2_TXDATA[8] J GTXE2_CHANNELXh+־, JXh9 J required timeXh7uA8 J arrival timeXh-, JXh1 JslackXhB@+'ngFEC/g_pm[8].phase_mon/PS_max_reg[2]/C,(ngFEC/g_pm[8].phase_mon/PS_max_reg[5]/CE*:BJZ(CARRY4=2 LUT4=1 LUT5=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsu@}33A>AKbG?K?33A=А=ү@$^:>hM?&?f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})f(rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow txWordclkl8_4 txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) o +'ngFEC/g_pm[8].phase_mon/PS_max_reg[2]/Q Prop_fdce_C_Q JFDCEXhzrZd>n .*ngFEC/g_pm[8].phase_mon/PS_max_reg_n_0_[2] Jnet (fo=3, routed)Xhf9?[ 0,ngFEC/g_pm[8].phase_mon/PS_max[9]_i_13__6/I2 JXhzrt /+ngFEC/g_pm[8].phase_mon/PS_max[9]_i_13__6/OProp_lut4_I2_O JLUT4Xhzr 0=q 1-ngFEC/g_pm[8].phase_mon/PS_max[9]_i_13__6_n_0 Jnet (fo=1, routed)Xh` 51ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_4__3/S[1] JXhzr 62ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_4__3/CO[3]Prop_carry4_S[1]_CO[3] JCARRY4Xhzr:>t 40ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_4__3_n_0 Jnet (fo=1, routed)Xh^ 3/ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_2__3/CI JXhzr 62ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_2__3/CO[0]Prop_carry4_CI_CO[0] JCARRY4XhzrV>` ngFEC/g_pm[8].phase_mon/gtOp Jnet (fo=1, routed)XhF ?Z /+ngFEC/g_pm[8].phase_mon/PS_max[9]_i_1__6/I2 JXhzrs .*ngFEC/g_pm[8].phase_mon/PS_max[9]_i_1__6/OProp_lut5_I2_O JLUT5Xhzr$>c "ngFEC/g_pm[8].phase_mon/PS_max Jnet (fo=10, routed)Xh ?[ ,(ngFEC/g_pm[8].phase_mon/PS_max_reg[5]/CE JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhG?Z +'ngFEC/g_pm[8].phase_mon/PS_max_reg[2]/C JFDCEXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzro -)ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] Jnet (fo=221, routed)XhK?Z +'ngFEC/g_pm[8].phase_mon/PS_max_reg[5]/C JFDCEXhzr; Jclock pessimismXh$^:>= Jclock uncertaintyXhl )%ngFEC/g_pm[8].phase_mon/PS_max_reg[5]Setup_fdce_C_CE JFDCEXhM, JXh9 J required timeXh>A8 J arrival timeXhc, JXh1 JslackXhү@  clk62_5_ub clk125_ub!)@1/@9A@I@epO@hq} =:9 rise - rise rise - rise  73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[6]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsu?}E T>?@:>А= == =$5^=H>d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[6]/Q Prop_fdre_C_Q JFDREXhzr5^=q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[6] Jnet (fo=1, routed)XhH>i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)XhNb0?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[6]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhxi?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>y 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6] Hold_fdre_C_D JFDREXhk<, JXh9 J required timeXhE 8 J arrival timeXhE@, JXh1 JslackXh =73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[2]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsu?}ߏT>?@:>А= ==Z=$=)?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[2]/Q Prop_fdre_C_Q JFDREXhzr=q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[2] Jnet (fo=1, routed)Xh)?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)XhNb0?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[2]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhxi?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>y 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2] Hold_fdre_C_D JFDREXh+=, JXh9 J required timeXhߏ8 J arrival timeXh@, JXh1 JslackXhZ=:6sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[0]/C=9sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsuU?}@re>?r@:>А= ===$=2?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[0]/Q Prop_fdre_C_Q JFDREXhzr=w 73sys/eth/phy/U0/transceiver_inst/rxcharisk_reg__0[0] Jnet (fo=1, routed)Xh2?l =9sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)XhMb0?i :6sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[0]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?l =9sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>| ;7sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0] Hold_fdre_C_D JFDREXh+=, JXh9 J required timeXh@8 J arrival timeXh>'@, JXh1 JslackXh=73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[9]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsu?} rb>?r@:>А= ==)=$5^=?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[9]/Q Prop_fdre_C_Q JFDREXhzr5^=q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[9] Jnet (fo=1, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)XhNb0?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[9]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>y 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9] Hold_fdre_C_D JFDREXht<, JXh9 J required timeXh 8 J arrival timeXhB@, JXh1 JslackXh)=:6sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/C=9sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsu?}@rT>Y?r@:>А= ===$=4??d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=w 73sys/eth/phy/U0/transceiver_inst/rxcharisk_reg__0[1] Jnet (fo=1, routed)Xh4??l =9sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhף0?i :6sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?l =9sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>| ;7sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1] Hold_fdre_C_D JFDREXh+=, JXh9 J required timeXh@8 J arrival timeXh`X@, JXh1 JslackXh=>:sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[0]/CA=sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsu>?}ޏrT>Y?r@:>А= ===$=?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[0]/Q Prop_fdre_C_Q JFDREXhzr={ ;7sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg__0[0] Jnet (fo=1, routed)Xh?p A=sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhף0?m >:sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[0]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?p A=sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:> ?;sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0] Hold_fdre_C_D JFDREXho=, JXh9 J required timeXhޏ8 J arrival timeXh@, JXh1 JslackXh==9sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[1]/C@Y?r@:>А= ==s=$5^=!?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) =9sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[1]/Q Prop_fdre_C_Q JFDREXhzr5^=z :6sys/eth/phy/U0/transceiver_inst/rxnotintable_reg__0[1] Jnet (fo=1, routed)Xh!?o @Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhף0?l =9sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[1]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?o @ >:sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[1] Hold_fdre_C_D JFDREXhT<, JXh9 J required timeXhX8 J arrival timeXhf}@, JXh1 JslackXhs=:6sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[1]/C=9sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsu?} rT>Y?r@:>А= ==<=$5^=+O?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[1]/Q Prop_fdre_C_Q JFDREXhzr5^=w 73sys/eth/phy/U0/transceiver_inst/rxdisperr_reg__0[1] Jnet (fo=1, routed)Xh+O?l =9sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhף0?i :6sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[1]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?l =9sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>| ;7sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1] Hold_fdre_C_D JFDREXht<, JXh9 J required timeXh 8 J arrival timeXhH@, JXh1 JslackXh<=:6sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[0]/C=9sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsu#?}yTre>?r@:>А= ===$=3k ?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[0]/Q Prop_fdre_C_Q JFDREXhzr=w 73sys/eth/phy/U0/transceiver_inst/rxdisperr_reg__0[0] Jnet (fo=1, routed)Xh3k ?l =9sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)XhMb0?i :6sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[0]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?l =9sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>| ;7sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0] Hold_fdre_C_D JFDREXhX94=, JXh9 J required timeXhyT8 J arrival timeXh@, JXh1 JslackXh=73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[4]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4]/D*:BJZj0clk125_ub rise@0.000ns - clk62_5_ub rise@0.000nsuW"?}rb>?r@:>А= ===$=^ ?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[4]/Q Prop_fdre_C_Q JFDREXhzr=q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[4] Jnet (fo=1, routed)Xh^ ?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)XhNb0?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[4]/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh_i?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>y 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4] Hold_fdre_C_D JFDREXh #=, JXh9 J required timeXh8 J arrival timeXh@, JXh1 JslackXh=73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsu=?}A<MAŸO@Ÿ@A:>А= ==pO@o_?Zd>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/Q Prop_fdre_C_Q JFDREXhzrZd>q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[0] Jnet (fo=1, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhk?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:z 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0]Setup_fdre_C_D JFDREXhY9, JXh9 J required timeXh<MA8 J arrival timeXh , JXh1 JslackXhpO@73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsu@m?}AKAҍ@@A:>А= ==@o_?aP>P?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/Q Prop_fdre_C_Q JFDREXhzraP>q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[7] Jnet (fo=1, routed)XhP?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:z 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7]Setup_fdre_C_D JFDREXhX9, JXh9 J required timeXhKA8 J arrival timeXh`, JXh1 JslackXh@<8sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C2.sys/eth/phy/U0/transceiver_inst/txbuferr_reg/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsu9Ԩ?}AnMA&ɄO@&Ʉ@A:>А= ==i@o_?Zd>H?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) <8sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/Q Prop_fdre_C_Q JFDREXhzrZd>v 62sys/eth/phy/U0/transceiver_inst/txbufstatus_reg[1] Jnet (fo=1, routed)XhH?a 2.sys/eth/phy/U0/transceiver_inst/txbuferr_reg/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh?k <8sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?a 2.sys/eth/phy/U0/transceiver_inst/txbuferr_reg/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:r 0,sys/eth/phy/U0/transceiver_inst/txbuferr_regSetup_fdre_C_D JFDREXhY9, JXh9 J required timeXhnMA8 J arrival timeXh, JXh1 JslackXhi@84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[12]/C;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsu?}A]MAŸO@Ÿ@A:>А= ==7@o_?Zd>p?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)| 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[12]/Q Prop_fdre_C_Q JFDREXhzrZd>r 2.sys/eth/phy/U0/transceiver_inst/rxdata_reg[12] Jnet (fo=1, routed)Xhp?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?g 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[12]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhk?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:{ 95sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12]Setup_fdre_C_D JFDREXh5<, JXh9 J required timeXh]MA8 J arrival timeXh, JXh1 JslackXh7@=9sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[0]/C@А= =="@o_?aP>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[0]/Q Prop_fdre_C_Q JFDREXhzraP>z :6sys/eth/phy/U0/transceiver_inst/rxnotintable_reg__0[0] Jnet (fo=1, routed)Xh?o @:sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[0]Setup_fdre_C_D JFDREXh7^, JXh9 J required timeXhKA8 J arrival timeXh , JXh1 JslackXh"@84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[13]/C;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsu?}AvMAŸO@Ÿ@A:>А= ==4$@o_?Zd>[?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)| 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[13]/Q Prop_fdre_C_Q JFDREXhzrZd>r 2.sys/eth/phy/U0/transceiver_inst/rxdata_reg[13] Jnet (fo=1, routed)Xh[?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?g 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[13]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhk?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:{ 95sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13]Setup_fdre_C_D JFDREXh[9<, JXh9 J required timeXhvMA8 J arrival timeXhh, JXh1 JslackXh4$@73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsuc?}AoELAŸO@Ÿ@A:>А= ==5~@o_?aP>?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/Q Prop_fdre_C_Q JFDREXhzraP>q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[5] Jnet (fo=1, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhk?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:z 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5]Setup_fdre_C_D JFDREXht, JXh9 J required timeXhoELA8 J arrival timeXh , JXh1 JslackXh5~@84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/C;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsu{M?}AcCMAҍ@@A:>А= ==׭@o_?Zd>9ˆ?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)| 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/Q Prop_fdre_C_Q JFDREXhzrZd>r 2.sys/eth/phy/U0/transceiver_inst/rxdata_reg[15] Jnet (fo=1, routed)Xh9ˆ?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?g 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:{ 95sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15]Setup_fdre_C_D JFDREXht, JXh9 J required timeXhcCMA8 J arrival timeXh, JXh1 JslackXh׭@84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/C;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsug?}AcCMAŸO@Ÿ@A:>А= ==@o_?Zd>%?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)| 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/Q Prop_fdre_C_Q JFDREXhzrZd>r 2.sys/eth/phy/U0/transceiver_inst/rxdata_reg[11] Jnet (fo=1, routed)Xh%?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?g 84sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhk?j ;7sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:{ 95sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11]Setup_fdre_C_D JFDREXh#, JXh9 J required timeXhcCMA8 J arrival timeXh, JXh1 JslackXh@73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[3]/C:6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3]/D*:BJZj0clk125_ub rise@8.000ns - clk62_5_ub rise@0.000nsu?}ASKAҍ@@A:>А= ==@o_?aP>~?d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk62_5_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR){ 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[3]/Q Prop_fdre_C_Q JFDREXhzraP>q 1-sys/eth/phy/U0/transceiver_inst/rxdata_reg[3] Jnet (fo=1, routed)Xh~?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3]/D JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrkY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk62_5_buf/I JXhzr` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzrv=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh+?f 73sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[3]/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:z 84sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3]Setup_fdre_C_D JFDREXhv, JXh9 J required timeXhSKA8 J arrival timeXh, JXh1 JslackXh@  clk_ipb_ub clk125_ub!)/@1?@9A@I@ej?hq}d:i=;9 rise - rise rise - rise  j!sys/ip_mac/ip_addr_o_reg[6]/C-)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu?} A>mr?A@.A>А===d:i=$R>|1>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)e !sys/ip_mac/ip_addr_o_reg[6]/Q Prop_fdce_C_Q JFDCEXhzr5^=q 1-sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[6] Jnet (fo=1, routed)Xh|1>Y .*sys/ipb/udp_if/IPADDR/My_IP_addr[6]_i_1/I4 JXhzrr -)sys/ipb/udp_if/IPADDR/My_IP_addr[6]_i_1/OProp_lut6_I4_O JLUT6Xhzro=o /+sys/ipb/udp_if/IPADDR/My_IP_addr[6]_i_1_n_0 Jnet (fo=1, routed)Xh\ -)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xh ?P !sys/ip_mac/ip_addr_o_reg[6]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)XhY?\ -)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>l +'sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6] Hold_fdre_C_D JFDREXh$y=, JXh9 J required timeXh 8 J arrival timeXhj@, JXh1 JslackXhd:i=j!sys/ip_mac/ip_addr_o_reg[9]/C-)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu?}*" j 0>ӭ?j @.A>А===b:m=$o>x>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)e !sys/ip_mac/ip_addr_o_reg[9]/Q Prop_fdce_C_Q JFDCEXhzr=q 1-sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[9] Jnet (fo=1, routed)Xhx>Y .*sys/ipb/udp_if/IPADDR/My_IP_addr[9]_i_1/I4 JXhzrr -)sys/ipb/udp_if/IPADDR/My_IP_addr[9]_i_1/OProp_lut6_I4_O JLUT6XhzrA`<o /+sys/ipb/udp_if/IPADDR/My_IP_addr[9]_i_1_n_0 Jnet (fo=1, routed)Xh\ -)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xhv?P !sys/ip_mac/ip_addr_o_reg[9]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xh? W?\ -)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>l +'sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9] Hold_fdre_C_D JFDREXh$y=, JXh9 J required timeXh*" 8 J arrival timeXh@, JXh1 JslackXhb:m=u"sys/ip_mac/ip_addr_o_reg[19]/C.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsuUn?})"   > ? @.A>А=== _p=$>)>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)f "sys/ip_mac/ip_addr_o_reg[19]/Q Prop_fdce_C_Q JFDCEXhzr=r 2.sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[19] Jnet (fo=1, routed)Xh)>Z /+sys/ipb/udp_if/IPADDR/My_IP_addr[19]_i_1/I4 JXhzrs .*sys/ipb/udp_if/IPADDR/My_IP_addr[19]_i_1/OProp_lut6_I4_O JLUT6XhzrA`<p 0,sys/ipb/udp_if/IPADDR/My_IP_addr[19]_i_1_n_0 Jnet (fo=1, routed)Xh] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xhd;?Q "sys/ip_mac/ip_addr_o_reg[19]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)XhKW?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>m ,(sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXh)" 8 J arrival timeXh@, JXh1 JslackXh _p=u"sys/ip_mac/ip_addr_o_reg[25]/C.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu1?} j 0>ӭ?j @.A>А===uct=$o>$>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)f "sys/ip_mac/ip_addr_o_reg[25]/Q Prop_fdce_C_Q JFDCEXhzr=r 2.sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[25] Jnet (fo=1, routed)Xh$>Z /+sys/ipb/udp_if/IPADDR/My_IP_addr[25]_i_1/I4 JXhzrs .*sys/ipb/udp_if/IPADDR/My_IP_addr[25]_i_1/OProp_lut6_I4_O JLUT6XhzrA`<p 0,sys/ipb/udp_if/IPADDR/My_IP_addr[25]_i_1_n_0 Jnet (fo=1, routed)Xh] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xhv?Q "sys/ip_mac/ip_addr_o_reg[25]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xh? W?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>m ,(sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXh 8 J arrival timeXhU@, JXh1 JslackXhuct=u"sys/ip_mac/ip_addr_o_reg[22]/C.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsun1"?}oA>mr?A@.A>А===oeu=$o>l?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)f "sys/ip_mac/ip_addr_o_reg[22]/Q Prop_fdce_C_Q JFDCEXhzr=r 2.sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[22] Jnet (fo=1, routed)Xhl?Z /+sys/ipb/udp_if/IPADDR/My_IP_addr[22]_i_1/I4 JXhzrs .*sys/ipb/udp_if/IPADDR/My_IP_addr[22]_i_1/OProp_lut6_I4_O JLUT6XhzrA`<p 0,sys/ipb/udp_if/IPADDR/My_IP_addr[22]_i_1_n_0 Jnet (fo=1, routed)Xh] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xh ?Q "sys/ip_mac/ip_addr_o_reg[22]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)XhY?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>m ,(sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXho8 J arrival timeXhE@, JXh1 JslackXhoeu=u"sys/ip_mac/ip_addr_o_reg[30]/C.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu?} A>Q?A@.A>А===Wy=$o>\>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)f "sys/ip_mac/ip_addr_o_reg[30]/Q Prop_fdce_C_Q JFDCEXhzr=r 2.sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[30] Jnet (fo=1, routed)Xh\>Z /+sys/ipb/udp_if/IPADDR/My_IP_addr[30]_i_1/I4 JXhzrs .*sys/ipb/udp_if/IPADDR/My_IP_addr[30]_i_1/OProp_lut6_I4_O JLUT6XhzrA`<p 0,sys/ipb/udp_if/IPADDR/My_IP_addr[30]_i_1_n_0 Jnet (fo=1, routed)Xh] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xhw?Q "sys/ip_mac/ip_addr_o_reg[30]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)XhY?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>m ,(sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXh 8 J arrival timeXhH@, JXh1 JslackXhWy=u"sys/ip_mac/ip_addr_o_reg[13]/C.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsuU?}c V>F >0?V>@.A>А===*z=$o>r'>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)f "sys/ip_mac/ip_addr_o_reg[13]/Q Prop_fdce_C_Q JFDCEXhzr=r 2.sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[13] Jnet (fo=1, routed)Xhr'>Z /+sys/ipb/udp_if/IPADDR/My_IP_addr[13]_i_1/I4 JXhzrs .*sys/ipb/udp_if/IPADDR/My_IP_addr[13]_i_1/OProp_lut6_I4_O JLUT6XhzrA`<p 0,sys/ipb/udp_if/IPADDR/My_IP_addr[13]_i_1_n_0 Jnet (fo=1, routed)Xh] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xh|?Q "sys/ip_mac/ip_addr_o_reg[13]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)XhQX?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>m ,(sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXhc 8 J arrival timeXhN@, JXh1 JslackXh*z=#sys/ip_mac/mac_addr_o_reg[44]/C73sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124]/D*:BJZ(LUT3=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu!?} i  ף>Y?i @.A>А===Gā=$ >5>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)g #sys/ip_mac/mac_addr_o_reg[44]/Q Prop_fdce_C_Q JFDCEXhzr5^=y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[44] Jnet (fo=8, routed)Xh5>a 62sys/ipb/udp_if/rx_reset_block/pkt_data[124]_i_1/I0 JXhzrz 51sys/ipb/udp_if/rx_reset_block/pkt_data[124]_i_1/OProp_lut3_I0_O JLUT3Xhzr+=i )%sys/ipb/udp_if/rx_packet_parser/D[68] Jnet (fo=1, routed)Xhf 73sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xh?R #sys/ip_mac/mac_addr_o_reg[44]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xh> W?f 73sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>v 51sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXh 8 J arrival timeXh@, JXh1 JslackXhGā=#sys/ip_mac/mac_addr_o_reg[33]/C40sys/ipb/udp_if/RARP_block/data_buffer_reg[153]/D*:BJZ(LUT4=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu_"?})" i Z>9?i @.A>А===3=$o>?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)g #sys/ip_mac/mac_addr_o_reg[33]/Q Prop_fdce_C_Q JFDCEXhzr=w 73sys/ipb/udp_if/RARP_block/data_buffer_reg[87]_0[33] Jnet (fo=8, routed)Xh?` 51sys/ipb/udp_if/RARP_block/data_buffer[153]_i_1/I1 JXhzry 40sys/ipb/udp_if/RARP_block/data_buffer[153]_i_1/OProp_lut4_I1_O JLUT4XhzrA`<s 3/sys/ipb/udp_if/RARP_block/data_buffer0_out[145] Jnet (fo=1, routed)Xhc 40sys/ipb/udp_if/RARP_block/data_buffer_reg[153]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)XhP?R #sys/ip_mac/mac_addr_o_reg[33]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<v 3/sys/ipb/udp_if/RARP_block/rarp_req_reg_rep__0_0 Jnet (fo=4650, routed)Xh> W?c 40sys/ipb/udp_if/RARP_block/data_buffer_reg[153]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>s 2.sys/ipb/udp_if/RARP_block/data_buffer_reg[153] Hold_fdre_C_D JFDREXh$y=, JXh9 J required timeXh)" 8 J arrival timeXh?@, JXh1 JslackXh3=u"sys/ip_mac/ip_addr_o_reg[17]/C.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17]/D*:BJZ(LUT6=1)j0clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu?} j > ?j @.A>А===g&=$>>e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)f "sys/ip_mac/ip_addr_o_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr=r 2.sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[17] Jnet (fo=1, routed)Xh>Z /+sys/ipb/udp_if/IPADDR/My_IP_addr[17]_i_1/I4 JXhzrs .*sys/ipb/udp_if/IPADDR/My_IP_addr[17]_i_1/OProp_lut6_I4_O JLUT6XhzrA`<p 0,sys/ipb/udp_if/IPADDR/My_IP_addr[17]_i_1_n_0 Jnet (fo=1, routed)Xh] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<V sys/ip_mac/out Jnet (fo=82108, routed)Xhd;?Q "sys/ip_mac/ip_addr_o_reg[17]/C JFDCEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xh? W?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>m ,(sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17] Hold_fdre_C_D JFDREXhu=, JXh9 J required timeXh 8 J arrival timeXhB@, JXh1 JslackXhg&=#%+'sys/ipb/trans/sm/addr_reg[17]_replica/C40sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]/D*:BJZ&(LUT4=3 LUT5=3 LUT6=6 MUXF7=1 MUXF8=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsun@}A#JA*l@*@A.A>А===j?o_?y?$@e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)%o +'sys/ipb/trans/sm/addr_reg[17]_replica/Q Prop_fdre_C_Q JFDREXhzrq>n ,(sys/ipb/trans/sm/addr_reg[31]_0[17]_repN Jnet (fo=241, routed)Xh>j ?;sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_8/I2 JXhzr >:sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_8/OProp_lut4_I2_O JLUT4Xhzrl= @j ?;sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_4/I2 JXhzr >:sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_4/OProp_lut6_I2_O JLUT6Xhzr 0= @J sys/ipb/trans/sm/ack_i_5/I0 JXhzrc sys/ipb/trans/sm/ack_i_5/OProp_lut6_I0_O JLUT6Xhzr 0=a sys/ipb/trans/sm/ack_i_5_n_0 Jnet (fo=15, routed)Xh ?i >:sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_2/I4 JXhzr =9sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_2/OProp_lut6_I4_O JLUT6Xhzr 0= ?;sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_2_n_0 Jnet (fo=33, routed)Xh&?i >:sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_1/I0 JXhzr =9sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_1/OProp_lut5_I0_O JLUT5Xhzr 0=` sys/ipb_mosi[8][ipb_strobe] Jnet (fo=47, routed)Xh*?Y .*sys/ipb_miso_i[8][ipb_ack]_inferred_i_8/I4 JXhzrr -)sys/ipb_miso_i[8][ipb_ack]_inferred_i_8/OProp_lut6_I4_O JLUT6Xhzr 0=o /+sys/ipb_miso_i[8][ipb_ack]_inferred_i_8_n_0 Jnet (fo=1, routed)Xh(>Y .*sys/ipb_miso_i[8][ipb_ack]_inferred_i_4/I0 JXhzrr -)sys/ipb_miso_i[8][ipb_ack]_inferred_i_4/OProp_lut6_I0_O JLUT6Xhzr 0=o /+sys/ipb_miso_i[8][ipb_ack]_inferred_i_4_n_0 Jnet (fo=1, routed)XhY .*sys/ipb_miso_i[8][ipb_ack]_inferred_i_2/I0 JXhzrt -)sys/ipb_miso_i[8][ipb_ack]_inferred_i_2/OProp_muxf7_I0_O JMUXF7Xhzr=o /+sys/ipb_miso_i[8][ipb_ack]_inferred_i_2_n_0 Jnet (fo=1, routed)XhY .*sys/ipb_miso_i[8][ipb_ack]_inferred_i_1/I0 JXhzrt -)sys/ipb_miso_i[8][ipb_ack]_inferred_i_1/OProp_muxf8_I0_O JMUXF8XhzrQ8=a !sys/ipb_fabric/addr[31]_i_3_5 Jnet (fo=1, routed)Xhv?M "sys/ipb_fabric/addr[31]_i_7/I5 JXhzrf !sys/ipb_fabric/addr[31]_i_7/OProp_lut6_I5_O JLUT6Xhzr%>l ,(sys/icap_if/icapInterface/addr_reg[31]_2 Jnet (fo=1, routed)Xhw=X -)sys/icap_if/icapInterface/addr[31]_i_3/I4 JXhzrq ,(sys/icap_if/icapInterface/addr[31]_i_3/OProp_lut5_I4_O JLUT5Xhzr 0=c #sys/ipb/trans/sm/addr_reg[31]_1 Jnet (fo=2, routed)Xh}}>T )%sys/ipb/trans/sm/words_todo[7]_i_3/I3 JXhzrm ($sys/ipb/trans/sm/words_todo[7]_i_3/OProp_lut4_I3_O JLUT4Xhzr 0=Y sys/ipb/trans/sm/ack Jnet (fo=38, routed)Xhw>Q &"sys/ipb/trans/sm/ram_reg_0_i_15/I1 JXhzrj %!sys/ipb/trans/sm/ram_reg_0_i_15/OProp_lut4_I1_O JLUT4Xhzf9H=c #sys/ipb/trans/iface/first_reg_0 Jnet (fo=6, routed)Xh%>S ($sys/ipb/trans/iface/ram_reg_0_i_1/I4 JXhzfl '#sys/ipb/trans/iface/ram_reg_0_i_1/OProp_lut5_I4_O JLUT5XhzrC >w 73sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]_0[0] Jnet (fo=9, routed)Xhz%?c 40sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=\ sys/ipb/trans/sm/out Jnet (fo=82108, routed)Xhn?Z +'sys/ipb/trans/sm/addr_reg[17]_replica/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr={ 84sys/ipb/udp_if/clock_crossing_if/busy_down_tff_reg_0 Jnet (fo=4650, routed)XhG?c 40sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.At 2.sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]Setup_fdre_C_D JFDREXh㥛, JXh9 J required timeXh#JA8 J arrival timeXh@, JXh1 JslackXhj?#sys/ip_mac/mac_addr_o_reg[27]/C95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu@}AIAjTZd o@jT@A.A>А==={@o_?d;> @e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[27]/Q Prop_fdce_C_Q JFDCEXhzr>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[27] Jnet (fo=9, routed)XhAA?c 84sys/ipb/udp_if/rx_reset_block/pkt_data[27]__1_i_1/I0 JXhzr| 73sys/ipb/udp_if/rx_reset_block/pkt_data[27]__1_i_1/OProp_lut3_I0_O JLUT3XhzrT=} =9sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[19] Jnet (fo=1, routed)Xh>h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)Xh -?R #sys/ip_mac/mac_addr_o_reg[27]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xh+?h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Ay 73sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1Setup_fdre_C_D JFDREXh/ݽ, JXh9 J required timeXhIA8 J arrival timeXh, JXh1 JslackXh{@ #sys/ip_mac/mac_addr_o_reg[15]/C62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95]/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu@@}AAJAM5^:w@@A.A>А===(פ@o_?ҍ>@e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[15]/Q Prop_fdce_C_Q JFDCEXhzrZd>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[15] Jnet (fo=9, routed)Xh,?` 51sys/ipb/udp_if/rx_reset_block/pkt_data[95]_i_1/I0 JXhzry 40sys/ipb/udp_if/rx_reset_block/pkt_data[95]_i_1/OProp_lut3_I0_O JLUT3Xhzr/]=i )%sys/ipb/udp_if/rx_packet_parser/D[39] Jnet (fo=1, routed)Xh>e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)XhM?R #sys/ip_mac/mac_addr_o_reg[15]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xhb?e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Av 40sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95]Setup_fdre_C_D JFDREXhaн, JXh9 J required timeXhAJA8 J arrival timeXhZa, JXh1 JslackXh(פ@ #sys/ip_mac/mac_addr_o_reg[17]/C62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97]/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu(@}AIAMb͏@@A.A>А===@o_?(> @e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[17]/Q Prop_fdce_C_Q JFDCEXhzr>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[17] Jnet (fo=9, routed)Xhi?` 51sys/ipb/udp_if/rx_reset_block/pkt_data[97]_i_1/I0 JXhzry 40sys/ipb/udp_if/rx_reset_block/pkt_data[97]_i_1/OProp_lut3_I0_O JLUT3Xhzrj<=i )%sys/ipb/udp_if/rx_packet_parser/D[41] Jnet (fo=1, routed)Xh>e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)Xh!?R #sys/ip_mac/mac_addr_o_reg[17]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xh?e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Av 40sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97]Setup_fdre_C_D JFDREXh/ݽ, JXh9 J required timeXhIA8 J arrival timeXha, JXh1 JslackXh@ #sys/ip_mac/mac_addr_o_reg[12]/C62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu5@}AIA`}A`:w@`}@A.A>А===;@o_?R>?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[12]/Q Prop_fdce_C_Q JFDCEXhzr>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[12] Jnet (fo=9, routed)Xh?` 51sys/ipb/udp_if/rx_reset_block/pkt_data[92]_i_1/I0 JXhzry 40sys/ipb/udp_if/rx_reset_block/pkt_data[92]_i_1/OProp_lut3_I0_O JLUT3Xhzr`P=i )%sys/ipb/udp_if/rx_packet_parser/D[36] Jnet (fo=1, routed)Xh+>e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)XhM?R #sys/ip_mac/mac_addr_o_reg[12]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)XhΧ?e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Av 40sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]Setup_fdre_C_D JFDREXhl罐, JXh9 J required timeXhIA8 J arrival timeXh%, JXh1 JslackXh;@ #sys/ip_mac/mac_addr_o_reg[18]/C62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98]/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsun@}AIAYDN@@A.A>А===@o_?A>z?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[18]/Q Prop_fdce_C_Q JFDCEXhzr>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[18] Jnet (fo=9, routed)Xh?` 51sys/ipb/udp_if/rx_reset_block/pkt_data[98]_i_1/I0 JXhzry 40sys/ipb/udp_if/rx_reset_block/pkt_data[98]_i_1/OProp_lut3_I0_O JLUT3Xhzr/]=i )%sys/ipb/udp_if/rx_packet_parser/D[42] Jnet (fo=1, routed)Xhs_>e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)Xh?R #sys/ip_mac/mac_addr_o_reg[18]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xhb?e 62sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Av 40sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98]Setup_fdre_C_D JFDREXhi, JXh9 J required timeXhIA8 J arrival timeXh, JXh1 JslackXh@ #sys/ip_mac/mac_addr_o_reg[24]/C95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu[@}AJAlMb:w@l@A.A>А===Nh@o_? >?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[24]/Q Prop_fdce_C_Q JFDCEXhzraP>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[24] Jnet (fo=9, routed)Xh,?c 84sys/ipb/udp_if/rx_reset_block/pkt_data[24]__1_i_1/I0 JXhzr| 73sys/ipb/udp_if/rx_reset_block/pkt_data[24]__1_i_1/OProp_lut3_I0_O JLUT3Xhzr$>} =9sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[16] Jnet (fo=1, routed)Xh>h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)XhM?R #sys/ip_mac/mac_addr_o_reg[24]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)XhP?h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Ay 73sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1Setup_fdre_C_D JFDREXht, JXh9 J required timeXhJA8 J arrival timeXh4, JXh1 JslackXhNh@ #sys/ip_mac/mac_addr_o_reg[21]/C95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu@}AAJAM5^:w@@A.A>А===xt@o_?C>^b?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[21]/Q Prop_fdce_C_Q JFDCEXhzrZd>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[21] Jnet (fo=9, routed)Xhc{?c 84sys/ipb/udp_if/rx_reset_block/pkt_data[21]__3_i_1/I0 JXhzr| 73sys/ipb/udp_if/rx_reset_block/pkt_data[21]__3_i_1/OProp_lut3_I0_O JLUT3Xhzr9H=} =9sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[13] Jnet (fo=1, routed)Xh>h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)XhM?R #sys/ip_mac/mac_addr_o_reg[21]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)Xhb?h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Ay 73sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3Setup_fdre_C_D JFDREXhaн, JXh9 J required timeXhAJA8 J arrival timeXh , JXh1 JslackXhxt@ #sys/ip_mac/mac_addr_o_reg[40]/C95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu*@}AIAlA`f@l@A.A>А===#@o_?H>Ɯ?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[40]/Q Prop_fdce_C_Q JFDCEXhzrq>y 95sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[40] Jnet (fo=8, routed)Xh?c 84sys/ipb/udp_if/rx_reset_block/pkt_data[40]__1_i_1/I0 JXhzr| 73sys/ipb/udp_if/rx_reset_block/pkt_data[40]__1_i_1/OProp_lut3_I0_O JLUT3Xhzr>} =9sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[32] Jnet (fo=1, routed)Xh>h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)XhJ ?R #sys/ip_mac/mac_addr_o_reg[40]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=| 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 Jnet (fo=4650, routed)XhP?h 95sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Ay 73sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1Setup_fdre_C_D JFDREXh뽐, JXh9 J required timeXhIA8 J arrival timeXh, JXh1 JslackXh#@#sys/ip_mac/mac_addr_o_reg[24]/C($sys/ipb/udp_if/RARP_block/x_reg[8]/D*:BJZ(LUT3=1)j0clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000nsu[W@}ALAV"[:w@V@A.A>А===L@o_? >1?e(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow clk125_ub clk_ipb_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)g #sys/ip_mac/mac_addr_o_reg[24]/Q Prop_fdce_C_Q JFDCEXhzraP>T sys/ip_mac/Q[24] Jnet (fo=9, routed)Xh1?E sys/ip_mac/x[8]_i_1/I0 JXhzr^ sys/ip_mac/x[8]_i_1/OProp_lut3_I0_O JLUT3Xhzr>l ,(sys/ipb/udp_if/RARP_block/x_reg[15]_1[8] Jnet (fo=1, routed)XhW ($sys/ipb/udp_if/RARP_block/x_reg[8]/D JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=V sys/ip_mac/out Jnet (fo=82108, routed)XhM?R #sys/ip_mac/mac_addr_o_reg[24]/C JFDCEXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=v 3/sys/ipb/udp_if/RARP_block/rarp_req_reg_rep__0_0 Jnet (fo=4650, routed)Xhr?W ($sys/ipb/udp_if/RARP_block/x_reg[8]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.Ah &"sys/ipb/udp_if/RARP_block/x_reg[8]Setup_fdre_C_D JFDREXhim=, JXh9 J required timeXhLA8 J arrival timeXh", JXh1 JslackXhL@  clk125_ub clk62_5_ub!)@1@9A@I/@e@hq}F=9: rise - rise rise - rise  =9sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[0]/C:6sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu?}ԨT>?Ԩ@:>А= ==F=$=&>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) =9sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[0]/Q Prop_fdre_C_Q JFDREXhzr=w 73sys/eth/phy/U0/transceiver_inst/txcharisk_double[0] Jnet (fo=1, routed)Xh&>i :6sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh`0?l =9sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[0]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?i :6sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>y 84sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0] Hold_fdre_C_D JFDREXhw=, JXh9 J required timeXh8 J arrival timeXhz@, JXh1 JslackXhF=;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[12]/C84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu ?}zTԨi>Y?Ԩ@:>А= ===$=?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[12]/Q Prop_fdre_C_Q JFDREXhzr=u 51sys/eth/phy/U0/transceiver_inst/txdata_double[12] Jnet (fo=1, routed)Xh?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhף0?j ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[12]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>w 62sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12] Hold_fdre_C_D JFDREXh 0=, JXh9 J required timeXhzT8 J arrival timeXhO@, JXh1 JslackXh=:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[7]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu?}1HԨT>?Ԩ@:>А= ==P=$5^=J?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[7]/Q Prop_fdre_C_Q JFDREXhzr5^=t 40sys/eth/phy/U0/transceiver_inst/txdata_double[7] Jnet (fo=1, routed)XhJ?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh`0?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[7]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>v 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7] Hold_fdre_C_D JFDREXhX94<, JXh9 J required timeXh1H8 J arrival timeXh-@, JXh1 JslackXhP=:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[8]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsuRO"?}dԨT>?Ԩ@:>А= ==0=$=?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[8]/Q Prop_fdre_C_Q JFDREXhzr=t 40sys/eth/phy/U0/transceiver_inst/txdata_double[8] Jnet (fo=1, routed)Xh?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh`0?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[8]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>v 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8] Hold_fdre_C_D JFDREXhX94=, JXh9 J required timeXhd8 J arrival timeXhd@, JXh1 JslackXh0=:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[5]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu$?}ǶԨT>?Ԩ@:>А= ===$=l ?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[5]/Q Prop_fdre_C_Q JFDREXhzr=t 40sys/eth/phy/U0/transceiver_inst/txdata_double[5] Jnet (fo=1, routed)Xhl ?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh`0?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[5]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>v 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5] Hold_fdre_C_D JFDREXh:H=, JXh9 J required timeXhǶ8 J arrival timeXh@, JXh1 JslackXh=B>sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[0]/C?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu"?}S#ԨT>?Ԩ@:>А= ===$=Z ?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) B>sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[0]/Q Prop_fdre_C_Q JFDREXhzr=| <8sys/eth/phy/U0/transceiver_inst/txchardispmode_double[0] Jnet (fo=1, routed)XhZ ?n ?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh`0?q B>sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[0]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?n ?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>~ =9sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0] Hold_fdre_C_D JFDREXh #=, JXh9 J required timeXhS#8 J arrival timeXhw@, JXh1 JslackXh=:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[4]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu?}1HԨi>Y?Ԩ@:>А= ==f=$5^=5?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[4]/Q Prop_fdre_C_Q JFDREXhzr5^=t 40sys/eth/phy/U0/transceiver_inst/txdata_double[4] Jnet (fo=1, routed)Xh5?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhף0?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[4]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>v 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4] Hold_fdre_C_D JFDREXhX94<, JXh9 J required timeXh1H8 J arrival timeXh,@, JXh1 JslackXhf=:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu1?}k'Ԩi>Y?Ԩ@:>А= ===$5^=kf?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/Q Prop_fdre_C_Q JFDREXhzr5^=t 40sys/eth/phy/U0/transceiver_inst/txdata_double[2] Jnet (fo=1, routed)Xhkf?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xhף0?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>v 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2] Hold_fdre_C_D JFDREXht<, JXh9 J required timeXhk'8 J arrival timeXh@, JXh1 JslackXh==9sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[1]/C:6sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsuxo!?}@ԨT>?Ԩ@:>А= ===$=?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) =9sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=w 73sys/eth/phy/U0/transceiver_inst/txcharisk_double[1] Jnet (fo=1, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh`0?l =9sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[1]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?i :6sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>y 84sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1] Hold_fdre_C_D JFDREXho=, JXh9 J required timeXh@8 J arrival timeXhmN@, JXh1 JslackXh=;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D*:BJZj0clk62_5_ub rise@0.000ns - clk125_ub rise@0.000nsu'?}dԨT>?Ԩ@:>А= ==?F>$=) ?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/Q Prop_fdre_C_Q JFDREXhzr=u 51sys/eth/phy/U0/transceiver_inst/txdata_double[15] Jnet (fo=1, routed)Xh) ?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh`0?j ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C JFDREXhzr K J(clock clk62_5_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzrY sys/clocks/clk62_5_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr<m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xhi?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh:>w 62sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15] Hold_fdre_C_D JFDREXhX94=, JXh9 J required timeXhd8 J arrival timeXh@@, JXh1 JslackXh?F>;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[14]/C84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsuT?}A˥A&ɄO@A&Ʉ@A:>А= ==@o_?Zd>^ɘ?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[14]/Q Prop_fdre_C_Q JFDREXhzrZd>u 51sys/eth/phy/U0/transceiver_inst/txdata_double[14] Jnet (fo=1, routed)Xh^ɘ?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?j ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[14]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:x 62sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]Setup_fdre_C_D JFDREXh#, JXh9 J required timeXh˥A8 J arrival timeXhuk, JXh1 JslackXh@:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[9]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[9]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsup?}AA&ɄO@A&Ʉ@A:>А= ==]@o_?aP>t 40sys/eth/phy/U0/transceiver_inst/txdata_double[9] Jnet (fo=1, routed)XhА= ==p @o_?aP>R?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[3]/Q Prop_fdre_C_Q JFDREXhzraP>t 40sys/eth/phy/U0/transceiver_inst/txdata_double[3] Jnet (fo=1, routed)XhR?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[3]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[3]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh0ݴ?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[3]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:w 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[3]Setup_fdre_C_D JFDREXhʽ, JXh9 J required timeXhxA8 J arrival timeXhh, JXh1 JslackXhp @A=sys/eth/phy/U0/transceiver_inst/txchardispval_double_reg[1]/C>:sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsu?}A\A&ɄO@A&Ʉ@A:>А= ==8@o_?Zd>o?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=sys/eth/phy/U0/transceiver_inst/txchardispval_double_reg[1]/Q Prop_fdre_C_Q JFDREXhzrZd>{ ;7sys/eth/phy/U0/transceiver_inst/txchardispval_double[1] Jnet (fo=1, routed)Xho?m >:sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?p A=sys/eth/phy/U0/transceiver_inst/txchardispval_double_reg[1]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh?m >:sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:~ <8sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1]Setup_fdre_C_D JFDREXh㥛, JXh9 J required timeXh\A8 J arrival timeXhW j, JXh1 JslackXh8@B>sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[1]/C?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsuG?}AA&ɄO@A&Ʉ@A:>А= ==V@o_?Zd>?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) B>sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[1]/Q Prop_fdre_C_Q JFDREXhzrZd>| <8sys/eth/phy/U0/transceiver_inst/txchardispmode_double[1] Jnet (fo=1, routed)Xh?n ?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?q B>sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[1]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh?n ?;sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh: =9sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1]Setup_fdre_C_D JFDREXhT, JXh9 J required timeXhA8 J arrival timeXhړi, JXh1 JslackXhV@;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[13]/C84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsu(?}A7A&ɄO@A&Ʉ@A:>А= ==@o_?Zd>?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[13]/Q Prop_fdre_C_Q JFDREXhzrZd>u 51sys/eth/phy/U0/transceiver_inst/txdata_double[13] Jnet (fo=1, routed)Xh?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?j ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[13]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:x 62sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13]Setup_fdre_C_D JFDREXhY9, JXh9 J required timeXh7A8 J arrival timeXhPi, JXh1 JslackXh@:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[6]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsu.Ǚ?}A`A&ɄO@A&Ʉ@A:>А= ==@o_?aP>U?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[6]/Q Prop_fdre_C_Q JFDREXhzraP>t 40sys/eth/phy/U0/transceiver_inst/txdata_double[6] Jnet (fo=1, routed)XhU?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[6]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:w 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6]Setup_fdre_C_D JFDREXhaн, JXh9 J required timeXh`A8 J arrival timeXhh, JXh1 JslackXh@;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsul?}A\A&ɄO@A&Ʉ@A:>А= ==U@o_?Zd>Y?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/Q Prop_fdre_C_Q JFDREXhzrZd>u 51sys/eth/phy/U0/transceiver_inst/txdata_double[15] Jnet (fo=1, routed)XhY?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?j ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:x 62sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]Setup_fdre_C_D JFDREXhᥛ, JXh9 J required timeXh\A8 J arrival timeXh8i, JXh1 JslackXhU@;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[10]/C84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsue?}A˥AO@A@A:>А= ==@o_?Zd>%?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[10]/Q Prop_fdre_C_Q JFDREXhzrZd>u 51sys/eth/phy/U0/transceiver_inst/txdata_double[10] Jnet (fo=1, routed)Xh%?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?j ;7sys/eth/phy/U0/transceiver_inst/txdata_double_reg[10]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh0ݴ?g 84sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:x 62sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10]Setup_fdre_C_D JFDREXht, JXh9 J required timeXh˥A8 J arrival timeXh-\i, JXh1 JslackXh@:6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D*:BJZj1clk62_5_ub rise@16.000ns - clk125_ub rise@8.000nsuI?}AAO@A@A:>А= ==@o_?aP>=?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})d(rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_ub clk125_ub clk62_5_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)~ :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/Q Prop_fdre_C_Q JFDREXhzraP>t 40sys/eth/phy/U0/transceiver_inst/txdata_double[2] Jnet (fo=1, routed)Xh=?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/eth/phy/U0/transceiver_inst/userclk2 Jnet (fo=4650, routed)Xh?i :6sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C JFDREXhzr K J(clock clk62_5_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT1Prop_plle2_adv_CLKIN1_CLKOUT1 J PLLE2_ADVXhzr@5vY sys/clocks/clk62_5_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk62_5_buf/I JXh` sys/clocks/clk62_5_buf/O Prop_bufg_I_O JBUFGXhzr=m +'sys/eth/phy/U0/transceiver_inst/userclk Jnet (fo=118, routed)Xh0ݴ?f 73sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/C JFDREXhzr; Jclock pessimismXho_?= Jclock uncertaintyXh:w 51sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]Setup_fdre_C_D JFDREXhv, JXh9 J required timeXhA8 J arrival timeXh h, JXh1 JslackXh@  clk125_ub clk_ipb_ub!)@1@9A/@I?@e#I@hq}/=9; rise - rise rise - rise  40ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21]/C2.ngFEC/clk_rate_gen[3].clkRate3/value_reg[24]/D*:BJZj0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu?}>Un?@.A>А===/=$=>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)x 40ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21]/Q Prop_fdre_C_Q JFDREXhzr=r 2.ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21] Jnet (fo=2, routed)Xh>a 2.ngFEC/clk_rate_gen[3].clkRate3/value_reg[24]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<s 0,ngFEC/clk_rate_gen[3].clkRate3/osc125_a_bufg Jnet (fo=4650, routed)Xh3?c 40ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<v 2.ngFEC/clk_rate_gen[3].clkRate3/clk_31_250_bufg Jnet (fo=82108, routed)Xhn?a 2.ngFEC/clk_rate_gen[3].clkRate3/value_reg[24]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>q 0,ngFEC/clk_rate_gen[3].clkRate3/value_reg[24] Hold_fdre_C_D JFDREXh 0=, JXh9 J required timeXh8 J arrival timeXh@, JXh1 JslackXh/=-)sys/uc_if/uc_pipe_if/w_addr_pipe_reg[1]/C62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1]/D*:BJZ(LUT6=1)j0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu%?}2 R >??R @.A>А===<=$>g{>b(rising edge-triggered cell FDSE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q -)sys/uc_if/uc_pipe_if/w_addr_pipe_reg[1]/Q Prop_fdse_C_Q JFDSEXhzr=n .*sys/uc_if/uc_pipe_if/w_addr_pipe_reg__0[1] Jnet (fo=8, routed)Xhg{>b 73sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][1]_i_1/I5 JXhzr{ 62sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][1]_i_1/OProp_lut6_I5_O JLUT6XhzrA`<x 84sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][1]_i_1_n_0 Jnet (fo=1, routed)Xhe 62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<p -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 Jnet (fo=4650, routed)XhE?\ -)sys/uc_if/uc_pipe_if/w_addr_pipe_reg[1]/C JFDSEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<` sys/uc_if/uc_pipe_if/out Jnet (fo=82108, routed)XhףP?e 62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>u 40sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1] Hold_fdre_C_D JFDREXh-=, JXh9 J required timeXh2 8 J arrival timeXh@, JXh1 JslackXh<=#ngFEC/clkRate0/rateCtr_reg[6]/C!ngFEC/clkRate0/value_reg[9]/D*:BJZj0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu?}l  ] َ>z? ] @.A>А===5E=$=>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)g #ngFEC/clkRate0/rateCtr_reg[6]/Q Prop_fdre_C_Q JFDREXhzr=a !ngFEC/clkRate0/rateCtr_reg[6] Jnet (fo=2, routed)Xh>P !ngFEC/clkRate0/value_reg[9]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c ngFEC/clkRate0/osc125_a_bufg Jnet (fo=4650, routed)Xhc?R #ngFEC/clkRate0/rateCtr_reg[6]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<f "ngFEC/clkRate0/clk_31_250_bufg Jnet (fo=82108, routed)XhL?P !ngFEC/clkRate0/value_reg[9]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>` ngFEC/clkRate0/value_reg[9] Hold_fdre_C_D JFDREXh@=, JXh9 J required timeXhl 8 J arrival timeXhg@, JXh1 JslackXh5E=-)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[8]/C62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8]/D*:BJZ(LUT6=1)j0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu?}.x nB >z?nB @.A>А===7=$o>>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[8]/Q Prop_fdre_C_Q JFDREXhzr=n .*sys/uc_if/uc_pipe_if/r_addr_pipe_reg__0[8] Jnet (fo=4, routed)Xh>b 73sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][8]_i_1/I2 JXhzr{ 62sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][8]_i_1/OProp_lut6_I2_O JLUT6XhzrA`<x 84sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][8]_i_1_n_0 Jnet (fo=1, routed)Xhe 62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<p -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 Jnet (fo=4650, routed)Xhc?\ -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[8]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<` sys/uc_if/uc_pipe_if/out Jnet (fo=82108, routed)XhNbP?e 62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>u 40sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8] Hold_fdre_C_D JFDREXh$y=, JXh9 J required timeXh.x 8 J arrival timeXhm@, JXh1 JslackXh7=40ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14]/C2.ngFEC/clk_rate_gen[8].clkRate3/value_reg[17]/D*:BJZj0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu"7#?}g>?@.A>А===p=$= ?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)x 40ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14]/Q Prop_fdre_C_Q JFDREXhzr=r 2.ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14] Jnet (fo=2, routed)Xh ?a 2.ngFEC/clk_rate_gen[8].clkRate3/value_reg[17]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<s 0,ngFEC/clk_rate_gen[8].clkRate3/osc125_a_bufg Jnet (fo=4650, routed)XhX94?c 40ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<v 2.ngFEC/clk_rate_gen[8].clkRate3/clk_31_250_bufg Jnet (fo=82108, routed)Xhn?a 2.ngFEC/clk_rate_gen[8].clkRate3/value_reg[17]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>q 0,ngFEC/clk_rate_gen[8].clkRate3/value_reg[17] Hold_fdre_C_D JFDREXhL7=, JXh9 J required timeXhg8 J arrival timeXhV@, JXh1 JslackXhp=40ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22]/C2.ngFEC/clk_rate_gen[7].clkRate3/value_reg[25]/D*:BJZj0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu?}>,?@.A>А====$=J?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)x 40ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22]/Q Prop_fdre_C_Q JFDREXhzr=r 2.ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22] Jnet (fo=2, routed)XhJ?a 2.ngFEC/clk_rate_gen[7].clkRate3/value_reg[25]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<s 0,ngFEC/clk_rate_gen[7].clkRate3/osc125_a_bufg Jnet (fo=4650, routed)Xht3?c 40ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<v 2.ngFEC/clk_rate_gen[7].clkRate3/clk_31_250_bufg Jnet (fo=82108, routed)Xhm?a 2.ngFEC/clk_rate_gen[7].clkRate3/value_reg[25]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>q 0,ngFEC/clk_rate_gen[7].clkRate3/value_reg[25] Hold_fdre_C_D JFDREXh:H=, JXh9 J required timeXh8 J arrival timeXhO@, JXh1 JslackXh=-)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]/C62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9]/D*:BJZ(LUT6=1)j0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu!?} R )>z?R @.A>А====$R>>b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]/Q Prop_fdre_C_Q JFDREXhzr5^=n .*sys/uc_if/uc_pipe_if/r_addr_pipe_reg__0[9] Jnet (fo=3, routed)Xh>b 73sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][9]_i_1/I2 JXhzr{ 62sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][9]_i_1/OProp_lut6_I2_O JLUT6Xhzro=x 84sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][9]_i_1_n_0 Jnet (fo=1, routed)Xhe 62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<p -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 Jnet (fo=4650, routed)Xhc?\ -)sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<` sys/uc_if/uc_pipe_if/out Jnet (fo=82108, routed)XhףP?e 62sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>u 40sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9] Hold_fdre_C_D JFDREXh$y=, JXh9 J required timeXh 8 J arrival timeXh'@, JXh1 JslackXh=3/ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1]/C1-ngFEC/clk_rate_gen[4].clkRate3/value_reg[4]/D*:BJZj0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsuq!?}a">?@.A>А===L=$=<?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)w 3/ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1]/Q Prop_fdre_C_Q JFDREXhzr=q 1-ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1] Jnet (fo=2, routed)Xh<?` 1-ngFEC/clk_rate_gen[4].clkRate3/value_reg[4]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<s 0,ngFEC/clk_rate_gen[4].clkRate3/osc125_a_bufg Jnet (fo=4650, routed)XhX94?b 3/ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<v 2.ngFEC/clk_rate_gen[4].clkRate3/clk_31_250_bufg Jnet (fo=82108, routed)Xho?` 1-ngFEC/clk_rate_gen[4].clkRate3/value_reg[4]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>p /+ngFEC/clk_rate_gen[4].clkRate3/value_reg[4] Hold_fdre_C_D JFDREXh:H=, JXh9 J required timeXha8 J arrival timeXh$@, JXh1 JslackXhL=3/ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4]/C1-ngFEC/clk_rate_gen[4].clkRate3/value_reg[7]/D*:BJZj0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsuED?}2">?@.A>А===M=$=?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)w 3/ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4]/Q Prop_fdre_C_Q JFDREXhzr=q 1-ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4] Jnet (fo=2, routed)Xh?` 1-ngFEC/clk_rate_gen[4].clkRate3/value_reg[7]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<s 0,ngFEC/clk_rate_gen[4].clkRate3/osc125_a_bufg Jnet (fo=4650, routed)XhX94?b 3/ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<v 2.ngFEC/clk_rate_gen[4].clkRate3/clk_31_250_bufg Jnet (fo=82108, routed)Xho?` 1-ngFEC/clk_rate_gen[4].clkRate3/value_reg[7]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>p /+ngFEC/clk_rate_gen[4].clkRate3/value_reg[7] Hold_fdre_C_D JFDREXh #=, JXh9 J required timeXh28 J arrival timeXh@, JXh1 JslackXhM=$ ngFEC/clkRate1/rateCtr_reg[20]/C"ngFEC/clkRate1/value_reg[23]/D*:BJZj0clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000nsu'?}Ͻ>Un?@.A>А====$= ?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})e(rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)h $ ngFEC/clkRate1/rateCtr_reg[20]/Q Prop_fdre_C_Q JFDREXhzr=b "ngFEC/clkRate1/rateCtr_reg[20] Jnet (fo=2, routed)Xh ?Q "ngFEC/clkRate1/value_reg[23]/D JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c ngFEC/clkRate1/osc125_a_bufg Jnet (fo=4650, routed)Xh3?S $ ngFEC/clkRate1/rateCtr_reg[20]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<f "ngFEC/clkRate1/clk_31_250_bufg Jnet (fo=82108, routed)Xhn?Q "ngFEC/clkRate1/value_reg[23]/C JFDREXhzr; Jclock pessimismXh$= Jclock uncertaintyXh.A>a ngFEC/clkRate1/value_reg[23] Hold_fdre_C_D JFDREXh'=, JXh9 J required timeXhϽ8 J arrival timeXh@, JXh1 JslackXh=sys/clocks/rst_125_reg/C2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[0]*:BJZ(LUT5=1 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsu |@}AB/?a@A@B.A>А===#I@o_??5> Ch@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>b sys/ipb/trans/sm/rst_125mhz Jnet (fo=1307, routed)Xh@Q &"sys/ipb/trans/sm/ram_reg_5_i_11/I1 JXhzfj %!sys/ipb/trans/sm/ram_reg_5_i_11/OProp_lut5_I1_O JLUT5Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_5_i_11_n_0 Jnet (fo=1, routed)Xh?P %!sys/ipb/trans/sm/ram_reg_5_i_4/I4 JXhzri $ sys/ipb/trans/sm/ram_reg_5_i_4/OProp_lut6_I4_O JLUT6Xhzr 0=j *&sys/ipb/udp_if/ipbus_tx_ram/tx_dia[20] Jnet (fo=2, routed)Xh\{?e 2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[0] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=o +'sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 Jnet (fo=82108, routed)Xh?f 3/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A )%sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5!Setup_ramb36e1_CLKARDCLK_DIADI[0] JRAMB36E1Xh  , JXh9 J required timeXhB8 J arrival timeXhU, JXh1 JslackXh#I@ sys/clocks/rst_125_reg/Csys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[20]*:BJZ(LUT5=1 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsuh@}A>B{Ka@A{@B.A>А===IX@o_??5>0NT@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>b sys/ipb/trans/sm/rst_125mhz Jnet (fo=1307, routed)Xh@Q &"sys/ipb/trans/sm/ram_reg_5_i_11/I1 JXhzfj %!sys/ipb/trans/sm/ram_reg_5_i_11/OProp_lut5_I1_O JLUT5Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_5_i_11_n_0 Jnet (fo=1, routed)Xh?P %!sys/ipb/trans/sm/ram_reg_5_i_4/I4 JXhzri $ sys/ipb/trans/sm/ram_reg_5_i_4/OProp_lut6_I4_O JLUT6Xhzr 0=g '#sys/uc_if/uc_trans/ram_out/dina[20] Jnet (fo=2, routed)Xh/+? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[20] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=g #sys/uc_if/uc_trans/ram_out/clka Jnet (fo=82108, routed)Xhȣ? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram"Setup_ramb36e1_CLKARDCLK_DIADI[20] JRAMB36E1Xh  , JXh9 J required timeXh>B8 J arrival timeXhY, JXh1 JslackXhIX@ .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/Csys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[18]*:BJZ(LUT4=1 LUT5=1 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsuO@}A>B{!s@A{@B.A>А===n@o_?>?6@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) r .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/Q Prop_fdre_C_Q JFDREXhzr>d $ sys/ipb/trans/sm/ram_reg_7_3[18] Jnet (fo=4, routed)Xhα?Q &"sys/ipb/trans/sm/ram_reg_4_i_16/I0 JXhzrj %!sys/ipb/trans/sm/ram_reg_4_i_16/OProp_lut4_I0_O JLUT4Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_4_i_16_n_0 Jnet (fo=1, routed)Xh>P %!sys/ipb/trans/sm/ram_reg_4_i_8/I5 JXhzri $ sys/ipb/trans/sm/ram_reg_4_i_8/OProp_lut6_I5_O JLUT6Xhzr 0=f &"sys/ipb/trans/sm/ram_reg_4_i_8_n_0 Jnet (fo=1, routed)Xh>P %!sys/ipb/trans/sm/ram_reg_4_i_2/I3 JXhzri $ sys/ipb/trans/sm/ram_reg_4_i_2/OProp_lut5_I3_O JLUT5Xhzr 0=g '#sys/uc_if/uc_trans/ram_out/dina[18] Jnet (fo=2, routed)Xh ? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[18] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xhp=?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=g #sys/uc_if/uc_trans/ram_out/clka Jnet (fo=82108, routed)Xhȣ? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram"Setup_ramb36e1_CLKARDCLK_DIADI[18] JRAMB36E1Xh  , JXh9 J required timeXh>B8 J arrival timeXh, JXh1 JslackXhn@.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/C2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[2]*:BJZ(LUT4=1 LUT5=1 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsuKH@}A\BФ-h!s@AФ@B.A>А===3u@o_?>v/@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) r .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/Q Prop_fdre_C_Q JFDREXhzr>d $ sys/ipb/trans/sm/ram_reg_7_3[18] Jnet (fo=4, routed)Xhα?Q &"sys/ipb/trans/sm/ram_reg_4_i_16/I0 JXhzrj %!sys/ipb/trans/sm/ram_reg_4_i_16/OProp_lut4_I0_O JLUT4Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_4_i_16_n_0 Jnet (fo=1, routed)Xh>P %!sys/ipb/trans/sm/ram_reg_4_i_8/I5 JXhzri $ sys/ipb/trans/sm/ram_reg_4_i_8/OProp_lut6_I5_O JLUT6Xhzr 0=f &"sys/ipb/trans/sm/ram_reg_4_i_8_n_0 Jnet (fo=1, routed)Xh>P %!sys/ipb/trans/sm/ram_reg_4_i_2/I3 JXhzri $ sys/ipb/trans/sm/ram_reg_4_i_2/OProp_lut5_I3_O JLUT5Xhzr 0=j *&sys/ipb/udp_if/ipbus_tx_ram/tx_dia[18] Jnet (fo=2, routed)Xh>e 2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[2] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xhp=?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=o +'sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 Jnet (fo=82108, routed)Xhl?f 3/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A )%sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4!Setup_ramb36e1_CLKARDCLK_DIADI[2] JRAMB36E1Xh  , JXh9 J required timeXh\B8 J arrival timeXhS, JXh1 JslackXh3u@.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/C2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3/DIADI[0]*:BJZ(LUT5=2 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsuI@}AB4vA@A@B.A>А===x@o_?X9>:3@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) r .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/Q Prop_fdre_C_Q JFDREXhzrZd>d $ sys/ipb/trans/sm/ram_reg_7_3[12] Jnet (fo=4, routed)Xh S?Q &"sys/ipb/trans/sm/ram_reg_3_i_18/I1 JXhzrj %!sys/ipb/trans/sm/ram_reg_3_i_18/OProp_lut5_I1_O JLUT5Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_3_i_18_n_0 Jnet (fo=1, routed)Xh7?Q &"sys/ipb/trans/sm/ram_reg_3_i_11/I5 JXhzrj %!sys/ipb/trans/sm/ram_reg_3_i_11/OProp_lut6_I5_O JLUT6Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_3_i_11_n_0 Jnet (fo=1, routed)Xhz}>P %!sys/ipb/trans/sm/ram_reg_3_i_4/I2 JXhzri $ sys/ipb/trans/sm/ram_reg_3_i_4/OProp_lut5_I2_O JLUT5Xhzr 0=j *&sys/ipb/udp_if/ipbus_tx_ram/tx_dia[12] Jnet (fo=2, routed)XhGn?e 2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3/DIADI[0] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xhx?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=o +'sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 Jnet (fo=82108, routed)Xhs;?f 3/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A )%sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3!Setup_ramb36e1_CLKARDCLK_DIADI[0] JRAMB36E1Xh  , JXh9 J required timeXhB8 J arrival timeXhZd, JXh1 JslackXhx@-)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[2]/Csys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2]*:BJZ(LUT5=2 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsu'+D@}A>B{;h,J@A{@B.A>А===bTy@o_?>*V+@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) q -)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[2]/Q Prop_fdre_C_Q JFDREXhzr>c #sys/ipb/trans/sm/ram_reg_7_3[2] Jnet (fo=4, routed)Xh u?Q &"sys/ipb/trans/sm/ram_reg_0_i_26/I4 JXhzrj %!sys/ipb/trans/sm/ram_reg_0_i_26/OProp_lut5_I4_O JLUT5Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_0_i_26_n_0 Jnet (fo=1, routed)Xh4@?Q &"sys/ipb/trans/sm/ram_reg_0_i_19/I5 JXhzrj %!sys/ipb/trans/sm/ram_reg_0_i_19/OProp_lut6_I5_O JLUT6Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_0_i_19_n_0 Jnet (fo=1, routed)Xh>Q &"sys/ipb/trans/sm/ram_reg_0_i_12/I2 JXhzrj %!sys/ipb/trans/sm/ram_reg_0_i_12/OProp_lut5_I2_O JLUT5Xhzr 0=f &"sys/uc_if/uc_trans/ram_out/dina[2] Jnet (fo=2, routed)Xh#? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xh?\ -)sys/ipb/udp_if/IPADDR/My_IP_addr_reg[2]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=g #sys/uc_if/uc_trans/ram_out/clka Jnet (fo=82108, routed)Xhȣ? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram!Setup_ramb36e1_CLKARDCLK_DIADI[2] JRAMB36E1Xh  , JXh9 J required timeXh>B8 J arrival timeXh , JXh1 JslackXhbTy@.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[21]/C2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[1]*:BJZ(LUT4=1 LUT5=1 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsubG@}AB.u^R@A@B.A>А===C4z@o_?X9>71@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) r .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[21]/Q Prop_fdre_C_Q JFDREXhzrZd>d $ sys/ipb/trans/sm/ram_reg_7_3[21] Jnet (fo=4, routed)Xhv:?Q &"sys/ipb/trans/sm/ram_reg_5_i_18/I0 JXhzrj %!sys/ipb/trans/sm/ram_reg_5_i_18/OProp_lut4_I0_O JLUT4Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_5_i_18_n_0 Jnet (fo=1, routed)Xh ?Q &"sys/ipb/trans/sm/ram_reg_5_i_10/I5 JXhzrj %!sys/ipb/trans/sm/ram_reg_5_i_10/OProp_lut6_I5_O JLUT6Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_5_i_10_n_0 Jnet (fo=1, routed)Xh8F>P %!sys/ipb/trans/sm/ram_reg_5_i_3/I3 JXhzri $ sys/ipb/trans/sm/ram_reg_5_i_3/OProp_lut5_I3_O JLUT5Xhzr 0=j *&sys/ipb/udp_if/ipbus_tx_ram/tx_dia[21] Jnet (fo=2, routed)Xht$?e 2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[1] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xh^?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[21]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=o +'sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 Jnet (fo=82108, routed)Xh?f 3/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A )%sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5!Setup_ramb36e1_CLKARDCLK_DIADI[1] JRAMB36E1Xh  , JXh9 J required timeXhB8 J arrival timeXhD, JXh1 JslackXhC4z@.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/Csys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[16]*:BJZ(LUT4=1 LUT5=1 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsu@F>@}A>B{zR{@A{@B.A>А===~@o_?>Bq%@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) r .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/Q Prop_fdre_C_Q JFDREXhzr>d $ sys/ipb/trans/sm/ram_reg_7_3[16] Jnet (fo=4, routed)Xhq?Q &"sys/ipb/trans/sm/ram_reg_4_i_18/I0 JXhzrj %!sys/ipb/trans/sm/ram_reg_4_i_18/OProp_lut4_I0_O JLUT4Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_4_i_18_n_0 Jnet (fo=1, routed)Xh4>Q &"sys/ipb/trans/sm/ram_reg_4_i_12/I5 JXhzrj %!sys/ipb/trans/sm/ram_reg_4_i_12/OProp_lut6_I5_O JLUT6Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_4_i_12_n_0 Jnet (fo=1, routed)XhDH>P %!sys/ipb/trans/sm/ram_reg_4_i_4/I3 JXhzri $ sys/ipb/trans/sm/ram_reg_4_i_4/OProp_lut5_I3_O JLUT5Xhzr 0=g '#sys/uc_if/uc_trans/ram_out/dina[16] Jnet (fo=2, routed)Xh0 ? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[16] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xh5^?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=g #sys/uc_if/uc_trans/ram_out/clka Jnet (fo=82108, routed)Xhȣ? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram"Setup_ramb36e1_CLKARDCLK_DIADI[16] JRAMB36E1Xh  , JXh9 J required timeXh>B8 J arrival timeXhγ, JXh1 JslackXh~@.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/C2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[0]*:BJZ(LUT4=1 LUT5=1 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsuT/:@}A\BФB띾R{@AФ@B.A>А===럁@o_?>VZ!@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) r .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/Q Prop_fdre_C_Q JFDREXhzr>d $ sys/ipb/trans/sm/ram_reg_7_3[16] Jnet (fo=4, routed)Xhq?Q &"sys/ipb/trans/sm/ram_reg_4_i_18/I0 JXhzrj %!sys/ipb/trans/sm/ram_reg_4_i_18/OProp_lut4_I0_O JLUT4Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_4_i_18_n_0 Jnet (fo=1, routed)Xh4>Q &"sys/ipb/trans/sm/ram_reg_4_i_12/I5 JXhzrj %!sys/ipb/trans/sm/ram_reg_4_i_12/OProp_lut6_I5_O JLUT6Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_4_i_12_n_0 Jnet (fo=1, routed)XhDH>P %!sys/ipb/trans/sm/ram_reg_4_i_4/I3 JXhzri $ sys/ipb/trans/sm/ram_reg_4_i_4/OProp_lut5_I3_O JLUT5Xhzr 0=j *&sys/ipb/udp_if/ipbus_tx_ram/tx_dia[16] Jnet (fo=2, routed)Xh<?e 2.sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[0] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xh5^?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=o +'sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 Jnet (fo=82108, routed)Xhl?f 3/sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A )%sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4!Setup_ramb36e1_CLKARDCLK_DIADI[0] JRAMB36E1Xh  , JXh9 J required timeXh\B8 J arrival timeXh`r, JXh1 JslackXh럁@.*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/Csys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[12]*:BJZ(LUT5=2 LUT6=1)j2clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000nsup6@}A>B{&圾A@A{@B.A>А===v@o_?X9>@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})i(rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow clk_ipb_ub clk125_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) r .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/Q Prop_fdre_C_Q JFDREXhzrZd>d $ sys/ipb/trans/sm/ram_reg_7_3[12] Jnet (fo=4, routed)Xh S?Q &"sys/ipb/trans/sm/ram_reg_3_i_18/I1 JXhzrj %!sys/ipb/trans/sm/ram_reg_3_i_18/OProp_lut5_I1_O JLUT5Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_3_i_18_n_0 Jnet (fo=1, routed)Xh7?Q &"sys/ipb/trans/sm/ram_reg_3_i_11/I5 JXhzrj %!sys/ipb/trans/sm/ram_reg_3_i_11/OProp_lut6_I5_O JLUT6Xhzr 0=g '#sys/ipb/trans/sm/ram_reg_3_i_11_n_0 Jnet (fo=1, routed)Xhz}>P %!sys/ipb/trans/sm/ram_reg_3_i_4/I2 JXhzri $ sys/ipb/trans/sm/ram_reg_3_i_4/OProp_lut5_I2_O JLUT5Xhzr 0=g '#sys/uc_if/uc_trans/ram_out/dina[12] Jnet (fo=2, routed)Xh!? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[12] JRAMB36E1Xhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=o ,(sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 Jnet (fo=4650, routed)Xhx?] .*sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/C JFDREXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=g #sys/uc_if/uc_trans/ram_out/clka Jnet (fo=82108, routed)Xhȣ? sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK JRAMB36E1Xhzr; Jclock pessimismXho_?= Jclock uncertaintyXh.A sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram"Setup_ramb36e1_CLKARDCLK_DIADI[12] JRAMB36E1Xh  , JXh9 J required timeXh>B8 J arrival timeXhO/, JXh1 JslackXhv@ **async_default** clk125_ub clk125_ub!)@1@9A@I@eV>@hq},?,d rise - rise rise - rise  hdsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C`\sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/PRE*:BJZ(LUT2=1)j/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>} 7ֿr_e<?r@?  >>b(rising edge-triggered cell FDPE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR) hdsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/Q Prop_fdpe_C_Q JFDPEXhzf5^= d`sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_out Jnet (fo=1, routed)Xh^8> zvsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1/I0 JXhzf yusys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1/OProp_lut2_I0_O JLUT2Xhzf+= ^Zsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_n_0 Jnet (fo=2, routed)XhN> `\sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/PRE JFDPEXhzfJ J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr< c_sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/userclk2 Jnet (fo=4650, routed)XhNb0? hdsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C JFDPEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr< HDsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/userclk2 Jnet (fo=4650, routed)Xh_i? ^Zsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/C JFDPEXhzr; Jclock pessimismXh  \Xsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_regRemov_fdpe_C_PRE JFDPEXht, JXh9 J required timeXh 7ֿ8 J arrival timeXhi @, JXh1 JslackXh?hdsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C[Wsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/PRE*:BJZ(LUT2=1)j/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>} 7ֿr_e<?r@?  >>b(rising edge-triggered cell FDPE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR) hdsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/Q Prop_fdpe_C_Q JFDPEXhzf5^= d`sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_out Jnet (fo=1, routed)Xh^8> zvsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1/I0 JXhzf yusys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1/OProp_lut2_I0_O JLUT2Xhzf+= ^Zsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_n_0 Jnet (fo=2, routed)XhN> [Wsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/PRE JFDPEXhzfJ J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr< c_sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/userclk2 Jnet (fo=4650, routed)XhNb0? hdsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C JFDPEXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr< HDsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/userclk2 Jnet (fo=4650, routed)Xh_i? YUsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/C JFDPEXhzr; Jclock pessimismXh  WSsys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_regRemov_fdpe_C_PRE JFDPEXht, JXh9 J required timeXh 7ֿ8 J arrival timeXhi @, JXh1 JslackXh?sys/clocks/rst_125_reg/C-)sys/uc_if/spi/SerialInRegister_reg[1]/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsucd?}Tn߿ ] K7>Y? ] @oH?۹=K?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhK?\ -)sys/uc_if/spi/SerialInRegister_reg[1]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhL?Z +'sys/uc_if/spi/SerialInRegister_reg[1]/C JFDCEXhzr; Jclock pessimismXh۹m )%sys/uc_if/spi/SerialInRegister_reg[1]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhTn߿8 J arrival timeXh!@, JXh1 JslackXhoH? sys/clocks/rst_125_reg/C-)sys/uc_if/spi/SerialInRegister_reg[2]/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsucd?}Tn߿ ] K7>Y? ] @oH?۹=K?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhK?\ -)sys/uc_if/spi/SerialInRegister_reg[2]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhL?Z +'sys/uc_if/spi/SerialInRegister_reg[2]/C JFDCEXhzr; Jclock pessimismXh۹m )%sys/uc_if/spi/SerialInRegister_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhTn߿8 J arrival timeXh!@, JXh1 JslackXhoH? sys/clocks/rst_125_reg/C-)sys/uc_if/spi/SerialInRegister_reg[3]/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsucd?}Tn߿ ] K7>Y? ] @oH?۹=K?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhK?\ -)sys/uc_if/spi/SerialInRegister_reg[3]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhL?Z +'sys/uc_if/spi/SerialInRegister_reg[3]/C JFDCEXhzr; Jclock pessimismXh۹m )%sys/uc_if/spi/SerialInRegister_reg[3]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhTn߿8 J arrival timeXh!@, JXh1 JslackXhoH? sys/clocks/rst_125_reg/C'#sys/uc_if/spi/SerialInValid_reg/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsucd?}Tn߿ ] K7>Y? ] @oH?۹=K?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhK?V '#sys/uc_if/spi/SerialInValid_reg/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhL?T %!sys/uc_if/spi/SerialInValid_reg/C JFDCEXhzr; Jclock pessimismXh۹g #sys/uc_if/spi/SerialInValid_regRemov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhTn߿8 J arrival timeXh!@, JXh1 JslackXhoH? sys/clocks/rst_125_reg/C.*sys/uc_if/spi/SerialInRegister_reg[10]/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>sj?}:?⿍4 5^:>Y?4 @~H?۹=P?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhP?] .*sys/uc_if/spi/SerialInRegister_reg[10]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhhM?[ ,(sys/uc_if/spi/SerialInRegister_reg[10]/C JFDCEXhzr; Jclock pessimismXh۹n *&sys/uc_if/spi/SerialInRegister_reg[10]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh:?⿐8 J arrival timeXhI#@, JXh1 JslackXh~H? sys/clocks/rst_125_reg/C.*sys/uc_if/spi/SerialInRegister_reg[11]/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>sj?}:?⿍4 5^:>Y?4 @~H?۹=P?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhP?] .*sys/uc_if/spi/SerialInRegister_reg[11]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhhM?[ ,(sys/uc_if/spi/SerialInRegister_reg[11]/C JFDCEXhzr; Jclock pessimismXh۹n *&sys/uc_if/spi/SerialInRegister_reg[11]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh:?⿐8 J arrival timeXhI#@, JXh1 JslackXh~H? sys/clocks/rst_125_reg/C.*sys/uc_if/spi/SerialInRegister_reg[14]/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>sj?}:?⿍4 5^:>Y?4 @~H?۹=P?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhP?] .*sys/uc_if/spi/SerialInRegister_reg[14]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhhM?[ ,(sys/uc_if/spi/SerialInRegister_reg[14]/C JFDCEXhzr; Jclock pessimismXh۹n *&sys/uc_if/spi/SerialInRegister_reg[14]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh:?⿐8 J arrival timeXhI#@, JXh1 JslackXh~H? sys/clocks/rst_125_reg/C-)sys/uc_if/spi/SerialInRegister_reg[8]/CLR*:BJZj/clk125_ub rise@0.000ns - clk125_ub rise@0.000nsu>sj?}:?⿍4 5^:>Y?4 @~H?۹=P?b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})_(removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default** clk125_ub clk125_ub(DCD - SCD - CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzf=_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhP?\ -)sys/uc_if/spi/SerialInRegister_reg[8]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr 㿐X sys/clocks/clk125_ub Jnet (fo=1, routed)Xh?F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xh?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrX sys/clocks/clk125_ub Jnet (fo=1, routed)XhX?C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr<o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhhM?Z +'sys/uc_if/spi/SerialInRegister_reg[8]/C JFDCEXhzr; Jclock pessimismXh۹m )%sys/uc_if/spi/SerialInRegister_reg[8]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh:?⿐8 J arrival timeXhI#@, JXh1 JslackXh~H? sys/clocks/rst_125_reg/C$ sys/uc_if/spi/cs_sreg_reg[0]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuZ@}AALA#+1a@#@A9=А=h=V>@S?Zd>AL@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhAL@S $ sys/uc_if/spi/cs_sreg_reg[0]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xh ?Q "sys/uc_if/spi/cs_sreg_reg[0]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9d sys/uc_if/spi/cs_sreg_reg[0]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhALA8 J arrival timeXh, JXh1 JslackXhV>@ sys/clocks/rst_125_reg/C$ sys/uc_if/spi/cs_sreg_reg[1]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuZ@}AALA#+1a@#@A9=А=h=V>@S?Zd>AL@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhAL@S $ sys/uc_if/spi/cs_sreg_reg[1]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xh ?Q "sys/uc_if/spi/cs_sreg_reg[1]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9d sys/uc_if/spi/cs_sreg_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhALA8 J arrival timeXh, JXh1 JslackXhV>@ sys/clocks/rst_125_reg/C%!sys/uc_if/spi/sck_sreg_reg[0]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuZ@}AALA#+1a@#@A9=А=h=V>@S?Zd>AL@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhAL@T %!sys/uc_if/spi/sck_sreg_reg[0]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xh ?R #sys/uc_if/spi/sck_sreg_reg[0]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9e !sys/uc_if/spi/sck_sreg_reg[0]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhALA8 J arrival timeXh, JXh1 JslackXhV>@ sys/clocks/rst_125_reg/C%!sys/uc_if/spi/sck_sreg_reg[1]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuZ@}AALA#+1a@#@A9=А=h=V>@S?Zd>AL@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhAL@T %!sys/uc_if/spi/sck_sreg_reg[1]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xh ?R #sys/uc_if/spi/sck_sreg_reg[1]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9e !sys/uc_if/spi/sck_sreg_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhALA8 J arrival timeXh, JXh1 JslackXhV>@ sys/clocks/rst_125_reg/C$ sys/uc_if/spi/si_sreg_reg[0]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuBR@}A)LAura@u@A9=А=h=@S?Zd>KC@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)XhKC@S $ sys/uc_if/spi/si_sreg_reg[0]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)XhĠ?Q "sys/uc_if/spi/si_sreg_reg[0]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9d sys/uc_if/spi/si_sreg_reg[0]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh)LA8 J arrival timeXh, JXh1 JslackXh@ sys/clocks/rst_125_reg/C$ sys/uc_if/spi/si_sreg_reg[1]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuuN@}AALA#+1a@#@A9=А=h=G@S?Zd>c/@@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)Xhc/@@S $ sys/uc_if/spi/si_sreg_reg[1]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xh ?Q "sys/uc_if/spi/si_sreg_reg[1]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9d sys/uc_if/spi/si_sreg_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhALA8 J arrival timeXhq, JXh1 JslackXhG@ sys/clocks/rst_125_reg/C!sys/uc_if/spi/mode_reg[0]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuN@}A_oLA~C a@~@A9=А=h=@S?Zd>@@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)Xh@@P !sys/uc_if/spi/mode_reg[0]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xhv?N sys/uc_if/spi/mode_reg[0]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9a sys/uc_if/spi/mode_reg[0]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXh_oLA8 J arrival timeXh, JXh1 JslackXh@ sys/clocks/rst_125_reg/C-)sys/uc_if/spi/SerialInRegister_reg[0]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuN@}ALA~C a@~@A9=А=h=č@S?Zd>@@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)Xh@@\ -)sys/uc_if/spi/SerialInRegister_reg[0]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xhv?Z +'sys/uc_if/spi/SerialInRegister_reg[0]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9m )%sys/uc_if/spi/SerialInRegister_reg[0]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhLA8 J arrival timeXh, JXh1 JslackXhč@ sys/clocks/rst_125_reg/C!sys/uc_if/spi/mode_reg[1]/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuN@}ALA~C a@~@A9=А=h=č@S?Zd>@@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)Xh@@P !sys/uc_if/spi/mode_reg[1]/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xhv?N sys/uc_if/spi/mode_reg[1]/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9a sys/uc_if/spi/mode_reg[1]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhLA8 J arrival timeXh, JXh1 JslackXhč@ sys/clocks/rst_125_reg/C"sys/uc_if/spi/rx_state_reg/CLR*:BJZj/clk125_ub rise@8.000ns - clk125_ub rise@0.000nsuN@}ALA~C a@~@A9=А=h=č@S?Zd>@@b(rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})`(recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default** clk125_ub clk125_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)` sys/clocks/rst_125_reg/Q Prop_fdre_C_Q JFDREXhzfZd>_ sys/uc_if/spi/rst_125mhz Jnet (fo=1307, routed)Xh@@Q "sys/uc_if/spi/rx_state_reg/CLR JFDCEXhzf J J(clock clk125_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzrkX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh @F sys/clocks/clk125_buf/I JXhzr_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzrv=c sys/clocks/PLLE2_BASE_inst_0 Jnet (fo=4650, routed)Xho?K sys/clocks/rst_125_reg/C JFDREXhzr J J(clock clk125_ub rise edge)XhzrA?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh '#sys/clocks/PLLE2_BASE_inst/CLKFBOUTProp_plle2_adv_CLKIN1_CLKFBOUT J PLLE2_ADVXhzr@5vX sys/clocks/clk125_ub Jnet (fo=1, routed)Xh@C sys/clocks/clk125_buf/I JXh_ sys/clocks/clk125_buf/O Prop_bufg_I_O JBUFGXhzr=o ,(sys/uc_if/spi/SerialOutRegister_reg[1]_0 Jnet (fo=4650, routed)Xhv?O sys/uc_if/spi/rx_state_reg/C JFDCEXhzr; Jclock pessimismXhS?= Jclock uncertaintyXh9b sys/uc_if/spi/rx_state_regRecov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhLA8 J arrival timeXh, JXh1 JslackXhč@  **async_default** clk_ipb_ub clk_ipb_ub!)/@1?@9A/@I?@ef{Ahq}=d rise - rise rise - rise  }RNngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/CWSngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsuhǛ>}ޯᅪ}$1>x?}@=۹=k(Q>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) RNngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzf= XTngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/response_length_reg[1]_0 Jnet (fo=164, routed)Xhk(Q> WSngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<v 2.ngFEC/SFP_GEN[12].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)XhJ "? RNngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< OKngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)XhOm? UQngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23]/C JFDCEXhzr; Jclock pessimismXh۹ SOngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhޯ￐8 J arrival timeXhmj?, JXh1 JslackXh=}RNngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/CWSngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsuhǛ>}ޯᅪ}$1>x?}@=۹=k(Q>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) RNngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/Q Prop_fdpe_C_Q JFDPEXhzf= XTngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/response_length_reg[1]_0 Jnet (fo=164, routed)Xhk(Q> WSngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<v 2.ngFEC/SFP_GEN[12].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)XhJ "? RNngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< OKngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)XhOm? UQngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25]/C JFDCEXhzr; Jclock pessimismXh۹ SOngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhޯ￐8 J arrival timeXhmj?, JXh1 JslackXh=8ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/CLHngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu>}8-A>&?-@v>ľ=s>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q Prop_fdpe_C_Q JFDPEXhzf=z 95ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] Jnet (fo=96, routed)Xhs>{ LHngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xhq=*? ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< C?ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg Jnet (fo=82108, routed)XhIz?y JFngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17]/C JFDCEXhzr; Jclock pessimismXhľ HDngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh88 J arrival timeXh@, JXh1 JslackXhv>`4ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/CKGngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu>}8-A>&?-@v>ľ=s>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q Prop_fdpe_C_Q JFDPEXhzf=z 95ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] Jnet (fo=96, routed)Xhs>z KGngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xhq=*? ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< C?ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg Jnet (fo=82108, routed)XhIz?x IEngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2]/C JFDCEXhzr; Jclock pessimismXhľ GCngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh88 J arrival timeXh@, JXh1 JslackXhv>`4ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/CKGngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu>}8-A>&?-@v>ľ=s>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q Prop_fdpe_C_Q JFDPEXhzf=z 95ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] Jnet (fo=96, routed)Xhs>z KGngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xhq=*? ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< C?ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg Jnet (fo=82108, routed)XhIz?x IEngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4]/C JFDCEXhzr; Jclock pessimismXhľ GCngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh88 J arrival timeXh@, JXh1 JslackXhv>`4ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/CKGngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu>}8-A>&?-@v>ľ=s>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q Prop_fdpe_C_Q JFDPEXhzf=z 95ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] Jnet (fo=96, routed)Xhs>z KGngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xhq=*? ZVngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< C?ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg Jnet (fo=82108, routed)XhIz?x IEngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6]/C JFDCEXhzr; Jclock pessimismXhľ GCngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh88 J arrival timeXh@, JXh1 JslackXhv>`ZVngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Cb^ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsu_>}x濍 i;_>? @)>=Zn>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) ZVngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q Prop_fdpe_C_Q JFDPEXhzf= QMngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/AR[0] Jnet (fo=96, routed)XhZn> b^ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[1].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh= ? ZVngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< [WngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/clk_31_250_bufg Jnet (fo=82108, routed)XhN? `\ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0]/C JFDCEXhzr; Jclock pessimismXh ^ZngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhx濐8 J arrival timeXh?, JXh1 JslackXh)>`fQMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/CTPngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsuZr>}ۿ"[>=j?@i,>=T~Z>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) QMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzf= RNngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/status_reg_reg[1]_0 Jnet (fo=167, routed)XhT~Z> TPngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[2].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? QMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)XhS>? RNngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25]/C JFDCEXhzr; Jclock pessimismXh PLngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhۿ8 J arrival timeXhӆ?, JXh1 JslackXhi,>fQMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/CTPngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsuZr>}ۿ"[>=j?@i,>=T~Z>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) QMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzf= RNngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/status_reg_reg[1]_0 Jnet (fo=167, routed)XhT~Z> TPngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[2].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? QMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)XhS>? RNngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28]/C JFDCEXhzr; Jclock pessimismXh PLngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhۿ8 J arrival timeXhӆ?, JXh1 JslackXhi,>fQMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/CTPngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29]/CLR*:BJZj1clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000nsuZr>}ۿ"[>=j?@i,>=T~Z>e(rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})b(removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default** clk_ipb_ub clk_ipb_ub(DCD - SCD - CPR) QMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/Q Prop_fdpe_C_Q JFDPEXhzf= RNngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/status_reg_reg[1]_0 Jnet (fo=167, routed)XhT~Z> TPngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr>Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhuN?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh@?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr 㿐Y sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh?G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr<u 1-ngFEC/SFP_GEN[2].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? QMngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C JFDPEXhzr K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrZd;?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr<] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)XhNb?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)XhX?D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr< NJngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg Jnet (fo=82108, routed)XhS>? RNngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29]/C JFDCEXhzr; Jclock pessimismXh PLngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhۿ8 J arrival timeXhӆ?, JXh1 JslackXhi,>)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CWSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu5A}BzB;w,^>t+@;w@B3=А==f{Aoh?>Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)Xh9sA WSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)XhF? UQngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 SOngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhzB8 J arrival timeXhB, JXh1 JslackXhf{A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CWSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu5A}BzB;w,^>t+@;w@B3=А==f{Aoh?>Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)Xh9sA WSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)XhF? UQngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 SOngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhzB8 J arrival timeXhB, JXh1 JslackXhf{A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CWSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu5A}BzB;w,^>t+@;w@B3=А==f{Aoh?>Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)Xh9sA WSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)XhF? UQngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 SOngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhzB8 J arrival timeXhB, JXh1 JslackXhf{A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CWSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu5A}BzB;w,^>t+@;w@B3=А==f{Aoh?>Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)Xh9sA WSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)XhF? UQngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 SOngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhzB8 J arrival timeXhB, JXh1 JslackXhf{A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CVRngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu'A}B1BlA>t+@l@B3=А== {Aoh?>Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)Xh(tA VRngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh ? TPngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 RNngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXh1B8 J arrival timeXh]r, JXh1 JslackXh {A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CXTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu|A}BB>t+@@B3=А==x~Aoh?>$~Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)XhpA XTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? VRngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 TPngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhB8 J arrival timeXhfǩ, JXh1 JslackXhx~A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CXTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu|A}BB>t+@@B3=А==x~Aoh?>$~Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)XhpA XTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? VRngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 TPngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhB8 J arrival timeXhfǩ, JXh1 JslackXhx~A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CXTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu|A}BB>t+@@B3=А==x~Aoh?>$~Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)XhpA XTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? VRngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 TPngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhB8 J arrival timeXhfǩ, JXh1 JslackXhx~A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CXTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsu|A}BB>t+@@B3=А==x~Aoh?>$~Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)XhpA XTngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)Xh? VRngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 TPngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhB8 J arrival timeXhfǩ, JXh1 JslackXhx~A[)%ngFEC/ctrl_regs_inst/regs_reg[1][8]/CWSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20]/CLR*:BJZ(LUT3=1)j2clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000nsungA}BzB;w,^>t+@;w@B3=А==~Aoh?>}Ae(rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})c(recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns})Slow**async_default** clk_ipb_ub clk_ipb_ub((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)m )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q Prop_fdce_C_Q JFDCEXhzr> HDsys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] Jnet (fo=7, routed)Xh4U?n C?sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/I1 JXhzr B>sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/OProp_lut3_I1_O JLUT3Xhzf 0=m )%ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst Jnet (fo=11748, routed)XhpA WSngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20]/CLR JFDCEXhzf K J(clock clk_ipb_ub rise edge)Xhzr?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhE osc125_a_p_IBUF_inst/I JXhzr^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9C sys/osc125a_gtebuf/I JXhzrj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2XhzrR@Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)Xh~2?C sys/osc125a_clkbuf/I JXhzr\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzrv=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?P %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXhzr &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzrkY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh @G sys/clocks/clk_ipb_buf/I JXhzr` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzrv=l ($ngFEC/ctrl_regs_inst/clk_31_250_bufg Jnet (fo=82108, routed)Xh?X )%ngFEC/ctrl_regs_inst/regs_reg[1][8]/C JFDCEXhzr K J(clock clk_ipb_ub rise edge)XhzrB?  osc125_a_p JXhzrF  osc125_a_p J net (fo=0)XhB osc125_a_p_IBUF_inst/I JXh^ osc125_a_p_IBUF_inst/O Prop_ibuf_I_O JIBUFXhzrW sys/osc125_a_p_IBUF Jnet (fo=1, routed)Xhd\9@ sys/osc125a_gtebuf/I JXhj sys/osc125a_gtebuf/OProp_ibufds_gte2_I_O J IBUFDS_GTE2Xhzr?Z sys/osc125a_gtebuf_n_0 Jnet (fo=2, routed)XhW?@ sys/osc125a_clkbuf/I JXh\ sys/osc125a_clkbuf/O Prop_bufg_I_O JBUFGXhzr=] sys/clocks/gtrefclk_bufg Jnet (fo=11, routed)Xh?M %!sys/clocks/PLLE2_BASE_inst/CLKIN1 JXh &"sys/clocks/PLLE2_BASE_inst/CLKOUT0Prop_plle2_adv_CLKIN1_CLKOUT0 J PLLE2_ADVXhzr@5vY sys/clocks/clk_ipb_ub Jnet (fo=1, routed)Xh@D sys/clocks/clk_ipb_buf/I JXh` sys/clocks/clk_ipb_buf/O Prop_bufg_I_O JBUFGXhzr=u 1-ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg Jnet (fo=82108, routed)XhF? UQngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20]/C JFDCEXhzr; Jclock pessimismXhoh?= Jclock uncertaintyXh3 SOngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhzB8 J arrival timeXhK, JXh1 JslackXh~A[" **async_default**fabric_clk_FBOUTfabric_clk_FBOUT!)ֳt(@1ֳt8@9Aֳt(@Iֳt8@eۇAhq}$h>$d rise - rise rise - rise  ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu.X>}sPhYC =wT?h?h>5=p=k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xhp=} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)XhCl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhsP8 J arrival timeXhL?, JXh1 JslackXhh>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu.X>}sPhYC =wT?h?h>5=p=k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xhp=} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)XhCl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhsP8 J arrival timeXhL?, JXh1 JslackXhh>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu.X>}sPhYC =wT?h?h>5=p=k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xhp=} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)XhCl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhsP8 J arrival timeXhL?, JXh1 JslackXhh>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu.X>}sPhYC =wT?h?h>5=p=k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xhp=} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)XhCl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhsP8 J arrival timeXhL?, JXh1 JslackXhh>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu.X>}KhYC =wT?h?|>5=p=k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xhp=} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)XhCl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhK8 J arrival timeXhL?, JXh1 JslackXh|>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsu.X>}KhYC =wT?h?|>5=p=k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xhp=} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)XhCl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhK8 J arrival timeXhL?, JXh1 JslackXh|>ESOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/COKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsud>}jPh\=wT?h?>5=a">k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xha">~ OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)Xhl?| MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12]/C JFDCEXhzr; Jclock pessimismXh5 KGngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhjP8 J arrival timeXh;_?, JXh1 JslackXh>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsud>}jPh\=wT?h?>5=a">k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xha">} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)Xhl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhjP8 J arrival timeXh;_?, JXh1 JslackXh>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsud>}jPh\=wT?h?>5=a">k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xha">} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)Xhl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhjP8 J arrival timeXh;_?, JXh1 JslackXh>ASOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/CNJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8]/CLR*:BJZj=fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000nsud>}jPh\=wT?h?>5=a">k(rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})h(removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Fast**async_default**fabric_clk_FBOUTfabric_clk_FBOUT(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf=~ =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] Jnet (fo=24, routed)Xha">} NJngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr?>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr(\Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh$?@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr< HDngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN Jnet (fo=39427, routed)Xhn2? SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr>Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xhh ?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh?= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr<x 40ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN Jnet (fo=39427, routed)Xhl?{ LHngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8]/C JFDCEXhzr; Jclock pessimismXh5 JFngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhjP8 J arrival timeXh;_?, JXh1 JslackXh>A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CKGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25]/PRE*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsub@}A+[A<n??Arӥ=А=.>ۇA=Q>@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)XhZ@z KGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25]/PRE JFDPEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)Xh֣?x IEngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25]/C JFDPEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ GCngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25]Recov_fdpe_C_PRE JFDPEXhE6, JXh9 J required timeXh+[A8 J arrival timeXh*, JXh1 JslackXhۇAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CKGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26]/PRE*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsub@}A+[A<n??Arӥ=А=.>ۇA=Q>@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)XhZ@z KGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26]/PRE JFDPEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)Xh֣?x IEngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26]/C JFDPEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ GCngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26]Recov_fdpe_C_PRE JFDPEXhE6, JXh9 J required timeXh+[A8 J arrival timeXh*, JXh1 JslackXhۇAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CKGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27]/PRE*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsub@}A+[A<n??Arӥ=А=.>ۇA=Q>@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)XhZ@z KGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27]/PRE JFDPEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)Xh֣?x IEngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27]/C JFDPEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ GCngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27]Recov_fdpe_C_PRE JFDPEXhE6, JXh9 J required timeXh+[A8 J arrival timeXh*, JXh1 JslackXhۇAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CKGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29]/PRE*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsu@}A7]Ad͠#9<n?d͠?Arӥ=А=.>A=Q>H@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)Xh@z KGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29]/PRE JFDPEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)Xhİ?x IEngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29]/C JFDPEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ GCngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29]Recov_fdpe_C_PRE JFDPEXhE6, JXh9 J required timeXh7]A8 J arrival timeXh´, JXh1 JslackXhAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CKGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30]/PRE*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsu@}A7]Ad͠#9<n?d͠?Arӥ=А=.>A=Q>H@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)Xh@z KGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30]/PRE JFDPEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)Xhİ?x IEngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30]/C JFDPEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ GCngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30]Recov_fdpe_C_PRE JFDPEXhE6, JXh9 J required timeXh7]A8 J arrival timeXh´, JXh1 JslackXhAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CKGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31]/PRE*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsu@}A7]Ad͠#9<n?d͠?Arӥ=А=.>A=Q>H@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)Xh@z KGngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31]/PRE JFDPEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)Xhİ?x IEngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31]/C JFDPEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ GCngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31]Recov_fdpe_C_PRE JFDPEXhE6, JXh9 J required timeXh7]A8 J arrival timeXh´, JXh1 JslackXhAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CHDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1]/CLR*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuS@}AeARJt<n?RJ?Arӥ=А=.>SA=Q>@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)Xho @w HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)XhA?u FBngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1]/C JFDCEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ D@ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXheA8 J arrival timeXhw, JXh1 JslackXhSAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CHDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2]/CLR*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuS@}AeARJt<n?RJ?Arӥ=А=.>SA=Q>@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)Xho @w HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)XhA?u FBngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2]/C JFDCEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ D@ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXheA8 J arrival timeXhw, JXh1 JslackXhSAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CHDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3]/CLR*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuS@}AeARJt<n?RJ?Arӥ=А=.>SA=Q>@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)Xho @w HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)XhA?u FBngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3]/C JFDCEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ D@ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXheA8 J arrival timeXhw, JXh1 JslackXhSAA=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/CHDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12]/CLR*:BJZ(LUT2=1)j>fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000nsuS@}AeARJt<n?RJ?Arӥ=А=.>SA=Q>@k(rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})i(recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns})Slow**async_default**fabric_clk_FBOUTfabric_clk_FBOUT((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q Prop_fdre_C_Q JFDREXhzfq>r 1-ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 Jnet (fo=67, routed)Xh'@p EAngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/I0 JXhzf D@ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/OProp_lut2_I0_O JLUT2Xhzf= HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] Jnet (fo=159, routed)Xho @w HDngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12]/CLR JFDCEXhzf Q J"(clock fabric_clk_FBOUT rise edge)XhzrA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh@ ngFEC/fclk_ibuf/I JXhzr] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzroM?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh5^?M "ngFEC/fabric_clk_MMCME2/CLKIN1 JXhzr $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzrjZ ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)Xh"@@ ngFEC/fclk_bufg/I JXhzrY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzrv=y 51ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN Jnet (fo=39427, routed)XhK7?p A=ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C JFDREXhzr Q J"(clock fabric_clk_FBOUT rise edge)XhzrAA  fabric_clk_p JXhzrN ngFEC/fabric_clk_p J net (fo=0)Xh= ngFEC/fclk_ibuf/I JXh] ngFEC/fclk_ibuf/OProp_ibufds_I_O JIBUFDSXhzr)9?Z ngFEC/fabric_clk_nobuf Jnet (fo=1, routed)Xh~j|?J "ngFEC/fabric_clk_MMCME2/CLKIN1 JXh $ ngFEC/fabric_clk_MMCME2/CLKFBOUTProp_mmcme2_adv_CLKIN1_CLKFBOUT J MMCME2_ADVXhzr]Z ngFEC/fabric_clk_FBOUT Jnet (fo=1, routed)XhM@= ngFEC/fclk_bufg/I JXhY ngFEC/fclk_bufg/O Prop_bufg_I_O JBUFGXhzr= <8ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN Jnet (fo=39427, routed)XhA?u FBngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12]/C JFDCEXhzr; Jclock pessimismXh== Jclock uncertaintyXhrӥ D@ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXheA8 J arrival timeXhw, JXh1 JslackXhSA **async_default**rxWordclkl12_1rxWordclkl12_1!)]_ff@1]_ff @9A]_ff@I]_ff @ex@hq}^)>d rise - rise rise - rise  95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu>}xAv=!>A?^)>=}->g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh}->f 73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhx8 J arrival timeXhQ?, JXh1 JslackXh^)>R 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu>}xAv=!>A?^)>=}->g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh}->f 73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhx8 J arrival timeXhQ?, JXh1 JslackXh^)>R 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu>}xAv=!>A?^)>=}->g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh}->f 73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhx8 J arrival timeXhQ?, JXh1 JslackXh^)>RB SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu>}GGD<k>G?HZ>(\=di>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhdi> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xhk> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhG? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92]/C JFDCEXhzr; Jclock pessimismXh(\ b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhG8 J arrival timeXhP.?, JXh1 JslackXhHZ>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu>}GGD<k>G?HZ>(\=di>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhdi> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xhk> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhG? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C JFDCEXhzr; Jclock pessimismXh(\ b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhG8 J arrival timeXhP.?, JXh1 JslackXhHZ>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu>}M8+=k>8?V->={>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh{> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xhk> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh8? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhM8 J arrival timeXh2?, JXh1 JslackXhV-> 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu캾>}y馾)/<!>>>=>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>f 73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhy馾8 J arrival timeXh8?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu캾>}y馾)/<!>>>=>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>f 73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhy馾8 J arrival timeXh8?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu캾>}y馾)/<!>>>=>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>f 73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhy馾8 J arrival timeXh8?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR*:BJZj9rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000nsu캾>}y馾)/<!>>>=>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_1rxWordclkl12_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>f 73ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>d 51ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhy馾8 J arrival timeXh8?, JXh1 JslackXh>RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2_[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuL@}33Ax{ A #,k? #?33A=А=x@?y @p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xh;? _[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh #? ]YngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhx{ A8 J arrival timeXhx, JXh1 JslackXhx@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuA@}33A A$k?$?33A=А=-@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhs ? a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? _[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh A8 J arrival timeXh |, JXh1 JslackXh-@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuA@}33A A$k?$?33A=А=-@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhs ? a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? _[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh A8 J arrival timeXh |, JXh1 JslackXh-@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuA@}33A A$k?$?33A=А=-@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhs ? a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? _[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh A8 J arrival timeXh |, JXh1 JslackXh-@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuA@}33A A$k?$?33A=А=-@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhs ? a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? _[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh A8 J arrival timeXh |, JXh1 JslackXh-@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsuA@}33A A$k?$?33A=А=-@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhs ? a]ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? _[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh A8 J arrival timeXh |, JXh1 JslackXh-@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu:=@}33A A$k?$?33A=А=P@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhv> ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh A8 J arrival timeXhx, JXh1 JslackXhP@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu:=@}33A A$k?$?33A=А=P@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= YUngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xhv> ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xh$? \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh A8 J arrival timeXhx, JXh1 JslackXhP@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu:=@}33A A$k?$?33A=А=@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhv> `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXh A8 J arrival timeXhx, JXh1 JslackXh@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000nsu:=@}33A A$k?$?33A=А=@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_1rxWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xhr? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhv> `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh$? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXh A8 J arrival timeXhx, JXh1 JslackXh@ **async_default**rxWordclkl12_2rxWordclkl12_2!)]_ff@1]_ff @9A]_ff@I]_ff @e|#@hq}>d rise - rise rise - rise  95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsuV>}efsu<J >?>Ob=E>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhE>f 73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ >h 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr; Jclock pessimismXhObw 3/ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhef8 J arrival timeXh.!?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsuV>}efsu<J >?>Ob=E>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhE>f 73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ >h 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr; Jclock pessimismXhObw 3/ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhef8 J arrival timeXh.!?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsuV>}efsu<J >?>Ob=E>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhE>f 73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ >h 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr; Jclock pessimismXhObw 3/ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhef8 J arrival timeXh.!?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsuV>}efsu<J >?>Ob=E>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhE>f 73ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ >h 95ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr; Jclock pessimismXhObw 3/ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhef8 J arrival timeXh.!?, JXh1 JslackXh>RB SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu>}󽾍~ t=>~ ?>=Z4>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ4> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh~ ? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh󽾐8 J arrival timeXh!-?, JXh1 JslackXh>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu>}󽾍~ t=>~ ?>=Z4>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ4> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh~ ? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh󽾐8 J arrival timeXh!-?, JXh1 JslackXh>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu>}󽾍~ t=>~ ?>=Z4>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ4> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh~ ? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh󽾐8 J arrival timeXh!-?, JXh1 JslackXh>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu>}󽾍~ t=>~ ?>=Z4>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ4> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh~ ? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh󽾐8 J arrival timeXh!-?, JXh1 JslackXh>F SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CgcngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu>}W9~ t=>~ ?|>=Z4>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ4> gcngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh~ ? eangFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105]/C JFDCEXhzr; Jclock pessimismXh c_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhW98 J arrival timeXh!-?, JXh1 JslackXh|>F SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CgcngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114]/CLR*:BJZj9rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000nsu>}W9~ t=>~ ?|>=Z4>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_2rxWordclkl12_2(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ4> gcngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh~ ? eangFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114]/C JFDCEXhzr; Jclock pessimismXh c_ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhW98 J arrival timeXh!-?, JXh1 JslackXh|>ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsuK@}33Ap A!2&e*'l?!2?33A=А=|#@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhk? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXhp A8 J arrival timeXhd{, JXh1 JslackXh|#@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsuK@}33Ap A!2&e*'l?!2?33A=А=|#@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhk? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXhp A8 J arrival timeXhd{, JXh1 JslackXh|#@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2kgngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsuoQJ@}33A i A!2&e*'l?!2?33A=А=v$@?w@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhge? kgngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? iengFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh i A8 J arrival timeXh, JXh1 JslackXhv$@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2kgngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsuoQJ@}33A i A!2&e*'l?!2?33A=А=v$@?w@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhge? kgngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? iengFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh i A8 J arrival timeXh, JXh1 JslackXhv$@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsu /J@}33A i A!2&e*'l?!2?33A=А=5@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhd? fbngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh i A8 J arrival timeXhk, JXh1 JslackXh5@|ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsu /J@}33A i A!2&e*'l?!2?33A=А=5@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhd? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh i A8 J arrival timeXhk, JXh1 JslackXh5@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsu /J@}33A i A!2&e*'l?!2?33A=А=5@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= YUngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xhd? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xh!2? \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh i A8 J arrival timeXhk, JXh1 JslackXh5@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsuK@}33AV A!2&e*'l?!2?33A=А=1@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhk? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_regRecov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhV A8 J arrival timeXhd{, JXh1 JslackXh1@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsuK@}33AV A!2&e*'l?!2?33A=А=1@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xhk? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh!2? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhV A8 J arrival timeXhd{, JXh1 JslackXh1@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2jfngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000nsuR[6@}33A\ A1h*'l?1?33A=А=@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_2rxWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh,G? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= YUngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xh? jfngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xh1? hdngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh fbngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh\ A8 J arrival timeXheq, JXh1 JslackXh@ **async_default**rxWordclkl12_3rxWordclkl12_3!)]_ff@1]_ff @9A]_ff@I]_ff @eUp@hq}W>d rise - rise rise - rise  95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuVͤ>}18t=23>8?W>=P>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhP>f 73ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh8?d 51ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh18 J arrival timeXhD,?, JXh1 JslackXhW>R 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuVͤ>}18t=23>8?W>=P>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhP>f 73ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh8?d 51ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh18 J arrival timeXhD,?, JXh1 JslackXhW>RB SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsu=Ǵ>}Qu=23>?>=|p>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|p> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh23> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhQ8 J arrival timeXh83?, JXh1 JslackXh>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsu=Ǵ>}Qu=23>?>=|p>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|p> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh23> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhQ8 J arrival timeXh83?, JXh1 JslackXh>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsu=Ǵ>}Qu=23>?>=|p>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|p> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh23> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhQ8 J arrival timeXh83?, JXh1 JslackXh>B SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsu=Ǵ>}Qu=23>?>=|p>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR) SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|p> fbngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh23> SOngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? d`ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_regRemov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhQ8 J arrival timeXh83?, JXh1 JslackXh>F 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuH.>}3^9m=23>9?G>=Í>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)XhÍ> SOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh9? QMngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh3^8 J arrival timeXh>?, JXh1 JslackXhG>RF 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuH.>}3^9m=23>9?G>=Í>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)XhÍ> SOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh9? QMngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh3^8 J arrival timeXh>?, JXh1 JslackXhG>RF 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuH.>}3^9m=23>9?G>=Í>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)XhÍ> SOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh9? QMngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh3^8 J arrival timeXh>?, JXh1 JslackXhG>RF 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR*:BJZj9rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000nsuH.>}3^9m=23>9?G>=Í>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_3rxWordclkl12_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)XhÍ> SOngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh9? QMngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh3^8 J arrival timeXh>?, JXh1 JslackXhG>RngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuU@}33AvP A&1di\j?&1?33A=А=Up@?v@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh<C? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xh&1? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXh0, JXh1 JslackXhUp@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuU@}33AvP A&1di\j?&1?33A=А=Up@?v@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh<C? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xh&1? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXh0, JXh1 JslackXhUp@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuU@}33AvP A&1di\j?&1?33A=А=Up@?v@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh<C? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xh&1? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXh0, JXh1 JslackXhUp@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuU@}33AvP A&1di\j?&1?33A=А=Up@?v@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh<C? `\ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xh&1? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXh0, JXh1 JslackXhUp@|ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuQ@}33A^L Aa0"ei\j?a0?33A=А=`@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh;>3? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xha0? \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh^L A8 J arrival timeXh8, JXh1 JslackXh`@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2_[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuQ@}33A^L Aa0"ei\j?a0?33A=А=`@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh;>3? _[ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xha0? ]YngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh^L A8 J arrival timeXh8, JXh1 JslackXh`@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuQ@}33A^L Aa0"ei\j?a0?33A=А=`@?@p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= YUngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xh;>3? ^ZngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xha0? \XngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh^L A8 J arrival timeXh8, JXh1 JslackXh`@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuqL@}33A^L Aa0"ei\j?a0?33A=А=<@? @p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= YUngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xhy? fbngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xha0? d`ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh^L A8 J arrival timeXh, JXh1 JslackXh<@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2jfngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuqL@}33AŲ Aa0"ei\j?a0?33A=А= @? @p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= YUngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xhy? jfngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE JFDPEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xha0? hdngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/C JFDPEXhzr; Jclock pessimismXh= Jclock uncertaintyXh fbngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]Recov_fdpe_C_PRE JFDPEXh|?, JXh9 J required timeXhŲ A8 J arrival timeXh, JXh1 JslackXh @ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2jfngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000nsuqL@}33AŲ Aa0"ei\j?a0?33A=А= @? @p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_3rxWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xhk? tpngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/I0 JXhzr songFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= YUngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xhy? jfngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xha0? hdngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh fbngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXhŲ A8 J arrival timeXh, JXh1 JslackXh @ **async_default**rxWordclkl12_4rxWordclkl12_4!)]_ff@1]_ff @9A]_ff@I]_ff @e@hq}>d rise - rise rise - rise  F 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsuwF>}C-\=X9>?>=&8>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh&8> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhC8 J arrival timeXh!?, JXh1 JslackXh>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsuwF>}C-\=X9>?>=&8>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh&8> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhC8 J arrival timeXh!?, JXh1 JslackXh>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsuwF>}C-\=X9>?>=&8>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh&8> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhC8 J arrival timeXh!?, JXh1 JslackXh>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsuwF>}C-\=X9>?>=&8>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh&8> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhC8 J arrival timeXh!?, JXh1 JslackXh>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu>}WJ t=X9>J ?Ǫ>=`>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh`> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ ? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhW8 J arrival timeXh+?, JXh1 JslackXhǪ>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu>}WJ t=X9>J ?Ǫ>=`>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh`> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ ? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhW8 J arrival timeXh+?, JXh1 JslackXhǪ>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu>}WJ t=X9>J ?Ǫ>=`>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh`> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ ? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhW8 J arrival timeXh+?, JXh1 JslackXhǪ>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu>}WJ t=X9>J ?Ǫ>=`>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh`> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ ? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhW8 J arrival timeXh+?, JXh1 JslackXhǪ>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu>}WJ t=X9>J ?>=㇉>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh㇉> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ ? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhW8 J arrival timeXh7z8?, JXh1 JslackXh>RF 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR*:BJZj9rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000nsu>}WJ t=X9>J ?>=㇉>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_4rxWordclkl12_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh㇉> SOngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhX9>h 95ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhJ ? QMngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhW8 J arrival timeXh7z8?, JXh1 JslackXh>RUQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CUQngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR*:BJZ(LUT1=1 LUT3=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu+@}33A'AU% m;?U%?33A=А=@!>V@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr> XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg_n_0_[1] Jnet (fo=1, routed)Xh> hdngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst_i_1/I2 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst_i_1/OProp_lut3_I2_O JLUT3Xhzr 0=y 95ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/DONE_o_reg_0 Jnet (fo=8, routed)XhDM?n C?ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtRxReady_s_i_1__2/I0 JXhzr B>ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtRxReady_s_i_1__2/OProp_lut1_I0_O JLUT1Xhzf@= XTngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh:> UQngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK Jnet (fo=1057, routed)Xhm;? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)XhU%? SOngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh QMngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_fdce_C_CLR JFDCEXh", JXh9 J required timeXh'A8 J arrival timeXhZ, JXh1 JslackXh@UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CZVngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR*:BJZ(LUT1=1 LUT3=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu+@}33A'AU% m;?U%?33A=А=@!>V@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/Q Prop_fdce_C_Q JFDCEXhzr> XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg_n_0_[1] Jnet (fo=1, routed)Xh> hdngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst_i_1/I2 JXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst_i_1/OProp_lut3_I2_O JLUT3Xhzr 0=y 95ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/DONE_o_reg_0 Jnet (fo=8, routed)XhDM?n C?ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtRxReady_s_i_1__2/I0 JXhzr B>ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtRxReady_s_i_1__2/OProp_lut1_I0_O JLUT1Xhzf@= XTngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh:> ZVngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK Jnet (fo=1057, routed)Xhm;? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)XhU%? XTngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh VRngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_fdce_C_CLR JFDCEXh", JXh9 J required timeXh'A8 J arrival timeXhZ, JXh1 JslackXh@c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu&@}33ArA\"Ľ";?\"?33A=А=@H>@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrq> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)Xhܼ> tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/OProp_lut1_I0_O JLUT1Xhzf> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh2V? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh";? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh\"? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Recov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhrA8 J arrival timeXhT, JXh1 JslackXh@Pc_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu&@}33ArA\"Ľ";?\"?33A=А=@H>@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrq> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)Xhܼ> tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/OProp_lut1_I0_O JLUT1Xhzf> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh2V? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh";? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh\"? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]Recov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhrA8 J arrival timeXhT, JXh1 JslackXh@Pc_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu&@}33ArA\"Ľ";?\"?33A=А=@H>@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrq> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)Xhܼ> tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/OProp_lut1_I0_O JLUT1Xhzf> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh2V? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh";? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh\"? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Recov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhrA8 J arrival timeXhT, JXh1 JslackXh@P ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsuR @}33A) A@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrq> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)Xhܼ> tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/OProp_lut1_I0_O JLUT1Xhzf> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh";? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)XhM"? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Recov_fdce_C_CLR JFDCEXhx, JXh9 J required timeXhA8 J arrival timeXhN, JXh1 JslackXhpg@Pc_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000nsu@}33AAo#";?o#?33A=А=ϫ@H>E@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_4rxWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrq> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)Xhܼ> tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/OProp_lut1_I0_O JLUT1Xhzf> ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)XhM\? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfO J (clock rxWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh";? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xho#? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Recov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhA8 J arrival timeXhjH, JXh1 JslackXhϫ@P **async_default**rxWordclkl12_5rxWordclkl12_5!)]_ff@1]_ff @9A]_ff@I]_ff @e"@hq}Ą>d rise - rise rise - rise  95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsue>} ףMt=i>M?Ą>=b,>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xhb,>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhM?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh ף8 J arrival timeXh-?, JXh1 JslackXhĄ>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsue>} ףMt=i>M?Ą>=b,>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xhb,>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhM?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh ף8 J arrival timeXh-?, JXh1 JslackXhĄ>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsue>} ףMt=i>M?Ą>=b,>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xhb,>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhM?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh ף8 J arrival timeXh-?, JXh1 JslackXhĄ>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsue>} ףMt=i>M?Ą>=b,>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xhb,>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhM?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh ף8 J arrival timeXh-?, JXh1 JslackXhĄ>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsue>} ףMt=i>M?Ą>=b,>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xhb,>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhM?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh ף8 J arrival timeXh-?, JXh1 JslackXhĄ>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsue>} ףMt=i>M?Ą>=b,>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xhb,>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhM?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh ף8 J arrival timeXh-?, JXh1 JslackXhĄ>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsu=Ջ>}MJ x`e<i>J ?C>Ob=D1>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhD1>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhJ ?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr; Jclock pessimismXhObw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhM8 J arrival timeXhH ?, JXh1 JslackXhC>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsu=Ջ>}MJ x`e<i>J ?C>Ob=D1>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhD1>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhJ ?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr; Jclock pessimismXhObw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhM8 J arrival timeXhH ?, JXh1 JslackXhC>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsu">}SJ <\=i>J ?.>=_>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh_>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhJ ?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhS8 J arrival timeXh+?, JXh1 JslackXh.>R 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR*:BJZj9rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000nsu">}SJ <\=i>J ?.>=_>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_5rxWordclkl12_5(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh_>f 73ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xhi>h 95ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhJ ?d 51ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhS8 J arrival timeXh+?, JXh1 JslackXh.>RngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsua0@}33AAsh1ik?sh1?33A=А="@l?V?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[2] Jnet (fo=5, routed)Xhm ? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf9H= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0_n_0 Jnet (fo=3, routed)Xhl ? WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr D@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out Jnet (fo=1055, routed)Xhsh1? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh SOngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2]Recov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhA8 J arrival timeXhZk, JXh1 JslackXh"@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsua0@}33AAsh1ik?sh1?33A=А="@l?V?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[2] Jnet (fo=5, routed)Xhm ? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf9H= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0_n_0 Jnet (fo=3, routed)Xhl ? WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr D@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out Jnet (fo=1055, routed)Xhsh1? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh SOngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2]Recov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhA8 J arrival timeXhZk, JXh1 JslackXh"@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsua0@}33AAsh1ik?sh1?33A=А="@l?V?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[2] Jnet (fo=5, routed)Xhm ? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf9H= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0_n_0 Jnet (fo=3, routed)Xhl ? VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr D@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out Jnet (fo=1055, routed)Xhsh1? TPngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2]Recov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhA8 J arrival timeXhZk, JXh1 JslackXh"@Uc_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C|xngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR*:BJZ(LUT1=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsu8@}33AA1/]|??1?33A=А=j@q=>'@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhwF? tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/OProp_lut1_I0_O JLUT1Xhzf@= iengFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=80, routed)Xh? |xngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh|?? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr gcngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=1055, routed)Xh1? zvngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh xtngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRecov_fdce_C_CLR JFDCEXh", JXh9 J required timeXhA8 J arrival timeXhh, JXh1 JslackXhj@Pc_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsur)@}33A A1Y|??1?33A=А=@q=>S@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhwF? tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/OProp_lut1_I0_O JLUT1Xhzf@= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)XhMZ? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh|?? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh1? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]Recov_fdce_C_CLR JFDCEXhIz, JXh9 J required timeXh A8 J arrival timeXhzY, JXh1 JslackXh@Pc_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsur)@}33A A1Y|??1?33A=А=@q=>S@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhwF? tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/OProp_lut1_I0_O JLUT1Xhzf@= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)XhMZ? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh|?? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh1? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]Recov_fdce_C_CLR JFDCEXhIz, JXh9 J required timeXh A8 J arrival timeXhzY, JXh1 JslackXh@Pc_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsur)@}33A A1Y|??1?33A=А=@q=>S@g(rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzrZd> c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhwF? tpngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/I0 JXhzr songFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/OProp_lut1_I0_O JLUT1Xhzf@= ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)XhMZ? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh|?? c_ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh1? ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]Recov_fdce_C_CLR JFDCEXhIz, JXh9 J required timeXh A8 J arrival timeXhzY, JXh1 JslackXh@PngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsu@}33Ad An2"ek?n2?33A=А=c@?L?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh>U? wsngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh? a]ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xhn2? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhd A8 J arrival timeXhT, JXh1 JslackXhc@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsu@}33Ad An2"ek?n2?33A=А=c@?L?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh>U? wsngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh? a]ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xhn2? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhd A8 J arrival timeXhT, JXh1 JslackXhc@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000nsu@}33Ad An2"ek?n2?33A=А=c@?L?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_5rxWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xh>U? wsngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh? a]ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xhn2? _[ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhd A8 J arrival timeXhT, JXh1 JslackXhc@ **async_default**rxWordclkl12_6rxWordclkl12_6!)]_ff@1]_ff @9A]_ff@I]_ff @ef@hq}Ѷ>d rise - rise rise - rise  > SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>}GA94<W>G>Ѷ>Mb=>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> eangFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhG> c_ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzr; Jclock pessimismXhMb a]ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_regRemov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh8 J arrival timeXh?, JXh1 JslackXhѶ>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0]/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>ע>})\GA94<W>G>l>Mb=H_>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhH_> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhG> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh)\8 J arrival timeXh'?, JXh1 JslackXhl>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1]/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>ע>})\GA94<W>G>l>Mb=H_>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhH_> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhG> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh)\8 J arrival timeXh'?, JXh1 JslackXhl>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2]/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>ע>})\GA94<W>G>l>Mb=H_>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhH_> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhG> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh)\8 J arrival timeXh'?, JXh1 JslackXhl>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>ע>})\GA94<W>G>l>Mb=H_>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhH_> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhG> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_regRemov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh)\8 J arrival timeXh'?, JXh1 JslackXhl>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37]/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>}shu<W>>q>Mb=Z>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhsh8 J arrival timeXh>?, JXh1 JslackXhq>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>}shu<W>>|>Mb=eў>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xheў> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhsh8 J arrival timeXhx??, JXh1 JslackXh|>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/CLR*:BJZj9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>}shu<W>>|>Mb=eў>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xheў> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhW> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/C JFDCEXhzr; Jclock pessimismXhMb b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhsh8 J arrival timeXhx??, JXh1 JslackXh|> XTngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CUQngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu>}ҍG #<h>G>>Mb>:>g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) XTngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/Q Prop_fdce_C_Q JFDCEXhzr= RNngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s Jnet (fo=1, routed)Xh= WSngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__4/I1 JXhzr VRngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__4/OProp_lut2_I1_O JLUT2XhzfA`< NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s0 Jnet (fo=1, routed)Xh> UQngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE JFDPEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)Xhh> XTngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)XhG> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzr; Jclock pessimismXhMb QMngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_regRemov_fdpe_C_PRE JFDPEXht, JXh9 J required timeXhҍ8 J arrival timeXh>?, JXh1 JslackXh>;c_ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000nsu,>}$~j`e<W>~j> ?Mbz>>g(rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_6rxWordclkl12_6(DCD - SCD - CPR) c_ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr= c_ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)Xhs> uqngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__14/I0 JXhzr tpngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__14/OProp_lut1_I0_O JLUT1Xhzf/< ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xhk> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhW> c_ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=1055, routed)Xh~j> ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr; Jclock pessimismXhMb ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_fdce_C_CLR JFDCEXhQ, JXh9 J required timeXh$8 J arrival timeXhlF?, JXh1 JslackXh ?PngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsut@@}33AAJ "󓎾DVi?J "?33A=А=f@?d?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xh1Į? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2XhzfY= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xhej? fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1055, routed)XhJ "? d`ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh b^ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_regRecov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhz, JXh1 JslackXhf@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2_[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu1L@@}33AA!DVi?!?33A=А=r@?¨?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)Xh1Į? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2XhzfY= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xh$? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1055, routed)Xh!? ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh [WngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_regRecov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh¡z, JXh1 JslackXhr@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu@@}33A^ AJ "󓎾DVi?J "?33A=А=鐕@?_?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[1] Jnet (fo=5, routed)Xh? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1_n_0 Jnet (fo=3, routed)Xh_> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK Jnet (fo=1055, routed)XhJ "? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh^ A8 J arrival timeXh_Yz, JXh1 JslackXh鐕@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu@@}33A^ AJ "󓎾DVi?J "?33A=А=鐕@?_?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[1] Jnet (fo=5, routed)Xh? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1_n_0 Jnet (fo=3, routed)Xh_> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK Jnet (fo=1055, routed)XhJ "? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh^ A8 J arrival timeXh_Yz, JXh1 JslackXh鐕@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu@@}33A^ AJ "󓎾DVi?J "?33A=А=鐕@?_?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_6rxWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[1] Jnet (fo=5, routed)Xh? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1_n_0 Jnet (fo=3, routed)Xh_> VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK Jnet (fo=1055, routed)XhJ "? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh^ A8 J arrival timeXh_Yz, JXh1 JslackXh鐕@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu8@}33AA!DVi?!?33A=А=~5@? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1055, routed)Xh!? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhs, JXh1 JslackXh~5@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu8@}33AA!DVi?!?33A=А=~5@? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1055, routed)Xh!? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhs, JXh1 JslackXh~5@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu8@}33AA!DVi?!?33A=А=~5@? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1055, routed)Xh!? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhs, JXh1 JslackXh~5@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu8@}33AA!DVi?!?33A=А=~5@? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1055, routed)Xh!? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhs, JXh1 JslackXh~5@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000nsu8@}33AA!DVi?!?33A=А=~5@? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR JFDCEXhzfO J (clock rxWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)XhDVi? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr d`ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1055, routed)Xh!? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhs, JXh1 JslackXh~5@ **async_default**rxWordclkl12_7rxWordclkl12_7!)]_ff@1]_ff @9A]_ff@I]_ff @ei@hq}H>d rise - rise rise - rise  B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsu[>}r|<->|>H>=N6>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhN6> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)Xh-> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh|> d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhr8 J arrival timeXh] ?, JXh1 JslackXhH>B SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuoϛ>}d;AT<->A?>*\=w8Q>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhw8Q> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1055, routed)Xh-> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)XhA? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr; Jclock pessimismXh*\ b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_regRemov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhd;8 J arrival timeXh?&?, JXh1 JslackXh> :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuH>}d;_<F>?+6>=+c>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh+c>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr; Jclock pessimismXhx 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhd;8 J arrival timeXh8,?, JXh1 JslackXh+6>R :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuH>}d;_<F>?+6>=+c>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh+c>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr; Jclock pessimismXhx 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhd;8 J arrival timeXh8,?, JXh1 JslackXh+6>R :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuG>}AD<F>?>>*\=(t>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh(t>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr; Jclock pessimismXh*\x 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhA8 J arrival timeXh~0?, JXh1 JslackXh>>R :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuG>}AD<F>?>>*\=(t>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh(t>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50]/C JFDCEXhzr; Jclock pessimismXh*\x 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhA8 J arrival timeXh~0?, JXh1 JslackXh>>R :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuG>}AD<F>?>>*\=(t>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh(t>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr; Jclock pessimismXh*\x 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhA8 J arrival timeXh~0?, JXh1 JslackXh>>R :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuG>}AD<F>?>>*\=(t>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh(t>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr; Jclock pessimismXh*\x 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhA8 J arrival timeXh~0?, JXh1 JslackXh>>R :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuG>}AD<F>?>>*\=(t>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh(t>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr; Jclock pessimismXh*\x 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhA8 J arrival timeXh~0?, JXh1 JslackXh>>R :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR*:BJZj9rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000nsuG>}AD<F>?>>*\=(t>g(rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_7rxWordclkl12_7(DCD - SCD - CPR)~ :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=i ($ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh(t>g 84ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)XhF>i :6ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzrt 1-ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1055, routed)Xh?e 62ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr; Jclock pessimismXh*\x 40ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhA8 J arrival timeXh~0?, JXh1 JslackXh>>RngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuX7@}33AB A/$k?/$?33A=А=i@? ?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhޮV? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh/$? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXhB A8 J arrival timeXh4Rr, JXh1 JslackXhi@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuX7@}33AB A/$k?/$?33A=А=i@? ?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhޮV? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh/$? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXhB A8 J arrival timeXh4Rr, JXh1 JslackXhi@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu7@}33A) A$󓎾k?$?33A=А=ܚ@?Df?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhhU? kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh$? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXh) A8 J arrival timeXhr, JXh1 JslackXhܚ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu7@}33A) A$󓎾k?$?33A=А=ܚ@?Df?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhhU? `\ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh$? ^ZngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXh) A8 J arrival timeXhr, JXh1 JslackXhܚ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu7@}33A) A$󓎾k?$?33A=А=ܚ@?Df?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhhU? `\ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh$? ^ZngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]Recov_fdce_C_CLR JFDCEXh|?, JXh9 J required timeXh) A8 J arrival timeXhr, JXh1 JslackXhܚ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuX7@}33Aly A/$k?/$?33A=А=ɛ@? ?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhޮV? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh/$? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhly A8 J arrival timeXh4Rr, JXh1 JslackXhɛ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuX7@}33Aly A/$k?/$?33A=А=ɛ@? ?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhޮV? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh/$? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhly A8 J arrival timeXh4Rr, JXh1 JslackXhɛ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsuX7@}33Aly A/$k?/$?33A=А=ɛ@? ?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhޮV? a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh/$? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhly A8 J arrival timeXh4Rr, JXh1 JslackXhɛ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu7@}33ASu A$󓎾k?$?33A=А=f@?Df?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhhU? kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh$? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhSu A8 J arrival timeXhr, JXh1 JslackXhf@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR*:BJZ(LUT2=1)j9rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000nsu7@}33ASu A$󓎾k?$?33A=А=f@?Df?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_7rxWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhody? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)XhhU? `\ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xhk? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1055, routed)Xh$? ^ZngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_regRecov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhSu A8 J arrival timeXhr, JXh1 JslackXhf@ **async_default**rxWordclkl12_8rxWordclkl12_8!)]_ff@1]_ff @9A]_ff@I]_ff @e@hq}M>d rise - rise rise - rise  G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsu>}SA94<$>?M>th=:>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh:> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18]/C JFDCEXhzr; Jclock pessimismXhth b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhS8 J arrival timeXh(?, JXh1 JslackXhM>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsu>}SA94<$>?M>th=:>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh:> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33]/C JFDCEXhzr; Jclock pessimismXhth b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhS8 J arrival timeXh(?, JXh1 JslackXhM>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsuMD>}Тl #<$>l?y>th=2"r>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh2"r> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xhl? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzr; Jclock pessimismXhth b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhТ8 J arrival timeXh96?, JXh1 JslackXhy>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsua]>}Q+=$>?>=.*>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh.*> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhQ8 J arrival timeXhñB?, JXh1 JslackXh>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsua]>}Q+=$>?>=.*>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh.*> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhQ8 J arrival timeXhñB?, JXh1 JslackXh>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsua]>}Q+=$>?>=.*>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh.*> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhQ8 J arrival timeXhñB?, JXh1 JslackXh>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsua]>}+=$>?>=.*>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh.*> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXhñB?, JXh1 JslackXh>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsua]>}+=$>?>=.*>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh.*> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXhñB?, JXh1 JslackXh>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsua]>}+=$>?>=.*>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh.*> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXhñB?, JXh1 JslackXh>G SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/CfbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR*:BJZj9rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000nsua]>}+=$>?>=.*>g(rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**rxWordclkl12_8rxWordclkl12_8(DCD - SCD - CPR) SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh.*> fbngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1055, routed)Xh$> SOngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr YUngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=1055, routed)Xh? d`ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr; Jclock pessimismXh b^ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_regRemov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXhñB?, JXh1 JslackXh> ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuW>@}33AA&1l*'l?&1?33A=А=@?;?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[3] Jnet (fo=5, routed)XhZ? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/OProp_lut1_I0_O JLUT1XhzfY= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0_n_0 Jnet (fo=3, routed)Xh> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 Jnet (fo=1055, routed)Xh&1? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh!y, JXh1 JslackXh@ ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuW>@}33AA&1l*'l?&1?33A=А=@?;?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[3] Jnet (fo=5, routed)XhZ? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/OProp_lut1_I0_O JLUT1XhzfY= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0_n_0 Jnet (fo=3, routed)Xh> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 Jnet (fo=1055, routed)Xh&1? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh!y, JXh1 JslackXh@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuW>@}33AA&1l*'l?&1?33A=А=@?;?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[3] Jnet (fo=5, routed)XhZ? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/OProp_lut1_I0_O JLUT1XhzfY= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0_n_0 Jnet (fo=3, routed)Xh> VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 Jnet (fo=1055, routed)Xh&1? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh!y, JXh1 JslackXh@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsu:@}33ApAף0L n*'l?ף0?33A=А=@?@?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xh;? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2XhzfY= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh ? kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xhף0? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhpA8 J arrival timeXhv, JXh1 JslackXh@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsu:@}33ApAף0L n*'l?ף0?33A=А=@?@?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xh;? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2XhzfY= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh ? kgngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xhף0? iengFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh gcngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhpA8 J arrival timeXhv, JXh1 JslackXh@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2jfngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsu5@}33AA-2pg*'l?-2?33A=А=Ù@?-?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xh;? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2XhzfY= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xh> jfngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1055, routed)Xh-2? hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhp, JXh1 JslackXhÙ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2jfngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsu5@}33AA-2pg*'l?-2?33A=А=Ù@?-?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xh;? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2XhzfY= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xh> jfngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1055, routed)Xh-2? hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhp, JXh1 JslackXhÙ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2jfngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE*:BJZ(LUT2=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsu5@}33AGs A-2pg*'l?-2?33A=А=Gښ@?-?p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xh;? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2XhzfY= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xh> jfngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE JFDPEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr [WngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1055, routed)Xh-2? hdngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/C JFDPEXhzr; Jclock pessimismXh= Jclock uncertaintyXh fbngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]Recov_fdpe_C_PRE JFDPEXhq=, JXh9 J required timeXhGs A8 J arrival timeXhp, JXh1 JslackXhGښ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuX^1@}33AA`0(m*'l?`0?33A=А=s@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xh;? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2XhzfY= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xha> a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xh`0? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh#hl, JXh1 JslackXhs@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/CLR*:BJZ(LUT2=1)j9rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000nsuX^1@}33AA`0(m*'l?`0?33A=А=s@??p(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**rxWordclkl12_8rxWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)Xh;? wsngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/I0 JXhzr vrngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/OProp_lut2_I0_O JLUT2XhzfY= XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xha> a]ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/CLR JFDCEXhzfO J (clock rxWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1055, routed)Xh*'l? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock rxWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr OKngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1055, routed)Xh`0? _[ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ]YngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh#hl, JXh1 JslackXhs@ **async_default** rxWordclkl8_1 rxWordclkl8_1!)]_ff@1]_ff @9A]_ff@I]_ff @e٣@hq}_>d rise - rise rise - rise  7 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CRNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu?Wu>}ZdL7 +=>L7 ?_>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh> RNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhL7 ? PLngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4]/C JFDCEXhzr; Jclock pessimismXh NJngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhZd8 J arrival timeXhb?, JXh1 JslackXh_>R7 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CRNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu?Wu>}ZdL7 +=>L7 ?_>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh> RNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhL7 ? PLngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5]/C JFDCEXhzr; Jclock pessimismXh NJngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhZd8 J arrival timeXhb?, JXh1 JslackXh_>R7 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CRNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu?Wu>}ZdL7 +=>L7 ?_>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh> RNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhL7 ? PLngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6]/C JFDCEXhzr; Jclock pessimismXh NJngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhZd8 J arrival timeXhb?, JXh1 JslackXh_>R7 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CRNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu?Wu>}ZdL7 +=>L7 ?_>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh> RNngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhL7 ? PLngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7]/C JFDCEXhzr; Jclock pessimismXh NJngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhZd8 J arrival timeXhb?, JXh1 JslackXh_>R< 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu Q>}l绾x C =>x ?/>=; >f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh; > SOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhx ? QMngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhl绾8 J arrival timeXhδ#?, JXh1 JslackXh/>R< 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu Q>}l绾x C =>x ?/>=; >f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh; > SOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhx ? QMngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhl绾8 J arrival timeXhδ#?, JXh1 JslackXh/>R< 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu Q>}l绾x C =>x ?/>=; >f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh; > SOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhx ? QMngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhl绾8 J arrival timeXhδ#?, JXh1 JslackXh/>R< 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu Q>}l绾x C =>x ?/>=; >f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xh; > SOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhx ? QMngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhl绾8 J arrival timeXhδ#?, JXh1 JslackXh/>R< 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu|>}l绾x C =>x ?>=p%>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xhp%> SOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhx ? QMngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhl绾8 J arrival timeXh%?, JXh1 JslackXh>R< 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/CSOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR*:BJZj7rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000nsu|>}l绾x C =>x ?>=p%>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_1 rxWordclkl8_1(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=t 3/ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] Jnet (fo=82, routed)Xhp%> SOngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh>h 95ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ?;ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xhx ? QMngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/C JFDCEXhzr; Jclock pessimismXh OKngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhl绾8 J arrival timeXh%?, JXh1 JslackXh>Rb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33AΉA$&3^p=?$&?33A=А=٣@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]Recov_fdce_C_CLR JFDCEXh(\, JXh9 J required timeXhΉA8 J arrival timeXhsZ, JXh1 JslackXh٣@Pb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33AΉA$&3^p=?$&?33A=А=٣@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]Recov_fdce_C_CLR JFDCEXh(\, JXh9 J required timeXhΉA8 J arrival timeXhsZ, JXh1 JslackXh٣@Pb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33AΉA$&3^p=?$&?33A=А=٣@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]Recov_fdce_C_CLR JFDCEXh(\, JXh9 J required timeXhΉA8 J arrival timeXhsZ, JXh1 JslackXh٣@Pb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33AΉA$&3^p=?$&?33A=А=٣@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7]Recov_fdce_C_CLR JFDCEXh(\, JXh9 J required timeXhΉA8 J arrival timeXhsZ, JXh1 JslackXh٣@Pb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33A A$&3^p=?$&?33A=А=@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]Recov_fdce_C_CLR JFDCEXh|, JXh9 J required timeXh A8 J arrival timeXhsZ, JXh1 JslackXh@Pb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33A A$&3^p=?$&?33A=А=@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]Recov_fdce_C_CLR JFDCEXh|, JXh9 J required timeXh A8 J arrival timeXhsZ, JXh1 JslackXh@Pb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33A A$&3^p=?$&?33A=А=@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]Recov_fdce_C_CLR JFDCEXh|, JXh9 J required timeXh A8 J arrival timeXhsZ, JXh1 JslackXh@Pb^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu+@}33A A$&3^p=?$&?33A=А=@d;>h0@f(rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q Prop_fdce_C_Q JFDCEXhzr> b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 Jnet (fo=3, routed)XhI3? tpngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/I0 JXhzr songFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/OProp_lut1_I0_O JLUT1XhzfT= ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=80, routed)Xh+}? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xhp=? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=1057, routed)Xh$&? ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]Recov_fdce_C_CLR JFDCEXh|, JXh9 J required timeXh A8 J arrival timeXhsZ, JXh1 JslackXh@PngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu?@}33AMA-2Ifk?-2?33A=А=p@= ?=?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)XheF? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2Xhzfj<= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_3 Jnet (fo=25, routed)Xh^#? eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh-2? c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_regRecov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhMA8 J arrival timeXhX, JXh1 JslackXhp@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000nsu?@}33AMA-2Ifk?-2?33A=А=p@= ?=?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_1 rxWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] Jnet (fo=5, routed)XheF? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2Xhzfj<= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_3 Jnet (fo=25, routed)Xh^#? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhk? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O JBUFHXhzr c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 Jnet (fo=1057, routed)Xh-2? [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_regRecov_fdce_C_CLR JFDCEXh, JXh9 J required timeXhMA8 J arrival timeXhX, JXh1 JslackXhp@ **async_default** rxWordclkl8_2 rxWordclkl8_2!)]_ff@1]_ff @9A]_ff@I]_ff @eԊ@hq}>d rise - rise rise - rise  . RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu>}d;C =&>?>=\>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh\> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhd;8 J arrival timeXhf)?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu>}d;C =&>?>=\>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh\> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhd;8 J arrival timeXhf)?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu>}d;C =&>?>=\>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh\> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhd;8 J arrival timeXhf)?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu>}d;C =&>?>=\>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh\> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhd;8 J arrival timeXhf)?, JXh1 JslackXh>* RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cd`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsu;>}wA-\=&>A?>=X>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhX> d`ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhA? b^ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzr; Jclock pessimismXh `\ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_regRemov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhw8 J arrival timeXh4?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuF>}wA-\=&>A?>=k>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhA? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhw8 J arrival timeXhb5?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuF>}wA-\=&>A?>=k>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhA? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhw8 J arrival timeXhb5?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuF>}wA-\=&>A?>=k>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhA? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhw8 J arrival timeXhb5?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuF>}wA-\=&>A?>=k>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhk> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhA? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhw8 J arrival timeXhb5?, JXh1 JslackXh>. RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0]/CLR*:BJZj7rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000nsuC>}xA-\=&>A?Wr>=>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_2 rxWordclkl8_2(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=1057, routed)Xh&> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)XhA? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhx8 J arrival timeXhM?, JXh1 JslackXhWr>ongFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu-P@}33A AZ$MDVi?Z$?33A=А=Ԋ@?5 @o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xh9|> ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)XhZ$? \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_regRecov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXh A8 J arrival timeXhA, JXh1 JslackXhԊ@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsu;I@}33AA #tDVi? #?33A=А=<@?'D@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xh> eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ZVngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xh #? c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_regRecov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhȁ, JXh1 JslackXh<@sngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2_[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuE;I@}33AA$`{DVi?$?33A=А= E@?vC@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xh> _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh$? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_regRecov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhkȁ, JXh1 JslackXh E@sngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2_[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuE;I@}33AA$`{DVi?$?33A=А= E@?vC@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xh> _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh$? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhkȁ, JXh1 JslackXh E@sngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2_[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuE;I@}33AA$`{DVi?$?33A=А= E@?vC@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xh> _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh$? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhkȁ, JXh1 JslackXh E@sngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2_[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuE;I@}33AA$`{DVi?$?33A=А= E@?vC@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xh> _[ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh$? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhkȁ, JXh1 JslackXh E@xngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuE;I@}33AA$`{DVi?$?33A=А= E@?vC@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)Xh> ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ZVngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xh$? [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_regRecov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXhkȁ, JXh1 JslackXh E@wngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuH@}33AA$`{DVi?$?33A=А=|@?@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhm> `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh$? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh|@wngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuH@}33AA$`{DVi?$?33A=А=|@?@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhm> `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh$? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh|@wngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2`\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR*:BJZ(LUT2=1)j7rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000nsuH@}33AA$`{DVi?$?33A=А=|@?@o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_2 rxWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] Jnet (fo=5, routed)Xhk ? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/OProp_lut2_I0_O JLUT2XhzfY= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 Jnet (fo=25, routed)Xhm> `\ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR JFDCEXhzfN J(clock rxWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)XhDVi? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK Jnet (fo=1057, routed)Xh$? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]Recov_fdce_C_CLR JFDCEXh㥛, JXh9 J required timeXhA8 J arrival timeXh, JXh1 JslackXh|@ **async_default** rxWordclkl8_3 rxWordclkl8_3!)]_ff@1]_ff @9A]_ff@I]_ff @e@hq}o^>d rise - rise rise - rise  95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuf>}d;}94<23>?o^>th=fZ>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhfZ>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzr; Jclock pessimismXhthw 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhd;8 J arrival timeXh)?, JXh1 JslackXho^>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuf>}d;}94<23>?o^>th=fZ>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhfZ>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzr; Jclock pessimismXhthw 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhd;8 J arrival timeXh)?, JXh1 JslackXho^>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuf>}d;}94<23>?o^>th=fZ>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhfZ>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr; Jclock pessimismXhthw 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhd;8 J arrival timeXh)?, JXh1 JslackXho^>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsuf>}d;}94<23>?o^>th=fZ>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhfZ>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]/C JFDCEXhzr; Jclock pessimismXhthw 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhd;8 J arrival timeXh)?, JXh1 JslackXho^>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsul>}A}94<23>A?>*\=pS>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhpS>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr; Jclock pessimismXh*\w 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXh(?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsul>}A}94<23>A?>*\=pS>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhpS>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr; Jclock pessimismXh*\w 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXh(?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsul>}A}94<23>A?>*\=pS>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhpS>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr; Jclock pessimismXh*\w 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXh(?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsul>}A}94<23>A?>*\=pS>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhpS>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr; Jclock pessimismXh*\w 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXh(?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsul>}A}94<23>A?>*\=pS>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhpS>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr; Jclock pessimismXh*\w 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXh(?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR*:BJZj7rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000nsul>}A}94<23>A?>*\=pS>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_3 rxWordclkl8_3(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)XhpS>f 73ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh23>h 95ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)XhA?d 51ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr; Jclock pessimismXh*\w 3/ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh8 J arrival timeXh(?, JXh1 JslackXh>R ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsu 5-@}33A7 A/ji\j?/?33A=А=@?(?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/rx_reset_done[3] Jnet (fo=5, routed)Xh+!? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1_n_0 Jnet (fo=3, routed)Xh> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 Jnet (fo=1057, routed)Xh/? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh7 A8 J arrival timeXh&g, JXh1 JslackXh@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsu 5-@}33A7 A/ji\j?/?33A=А=@?(?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/rx_reset_done[3] Jnet (fo=5, routed)Xh+!? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1_n_0 Jnet (fo=3, routed)Xh> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 Jnet (fo=1057, routed)Xh/? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh7 A8 J arrival timeXh&g, JXh1 JslackXh@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsu 5-@}33A7 A/ji\j?/?33A=А=@?(?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/rx_reset_done[3] Jnet (fo=5, routed)Xh+!? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1_n_0 Jnet (fo=3, routed)Xh> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 Jnet (fo=1057, routed)Xh/? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh7 A8 J arrival timeXh&g, JXh1 JslackXh@ongFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsuc.@}33A5 Aף0Ifi\j?ף0?33A=А=@?=?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_3 rxWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] Jnet (fo=5, routed)XhU? vrngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/I0 JXhzr uqngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/OProp_lut2_I0_O JLUT2Xhzf 0= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_1 Jnet (fo=25, routed)Xh,? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xhi\j? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK Jnet (fo=1057, routed)Xhף0? \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_regRecov_fdce_C_CLR JFDCEXh., JXh9 J required timeXh5 A8 J arrival timeXh1h, JXh1 JslackXh@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2jfngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR*:BJZ(LUT2=1)j7rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000nsuo/*@}33A; Ad rise - rise rise - rise  WSngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CTPngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE*:BJZ(LUT2=1)j7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsulT>}Ġ8[`e<X9>8?(>*\>'S>f(rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) WSngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/Q Prop_fdce_C_Q JFDCEXhzr= QMngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s Jnet (fo=1, routed)Xh= WSngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__10/I1 JXhzr VRngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__10/OProp_lut2_I1_O JLUT2XhzfA`< MIngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s0 Jnet (fo=1, routed)Xh= TPngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE JFDPEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)XhX9> WSngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh8? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzr; Jclock pessimismXh*\ PLngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_regRemov_fdpe_C_PRE JFDPEXhT, JXh9 J required timeXhĠ8 J arrival timeXhF4?, JXh1 JslackXh(>3 RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu]>}գ9}=X9>9?4>=4>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh4> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)XhX9> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh9? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhգ8 J arrival timeXhZlC?, JXh1 JslackXh4>3 RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu]>}գ9}=X9>9?4>=4>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh4> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)XhX9> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh9? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhգ8 J arrival timeXhZlC?, JXh1 JslackXh4>3 RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu]>}գ9}=X9>9?4>=4>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh4> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)XhX9> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh9? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhգ8 J arrival timeXhZlC?, JXh1 JslackXh4>3 RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu]>}գ9}=X9>9?4>=4>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh4> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)XhX9> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh9? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhգ8 J arrival timeXhZlC?, JXh1 JslackXh4> 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsuK>}M8W=!>8?>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>f 73ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh8?d 51ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhM8 J arrival timeXhC?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C73ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsuK>}M8W=!>8?>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>f 73ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh8?d 51ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr; Jclock pessimismXhw 3/ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhM8 J arrival timeXhC?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C62ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsuK>}M8W=!>8?>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>e 62ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh8?c 40ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr; Jclock pessimismXhv 2.ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhM8 J arrival timeXhC?, JXh1 JslackXh>R 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C62ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsuK>}M8W=!>8?>=>f(rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR)} 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q Prop_fdre_C_Q JFDREXhzf=h '#ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset Jnet (fo=82, routed)Xh>e 62ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr >:ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh!>h 95ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C JFDREXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzrs 0,ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] Jnet (fo=1057, routed)Xh8?c 40ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr; Jclock pessimismXhv 2.ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhM8 J arrival timeXhC?, JXh1 JslackXh>R3 RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20]/CLR*:BJZj7rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000nsu3>}գ9}=X9>9?O>=O>f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** rxWordclkl8_4 rxWordclkl8_4(DCD - SCD - CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf= eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhO> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)XhX9> RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh9? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20]/C JFDCEXhzr; Jclock pessimismXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhգ8 J arrival timeXhL?, JXh1 JslackXhO>ingFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu`&@}33AQJ A1h*'l?1?33A=А=pߥ@?@?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/out[0] Jnet (fo=5, routed)Xh(/? songFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/I0 JXhzr rnngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)XhY\? ^ZngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK Jnet (fo=1057, routed)Xh1? \XngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh ZVngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_regRecov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhQJ A8 J arrival timeXhbja, JXh1 JslackXhpߥ@rngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu`&@}33AQJ A1h*'l?1?33A=А=pߥ@?@?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/out[0] Jnet (fo=5, routed)Xh(/? songFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/I0 JXhzr rnngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/RX_RESET_I Jnet (fo=25, routed)XhY\? ]YngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ZVngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/RX_WORDCLK_I Jnet (fo=1057, routed)Xh1? [WngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh YUngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_regRecov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhQJ A8 J arrival timeXhbja, JXh1 JslackXhpߥ@ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg/CLR*:BJZ(LUT2=1)j7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu@}33A\ A1h*'l?1?33A=А=\@?]?o(rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE(Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE J GTXE2_CHANNELXhzr&? QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/out[0] Jnet (fo=5, routed)Xh(/? songFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/I0 JXhzr rnngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/OProp_lut2_I0_O JLUT2Xhzf 0= WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/rx_reset_s_0 Jnet (fo=25, routed)Xh/? eangFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in Jnet (fo=1057, routed)Xh*'l? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr NJngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK Jnet (fo=1057, routed)Xh1? c_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_regRecov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh\ A8 J arrival timeXhJ V, JXh1 JslackXh\@ RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR*:BJZj7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuh(@}33AvP A&1wD1?&1?33A=А=@>@f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh1? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXhJU, JXh1 JslackXh@ RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34]/CLR*:BJZj7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuh(@}33AvP A&1wD1?&1?33A=А=@>@f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh1? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXhJU, JXh1 JslackXh@ RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64]/CLR*:BJZj7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuh(@}33AvP A&1wD1?&1?33A=А=@>@f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh1? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXhJU, JXh1 JslackXh@ RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65]/CLR*:BJZj7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsuh(@}33AvP A&1wD1?&1?33A=А=@>@f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@ eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh1? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXhJU, JXh1 JslackXh@ RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40]/CLR*:BJZj7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu2#@}33AvP A&1wD1?&1?33A=А=<ʬ@> @f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh @ eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh1? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXhbO, JXh1 JslackXh<ʬ@ RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR*:BJZj7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu2#@}33AvP A&1wD1?&1?33A=А=<ʬ@> @f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh @ eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh1? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXhbO, JXh1 JslackXh<ʬ@ RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/CeangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66]/CLR*:BJZj7rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000nsu2#@}33AvP A&1wD1?&1?33A=А=<ʬ@> @f(rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** rxWordclkl8_4 rxWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q Prop_fdpe_C_Q JFDPEXhzf> eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh @ eangFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66]/CLR JFDCEXhzfN J(clock rxWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 Jnet (fo=1057, routed)Xh1? RNngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrN J(clock rxWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O JBUFHXhzr XTngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=1057, routed)Xh&1? c_ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66]/C JFDCEXhzr; Jclock pessimismXh= Jclock uncertaintyXh a]ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhvP A8 J arrival timeXhbO, JXh1 JslackXh<ʬ@ **async_default**txWordclkl12_1txWordclkl12_1!)]_ff@1]_ff @9A]_ff@I]_ff @e@hq}r?d rise - rise rise - rise ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu?}$fe;2 i?e;?r?D?Q?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xh-7? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 Jnet (fo=2, routed)Xh= WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhi? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xhe;? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXhD SOngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh$f8 J arrival timeXhB@, JXh1 JslackXhr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000nsu?}$fe;2 i?e;?r?D?Q?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_1txWordclkl12_1(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xh-7? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 Jnet (fo=2, routed)Xh= VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhi? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xhe;? TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXhD RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh$f8 J arrival timeXhB@, JXh1 JslackXhr? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsun!@}33AEHAOz_@O?33A=А=@ = |?؜?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xh? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 Jnet (fo=2, routed)Xhp> WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh_@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)XhO? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXh == Jclock uncertaintyXh SOngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhEHA8 J arrival timeXh, JXh1 JslackXh@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000nsun!@}33AEHAOz_@O?33A=А=@ = |?؜?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_1txWordclkl12_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xh? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 Jnet (fo=2, routed)Xhp> VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_1 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh_@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_1 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)XhO? TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXh == Jclock uncertaintyXh RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhEHA8 J arrival timeXh, JXh1 JslackXh@ **async_default**txWordclkl12_2txWordclkl12_2!)]_ff@1]_ff @9A]_ff@I]_ff @e2@hq}8?d rise - rise rise - rise ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu壠?}Q|i?|?8?n?=2?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh ? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 Jnet (fo=2, routed)Xh'J> WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhi? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh|? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXhn SOngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhQ8 J arrival timeXh@, JXh1 JslackXh8? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000nsu壠?}Q|i?|?8?n?=2?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_2txWordclkl12_2(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh ? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 Jnet (fo=2, routed)Xh'J> VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhi? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh|? TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXhn RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhQ8 J arrival timeXh@, JXh1 JslackXh8? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsuH5@}33AA-Ϳ!m_@-?33A=А=2@^d;> |??p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)XhE? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 Jnet (fo=2, routed)Xh;> WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh_@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh-? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXh^d;>= Jclock uncertaintyXh SOngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXhʋ, JXh1 JslackXh2@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000nsuH5@}33AA-Ϳ!m_@-?33A=А=2@^d;> |??p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_2txWordclkl12_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)XhE? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 Jnet (fo=2, routed)Xh;> VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_2 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh_@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_2 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh-? TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXh^d;>= Jclock uncertaintyXh RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXhʋ, JXh1 JslackXh2@ **async_default**txWordclkl12_3txWordclkl12_3!)]_ff@1]_ff @9A]_ff@I]_ff @eh@hq}?d rise - rise rise - rise ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu?}}?UَŃ?َ??n?j?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xh.F? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 Jnet (fo=2, routed)Xh"> WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhŃ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)Xhَ? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXhn SOngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh}?U8 J arrival timeXh6 @, JXh1 JslackXh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000nsu?}}?UَŃ?َ??n?j?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_3txWordclkl12_3(DCD - SCD - CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xh.F? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 Jnet (fo=2, routed)Xh"> VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhŃ? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)Xhَ? TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXhn RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh}?U8 J arrival timeXh6 @, JXh1 JslackXh? ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuM-@}33AAVͿhZ@V?33A=А=h@^d;> |??E?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)XhE? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 Jnet (fo=2, routed)Xh'> WSngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhZ@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)XhV? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXh^d;>= Jclock uncertaintyXh SOngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhA8 J arrival timeXh , JXh1 JslackXhh@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000nsuM-@}33AAVͿhZ@V?33A=А=h@^d;> |??E?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_3txWordclkl12_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)XhE? UQngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/I0 JXhzr TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 Jnet (fo=2, routed)Xh'> VRngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_3 rise edge)Xhzr MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhZ@ ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_3 rise edge)Xhzr33A MIngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)XhV? TPngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXh^d;>= Jclock uncertaintyXh RNngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhA8 J arrival timeXh , JXh1 JslackXhh@ **async_default**txWordclkl12_4txWordclkl12_4!)]_ff@1]_ff @9A]_ff@I]_ff @e@hq}5?d rise - rise rise - rise ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsuk?}K B!'s?!?5?Z?F0?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhO? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 Jnet (fo=2, routed)Xhg;> WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)Xhs? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=225, routed)Xh!? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXhZ SOngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhK B8 J arrival timeXhޝ @, JXh1 JslackXh5? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000nsuk?}K B!'s?!?5?Z?F0?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_4txWordclkl12_4(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhO? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 Jnet (fo=2, routed)Xhg;> VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)Xhs? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=225, routed)Xh!? TPngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXhZ RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhK B8 J arrival timeXhޝ @, JXh1 JslackXh5?ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu2D@}33A@AWc?W?33A=А=@> |?c2?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xhq? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 Jnet (fo=2, routed)Xh> WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)Xh? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=225, routed)XhW? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXh>= Jclock uncertaintyXh SOngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXh@A8 J arrival timeXhi, JXh1 JslackXh@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000nsu2D@}33A@AWc?W?33A=А=@> |?c2?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_4txWordclkl12_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xhq? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 Jnet (fo=2, routed)Xh> VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_4 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=225, routed)Xh? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_4 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=225, routed)XhW? TPngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXh>= Jclock uncertaintyXh RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXh@A8 J arrival timeXhi, JXh1 JslackXh@ **async_default**txWordclkl12_5txWordclkl12_5!)]_ff@1]_ff @9A]_ff@I]_ff @e@hq}?d rise - rise rise - rise ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu7+~?}5^:w@!OXt???o?S'>p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh.> XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 Jnet (fo=2, routed)XhB9> WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhOXt? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXho SOngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh5^:8 J arrival timeXhA?, JXh1 JslackXh? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000nsu7+~?}5^:w@!OXt???o?S'>p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_5txWordclkl12_5(DCD - SCD - CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh.> XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 Jnet (fo=2, routed)XhB9> VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhOXt? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh? TPngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXho RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh5^:8 J arrival timeXhA?, JXh1 JslackXh?ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuB?}33AA?50ID??5?33A=А=@K7> |?Ke?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 Jnet (fo=2, routed)Xhuq> WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhD? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh?5? UQngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXhK7>= Jclock uncertaintyXh SOngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXho, JXh1 JslackXh@ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000nsuB?}33AA?50ID??5?33A=А=@K7> |?Ke?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_5txWordclkl12_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh? XTngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/I0 JXhzr WSngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 Jnet (fo=2, routed)Xhuq> VRngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_5 rise edge)Xhzr MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)XhD? ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_5 rise edge)Xhzr33A MIngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh?5? TPngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXhK7>= Jclock uncertaintyXh RNngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXho, JXh1 JslackXh@ **async_default**txWordclkl12_6txWordclkl12_6!)]_ff@1]_ff @9A]_ff@I]_ff @eM@hq}?d rise - rise rise - rise ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu9?}T%h!^?h??ˡE?k?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhQ? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 Jnet (fo=2, routed)Xh= WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh^? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xhh? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXhˡE SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhT%8 J arrival timeXh5B@, JXh1 JslackXh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000nsu9?}T%h!^?h??ˡE?k?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_6txWordclkl12_6(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhQ? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 Jnet (fo=2, routed)Xh= VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh^? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xhh? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXhˡE RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhT%8 J arrival timeXh5B@, JXh1 JslackXh?ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsu.@}33A1A"L n?"?33A=А=M@t= |?^?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xhn? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 Jnet (fo=2, routed)Xhp> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xh"? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXh SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh1A8 J arrival timeXh, JXh1 JslackXhM@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j9txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000nsu.@}33A1A"L n?"?33A=А=M@t= |?^?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_6txWordclkl12_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)Xhn? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 Jnet (fo=2, routed)Xhp> VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfO J (clock txWordclkl12_6 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_6 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr D@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xh"? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXh RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh1A8 J arrival timeXh, JXh1 JslackXhM@ **async_default**txWordclkl12_7txWordclkl12_7!)]_ff@1]_ff @9A]_ff@I]_ff @eۄ@hq}?d rise - rise rise - rise ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu=?}$AjTRo_?jT??r?c?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh\> XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 Jnet (fo=2, routed)XhnF> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xho_? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)XhjT? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXhr SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh$A8 J arrival timeXh,?, JXh1 JslackXh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000nsu=?}$AjTRo_?jT??r?c?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_7txWordclkl12_7(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh\> XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 Jnet (fo=2, routed)XhnF> VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xho_? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)XhjT? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXhr RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh$A8 J arrival timeXh,?, JXh1 JslackXh?ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsuAU@}33AA휿<쾵??33A=А=ۄ@T< |?~T?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)XhU? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 Jnet (fo=2, routed)XhQ3> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXh/:m, JXh1 JslackXhۄ@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j9txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000nsuAU@}33AA휿<쾵??33A=А=ۄ@T< |?~T?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_7txWordclkl12_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)XhU? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 Jnet (fo=2, routed)XhQ3> VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfO J (clock txWordclkl12_7 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_7 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXhT<= Jclock uncertaintyXh RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXh/:m, JXh1 JslackXhۄ@ **async_default**txWordclkl12_8txWordclkl12_8!)]_ff@1]_ff @9A]_ff@I]_ff @ev@hq}nN?d rise - rise rise - rise ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu^?}L7)Ilo_?Il?nN?ˡE?+_3?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xh? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 Jnet (fo=2, routed)Xh> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xho_? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)XhIl? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXhˡE SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhL7)8 J arrival timeXh u@, JXh1 JslackXhnN? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000nsu^?}L7)Ilo_?Il?nN?ˡE?+_3?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})d(removal check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default**txWordclkl12_8txWordclkl12_8(DCD - SCD - CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xh? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/OProp_lut1_I0_O JLUT1XhzfA`< YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 Jnet (fo=2, routed)Xh> VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xho_? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)XhIl? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXhˡE RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXhL7)8 J arrival timeXh u@, JXh1 JslackXhnN?ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsu#@}33A?AC l?C?33A=А=v@t= |?A̳?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xh? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 Jnet (fo=2, routed)Xh> WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)XhC? UQngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXh SOngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh?A8 J arrival timeXh, JXh1 JslackXhv@ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j9txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000nsu#@}33A?AC l?C?33A=А=v@t= |?A̳?p(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})e(recovery check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default**txWordclkl12_8txWordclkl12_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?} =9ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xh? XTngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/I0 JXhzr WSngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/OProp_lut1_I0_O JLUT1Xhzf 0= YUngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 Jnet (fo=2, routed)Xh> VRngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR JFDCEXhzfO J (clock txWordclkl12_8 rise edge)Xhzr MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrO J (clock txWordclkl12_8 rise edge)Xhzr33A MIngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr FBngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)XhC? TPngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXht== Jclock uncertaintyXh RNngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXh?A8 J arrival timeXh, JXh1 JslackXhv@ **async_default** txWordclkl8_1 txWordclkl8_1!)]_ff@1]_ff @9A]_ff@I]_ff @e:}@hq}y?d rise - rise rise - rise ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsuC?}/(| j?(|?y?TV?c>o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhM> WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/OProp_lut1_I0_O JLUT1Xhzf/< XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 Jnet (fo=2, routed)Xh,> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhj? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xh(|? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXhT RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Remov_fdce_C_CLR JFDCEXh5^, JXh9 J required timeXh/8 J arrival timeXhSQ?, JXh1 JslackXhy? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j7txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000nsuC?}/(| j?(|?y?TV?c>o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_1 txWordclkl8_1(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhM> WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/OProp_lut1_I0_O JLUT1Xhzf/< XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 Jnet (fo=2, routed)Xh,> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhj? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xh(|? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXhT QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Remov_fdce_C_CLR JFDCEXh5^, JXh9 J required timeXh/8 J arrival timeXhSQ?, JXh1 JslackXhy? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR*:BJZ(LUT1=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu7'?}33Aw{Aʿd??33A=А=:}@Q=,}?Bx?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhW,? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/OProp_lut1_I0_O JLUT1Xhzf@= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 Jnet (fo=2, routed)Xh> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR JFDCEXhzfN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xh? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]Recov_fdce_C_CLR JFDCEXhIz, JXh9 J required timeXhw{A8 J arrival timeXhjv, JXh1 JslackXh:}@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR*:BJZ(LUT1=1)j7txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000nsu7'?}33Aw{Aʿd??33A=А=:}@Q=,}?Bx?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_1 txWordclkl8_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] Jnet (fo=3, routed)XhW,? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/OProp_lut1_I0_O JLUT1Xhzf@= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 Jnet (fo=2, routed)Xh> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR JFDCEXhzfN J(clock txWordclkl8_1 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_1 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O JBUFGXhzr C?ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out Jnet (fo=221, routed)Xh? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]Recov_fdce_C_CLR JFDCEXhIz, JXh9 J required timeXhw{A8 J arrival timeXhjv, JXh1 JslackXh:}@ **async_default** txWordclkl8_2 txWordclkl8_2!)]_ff@1]_ff @9A]_ff@I]_ff @eNL@hq}0q?d rise - rise rise - rise ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsur?}8Iz 1h?Iz?0q?T?L?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh> WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/OProp_lut1_I0_O JLUT1XhzfA`< XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 Jnet (fo=2, routed)Xht> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh1h? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)XhIz? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXhT RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh88 J arrival timeXhm@, JXh1 JslackXh0q? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j7txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000nsur?}8Iz 1h?Iz?0q?T?L?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_2 txWordclkl8_2(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xh> WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/OProp_lut1_I0_O JLUT1XhzfA`< XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 Jnet (fo=2, routed)Xht> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh1h? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)XhIz? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXhT QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXh88 J arrival timeXhm@, JXh1 JslackXh0q? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR*:BJZ(LUT1=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu @}33AAɿq`??33A=А=NL@Q= |?ݽ?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xhl? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/OProp_lut1_I0_O JLUT1Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 Jnet (fo=2, routed)Xh> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR JFDCEXhzfN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhA8 J arrival timeXh%k, JXh1 JslackXhNL@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR*:BJZ(LUT1=1)j7txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000nsu @}33AAɿq`??33A=А=NL@Q= |?ݽ?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_2 txWordclkl8_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] Jnet (fo=3, routed)Xhl? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/OProp_lut1_I0_O JLUT1Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 Jnet (fo=2, routed)Xh> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR JFDCEXhzfN J(clock txWordclkl8_2 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_2 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 Jnet (fo=221, routed)Xh? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhA8 J arrival timeXh%k, JXh1 JslackXhNL@ **async_default** txWordclkl8_3 txWordclkl8_3!)]_ff@1]_ff @9A]_ff@I]_ff @ea@hq}/ʤ?d rise - rise rise - rise ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsuh?}b8z 1h?z?/ʤ?T?: ?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)XhF> WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/OProp_lut1_I0_O JLUT1XhzfA`< XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 Jnet (fo=2, routed)Xh^Z> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR JFDCEXhzfN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh1h? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)Xhz? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXhT RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhb88 J arrival timeXh0i@, JXh1 JslackXh/ʤ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j7txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000nsuh?}b8z 1h?z?/ʤ?T?: ?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_3 txWordclkl8_3(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)XhF> WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/OProp_lut1_I0_O JLUT1XhzfA`< XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 Jnet (fo=2, routed)Xh^Z> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR JFDCEXhzfN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh1h? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)Xhz? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXhT QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]Remov_fdce_C_CLR JFDCEXhL, JXh9 J required timeXhb88 J arrival timeXh0i@, JXh1 JslackXh/ʤ? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR*:BJZ(LUT1=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu>@}33AoAɿc??33A=А=a@Q= |?='?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xhi#D? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 Jnet (fo=2, routed)Xh%V> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR JFDCEXhzfN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)Xh? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhoA8 J arrival timeXh ~, JXh1 JslackXha@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR*:BJZ(LUT1=1)j7txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000nsu>@}33AoAɿc??33A=А=a@Q= |?='?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_3 txWordclkl8_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] Jnet (fo=3, routed)Xhi#D? WSngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/I0 JXhzr VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/OProp_lut1_I0_O JLUT1Xhzf 0= XTngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 Jnet (fo=2, routed)Xh%V> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR JFDCEXhzfN J(clock txWordclkl8_3 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_3 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 Jnet (fo=221, routed)Xh? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]Recov_fdce_C_CLR JFDCEXh., JXh9 J required timeXhoA8 J arrival timeXh ~, JXh1 JslackXha@ **async_default** txWordclkl8_4 txWordclkl8_4!)]_ff@1]_ff @9A]_ff@I]_ff @eù@hq}?d rise - rise rise - rise ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR*:BJZ(LUT1=1)j7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsu8?}}?5(| j?(|??T?}>o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] Jnet (fo=3, routed)XhX> TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/I0 JXhzr SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 Jnet (fo=2, routed)Xh'J> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR JFDCEXhzfN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhj? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 Jnet (fo=221, routed)Xh(|? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/C JFDCEXhzr; Jclock pessimismXhT RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh}?58 J arrival timeXh?, JXh1 JslackXh?| ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR*:BJZ(LUT1=1)j7txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000nsu8?}}?5(| j?(|??T?}>o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})c(removal check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Fast**async_default** txWordclkl8_4 txWordclkl8_4(DCD - SCD - CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrl?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] Jnet (fo=3, routed)XhX> TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/I0 JXhzr SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/OProp_lut1_I0_O JLUT1XhzfA`< UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 Jnet (fo=2, routed)Xh'J> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR JFDCEXhzfN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xhj? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 Jnet (fo=221, routed)Xh(|? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/C JFDCEXhzr; Jclock pessimismXhT QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]Remov_fdce_C_CLR JFDCEXhO, JXh9 J required timeXh}?58 J arrival timeXh?, JXh1 JslackXh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR*:BJZ(LUT1=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsu&?}33AA~ʿe?~?33A=А=ù@Q= |?'o?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] Jnet (fo=3, routed)XhZ? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/I0 JXhzr SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 Jnet (fo=2, routed)Xh;> VRngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR JFDCEXhzfN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 Jnet (fo=221, routed)Xh~? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh RNngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXhrt, JXh1 JslackXhù@ ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR*:BJZ(LUT1=1)j7txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000nsu&?}33AA~ʿe?~?33A=А=ù@Q= |?'o?o(rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})d(recovery check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns})Slow**async_default** txWordclkl8_4 txWordclkl8_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE(Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE J GTXE2_CHANNELXhzrq?| <8ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] Jnet (fo=3, routed)XhZ? TPngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/I0 JXhzr SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/OProp_lut1_I0_O JLUT1Xhzf 0= UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 Jnet (fo=2, routed)Xh;> UQngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR JFDCEXhzfN J(clock txWordclkl8_4 rise edge)Xhzr LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in Jnet (fo=221, routed)Xh? ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 J GTXE2_CHANNELXhzrN J(clock txWordclkl8_4 rise edge)Xhzr33A LHngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O JBUFGXhzr EAngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 Jnet (fo=221, routed)Xh~? SOngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/C JFDCEXhzr; Jclock pessimismXhQ== Jclock uncertaintyXh QMngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]Recov_fdce_C_CLR JFDCEXhY, JXh9 J required timeXhA8 J arrival timeXhrt, JXh1 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pga_ebi_nwe_0cpld2fpga_gpio[0]cpld2fpga_gpio[1]cpld2fpga_gpio[3]fmc_l12_la_n[10]fmc_l12_la_n[12]fmc_l12_la_n[14]fmc_l12_la_n[15]fmc_l12_la_n[16]fmc_l12_la_n[17]fmc_l12_la_n[21]fmc_l12_la_n[23]fmc_l12_la_n[24]fmc_l12_la_n[25]fmc_l12_la_n[26]fmc_l12_la_n[28]fmc_l12_la_n[30]fmc_l12_la_n[31]fmc_l12_la_n[32]fmc_l12_la_n[33]fmc_l12_la_n[5]fmc_l12_la_n[7]fmc_l12_la_n[8]fmc_l12_la_n[9]fmc_l12_la_p[11]fmc_l12_la_p[12]fmc_l12_la_p[13]fmc_l12_la_p[14]fmc_l12_la_p[16]fmc_l12_la_p[20]fmc_l12_la_p[21]fmc_l12_la_p[22]fmc_l12_la_p[23]fmc_l12_la_p[25]fmc_l12_la_p[27]fmc_l12_la_p[28]fmc_l12_la_p[29]fmc_l12_la_p[30]fmc_l12_la_p[32]fmc_l12_la_p[4]fmc_l12_la_p[5]fmc_l12_la_p[6]fmc_l12_la_p[7]fmc_l12_la_p[9]fmc_l12_pg_m2cfmc_l12_prsnt_lfmc_l8_la_n[10]fmc_l8_la_n[12]fmc_l8_la_n[14]fmc_l8_la_n[15]fmc_l8_la_n[16]fmc_l8_la_n[17]fmc_l8_la_n[5]fmc_l8_la_n[7]fmc_l8_la_n[8]fmc_l8_la_n[9]fmc_l8_la_p[11]fmc_l8_la_p[12]fmc_l8_la_p[13]fmc_l8_la_p[14]fmc_l8_la_p[16]fmc_l8_la_p[4]fmc_l8_la_p[5]fmc_l8_la_p[6]fmc_l8_la_p[7]fmc_l8_la_p[9] fmc_l8_pg_m2cfmc_l8_prsnt_lfmc_l8_spare[10]fmc_l8_spare[11]fpga_config_data[0]fpga_config_data[10]fpga_config_data[11]fpga_config_data[12]fpga_config_data[13]fpga_config_data[14]fpga_config_data[15]fpga_config_data[1]fpga_config_data[2]fpga_config_data[3]fpga_config_data[4]fpga_config_data[5]fpga_config_data[6]fpga_config_data[7]fpga_config_data[8]fpga_config_data[9]k7_fabric_amc_rx_p03 local_i2c_sda pca8574_intsw3Wcdce_ctrla4_r1 cdce_sync_r1cpld2fpga_gpio[2]fmc_l12_la_n[12]fmc_l12_la_n[13]fmc_l12_la_n[16]fmc_l12_la_n[21]fmc_l12_la_n[22]fmc_l12_la_n[25]fmc_l12_la_n[28]fmc_l12_la_n[29]fmc_l12_la_n[32]fmc_l12_la_n[5]fmc_l12_la_n[6]fmc_l12_la_n[9]fmc_l12_la_p[10]fmc_l12_la_p[13]fmc_l12_la_p[16]fmc_l12_la_p[17]fmc_l12_la_p[22]fmc_l12_la_p[25]fmc_l12_la_p[26]fmc_l12_la_p[29]fmc_l12_la_p[32]fmc_l12_la_p[33]fmc_l12_la_p[6]fmc_l12_la_p[9]fmc_l8_la_n[12]fmc_l8_la_n[13]fmc_l8_la_n[16]fmc_l8_la_n[5]fmc_l8_la_n[6]fmc_l8_la_n[9]fmc_l8_la_p[10]fmc_l8_la_p[13]fmc_l8_la_p[16]fmc_l8_la_p[17]fmc_l8_la_p[6]fmc_l8_la_p[9]fmc_l8_spare[0]fmc_l8_spare[12]fmc_l8_spare[13]fmc_l8_spare[14]fmc_l8_spare[15]fmc_l8_spare[16]fmc_l8_spare[17]fmc_l8_spare[18]fmc_l8_spare[19]fmc_l8_spare[1]fmc_l8_spare[2]fmc_l8_spare[3]fmc_l8_spare[4]fmc_l8_spare[5]fmc_l8_spare[9]fpga_config_data[0]fpga_config_data[10]fpga_config_data[11]fpga_config_data[12]fpga_config_data[13]fpga_config_data[14]fpga_config_data[15]fpga_config_data[1]fpga_config_data[2]fpga_config_data[3]fpga_config_data[4]fpga_config_data[5]fpga_config_data[6]fpga_config_data[7]fpga_config_data[8]fpga_config_data[9]k7_master_xpoint_ctrl[0]k7_master_xpoint_ctrl[1]k7_master_xpoint_ctrl[6]k7_master_xpoint_ctrl[7]k7_master_xpoint_ctrl[8]k7_master_xpoint_ctrl[9]k7_pcie_clk_ctrl[0]k7_pcie_clk_ctrl[1] k7_tclkb_en k7_tclkd_en local_i2c_scl local_i2c_sda  sysled1_b  sysled1_r  sysled2_b  sysled2_g  sysled2_r